1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
118 - arm,armv8 # Only for s/w models
153 - nvidia,tegra132-denver
154 - nvidia,tegra186-denver
155 - nvidia,tegra194-carmel
164 - $ref: '/schemas/types.yaml#/definitions/string'
166 # On ARM v8 64-bit this property is required
170 # On ARM 32-bit systems this property is optional
173 - allwinner,sun6i-a31
174 - allwinner,sun8i-a23
175 - allwinner,sun9i-a80-smp
176 - allwinner,sun8i-a83t-smp
178 - amlogic,meson8b-smp
181 - brcm,bcm11351-cpu-method
187 - marvell,armada-375-smp
188 - marvell,armada-380-smp
189 - marvell,armada-390-smp
190 - marvell,armada-xp-smp
191 - marvell,98dx3236-smp
193 - mediatek,mt6589-smp
194 - mediatek,mt81xx-tz-smp
199 - renesas,r9a06g032-smp
200 - rockchip,rk3036-smp
201 - rockchip,rk3066-smp
202 - socionext,milbeaut-m10v-smp
206 $ref: '/schemas/types.yaml#/definitions/uint64'
209 Required for systems that have an "enable-method"
210 property value of "spin-table".
211 On ARM v8 64-bit systems must be a two cell
212 property identifying a 64-bit zero-initialised
216 $ref: '/schemas/types.yaml#/definitions/phandle-array'
218 List of phandles to idle state nodes supported
219 by this cpu (see ./idle-states.yaml).
222 $ref: '/schemas/types.yaml#/definitions/uint32'
224 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
225 DMIPS/MHz, relative to highest capacity-dmips-mhz
228 dynamic-power-coefficient:
229 $ref: '/schemas/types.yaml#/definitions/uint32'
231 A u32 value that represents the running time dynamic
232 power coefficient in units of uW/MHz/V^2. The
233 coefficient can either be calculated from power
234 measurements or derived by analysis.
236 The dynamic power consumption of the CPU is
237 proportional to the square of the Voltage (V) and
238 the clock frequency (f). The coefficient is used to
239 calculate the dynamic power as below -
241 Pdyn = dynamic-power-coefficient * V^2 * f
243 where voltage is in V, frequency is in MHz.
246 $ref: '/schemas/types.yaml#/definitions/phandle-array'
248 List of phandles and PM domain specifiers, as defined by bindings of the
249 PM domain provider (see also ../power_domain.txt).
252 $ref: '/schemas/types.yaml#/definitions/string-array'
254 A list of power domain name strings sorted in the same order as the
255 power-domains property.
257 For PSCI based platforms, the name corresponding to the index of the PSCI
258 PM domain provider, must be "psci".
261 $ref: '/schemas/types.yaml#/definitions/phandle'
263 Specifies the SAW* node associated with this CPU.
265 Required for systems that have an "enable-method" property
266 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
268 * arm/msm/qcom,saw2.txt
271 $ref: '/schemas/types.yaml#/definitions/phandle'
273 Specifies the ACC* node associated with this CPU.
275 Required for systems that have an "enable-method" property
276 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
278 * arm/msm/qcom,kpss-acc.txt
281 $ref: '/schemas/types.yaml#/definitions/phandle'
283 Specifies the syscon node controlling the cpu core power domains.
285 Optional for systems that have an "enable-method"
286 property value of "rockchip,rk3066-smp"
287 While optional, it is the preferred way to get access to
288 the cpu-core power-domains.
296 rockchip,pmu: [enable-method]
302 #address-cells = <1>;
306 compatible = "arm,cortex-a15";
312 compatible = "arm,cortex-a15";
318 compatible = "arm,cortex-a7";
324 compatible = "arm,cortex-a7";
330 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
333 #address-cells = <1>;
337 compatible = "arm,cortex-a8";
343 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
346 #address-cells = <1>;
350 compatible = "arm,arm926ej-s";
356 // Example 4 (ARM Cortex-A57 64-bit system):
359 #address-cells = <2>;
363 compatible = "arm,cortex-a57";
365 enable-method = "spin-table";
366 cpu-release-addr = <0 0x20000000>;
371 compatible = "arm,cortex-a57";
373 enable-method = "spin-table";
374 cpu-release-addr = <0 0x20000000>;
379 compatible = "arm,cortex-a57";
381 enable-method = "spin-table";
382 cpu-release-addr = <0 0x20000000>;
387 compatible = "arm,cortex-a57";
389 enable-method = "spin-table";
390 cpu-release-addr = <0 0x20000000>;
395 compatible = "arm,cortex-a57";
397 enable-method = "spin-table";
398 cpu-release-addr = <0 0x20000000>;
403 compatible = "arm,cortex-a57";
405 enable-method = "spin-table";
406 cpu-release-addr = <0 0x20000000>;
411 compatible = "arm,cortex-a57";
413 enable-method = "spin-table";
414 cpu-release-addr = <0 0x20000000>;
419 compatible = "arm,cortex-a57";
421 enable-method = "spin-table";
422 cpu-release-addr = <0 0x20000000>;
427 compatible = "arm,cortex-a57";
429 enable-method = "spin-table";
430 cpu-release-addr = <0 0x20000000>;
435 compatible = "arm,cortex-a57";
437 enable-method = "spin-table";
438 cpu-release-addr = <0 0x20000000>;
443 compatible = "arm,cortex-a57";
445 enable-method = "spin-table";
446 cpu-release-addr = <0 0x20000000>;
451 compatible = "arm,cortex-a57";
453 enable-method = "spin-table";
454 cpu-release-addr = <0 0x20000000>;
459 compatible = "arm,cortex-a57";
461 enable-method = "spin-table";
462 cpu-release-addr = <0 0x20000000>;
467 compatible = "arm,cortex-a57";
469 enable-method = "spin-table";
470 cpu-release-addr = <0 0x20000000>;
475 compatible = "arm,cortex-a57";
477 enable-method = "spin-table";
478 cpu-release-addr = <0 0x20000000>;
483 compatible = "arm,cortex-a57";
485 enable-method = "spin-table";
486 cpu-release-addr = <0 0x20000000>;