Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-m0"
 162                             "arm,cortex-m0+"
 163                             "arm,cortex-m1"
 164                             "arm,cortex-m3"
 165                             "arm,cortex-m4"
 166                             "arm,cortex-r4"
 167                             "arm,cortex-r5"
 168                             "arm,cortex-r7"
 169                             "brcm,brahma-b15"
 170                             "cavium,thunder"
 171                             "faraday,fa526"
 172                             "intel,sa110"
 173                             "intel,sa1100"
 174                             "marvell,feroceon"
 175                             "marvell,mohawk"
 176                             "marvell,pj4a"
 177                             "marvell,pj4b"
 178                             "marvell,sheeva-v5"
 179                             "nvidia,tegra132-denver"
 180                             "qcom,krait"
 181                             "qcom,scorpion"
 182         - enable-method
 183                 Value type: <stringlist>
 184                 Usage and definition depend on ARM architecture version.
 185                         # On ARM v8 64-bit this property is required and must
 186                           be one of:
 187                              "psci"
 188                              "spin-table"
 189                         # On ARM 32-bit systems this property is optional and
 190                           can be one of:
 191                             "allwinner,sun6i-a31"
 192                             "allwinner,sun8i-a23"
 193                             "arm,psci"
 194                             "arm,realview-smp"
 195                             "brcm,brahma-b15"
 196                             "marvell,armada-375-smp"
 197                             "marvell,armada-380-smp"
 198                             "marvell,armada-390-smp"
 199                             "marvell,armada-xp-smp"
 200                             "mediatek,mt6589-smp"
 201                             "mediatek,mt81xx-tz-smp"
 202                             "qcom,gcc-msm8660"
 203                             "qcom,kpss-acc-v1"
 204                             "qcom,kpss-acc-v2"
 205                             "rockchip,rk3066-smp"
 206                             "ste,dbx500-smp"
 207
 208         - cpu-release-addr
 209                 Usage: required for systems that have an "enable-method"
 210                        property value of "spin-table".
 211                 Value type: <prop-encoded-array>
 212                 Definition:
 213                         # On ARM v8 64-bit systems must be a two cell
 214                           property identifying a 64-bit zero-initialised
 215                           memory location.
 216
 217         - qcom,saw
 218                 Usage: required for systems that have an "enable-method"
 219                        property value of "qcom,kpss-acc-v1" or
 220                        "qcom,kpss-acc-v2"
 221                 Value type: <phandle>
 222                 Definition: Specifies the SAW[1] node associated with this CPU.
 223
 224         - qcom,acc
 225                 Usage: required for systems that have an "enable-method"
 226                        property value of "qcom,kpss-acc-v1" or
 227                        "qcom,kpss-acc-v2"
 228                 Value type: <phandle>
 229                 Definition: Specifies the ACC[2] node associated with this CPU.
 230
 231         - cpu-idle-states
 232                 Usage: Optional
 233                 Value type: <prop-encoded-array>
 234                 Definition:
 235                         # List of phandles to idle state nodes supported
 236                           by this cpu [3].
 237
 238         - rockchip,pmu
 239                 Usage: optional for systems that have an "enable-method"
 240                        property value of "rockchip,rk3066-smp"
 241                        While optional, it is the preferred way to get access to
 242                        the cpu-core power-domains.
 243                 Value type: <phandle>
 244                 Definition: Specifies the syscon node controlling the cpu core
 245                             power domains.
 246
 247         - dynamic-power-coefficient
 248                 Usage: optional
 249                 Value type: <prop-encoded-array>
 250                 Definition: A u32 value that represents the running time dynamic
 251                             power coefficient in units of mW/MHz/uVolt^2. The
 252                             coefficient can either be calculated from power
 253                             measurements or derived by analysis.
 254
 255                             The dynamic power consumption of the CPU  is
 256                             proportional to the square of the Voltage (V) and
 257                             the clock frequency (f). The coefficient is used to
 258                             calculate the dynamic power as below -
 259
 260                             Pdyn = dynamic-power-coefficient * V^2 * f
 261
 262                             where voltage is in uV, frequency is in MHz.
 263
 264 Example 1 (dual-cluster big.LITTLE system 32-bit):
 265
 266         cpus {
 267                 #size-cells = <0>;
 268                 #address-cells = <1>;
 269
 270                 cpu@0 {
 271                         device_type = "cpu";
 272                         compatible = "arm,cortex-a15";
 273                         reg = <0x0>;
 274                 };
 275
 276                 cpu@1 {
 277                         device_type = "cpu";
 278                         compatible = "arm,cortex-a15";
 279                         reg = <0x1>;
 280                 };
 281
 282                 cpu@100 {
 283                         device_type = "cpu";
 284                         compatible = "arm,cortex-a7";
 285                         reg = <0x100>;
 286                 };
 287
 288                 cpu@101 {
 289                         device_type = "cpu";
 290                         compatible = "arm,cortex-a7";
 291                         reg = <0x101>;
 292                 };
 293         };
 294
 295 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 296
 297         cpus {
 298                 #size-cells = <0>;
 299                 #address-cells = <1>;
 300
 301                 cpu@0 {
 302                         device_type = "cpu";
 303                         compatible = "arm,cortex-a8";
 304                         reg = <0x0>;
 305                 };
 306         };
 307
 308 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 309
 310         cpus {
 311                 #size-cells = <0>;
 312                 #address-cells = <1>;
 313
 314                 cpu@0 {
 315                         device_type = "cpu";
 316                         compatible = "arm,arm926ej-s";
 317                         reg = <0x0>;
 318                 };
 319         };
 320
 321 Example 4 (ARM Cortex-A57 64-bit system):
 322
 323 cpus {
 324         #size-cells = <0>;
 325         #address-cells = <2>;
 326
 327         cpu@0 {
 328                 device_type = "cpu";
 329                 compatible = "arm,cortex-a57";
 330                 reg = <0x0 0x0>;
 331                 enable-method = "spin-table";
 332                 cpu-release-addr = <0 0x20000000>;
 333         };
 334
 335         cpu@1 {
 336                 device_type = "cpu";
 337                 compatible = "arm,cortex-a57";
 338                 reg = <0x0 0x1>;
 339                 enable-method = "spin-table";
 340                 cpu-release-addr = <0 0x20000000>;
 341         };
 342
 343         cpu@100 {
 344                 device_type = "cpu";
 345                 compatible = "arm,cortex-a57";
 346                 reg = <0x0 0x100>;
 347                 enable-method = "spin-table";
 348                 cpu-release-addr = <0 0x20000000>;
 349         };
 350
 351         cpu@101 {
 352                 device_type = "cpu";
 353                 compatible = "arm,cortex-a57";
 354                 reg = <0x0 0x101>;
 355                 enable-method = "spin-table";
 356                 cpu-release-addr = <0 0x20000000>;
 357         };
 358
 359         cpu@10000 {
 360                 device_type = "cpu";
 361                 compatible = "arm,cortex-a57";
 362                 reg = <0x0 0x10000>;
 363                 enable-method = "spin-table";
 364                 cpu-release-addr = <0 0x20000000>;
 365         };
 366
 367         cpu@10001 {
 368                 device_type = "cpu";
 369                 compatible = "arm,cortex-a57";
 370                 reg = <0x0 0x10001>;
 371                 enable-method = "spin-table";
 372                 cpu-release-addr = <0 0x20000000>;
 373         };
 374
 375         cpu@10100 {
 376                 device_type = "cpu";
 377                 compatible = "arm,cortex-a57";
 378                 reg = <0x0 0x10100>;
 379                 enable-method = "spin-table";
 380                 cpu-release-addr = <0 0x20000000>;
 381         };
 382
 383         cpu@10101 {
 384                 device_type = "cpu";
 385                 compatible = "arm,cortex-a57";
 386                 reg = <0x0 0x10101>;
 387                 enable-method = "spin-table";
 388                 cpu-release-addr = <0 0x20000000>;
 389         };
 390
 391         cpu@100000000 {
 392                 device_type = "cpu";
 393                 compatible = "arm,cortex-a57";
 394                 reg = <0x1 0x0>;
 395                 enable-method = "spin-table";
 396                 cpu-release-addr = <0 0x20000000>;
 397         };
 398
 399         cpu@100000001 {
 400                 device_type = "cpu";
 401                 compatible = "arm,cortex-a57";
 402                 reg = <0x1 0x1>;
 403                 enable-method = "spin-table";
 404                 cpu-release-addr = <0 0x20000000>;
 405         };
 406
 407         cpu@100000100 {
 408                 device_type = "cpu";
 409                 compatible = "arm,cortex-a57";
 410                 reg = <0x1 0x100>;
 411                 enable-method = "spin-table";
 412                 cpu-release-addr = <0 0x20000000>;
 413         };
 414
 415         cpu@100000101 {
 416                 device_type = "cpu";
 417                 compatible = "arm,cortex-a57";
 418                 reg = <0x1 0x101>;
 419                 enable-method = "spin-table";
 420                 cpu-release-addr = <0 0x20000000>;
 421         };
 422
 423         cpu@100010000 {
 424                 device_type = "cpu";
 425                 compatible = "arm,cortex-a57";
 426                 reg = <0x1 0x10000>;
 427                 enable-method = "spin-table";
 428                 cpu-release-addr = <0 0x20000000>;
 429         };
 430
 431         cpu@100010001 {
 432                 device_type = "cpu";
 433                 compatible = "arm,cortex-a57";
 434                 reg = <0x1 0x10001>;
 435                 enable-method = "spin-table";
 436                 cpu-release-addr = <0 0x20000000>;
 437         };
 438
 439         cpu@100010100 {
 440                 device_type = "cpu";
 441                 compatible = "arm,cortex-a57";
 442                 reg = <0x1 0x10100>;
 443                 enable-method = "spin-table";
 444                 cpu-release-addr = <0 0x20000000>;
 445         };
 446
 447         cpu@100010101 {
 448                 device_type = "cpu";
 449                 compatible = "arm,cortex-a57";
 450                 reg = <0x1 0x10101>;
 451                 enable-method = "spin-table";
 452                 cpu-release-addr = <0 0x20000000>;
 453         };
 454 };
 455
 456 --
 457 [1] arm/msm/qcom,saw2.txt
 458 [2] arm/msm/qcom,kpss-acc.txt
 459 [3] ARM Linux kernel documentation - idle states bindings
 460     Documentation/devicetree/bindings/arm/idle-states.txt