5 Some platforms may have multiple types of memory attached to a compute
6 node. These disparate memory ranges may share some characteristics, such
7 as CPU cache coherence, but may have different performance. For example,
8 different media types and buses affect bandwidth and latency.
10 A system supports such heterogeneous memory by grouping each memory type
11 under different domains, or "nodes", based on locality and performance
12 characteristics. Some memory may share the same node as a CPU, and others
13 are provided as memory only nodes. While memory only nodes do not provide
14 CPUs, they may still be local to one or more compute nodes relative to
15 other nodes. The following diagram shows one such example of two compute
16 nodes with local memory and a memory only node for each of compute node::
18 +------------------+ +------------------+
19 | Compute Node 0 +-----+ Compute Node 1 |
20 | Local Node0 Mem | | Local Node1 Mem |
21 +--------+---------+ +--------+---------+
23 +--------+---------+ +--------+---------+
24 | Slower Node2 Mem | | Slower Node3 Mem |
25 +------------------+ +--------+---------+
27 A "memory initiator" is a node containing one or more devices such as
28 CPUs or separate memory I/O devices that can initiate memory requests.
29 A "memory target" is a node containing one or more physical address
30 ranges accessible from one or more memory initiators.
32 When multiple memory initiators exist, they may not all have the same
33 performance when accessing a given memory target. Each initiator-target
34 pair may be organized into different ranked access classes to represent
35 this relationship. The highest performing initiator to a given target
36 is considered to be one of that target's local initiators, and given
37 the highest access class, 0. Any given target may have one or more
38 local initiators, and any given initiator may have multiple local
41 To aid applications matching memory targets with their initiators, the
42 kernel provides symlinks to each other. The following example lists the
43 relationship for the access class "0" memory initiators and targets::
45 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
46 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
48 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
49 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
51 A memory initiator may have multiple memory targets in the same access
52 class. The target memory's initiators in a given class indicate the
53 nodes' access characteristics share the same performance relative to other
54 linked initiator nodes. Each target within an initiator's access class,
55 though, do not necessarily perform the same as each other.
57 The access class "1" is used to allow differentiation between initiators
58 that are CPUs and hence suitable for generic task scheduling, and
59 IO initiators such as GPUs and NICs. Unlike access class 0, only
60 nodes containing CPUs are considered.
66 Applications may wish to consider which node they want their memory to
67 be allocated from based on the node's performance characteristics. If
68 the system provides these attributes, the kernel exports them under the
69 node sysfs hierarchy by appending the attributes directory under the
70 memory node's access class 0 initiators as follows::
72 /sys/devices/system/node/nodeY/access0/initiators/
74 These attributes apply only when accessed from nodes that have the
75 are linked under the this access's initiators.
77 The performance characteristics the kernel provides for the local initiators
78 are exported are as follows::
80 # tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
81 /sys/devices/system/node/nodeY/access0/initiators/
87 The bandwidth attributes are provided in MiB/second.
89 The latency attributes are provided in nanoseconds.
91 The values reported here correspond to the rated latency and bandwidth
94 Access class 1 takes the same form but only includes values for CPU to
101 System memory may be constructed in a hierarchy of elements with various
102 performance characteristics in order to provide large address space of
103 slower performing memory cached by a smaller higher performing memory. The
104 system physical addresses memory initiators are aware of are provided
105 by the last memory level in the hierarchy. The system meanwhile uses
106 higher performing memory to transparently cache access to progressively
109 The term "far memory" is used to denote the last level memory in the
110 hierarchy. Each increasing cache level provides higher performing
111 initiator access, and the term "near memory" represents the fastest
112 cache provided by the system.
114 This numbering is different than CPU caches where the cache level (ex:
115 L1, L2, L3) uses the CPU-side view where each increased level is lower
116 performing. In contrast, the memory cache level is centric to the last
117 level memory, so the higher numbered cache level corresponds to memory
118 nearer to the CPU, and further from far memory.
120 The memory-side caches are not directly addressable by software. When
121 software accesses a system address, the system will return it from the
122 near memory cache if it is present. If it is not present, the system
123 accesses the next level of memory until there is either a hit in that
124 cache level, or it reaches far memory.
126 An application does not need to know about caching attributes in order
127 to use the system. Software may optionally query the memory cache
128 attributes in order to maximize the performance out of such a setup.
129 If the system provides a way for the kernel to discover this information,
130 for example with ACPI HMAT (Heterogeneous Memory Attribute Table),
131 the kernel will append these attributes to the NUMA node memory target.
133 When the kernel first registers a memory cache with a node, the kernel
134 will create the following directory::
136 /sys/devices/system/node/nodeX/memory_side_cache/
138 If that directory is not present, the system either does not provide
139 a memory-side cache, or that information is not accessible to the kernel.
141 The attributes for each level of cache is provided under its cache
144 /sys/devices/system/node/nodeX/memory_side_cache/indexA/
145 /sys/devices/system/node/nodeX/memory_side_cache/indexB/
146 /sys/devices/system/node/nodeX/memory_side_cache/indexC/
148 Each cache level's directory provides its attributes. For example, the
149 following shows a single cache level and the attributes available for
152 # tree /sys/devices/system/node/node0/memory_side_cache/
153 /sys/devices/system/node/node0/memory_side_cache/
160 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
161 for any other indexed based, multi-way associativity.
163 The "line_size" is the number of bytes accessed from the next cache
166 The "size" is the number of bytes provided by this cache level.
168 The "write_policy" will be 0 for write-back, and non-zero for
169 write-through caching.
175 [1] https://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf