| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver |
| 4 | // |
| 5 | // Author: Timur Tabi <timur@freescale.com> |
| 6 | // |
| 7 | // Copyright 2007-2010 Freescale Semiconductor, Inc. |
| 8 | // |
| 9 | // Some notes why imx-pcm-fiq is used instead of DMA on some boards: |
| 10 | // |
| 11 | // The i.MX SSI core has some nasty limitations in AC97 mode. While most |
| 12 | // sane processor vendors have a FIFO per AC97 slot, the i.MX has only |
| 13 | // one FIFO which combines all valid receive slots. We cannot even select |
| 14 | // which slots we want to receive. The WM9712 with which this driver |
| 15 | // was developed with always sends GPIO status data in slot 12 which |
| 16 | // we receive in our (PCM-) data stream. The only chance we have is to |
| 17 | // manually skip this data in the FIQ handler. With sampling rates different |
| 18 | // from 48000Hz not every frame has valid receive data, so the ratio |
| 19 | // between pcm data and GPIO status data changes. Our FIQ handler is not |
| 20 | // able to handle this, hence this driver only works with 48000Hz sampling |
| 21 | // rate. |
| 22 | // Reading and writing AC97 registers is another challenge. The core |
| 23 | // provides us status bits when the read register is updated with *another* |
| 24 | // value. When we read the same register two times (and the register still |
| 25 | // contains the same value) these status bits are not set. We work |
| 26 | // around this by not polling these bits but only wait a fixed delay. |
| 27 | |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/io.h> |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/clk.h> |
| 33 | #include <linux/ctype.h> |
| 34 | #include <linux/device.h> |
| 35 | #include <linux/delay.h> |
| 36 | #include <linux/mutex.h> |
| 37 | #include <linux/slab.h> |
| 38 | #include <linux/spinlock.h> |
| 39 | #include <linux/of.h> |
| 40 | #include <linux/of_address.h> |
| 41 | #include <linux/of_irq.h> |
| 42 | #include <linux/of_platform.h> |
| 43 | |
| 44 | #include <sound/core.h> |
| 45 | #include <sound/pcm.h> |
| 46 | #include <sound/pcm_params.h> |
| 47 | #include <sound/initval.h> |
| 48 | #include <sound/soc.h> |
| 49 | #include <sound/dmaengine_pcm.h> |
| 50 | |
| 51 | #include "fsl_ssi.h" |
| 52 | #include "imx-pcm.h" |
| 53 | |
| 54 | /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */ |
| 55 | #define RX 0 |
| 56 | #define TX 1 |
| 57 | |
| 58 | /** |
| 59 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI |
| 60 | * |
| 61 | * The SSI has a limitation in that the samples must be in the same byte |
| 62 | * order as the host CPU. This is because when multiple bytes are written |
| 63 | * to the STX register, the bytes and bits must be written in the same |
| 64 | * order. The STX is a shift register, so all the bits need to be aligned |
| 65 | * (bit-endianness must match byte-endianness). Processors typically write |
| 66 | * the bits within a byte in the same order that the bytes of a word are |
| 67 | * written in. So if the host CPU is big-endian, then only big-endian |
| 68 | * samples will be written to STX properly. |
| 69 | */ |
| 70 | #ifdef __BIG_ENDIAN |
| 71 | #define FSLSSI_I2S_FORMATS \ |
| 72 | (SNDRV_PCM_FMTBIT_S8 | \ |
| 73 | SNDRV_PCM_FMTBIT_S16_BE | \ |
| 74 | SNDRV_PCM_FMTBIT_S18_3BE | \ |
| 75 | SNDRV_PCM_FMTBIT_S20_3BE | \ |
| 76 | SNDRV_PCM_FMTBIT_S24_3BE | \ |
| 77 | SNDRV_PCM_FMTBIT_S24_BE) |
| 78 | #else |
| 79 | #define FSLSSI_I2S_FORMATS \ |
| 80 | (SNDRV_PCM_FMTBIT_S8 | \ |
| 81 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 82 | SNDRV_PCM_FMTBIT_S18_3LE | \ |
| 83 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 84 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
| 85 | SNDRV_PCM_FMTBIT_S24_LE) |
| 86 | #endif |
| 87 | |
| 88 | /* |
| 89 | * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1: |
| 90 | * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS |
| 91 | * - Also have NB_NF to mark these two clocks will not be inverted |
| 92 | */ |
| 93 | #define FSLSSI_AC97_DAIFMT \ |
| 94 | (SND_SOC_DAIFMT_AC97 | \ |
| 95 | SND_SOC_DAIFMT_CBM_CFS | \ |
| 96 | SND_SOC_DAIFMT_NB_NF) |
| 97 | |
| 98 | #define FSLSSI_SIER_DBG_RX_FLAGS \ |
| 99 | (SSI_SIER_RFF0_EN | \ |
| 100 | SSI_SIER_RLS_EN | \ |
| 101 | SSI_SIER_RFS_EN | \ |
| 102 | SSI_SIER_ROE0_EN | \ |
| 103 | SSI_SIER_RFRC_EN) |
| 104 | #define FSLSSI_SIER_DBG_TX_FLAGS \ |
| 105 | (SSI_SIER_TFE0_EN | \ |
| 106 | SSI_SIER_TLS_EN | \ |
| 107 | SSI_SIER_TFS_EN | \ |
| 108 | SSI_SIER_TUE0_EN | \ |
| 109 | SSI_SIER_TFRC_EN) |
| 110 | |
| 111 | enum fsl_ssi_type { |
| 112 | FSL_SSI_MCP8610, |
| 113 | FSL_SSI_MX21, |
| 114 | FSL_SSI_MX35, |
| 115 | FSL_SSI_MX51, |
| 116 | }; |
| 117 | |
| 118 | struct fsl_ssi_regvals { |
| 119 | u32 sier; |
| 120 | u32 srcr; |
| 121 | u32 stcr; |
| 122 | u32 scr; |
| 123 | }; |
| 124 | |
| 125 | static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) |
| 126 | { |
| 127 | switch (reg) { |
| 128 | case REG_SSI_SACCEN: |
| 129 | case REG_SSI_SACCDIS: |
| 130 | return false; |
| 131 | default: |
| 132 | return true; |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) |
| 137 | { |
| 138 | switch (reg) { |
| 139 | case REG_SSI_STX0: |
| 140 | case REG_SSI_STX1: |
| 141 | case REG_SSI_SRX0: |
| 142 | case REG_SSI_SRX1: |
| 143 | case REG_SSI_SISR: |
| 144 | case REG_SSI_SFCSR: |
| 145 | case REG_SSI_SACNT: |
| 146 | case REG_SSI_SACADD: |
| 147 | case REG_SSI_SACDAT: |
| 148 | case REG_SSI_SATAG: |
| 149 | case REG_SSI_SACCST: |
| 150 | case REG_SSI_SOR: |
| 151 | return true; |
| 152 | default: |
| 153 | return false; |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) |
| 158 | { |
| 159 | switch (reg) { |
| 160 | case REG_SSI_SRX0: |
| 161 | case REG_SSI_SRX1: |
| 162 | case REG_SSI_SISR: |
| 163 | case REG_SSI_SACADD: |
| 164 | case REG_SSI_SACDAT: |
| 165 | case REG_SSI_SATAG: |
| 166 | return true; |
| 167 | default: |
| 168 | return false; |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) |
| 173 | { |
| 174 | switch (reg) { |
| 175 | case REG_SSI_SRX0: |
| 176 | case REG_SSI_SRX1: |
| 177 | case REG_SSI_SACCST: |
| 178 | return false; |
| 179 | default: |
| 180 | return true; |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | static const struct regmap_config fsl_ssi_regconfig = { |
| 185 | .max_register = REG_SSI_SACCDIS, |
| 186 | .reg_bits = 32, |
| 187 | .val_bits = 32, |
| 188 | .reg_stride = 4, |
| 189 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
| 190 | .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, |
| 191 | .readable_reg = fsl_ssi_readable_reg, |
| 192 | .volatile_reg = fsl_ssi_volatile_reg, |
| 193 | .precious_reg = fsl_ssi_precious_reg, |
| 194 | .writeable_reg = fsl_ssi_writeable_reg, |
| 195 | .cache_type = REGCACHE_FLAT, |
| 196 | }; |
| 197 | |
| 198 | struct fsl_ssi_soc_data { |
| 199 | bool imx; |
| 200 | bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ |
| 201 | bool offline_config; |
| 202 | u32 sisr_write_mask; |
| 203 | }; |
| 204 | |
| 205 | /** |
| 206 | * fsl_ssi: per-SSI private data |
| 207 | * |
| 208 | * @regs: Pointer to the regmap registers |
| 209 | * @irq: IRQ of this SSI |
| 210 | * @cpu_dai_drv: CPU DAI driver for this device |
| 211 | * |
| 212 | * @dai_fmt: DAI configuration this device is currently used with |
| 213 | * @streams: Mask of current active streams: BIT(TX) and BIT(RX) |
| 214 | * @i2s_net: I2S and Network mode configurations of SCR register |
| 215 | * (this is the initial settings based on the DAI format) |
| 216 | * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK |
| 217 | * @use_dma: DMA is used or FIQ with stream filter |
| 218 | * @use_dual_fifo: DMA with support for dual FIFO mode |
| 219 | * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree |
| 220 | * @fifo_depth: Depth of the SSI FIFOs |
| 221 | * @slot_width: Width of each DAI slot |
| 222 | * @slots: Number of slots |
| 223 | * @regvals: Specific RX/TX register settings |
| 224 | * |
| 225 | * @clk: Clock source to access register |
| 226 | * @baudclk: Clock source to generate bit and frame-sync clocks |
| 227 | * @baudclk_streams: Active streams that are using baudclk |
| 228 | * |
| 229 | * @regcache_sfcsr: Cache sfcsr register value during suspend and resume |
| 230 | * @regcache_sacnt: Cache sacnt register value during suspend and resume |
| 231 | * |
| 232 | * @dma_params_tx: DMA transmit parameters |
| 233 | * @dma_params_rx: DMA receive parameters |
| 234 | * @ssi_phys: physical address of the SSI registers |
| 235 | * |
| 236 | * @fiq_params: FIQ stream filtering parameters |
| 237 | * |
| 238 | * @card_pdev: Platform_device pointer to register a sound card for PowerPC or |
| 239 | * to register a CODEC platform device for AC97 |
| 240 | * @card_name: Platform_device name to register a sound card for PowerPC or |
| 241 | * to register a CODEC platform device for AC97 |
| 242 | * @card_idx: The index of SSI to register a sound card for PowerPC or |
| 243 | * to register a CODEC platform device for AC97 |
| 244 | * |
| 245 | * @dbg_stats: Debugging statistics |
| 246 | * |
| 247 | * @soc: SoC specific data |
| 248 | * @dev: Pointer to &pdev->dev |
| 249 | * |
| 250 | * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are |
| 251 | * @fifo_watermark or fewer words in TX fifo or |
| 252 | * @fifo_watermark or more empty words in RX fifo. |
| 253 | * @dma_maxburst: Max number of words to transfer in one go. So far, |
| 254 | * this is always the same as fifo_watermark. |
| 255 | * |
| 256 | * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations |
| 257 | */ |
| 258 | struct fsl_ssi { |
| 259 | struct regmap *regs; |
| 260 | int irq; |
| 261 | struct snd_soc_dai_driver cpu_dai_drv; |
| 262 | |
| 263 | unsigned int dai_fmt; |
| 264 | u8 streams; |
| 265 | u8 i2s_net; |
| 266 | bool synchronous; |
| 267 | bool use_dma; |
| 268 | bool use_dual_fifo; |
| 269 | bool has_ipg_clk_name; |
| 270 | unsigned int fifo_depth; |
| 271 | unsigned int slot_width; |
| 272 | unsigned int slots; |
| 273 | struct fsl_ssi_regvals regvals[2]; |
| 274 | |
| 275 | struct clk *clk; |
| 276 | struct clk *baudclk; |
| 277 | unsigned int baudclk_streams; |
| 278 | |
| 279 | u32 regcache_sfcsr; |
| 280 | u32 regcache_sacnt; |
| 281 | |
| 282 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
| 283 | struct snd_dmaengine_dai_dma_data dma_params_rx; |
| 284 | dma_addr_t ssi_phys; |
| 285 | |
| 286 | struct imx_pcm_fiq_params fiq_params; |
| 287 | |
| 288 | struct platform_device *card_pdev; |
| 289 | char card_name[32]; |
| 290 | u32 card_idx; |
| 291 | |
| 292 | struct fsl_ssi_dbg dbg_stats; |
| 293 | |
| 294 | const struct fsl_ssi_soc_data *soc; |
| 295 | struct device *dev; |
| 296 | |
| 297 | u32 fifo_watermark; |
| 298 | u32 dma_maxburst; |
| 299 | |
| 300 | struct mutex ac97_reg_lock; |
| 301 | }; |
| 302 | |
| 303 | /* |
| 304 | * SoC specific data |
| 305 | * |
| 306 | * Notes: |
| 307 | * 1) SSI in earlier SoCS has critical bits in control registers that |
| 308 | * cannot be changed after SSI starts running -- a software reset |
| 309 | * (set SSIEN to 0) is required to change their values. So adding |
| 310 | * an offline_config flag for these SoCs. |
| 311 | * 2) SDMA is available since imx35. However, imx35 does not support |
| 312 | * DMA bits changing when SSI is running, so set offline_config. |
| 313 | * 3) imx51 and later versions support register configurations when |
| 314 | * SSI is running (SSIEN); For these versions, DMA needs to be |
| 315 | * configured before SSI sends DMA request to avoid an undefined |
| 316 | * DMA request on the SDMA side. |
| 317 | */ |
| 318 | |
| 319 | static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { |
| 320 | .imx = false, |
| 321 | .offline_config = true, |
| 322 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
| 323 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
| 324 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
| 325 | }; |
| 326 | |
| 327 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { |
| 328 | .imx = true, |
| 329 | .imx21regs = true, |
| 330 | .offline_config = true, |
| 331 | .sisr_write_mask = 0, |
| 332 | }; |
| 333 | |
| 334 | static struct fsl_ssi_soc_data fsl_ssi_imx35 = { |
| 335 | .imx = true, |
| 336 | .offline_config = true, |
| 337 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
| 338 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
| 339 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
| 340 | }; |
| 341 | |
| 342 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { |
| 343 | .imx = true, |
| 344 | .offline_config = false, |
| 345 | .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
| 346 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
| 347 | }; |
| 348 | |
| 349 | static const struct of_device_id fsl_ssi_ids[] = { |
| 350 | { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, |
| 351 | { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, |
| 352 | { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, |
| 353 | { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, |
| 354 | {} |
| 355 | }; |
| 356 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); |
| 357 | |
| 358 | static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) |
| 359 | { |
| 360 | return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == |
| 361 | SND_SOC_DAIFMT_AC97; |
| 362 | } |
| 363 | |
| 364 | static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi) |
| 365 | { |
| 366 | return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == |
| 367 | SND_SOC_DAIFMT_CBS_CFS; |
| 368 | } |
| 369 | |
| 370 | static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi) |
| 371 | { |
| 372 | return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == |
| 373 | SND_SOC_DAIFMT_CBM_CFS; |
| 374 | } |
| 375 | |
| 376 | /** |
| 377 | * Interrupt handler to gather states |
| 378 | */ |
| 379 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) |
| 380 | { |
| 381 | struct fsl_ssi *ssi = dev_id; |
| 382 | struct regmap *regs = ssi->regs; |
| 383 | u32 sisr, sisr2; |
| 384 | |
| 385 | regmap_read(regs, REG_SSI_SISR, &sisr); |
| 386 | |
| 387 | sisr2 = sisr & ssi->soc->sisr_write_mask; |
| 388 | /* Clear the bits that we set */ |
| 389 | if (sisr2) |
| 390 | regmap_write(regs, REG_SSI_SISR, sisr2); |
| 391 | |
| 392 | fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); |
| 393 | |
| 394 | return IRQ_HANDLED; |
| 395 | } |
| 396 | |
| 397 | /** |
| 398 | * Set SCR, SIER, STCR and SRCR registers with cached values in regvals |
| 399 | * |
| 400 | * Notes: |
| 401 | * 1) For offline_config SoCs, enable all necessary bits of both streams |
| 402 | * when 1st stream starts, even if the opposite stream will not start |
| 403 | * 2) It also clears FIFO before setting regvals; SOR is safe to set online |
| 404 | */ |
| 405 | static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx) |
| 406 | { |
| 407 | struct fsl_ssi_regvals *vals = ssi->regvals; |
| 408 | int dir = tx ? TX : RX; |
| 409 | u32 sier, srcr, stcr; |
| 410 | |
| 411 | /* Clear dirty data in the FIFO; It also prevents channel slipping */ |
| 412 | regmap_update_bits(ssi->regs, REG_SSI_SOR, |
| 413 | SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); |
| 414 | |
| 415 | /* |
| 416 | * On offline_config SoCs, SxCR and SIER are already configured when |
| 417 | * the previous stream started. So skip all SxCR and SIER settings |
| 418 | * to prevent online reconfigurations, then jump to set SCR directly |
| 419 | */ |
| 420 | if (ssi->soc->offline_config && ssi->streams) |
| 421 | goto enable_scr; |
| 422 | |
| 423 | if (ssi->soc->offline_config) { |
| 424 | /* |
| 425 | * Online reconfiguration not supported, so enable all bits for |
| 426 | * both streams at once to avoid necessity of reconfigurations |
| 427 | */ |
| 428 | srcr = vals[RX].srcr | vals[TX].srcr; |
| 429 | stcr = vals[RX].stcr | vals[TX].stcr; |
| 430 | sier = vals[RX].sier | vals[TX].sier; |
| 431 | } else { |
| 432 | /* Otherwise, only set bits for the current stream */ |
| 433 | srcr = vals[dir].srcr; |
| 434 | stcr = vals[dir].stcr; |
| 435 | sier = vals[dir].sier; |
| 436 | } |
| 437 | |
| 438 | /* Configure SRCR, STCR and SIER at once */ |
| 439 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr); |
| 440 | regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr); |
| 441 | regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier); |
| 442 | |
| 443 | enable_scr: |
| 444 | /* |
| 445 | * Start DMA before setting TE to avoid FIFO underrun |
| 446 | * which may cause a channel slip or a channel swap |
| 447 | * |
| 448 | * TODO: FIQ cases might also need this upon testing |
| 449 | */ |
| 450 | if (ssi->use_dma && tx) { |
| 451 | int try = 100; |
| 452 | u32 sfcsr; |
| 453 | |
| 454 | /* Enable SSI first to send TX DMA request */ |
| 455 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 456 | SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
| 457 | |
| 458 | /* Busy wait until TX FIFO not empty -- DMA working */ |
| 459 | do { |
| 460 | regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr); |
| 461 | if (SSI_SFCSR_TFCNT0(sfcsr)) |
| 462 | break; |
| 463 | } while (--try); |
| 464 | |
| 465 | /* FIFO still empty -- something might be wrong */ |
| 466 | if (!SSI_SFCSR_TFCNT0(sfcsr)) |
| 467 | dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n"); |
| 468 | } |
| 469 | /* Enable all remaining bits in SCR */ |
| 470 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 471 | vals[dir].scr, vals[dir].scr); |
| 472 | |
| 473 | /* Log the enabled stream to the mask */ |
| 474 | ssi->streams |= BIT(dir); |
| 475 | } |
| 476 | |
| 477 | /** |
| 478 | * Exclude bits that are used by the opposite stream |
| 479 | * |
| 480 | * When both streams are active, disabling some bits for the current stream |
| 481 | * might break the other stream if these bits are used by it. |
| 482 | * |
| 483 | * @vals : regvals of the current stream |
| 484 | * @avals: regvals of the opposite stream |
| 485 | * @aactive: active state of the opposite stream |
| 486 | * |
| 487 | * 1) XOR vals and avals to get the differences if the other stream is active; |
| 488 | * Otherwise, return current vals if the other stream is not active |
| 489 | * 2) AND the result of 1) with the current vals |
| 490 | */ |
| 491 | #define _ssi_xor_shared_bits(vals, avals, aactive) \ |
| 492 | ((vals) ^ ((avals) * (aactive))) |
| 493 | |
| 494 | #define ssi_excl_shared_bits(vals, avals, aactive) \ |
| 495 | ((vals) & _ssi_xor_shared_bits(vals, avals, aactive)) |
| 496 | |
| 497 | /** |
| 498 | * Unset SCR, SIER, STCR and SRCR registers with cached values in regvals |
| 499 | * |
| 500 | * Notes: |
| 501 | * 1) For offline_config SoCs, to avoid online reconfigurations, disable all |
| 502 | * bits of both streams at once when the last stream is abort to end |
| 503 | * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online |
| 504 | */ |
| 505 | static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx) |
| 506 | { |
| 507 | struct fsl_ssi_regvals *vals, *avals; |
| 508 | u32 sier, srcr, stcr, scr; |
| 509 | int adir = tx ? RX : TX; |
| 510 | int dir = tx ? TX : RX; |
| 511 | bool aactive; |
| 512 | |
| 513 | /* Check if the opposite stream is active */ |
| 514 | aactive = ssi->streams & BIT(adir); |
| 515 | |
| 516 | vals = &ssi->regvals[dir]; |
| 517 | |
| 518 | /* Get regvals of the opposite stream to keep opposite stream safe */ |
| 519 | avals = &ssi->regvals[adir]; |
| 520 | |
| 521 | /* |
| 522 | * To keep the other stream safe, exclude shared bits between |
| 523 | * both streams, and get safe bits to disable current stream |
| 524 | */ |
| 525 | scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive); |
| 526 | |
| 527 | /* Disable safe bits of SCR register for the current stream */ |
| 528 | regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0); |
| 529 | |
| 530 | /* Log the disabled stream to the mask */ |
| 531 | ssi->streams &= ~BIT(dir); |
| 532 | |
| 533 | /* |
| 534 | * On offline_config SoCs, if the other stream is active, skip |
| 535 | * SxCR and SIER settings to prevent online reconfigurations |
| 536 | */ |
| 537 | if (ssi->soc->offline_config && aactive) |
| 538 | goto fifo_clear; |
| 539 | |
| 540 | if (ssi->soc->offline_config) { |
| 541 | /* Now there is only current stream active, disable all bits */ |
| 542 | srcr = vals->srcr | avals->srcr; |
| 543 | stcr = vals->stcr | avals->stcr; |
| 544 | sier = vals->sier | avals->sier; |
| 545 | } else { |
| 546 | /* |
| 547 | * To keep the other stream safe, exclude shared bits between |
| 548 | * both streams, and get safe bits to disable current stream |
| 549 | */ |
| 550 | sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive); |
| 551 | srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive); |
| 552 | stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive); |
| 553 | } |
| 554 | |
| 555 | /* Clear configurations of SRCR, STCR and SIER at once */ |
| 556 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0); |
| 557 | regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0); |
| 558 | regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0); |
| 559 | |
| 560 | fifo_clear: |
| 561 | /* Clear remaining data in the FIFO */ |
| 562 | regmap_update_bits(ssi->regs, REG_SSI_SOR, |
| 563 | SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); |
| 564 | } |
| 565 | |
| 566 | static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) |
| 567 | { |
| 568 | struct regmap *regs = ssi->regs; |
| 569 | |
| 570 | /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ |
| 571 | if (!ssi->soc->imx21regs) { |
| 572 | /* Disable all channel slots */ |
| 573 | regmap_write(regs, REG_SSI_SACCDIS, 0xff); |
| 574 | /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ |
| 575 | regmap_write(regs, REG_SSI_SACCEN, 0x300); |
| 576 | } |
| 577 | } |
| 578 | |
| 579 | /** |
| 580 | * Cache critical bits of SIER, SRCR, STCR and SCR to later set them safely |
| 581 | */ |
| 582 | static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) |
| 583 | { |
| 584 | struct fsl_ssi_regvals *vals = ssi->regvals; |
| 585 | |
| 586 | vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS; |
| 587 | vals[RX].srcr = SSI_SRCR_RFEN0; |
| 588 | vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE; |
| 589 | vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; |
| 590 | vals[TX].stcr = SSI_STCR_TFEN0; |
| 591 | vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; |
| 592 | |
| 593 | /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ |
| 594 | if (fsl_ssi_is_ac97(ssi)) |
| 595 | vals[RX].scr = vals[TX].scr = 0; |
| 596 | |
| 597 | if (ssi->use_dual_fifo) { |
| 598 | vals[RX].srcr |= SSI_SRCR_RFEN1; |
| 599 | vals[TX].stcr |= SSI_STCR_TFEN1; |
| 600 | } |
| 601 | |
| 602 | if (ssi->use_dma) { |
| 603 | vals[RX].sier |= SSI_SIER_RDMAE; |
| 604 | vals[TX].sier |= SSI_SIER_TDMAE; |
| 605 | } else { |
| 606 | vals[RX].sier |= SSI_SIER_RIE; |
| 607 | vals[TX].sier |= SSI_SIER_TIE; |
| 608 | } |
| 609 | } |
| 610 | |
| 611 | static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) |
| 612 | { |
| 613 | struct regmap *regs = ssi->regs; |
| 614 | |
| 615 | /* Setup the clock control register */ |
| 616 | regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
| 617 | regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
| 618 | |
| 619 | /* Enable AC97 mode and startup the SSI */ |
| 620 | regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); |
| 621 | |
| 622 | /* AC97 has to communicate with codec before starting a stream */ |
| 623 | regmap_update_bits(regs, REG_SSI_SCR, |
| 624 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, |
| 625 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); |
| 626 | |
| 627 | regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); |
| 628 | } |
| 629 | |
| 630 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
| 631 | struct snd_soc_dai *dai) |
| 632 | { |
| 633 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 634 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 635 | int ret; |
| 636 | |
| 637 | ret = clk_prepare_enable(ssi->clk); |
| 638 | if (ret) |
| 639 | return ret; |
| 640 | |
| 641 | /* |
| 642 | * When using dual fifo mode, it is safer to ensure an even period |
| 643 | * size. If appearing to an odd number while DMA always starts its |
| 644 | * task from fifo0, fifo1 would be neglected at the end of each |
| 645 | * period. But SSI would still access fifo1 with an invalid data. |
| 646 | */ |
| 647 | if (ssi->use_dual_fifo) |
| 648 | snd_pcm_hw_constraint_step(substream->runtime, 0, |
| 649 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); |
| 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
| 654 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
| 655 | struct snd_soc_dai *dai) |
| 656 | { |
| 657 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 658 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 659 | |
| 660 | clk_disable_unprepare(ssi->clk); |
| 661 | } |
| 662 | |
| 663 | /** |
| 664 | * Configure Digital Audio Interface bit clock |
| 665 | * |
| 666 | * Note: This function can be only called when using SSI as DAI master |
| 667 | * |
| 668 | * Quick instruction for parameters: |
| 669 | * freq: Output BCLK frequency = samplerate * slots * slot_width |
| 670 | * (In 2-channel I2S Master mode, slot_width is fixed 32) |
| 671 | */ |
| 672 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
| 673 | struct snd_soc_dai *dai, |
| 674 | struct snd_pcm_hw_params *hw_params) |
| 675 | { |
| 676 | bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
| 677 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
| 678 | struct regmap *regs = ssi->regs; |
| 679 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; |
| 680 | unsigned long clkrate, baudrate, tmprate; |
| 681 | unsigned int slots = params_channels(hw_params); |
| 682 | unsigned int slot_width = 32; |
| 683 | u64 sub, savesub = 100000; |
| 684 | unsigned int freq; |
| 685 | bool baudclk_is_used; |
| 686 | int ret; |
| 687 | |
| 688 | /* Override slots and slot_width if being specifically set... */ |
| 689 | if (ssi->slots) |
| 690 | slots = ssi->slots; |
| 691 | /* ...but keep 32 bits if slots is 2 -- I2S Master mode */ |
| 692 | if (ssi->slot_width && slots != 2) |
| 693 | slot_width = ssi->slot_width; |
| 694 | |
| 695 | /* Generate bit clock based on the slot number and slot width */ |
| 696 | freq = slots * slot_width * params_rate(hw_params); |
| 697 | |
| 698 | /* Don't apply it to any non-baudclk circumstance */ |
| 699 | if (IS_ERR(ssi->baudclk)) |
| 700 | return -EINVAL; |
| 701 | |
| 702 | /* |
| 703 | * Hardware limitation: The bclk rate must be |
| 704 | * never greater than 1/5 IPG clock rate |
| 705 | */ |
| 706 | if (freq * 5 > clk_get_rate(ssi->clk)) { |
| 707 | dev_err(dai->dev, "bitclk > ipgclk / 5\n"); |
| 708 | return -EINVAL; |
| 709 | } |
| 710 | |
| 711 | baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); |
| 712 | |
| 713 | /* It should be already enough to divide clock by setting pm alone */ |
| 714 | psr = 0; |
| 715 | div2 = 0; |
| 716 | |
| 717 | factor = (div2 + 1) * (7 * psr + 1) * 2; |
| 718 | |
| 719 | for (i = 0; i < 255; i++) { |
| 720 | tmprate = freq * factor * (i + 1); |
| 721 | |
| 722 | if (baudclk_is_used) |
| 723 | clkrate = clk_get_rate(ssi->baudclk); |
| 724 | else |
| 725 | clkrate = clk_round_rate(ssi->baudclk, tmprate); |
| 726 | |
| 727 | clkrate /= factor; |
| 728 | afreq = clkrate / (i + 1); |
| 729 | |
| 730 | if (freq == afreq) |
| 731 | sub = 0; |
| 732 | else if (freq / afreq == 1) |
| 733 | sub = freq - afreq; |
| 734 | else if (afreq / freq == 1) |
| 735 | sub = afreq - freq; |
| 736 | else |
| 737 | continue; |
| 738 | |
| 739 | /* Calculate the fraction */ |
| 740 | sub *= 100000; |
| 741 | do_div(sub, freq); |
| 742 | |
| 743 | if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { |
| 744 | baudrate = tmprate; |
| 745 | savesub = sub; |
| 746 | pm = i; |
| 747 | } |
| 748 | |
| 749 | /* We are lucky */ |
| 750 | if (savesub == 0) |
| 751 | break; |
| 752 | } |
| 753 | |
| 754 | /* No proper pm found if it is still remaining the initial value */ |
| 755 | if (pm == 999) { |
| 756 | dev_err(dai->dev, "failed to handle the required sysclk\n"); |
| 757 | return -EINVAL; |
| 758 | } |
| 759 | |
| 760 | stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | |
| 761 | (psr ? SSI_SxCCR_PSR : 0); |
| 762 | mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; |
| 763 | |
| 764 | /* STCCR is used for RX in synchronous mode */ |
| 765 | tx2 = tx || ssi->synchronous; |
| 766 | regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); |
| 767 | |
| 768 | if (!baudclk_is_used) { |
| 769 | ret = clk_set_rate(ssi->baudclk, baudrate); |
| 770 | if (ret) { |
| 771 | dev_err(dai->dev, "failed to set baudclk rate\n"); |
| 772 | return -EINVAL; |
| 773 | } |
| 774 | } |
| 775 | |
| 776 | return 0; |
| 777 | } |
| 778 | |
| 779 | /** |
| 780 | * Configure SSI based on PCM hardware parameters |
| 781 | * |
| 782 | * Notes: |
| 783 | * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily |
| 784 | * disabled on offline_config SoCs. Even for online configurable SoCs |
| 785 | * running in synchronous mode (both TX and RX use STCCR), it is not |
| 786 | * safe to re-configure them when both two streams start running. |
| 787 | * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the |
| 788 | * fsl_ssi_set_bclk() if SSI is the DAI clock master. |
| 789 | */ |
| 790 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
| 791 | struct snd_pcm_hw_params *hw_params, |
| 792 | struct snd_soc_dai *dai) |
| 793 | { |
| 794 | bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
| 795 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
| 796 | struct regmap *regs = ssi->regs; |
| 797 | unsigned int channels = params_channels(hw_params); |
| 798 | unsigned int sample_size = params_width(hw_params); |
| 799 | u32 wl = SSI_SxCCR_WL(sample_size); |
| 800 | int ret; |
| 801 | |
| 802 | /* |
| 803 | * SSI is properly configured if it is enabled and running in |
| 804 | * the synchronous mode; Note that AC97 mode is an exception |
| 805 | * that should set separate configurations for STCCR and SRCCR |
| 806 | * despite running in the synchronous mode. |
| 807 | */ |
| 808 | if (ssi->streams && ssi->synchronous) |
| 809 | return 0; |
| 810 | |
| 811 | if (fsl_ssi_is_i2s_master(ssi)) { |
| 812 | ret = fsl_ssi_set_bclk(substream, dai, hw_params); |
| 813 | if (ret) |
| 814 | return ret; |
| 815 | |
| 816 | /* Do not enable the clock if it is already enabled */ |
| 817 | if (!(ssi->baudclk_streams & BIT(substream->stream))) { |
| 818 | ret = clk_prepare_enable(ssi->baudclk); |
| 819 | if (ret) |
| 820 | return ret; |
| 821 | |
| 822 | ssi->baudclk_streams |= BIT(substream->stream); |
| 823 | } |
| 824 | } |
| 825 | |
| 826 | if (!fsl_ssi_is_ac97(ssi)) { |
| 827 | /* |
| 828 | * Keep the ssi->i2s_net intact while having a local variable |
| 829 | * to override settings for special use cases. Otherwise, the |
| 830 | * ssi->i2s_net will lose the settings for regular use cases. |
| 831 | */ |
| 832 | u8 i2s_net = ssi->i2s_net; |
| 833 | |
| 834 | /* Normal + Network mode to send 16-bit data in 32-bit frames */ |
| 835 | if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) |
| 836 | i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; |
| 837 | |
| 838 | /* Use Normal mode to send mono data at 1st slot of 2 slots */ |
| 839 | if (channels == 1) |
| 840 | i2s_net = SSI_SCR_I2S_MODE_NORMAL; |
| 841 | |
| 842 | regmap_update_bits(regs, REG_SSI_SCR, |
| 843 | SSI_SCR_I2S_NET_MASK, i2s_net); |
| 844 | } |
| 845 | |
| 846 | /* In synchronous mode, the SSI uses STCCR for capture */ |
| 847 | tx2 = tx || ssi->synchronous; |
| 848 | regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); |
| 849 | |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, |
| 854 | struct snd_soc_dai *dai) |
| 855 | { |
| 856 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 857 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 858 | |
| 859 | if (fsl_ssi_is_i2s_master(ssi) && |
| 860 | ssi->baudclk_streams & BIT(substream->stream)) { |
| 861 | clk_disable_unprepare(ssi->baudclk); |
| 862 | ssi->baudclk_streams &= ~BIT(substream->stream); |
| 863 | } |
| 864 | |
| 865 | return 0; |
| 866 | } |
| 867 | |
| 868 | static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) |
| 869 | { |
| 870 | u32 strcr = 0, scr = 0, stcr, srcr, mask; |
| 871 | |
| 872 | ssi->dai_fmt = fmt; |
| 873 | |
| 874 | /* Synchronize frame sync clock for TE to avoid data slipping */ |
| 875 | scr |= SSI_SCR_SYNC_TX_FS; |
| 876 | |
| 877 | /* Set to default shifting settings: LSB_ALIGNED */ |
| 878 | strcr |= SSI_STCR_TXBIT0; |
| 879 | |
| 880 | /* Use Network mode as default */ |
| 881 | ssi->i2s_net = SSI_SCR_NET; |
| 882 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 883 | case SND_SOC_DAIFMT_I2S: |
| 884 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 885 | case SND_SOC_DAIFMT_CBS_CFS: |
| 886 | if (IS_ERR(ssi->baudclk)) { |
| 887 | dev_err(ssi->dev, |
| 888 | "missing baudclk for master mode\n"); |
| 889 | return -EINVAL; |
| 890 | } |
| 891 | /* fall through */ |
| 892 | case SND_SOC_DAIFMT_CBM_CFS: |
| 893 | ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER; |
| 894 | break; |
| 895 | case SND_SOC_DAIFMT_CBM_CFM: |
| 896 | ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE; |
| 897 | break; |
| 898 | default: |
| 899 | return -EINVAL; |
| 900 | } |
| 901 | |
| 902 | regmap_update_bits(ssi->regs, REG_SSI_STCCR, |
| 903 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); |
| 904 | regmap_update_bits(ssi->regs, REG_SSI_SRCCR, |
| 905 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); |
| 906 | |
| 907 | /* Data on rising edge of bclk, frame low, 1clk before data */ |
| 908 | strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS; |
| 909 | break; |
| 910 | case SND_SOC_DAIFMT_LEFT_J: |
| 911 | /* Data on rising edge of bclk, frame high */ |
| 912 | strcr |= SSI_STCR_TSCKP; |
| 913 | break; |
| 914 | case SND_SOC_DAIFMT_DSP_A: |
| 915 | /* Data on rising edge of bclk, frame high, 1clk before data */ |
| 916 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS; |
| 917 | break; |
| 918 | case SND_SOC_DAIFMT_DSP_B: |
| 919 | /* Data on rising edge of bclk, frame high */ |
| 920 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP; |
| 921 | break; |
| 922 | case SND_SOC_DAIFMT_AC97: |
| 923 | /* Data on falling edge of bclk, frame high, 1clk before data */ |
| 924 | strcr |= SSI_STCR_TEFS; |
| 925 | break; |
| 926 | default: |
| 927 | return -EINVAL; |
| 928 | } |
| 929 | |
| 930 | scr |= ssi->i2s_net; |
| 931 | |
| 932 | /* DAI clock inversion */ |
| 933 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 934 | case SND_SOC_DAIFMT_NB_NF: |
| 935 | /* Nothing to do for both normal cases */ |
| 936 | break; |
| 937 | case SND_SOC_DAIFMT_IB_NF: |
| 938 | /* Invert bit clock */ |
| 939 | strcr ^= SSI_STCR_TSCKP; |
| 940 | break; |
| 941 | case SND_SOC_DAIFMT_NB_IF: |
| 942 | /* Invert frame clock */ |
| 943 | strcr ^= SSI_STCR_TFSI; |
| 944 | break; |
| 945 | case SND_SOC_DAIFMT_IB_IF: |
| 946 | /* Invert both clocks */ |
| 947 | strcr ^= SSI_STCR_TSCKP; |
| 948 | strcr ^= SSI_STCR_TFSI; |
| 949 | break; |
| 950 | default: |
| 951 | return -EINVAL; |
| 952 | } |
| 953 | |
| 954 | /* DAI clock master masks */ |
| 955 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 956 | case SND_SOC_DAIFMT_CBS_CFS: |
| 957 | /* Output bit and frame sync clocks */ |
| 958 | strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; |
| 959 | scr |= SSI_SCR_SYS_CLK_EN; |
| 960 | break; |
| 961 | case SND_SOC_DAIFMT_CBM_CFM: |
| 962 | /* Input bit or frame sync clocks */ |
| 963 | break; |
| 964 | case SND_SOC_DAIFMT_CBM_CFS: |
| 965 | /* Input bit clock but output frame sync clock */ |
| 966 | strcr |= SSI_STCR_TFDIR; |
| 967 | break; |
| 968 | default: |
| 969 | return -EINVAL; |
| 970 | } |
| 971 | |
| 972 | stcr = strcr; |
| 973 | srcr = strcr; |
| 974 | |
| 975 | /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ |
| 976 | if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) { |
| 977 | srcr &= ~SSI_SRCR_RXDIR; |
| 978 | scr |= SSI_SCR_SYN; |
| 979 | } |
| 980 | |
| 981 | mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP | |
| 982 | SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; |
| 983 | |
| 984 | regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr); |
| 985 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr); |
| 986 | |
| 987 | mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK | |
| 988 | SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN; |
| 989 | regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr); |
| 990 | |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | /** |
| 995 | * Configure Digital Audio Interface (DAI) Format |
| 996 | */ |
| 997 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 998 | { |
| 999 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
| 1000 | |
| 1001 | /* AC97 configured DAIFMT earlier in the probe() */ |
| 1002 | if (fsl_ssi_is_ac97(ssi)) |
| 1003 | return 0; |
| 1004 | |
| 1005 | return _fsl_ssi_set_dai_fmt(ssi, fmt); |
| 1006 | } |
| 1007 | |
| 1008 | /** |
| 1009 | * Set TDM slot number and slot width |
| 1010 | */ |
| 1011 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, |
| 1012 | u32 rx_mask, int slots, int slot_width) |
| 1013 | { |
| 1014 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
| 1015 | struct regmap *regs = ssi->regs; |
| 1016 | u32 val; |
| 1017 | |
| 1018 | /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ |
| 1019 | if (slot_width & 1 || slot_width < 8 || slot_width > 24) { |
| 1020 | dev_err(dai->dev, "invalid slot width: %d\n", slot_width); |
| 1021 | return -EINVAL; |
| 1022 | } |
| 1023 | |
| 1024 | /* The slot number should be >= 2 if using Network mode or I2S mode */ |
| 1025 | if (ssi->i2s_net && slots < 2) { |
| 1026 | dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n"); |
| 1027 | return -EINVAL; |
| 1028 | } |
| 1029 | |
| 1030 | regmap_update_bits(regs, REG_SSI_STCCR, |
| 1031 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
| 1032 | regmap_update_bits(regs, REG_SSI_SRCCR, |
| 1033 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
| 1034 | |
| 1035 | /* Save the SCR register value */ |
| 1036 | regmap_read(regs, REG_SSI_SCR, &val); |
| 1037 | /* Temporarily enable SSI to allow SxMSKs to be configurable */ |
| 1038 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
| 1039 | |
| 1040 | regmap_write(regs, REG_SSI_STMSK, ~tx_mask); |
| 1041 | regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); |
| 1042 | |
| 1043 | /* Restore the value of SSIEN bit */ |
| 1044 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); |
| 1045 | |
| 1046 | ssi->slot_width = slot_width; |
| 1047 | ssi->slots = slots; |
| 1048 | |
| 1049 | return 0; |
| 1050 | } |
| 1051 | |
| 1052 | /** |
| 1053 | * Start or stop SSI and corresponding DMA transaction. |
| 1054 | * |
| 1055 | * The DMA channel is in external master start and pause mode, which |
| 1056 | * means the SSI completely controls the flow of data. |
| 1057 | */ |
| 1058 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
| 1059 | struct snd_soc_dai *dai) |
| 1060 | { |
| 1061 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 1062 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 1063 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
| 1064 | |
| 1065 | switch (cmd) { |
| 1066 | case SNDRV_PCM_TRIGGER_START: |
| 1067 | case SNDRV_PCM_TRIGGER_RESUME: |
| 1068 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 1069 | /* |
| 1070 | * SACCST might be modified via AC Link by a CODEC if it sends |
| 1071 | * extra bits in their SLOTREQ requests, which'll accidentally |
| 1072 | * send valid data to slots other than normal playback slots. |
| 1073 | * |
| 1074 | * To be safe, configure SACCST right before TX starts. |
| 1075 | */ |
| 1076 | if (tx && fsl_ssi_is_ac97(ssi)) |
| 1077 | fsl_ssi_tx_ac97_saccst_setup(ssi); |
| 1078 | fsl_ssi_config_enable(ssi, tx); |
| 1079 | break; |
| 1080 | |
| 1081 | case SNDRV_PCM_TRIGGER_STOP: |
| 1082 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 1083 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 1084 | fsl_ssi_config_disable(ssi, tx); |
| 1085 | break; |
| 1086 | |
| 1087 | default: |
| 1088 | return -EINVAL; |
| 1089 | } |
| 1090 | |
| 1091 | return 0; |
| 1092 | } |
| 1093 | |
| 1094 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
| 1095 | { |
| 1096 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
| 1097 | |
| 1098 | if (ssi->soc->imx && ssi->use_dma) |
| 1099 | snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx, |
| 1100 | &ssi->dma_params_rx); |
| 1101 | |
| 1102 | return 0; |
| 1103 | } |
| 1104 | |
| 1105 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
| 1106 | .startup = fsl_ssi_startup, |
| 1107 | .shutdown = fsl_ssi_shutdown, |
| 1108 | .hw_params = fsl_ssi_hw_params, |
| 1109 | .hw_free = fsl_ssi_hw_free, |
| 1110 | .set_fmt = fsl_ssi_set_dai_fmt, |
| 1111 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, |
| 1112 | .trigger = fsl_ssi_trigger, |
| 1113 | }; |
| 1114 | |
| 1115 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { |
| 1116 | .probe = fsl_ssi_dai_probe, |
| 1117 | .playback = { |
| 1118 | .stream_name = "CPU-Playback", |
| 1119 | .channels_min = 1, |
| 1120 | .channels_max = 32, |
| 1121 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
| 1122 | .formats = FSLSSI_I2S_FORMATS, |
| 1123 | }, |
| 1124 | .capture = { |
| 1125 | .stream_name = "CPU-Capture", |
| 1126 | .channels_min = 1, |
| 1127 | .channels_max = 32, |
| 1128 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
| 1129 | .formats = FSLSSI_I2S_FORMATS, |
| 1130 | }, |
| 1131 | .ops = &fsl_ssi_dai_ops, |
| 1132 | }; |
| 1133 | |
| 1134 | static const struct snd_soc_component_driver fsl_ssi_component = { |
| 1135 | .name = "fsl-ssi", |
| 1136 | }; |
| 1137 | |
| 1138 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
| 1139 | .bus_control = true, |
| 1140 | .symmetric_channels = 1, |
| 1141 | .probe = fsl_ssi_dai_probe, |
| 1142 | .playback = { |
| 1143 | .stream_name = "AC97 Playback", |
| 1144 | .channels_min = 2, |
| 1145 | .channels_max = 2, |
| 1146 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 1147 | .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20, |
| 1148 | }, |
| 1149 | .capture = { |
| 1150 | .stream_name = "AC97 Capture", |
| 1151 | .channels_min = 2, |
| 1152 | .channels_max = 2, |
| 1153 | .rates = SNDRV_PCM_RATE_48000, |
| 1154 | /* 16-bit capture is broken (errata ERR003778) */ |
| 1155 | .formats = SNDRV_PCM_FMTBIT_S20, |
| 1156 | }, |
| 1157 | .ops = &fsl_ssi_dai_ops, |
| 1158 | }; |
| 1159 | |
| 1160 | static struct fsl_ssi *fsl_ac97_data; |
| 1161 | |
| 1162 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
| 1163 | unsigned short val) |
| 1164 | { |
| 1165 | struct regmap *regs = fsl_ac97_data->regs; |
| 1166 | unsigned int lreg; |
| 1167 | unsigned int lval; |
| 1168 | int ret; |
| 1169 | |
| 1170 | if (reg > 0x7f) |
| 1171 | return; |
| 1172 | |
| 1173 | mutex_lock(&fsl_ac97_data->ac97_reg_lock); |
| 1174 | |
| 1175 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
| 1176 | if (ret) { |
| 1177 | pr_err("ac97 write clk_prepare_enable failed: %d\n", |
| 1178 | ret); |
| 1179 | goto ret_unlock; |
| 1180 | } |
| 1181 | |
| 1182 | lreg = reg << 12; |
| 1183 | regmap_write(regs, REG_SSI_SACADD, lreg); |
| 1184 | |
| 1185 | lval = val << 4; |
| 1186 | regmap_write(regs, REG_SSI_SACDAT, lval); |
| 1187 | |
| 1188 | regmap_update_bits(regs, REG_SSI_SACNT, |
| 1189 | SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); |
| 1190 | udelay(100); |
| 1191 | |
| 1192 | clk_disable_unprepare(fsl_ac97_data->clk); |
| 1193 | |
| 1194 | ret_unlock: |
| 1195 | mutex_unlock(&fsl_ac97_data->ac97_reg_lock); |
| 1196 | } |
| 1197 | |
| 1198 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
| 1199 | unsigned short reg) |
| 1200 | { |
| 1201 | struct regmap *regs = fsl_ac97_data->regs; |
| 1202 | unsigned short val = 0; |
| 1203 | u32 reg_val; |
| 1204 | unsigned int lreg; |
| 1205 | int ret; |
| 1206 | |
| 1207 | mutex_lock(&fsl_ac97_data->ac97_reg_lock); |
| 1208 | |
| 1209 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
| 1210 | if (ret) { |
| 1211 | pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); |
| 1212 | goto ret_unlock; |
| 1213 | } |
| 1214 | |
| 1215 | lreg = (reg & 0x7f) << 12; |
| 1216 | regmap_write(regs, REG_SSI_SACADD, lreg); |
| 1217 | regmap_update_bits(regs, REG_SSI_SACNT, |
| 1218 | SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); |
| 1219 | |
| 1220 | udelay(100); |
| 1221 | |
| 1222 | regmap_read(regs, REG_SSI_SACDAT, ®_val); |
| 1223 | val = (reg_val >> 4) & 0xffff; |
| 1224 | |
| 1225 | clk_disable_unprepare(fsl_ac97_data->clk); |
| 1226 | |
| 1227 | ret_unlock: |
| 1228 | mutex_unlock(&fsl_ac97_data->ac97_reg_lock); |
| 1229 | return val; |
| 1230 | } |
| 1231 | |
| 1232 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { |
| 1233 | .read = fsl_ssi_ac97_read, |
| 1234 | .write = fsl_ssi_ac97_write, |
| 1235 | }; |
| 1236 | |
| 1237 | /** |
| 1238 | * Initialize SSI registers |
| 1239 | */ |
| 1240 | static int fsl_ssi_hw_init(struct fsl_ssi *ssi) |
| 1241 | { |
| 1242 | u32 wm = ssi->fifo_watermark; |
| 1243 | |
| 1244 | /* Initialize regvals */ |
| 1245 | fsl_ssi_setup_regvals(ssi); |
| 1246 | |
| 1247 | /* Set watermarks */ |
| 1248 | regmap_write(ssi->regs, REG_SSI_SFCSR, |
| 1249 | SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | |
| 1250 | SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); |
| 1251 | |
| 1252 | /* Enable Dual FIFO mode */ |
| 1253 | if (ssi->use_dual_fifo) |
| 1254 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 1255 | SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); |
| 1256 | |
| 1257 | /* AC97 should start earlier to communicate with CODECs */ |
| 1258 | if (fsl_ssi_is_ac97(ssi)) { |
| 1259 | _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt); |
| 1260 | fsl_ssi_setup_ac97(ssi); |
| 1261 | } |
| 1262 | |
| 1263 | return 0; |
| 1264 | } |
| 1265 | |
| 1266 | /** |
| 1267 | * Clear SSI registers |
| 1268 | */ |
| 1269 | static void fsl_ssi_hw_clean(struct fsl_ssi *ssi) |
| 1270 | { |
| 1271 | /* Disable registers for AC97 */ |
| 1272 | if (fsl_ssi_is_ac97(ssi)) { |
| 1273 | /* Disable TE and RE bits first */ |
| 1274 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 1275 | SSI_SCR_TE | SSI_SCR_RE, 0); |
| 1276 | /* Disable AC97 mode */ |
| 1277 | regmap_write(ssi->regs, REG_SSI_SACNT, 0); |
| 1278 | /* Unset WAIT bits */ |
| 1279 | regmap_write(ssi->regs, REG_SSI_SOR, 0); |
| 1280 | /* Disable SSI -- software reset */ |
| 1281 | regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0); |
| 1282 | } |
| 1283 | } |
| 1284 | /** |
| 1285 | * Make every character in a string lower-case |
| 1286 | */ |
| 1287 | static void make_lowercase(char *s) |
| 1288 | { |
| 1289 | if (!s) |
| 1290 | return; |
| 1291 | for (; *s; s++) |
| 1292 | *s = tolower(*s); |
| 1293 | } |
| 1294 | |
| 1295 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
| 1296 | struct fsl_ssi *ssi, void __iomem *iomem) |
| 1297 | { |
| 1298 | struct device *dev = &pdev->dev; |
| 1299 | int ret; |
| 1300 | |
| 1301 | /* Backward compatible for a DT without ipg clock name assigned */ |
| 1302 | if (ssi->has_ipg_clk_name) |
| 1303 | ssi->clk = devm_clk_get(dev, "ipg"); |
| 1304 | else |
| 1305 | ssi->clk = devm_clk_get(dev, NULL); |
| 1306 | if (IS_ERR(ssi->clk)) { |
| 1307 | ret = PTR_ERR(ssi->clk); |
| 1308 | dev_err(dev, "failed to get clock: %d\n", ret); |
| 1309 | return ret; |
| 1310 | } |
| 1311 | |
| 1312 | /* Enable the clock since regmap will not handle it in this case */ |
| 1313 | if (!ssi->has_ipg_clk_name) { |
| 1314 | ret = clk_prepare_enable(ssi->clk); |
| 1315 | if (ret) { |
| 1316 | dev_err(dev, "clk_prepare_enable failed: %d\n", ret); |
| 1317 | return ret; |
| 1318 | } |
| 1319 | } |
| 1320 | |
| 1321 | /* Do not error out for slave cases that live without a baud clock */ |
| 1322 | ssi->baudclk = devm_clk_get(dev, "baud"); |
| 1323 | if (IS_ERR(ssi->baudclk)) |
| 1324 | dev_dbg(dev, "failed to get baud clock: %ld\n", |
| 1325 | PTR_ERR(ssi->baudclk)); |
| 1326 | |
| 1327 | ssi->dma_params_tx.maxburst = ssi->dma_maxburst; |
| 1328 | ssi->dma_params_rx.maxburst = ssi->dma_maxburst; |
| 1329 | ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0; |
| 1330 | ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0; |
| 1331 | |
| 1332 | /* Use even numbers to avoid channel swap due to SDMA script design */ |
| 1333 | if (ssi->use_dual_fifo) { |
| 1334 | ssi->dma_params_tx.maxburst &= ~0x1; |
| 1335 | ssi->dma_params_rx.maxburst &= ~0x1; |
| 1336 | } |
| 1337 | |
| 1338 | if (!ssi->use_dma) { |
| 1339 | /* |
| 1340 | * Some boards use an incompatible codec. Use imx-fiq-pcm-audio |
| 1341 | * to get it working, as DMA is not possible in this situation. |
| 1342 | */ |
| 1343 | ssi->fiq_params.irq = ssi->irq; |
| 1344 | ssi->fiq_params.base = iomem; |
| 1345 | ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx; |
| 1346 | ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx; |
| 1347 | |
| 1348 | ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params); |
| 1349 | if (ret) |
| 1350 | goto error_pcm; |
| 1351 | } else { |
| 1352 | ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); |
| 1353 | if (ret) |
| 1354 | goto error_pcm; |
| 1355 | } |
| 1356 | |
| 1357 | return 0; |
| 1358 | |
| 1359 | error_pcm: |
| 1360 | if (!ssi->has_ipg_clk_name) |
| 1361 | clk_disable_unprepare(ssi->clk); |
| 1362 | |
| 1363 | return ret; |
| 1364 | } |
| 1365 | |
| 1366 | static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) |
| 1367 | { |
| 1368 | if (!ssi->use_dma) |
| 1369 | imx_pcm_fiq_exit(pdev); |
| 1370 | if (!ssi->has_ipg_clk_name) |
| 1371 | clk_disable_unprepare(ssi->clk); |
| 1372 | } |
| 1373 | |
| 1374 | static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi) |
| 1375 | { |
| 1376 | struct device *dev = ssi->dev; |
| 1377 | struct device_node *np = dev->of_node; |
| 1378 | const struct of_device_id *of_id; |
| 1379 | const char *p, *sprop; |
| 1380 | const __be32 *iprop; |
| 1381 | u32 dmas[4]; |
| 1382 | int ret; |
| 1383 | |
| 1384 | of_id = of_match_device(fsl_ssi_ids, dev); |
| 1385 | if (!of_id || !of_id->data) |
| 1386 | return -EINVAL; |
| 1387 | |
| 1388 | ssi->soc = of_id->data; |
| 1389 | |
| 1390 | ret = of_property_match_string(np, "clock-names", "ipg"); |
| 1391 | /* Get error code if not found */ |
| 1392 | ssi->has_ipg_clk_name = ret >= 0; |
| 1393 | |
| 1394 | /* Check if being used in AC97 mode */ |
| 1395 | sprop = of_get_property(np, "fsl,mode", NULL); |
| 1396 | if (sprop && !strcmp(sprop, "ac97-slave")) { |
| 1397 | ssi->dai_fmt = FSLSSI_AC97_DAIFMT; |
| 1398 | |
| 1399 | ret = of_property_read_u32(np, "cell-index", &ssi->card_idx); |
| 1400 | if (ret) { |
| 1401 | dev_err(dev, "failed to get SSI index property\n"); |
| 1402 | return -EINVAL; |
| 1403 | } |
| 1404 | strcpy(ssi->card_name, "ac97-codec"); |
| 1405 | } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
| 1406 | /* |
| 1407 | * In synchronous mode, STCK and STFS ports are used by RX |
| 1408 | * as well. So the software should limit the sample rates, |
| 1409 | * sample bits and channels to be symmetric. |
| 1410 | * |
| 1411 | * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs |
| 1412 | * in the SSI synchronous mode however it does not have to |
| 1413 | * limit symmetric sample rates and sample bits. |
| 1414 | */ |
| 1415 | ssi->synchronous = true; |
| 1416 | } |
| 1417 | |
| 1418 | /* Select DMA or FIQ */ |
| 1419 | ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter"); |
| 1420 | |
| 1421 | /* Fetch FIFO depth; Set to 8 for older DT without this property */ |
| 1422 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); |
| 1423 | if (iprop) |
| 1424 | ssi->fifo_depth = be32_to_cpup(iprop); |
| 1425 | else |
| 1426 | ssi->fifo_depth = 8; |
| 1427 | |
| 1428 | /* Use dual FIFO mode depending on the support from SDMA script */ |
| 1429 | ret = of_property_read_u32_array(np, "dmas", dmas, 4); |
| 1430 | if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) |
| 1431 | ssi->use_dual_fifo = true; |
| 1432 | |
| 1433 | /* |
| 1434 | * Backward compatible for older bindings by manually triggering the |
| 1435 | * machine driver's probe(). Use /compatible property, including the |
| 1436 | * address of CPU DAI driver structure, as the name of machine driver |
| 1437 | * |
| 1438 | * If card_name is set by AC97 earlier, bypass here since it uses a |
| 1439 | * different name to register the device. |
| 1440 | */ |
| 1441 | if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) { |
| 1442 | struct device_node *root = of_find_node_by_path("/"); |
| 1443 | |
| 1444 | sprop = of_get_property(root, "compatible", NULL); |
| 1445 | of_node_put(root); |
| 1446 | /* Strip "fsl," in the compatible name if applicable */ |
| 1447 | p = strrchr(sprop, ','); |
| 1448 | if (p) |
| 1449 | sprop = p + 1; |
| 1450 | snprintf(ssi->card_name, sizeof(ssi->card_name), |
| 1451 | "snd-soc-%s", sprop); |
| 1452 | make_lowercase(ssi->card_name); |
| 1453 | ssi->card_idx = 0; |
| 1454 | } |
| 1455 | |
| 1456 | return 0; |
| 1457 | } |
| 1458 | |
| 1459 | static int fsl_ssi_probe(struct platform_device *pdev) |
| 1460 | { |
| 1461 | struct regmap_config regconfig = fsl_ssi_regconfig; |
| 1462 | struct device *dev = &pdev->dev; |
| 1463 | struct fsl_ssi *ssi; |
| 1464 | struct resource *res; |
| 1465 | void __iomem *iomem; |
| 1466 | int ret = 0; |
| 1467 | |
| 1468 | ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); |
| 1469 | if (!ssi) |
| 1470 | return -ENOMEM; |
| 1471 | |
| 1472 | ssi->dev = dev; |
| 1473 | |
| 1474 | /* Probe from DT */ |
| 1475 | ret = fsl_ssi_probe_from_dt(ssi); |
| 1476 | if (ret) |
| 1477 | return ret; |
| 1478 | |
| 1479 | if (fsl_ssi_is_ac97(ssi)) { |
| 1480 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, |
| 1481 | sizeof(fsl_ssi_ac97_dai)); |
| 1482 | fsl_ac97_data = ssi; |
| 1483 | } else { |
| 1484 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, |
| 1485 | sizeof(fsl_ssi_dai_template)); |
| 1486 | } |
| 1487 | ssi->cpu_dai_drv.name = dev_name(dev); |
| 1488 | |
| 1489 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1490 | iomem = devm_ioremap_resource(dev, res); |
| 1491 | if (IS_ERR(iomem)) |
| 1492 | return PTR_ERR(iomem); |
| 1493 | ssi->ssi_phys = res->start; |
| 1494 | |
| 1495 | if (ssi->soc->imx21regs) { |
| 1496 | /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ |
| 1497 | regconfig.max_register = REG_SSI_SRMSK; |
| 1498 | regconfig.num_reg_defaults_raw = |
| 1499 | REG_SSI_SRMSK / sizeof(uint32_t) + 1; |
| 1500 | } |
| 1501 | |
| 1502 | if (ssi->has_ipg_clk_name) |
| 1503 | ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem, |
| 1504 | ®config); |
| 1505 | else |
| 1506 | ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config); |
| 1507 | if (IS_ERR(ssi->regs)) { |
| 1508 | dev_err(dev, "failed to init register map\n"); |
| 1509 | return PTR_ERR(ssi->regs); |
| 1510 | } |
| 1511 | |
| 1512 | ssi->irq = platform_get_irq(pdev, 0); |
| 1513 | if (ssi->irq < 0) { |
| 1514 | dev_err(dev, "no irq for node %s\n", pdev->name); |
| 1515 | return ssi->irq; |
| 1516 | } |
| 1517 | |
| 1518 | /* Set software limitations for synchronous mode except AC97 */ |
| 1519 | if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) { |
| 1520 | ssi->cpu_dai_drv.symmetric_rates = 1; |
| 1521 | ssi->cpu_dai_drv.symmetric_channels = 1; |
| 1522 | ssi->cpu_dai_drv.symmetric_samplebits = 1; |
| 1523 | } |
| 1524 | |
| 1525 | /* |
| 1526 | * Configure TX and RX DMA watermarks -- when to send a DMA request |
| 1527 | * |
| 1528 | * Values should be tested to avoid FIFO under/over run. Set maxburst |
| 1529 | * to fifo_watermark to maxiumize DMA transaction to reduce overhead. |
| 1530 | */ |
| 1531 | switch (ssi->fifo_depth) { |
| 1532 | case 15: |
| 1533 | /* |
| 1534 | * Set to 8 as a balanced configuration -- When TX FIFO has 8 |
| 1535 | * empty slots, send a DMA request to fill these 8 slots. The |
| 1536 | * remaining 7 slots should be able to allow DMA to finish the |
| 1537 | * transaction before TX FIFO underruns; Same applies to RX. |
| 1538 | * |
| 1539 | * Tested with cases running at 48kHz @ 16 bits x 16 channels |
| 1540 | */ |
| 1541 | ssi->fifo_watermark = 8; |
| 1542 | ssi->dma_maxburst = 8; |
| 1543 | break; |
| 1544 | case 8: |
| 1545 | default: |
| 1546 | /* Safely use old watermark configurations for older chips */ |
| 1547 | ssi->fifo_watermark = ssi->fifo_depth - 2; |
| 1548 | ssi->dma_maxburst = ssi->fifo_depth - 2; |
| 1549 | break; |
| 1550 | } |
| 1551 | |
| 1552 | dev_set_drvdata(dev, ssi); |
| 1553 | |
| 1554 | if (ssi->soc->imx) { |
| 1555 | ret = fsl_ssi_imx_probe(pdev, ssi, iomem); |
| 1556 | if (ret) |
| 1557 | return ret; |
| 1558 | } |
| 1559 | |
| 1560 | if (fsl_ssi_is_ac97(ssi)) { |
| 1561 | mutex_init(&ssi->ac97_reg_lock); |
| 1562 | ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); |
| 1563 | if (ret) { |
| 1564 | dev_err(dev, "failed to set AC'97 ops\n"); |
| 1565 | goto error_ac97_ops; |
| 1566 | } |
| 1567 | } |
| 1568 | |
| 1569 | ret = devm_snd_soc_register_component(dev, &fsl_ssi_component, |
| 1570 | &ssi->cpu_dai_drv, 1); |
| 1571 | if (ret) { |
| 1572 | dev_err(dev, "failed to register DAI: %d\n", ret); |
| 1573 | goto error_asoc_register; |
| 1574 | } |
| 1575 | |
| 1576 | if (ssi->use_dma) { |
| 1577 | ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0, |
| 1578 | dev_name(dev), ssi); |
| 1579 | if (ret < 0) { |
| 1580 | dev_err(dev, "failed to claim irq %u\n", ssi->irq); |
| 1581 | goto error_asoc_register; |
| 1582 | } |
| 1583 | } |
| 1584 | |
| 1585 | ret = fsl_ssi_debugfs_create(&ssi->dbg_stats, dev); |
| 1586 | if (ret) |
| 1587 | goto error_asoc_register; |
| 1588 | |
| 1589 | /* Initially configures SSI registers */ |
| 1590 | fsl_ssi_hw_init(ssi); |
| 1591 | |
| 1592 | /* Register a platform device for older bindings or AC97 */ |
| 1593 | if (ssi->card_name[0]) { |
| 1594 | struct device *parent = dev; |
| 1595 | /* |
| 1596 | * Do not set SSI dev as the parent of AC97 CODEC device since |
| 1597 | * it does not have a DT node. Otherwise ASoC core will assume |
| 1598 | * CODEC has the same DT node as the SSI, so it may bypass the |
| 1599 | * dai_probe() of SSI and then cause NULL DMA data pointers. |
| 1600 | */ |
| 1601 | if (fsl_ssi_is_ac97(ssi)) |
| 1602 | parent = NULL; |
| 1603 | |
| 1604 | ssi->card_pdev = platform_device_register_data(parent, |
| 1605 | ssi->card_name, ssi->card_idx, NULL, 0); |
| 1606 | if (IS_ERR(ssi->card_pdev)) { |
| 1607 | ret = PTR_ERR(ssi->card_pdev); |
| 1608 | dev_err(dev, "failed to register %s: %d\n", |
| 1609 | ssi->card_name, ret); |
| 1610 | goto error_sound_card; |
| 1611 | } |
| 1612 | } |
| 1613 | |
| 1614 | return 0; |
| 1615 | |
| 1616 | error_sound_card: |
| 1617 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
| 1618 | error_asoc_register: |
| 1619 | if (fsl_ssi_is_ac97(ssi)) |
| 1620 | snd_soc_set_ac97_ops(NULL); |
| 1621 | error_ac97_ops: |
| 1622 | if (fsl_ssi_is_ac97(ssi)) |
| 1623 | mutex_destroy(&ssi->ac97_reg_lock); |
| 1624 | |
| 1625 | if (ssi->soc->imx) |
| 1626 | fsl_ssi_imx_clean(pdev, ssi); |
| 1627 | |
| 1628 | return ret; |
| 1629 | } |
| 1630 | |
| 1631 | static int fsl_ssi_remove(struct platform_device *pdev) |
| 1632 | { |
| 1633 | struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev); |
| 1634 | |
| 1635 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
| 1636 | |
| 1637 | if (ssi->card_pdev) |
| 1638 | platform_device_unregister(ssi->card_pdev); |
| 1639 | |
| 1640 | /* Clean up SSI registers */ |
| 1641 | fsl_ssi_hw_clean(ssi); |
| 1642 | |
| 1643 | if (ssi->soc->imx) |
| 1644 | fsl_ssi_imx_clean(pdev, ssi); |
| 1645 | |
| 1646 | if (fsl_ssi_is_ac97(ssi)) { |
| 1647 | snd_soc_set_ac97_ops(NULL); |
| 1648 | mutex_destroy(&ssi->ac97_reg_lock); |
| 1649 | } |
| 1650 | |
| 1651 | return 0; |
| 1652 | } |
| 1653 | |
| 1654 | #ifdef CONFIG_PM_SLEEP |
| 1655 | static int fsl_ssi_suspend(struct device *dev) |
| 1656 | { |
| 1657 | struct fsl_ssi *ssi = dev_get_drvdata(dev); |
| 1658 | struct regmap *regs = ssi->regs; |
| 1659 | |
| 1660 | regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr); |
| 1661 | regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt); |
| 1662 | |
| 1663 | regcache_cache_only(regs, true); |
| 1664 | regcache_mark_dirty(regs); |
| 1665 | |
| 1666 | return 0; |
| 1667 | } |
| 1668 | |
| 1669 | static int fsl_ssi_resume(struct device *dev) |
| 1670 | { |
| 1671 | struct fsl_ssi *ssi = dev_get_drvdata(dev); |
| 1672 | struct regmap *regs = ssi->regs; |
| 1673 | |
| 1674 | regcache_cache_only(regs, false); |
| 1675 | |
| 1676 | regmap_update_bits(regs, REG_SSI_SFCSR, |
| 1677 | SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | |
| 1678 | SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, |
| 1679 | ssi->regcache_sfcsr); |
| 1680 | regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); |
| 1681 | |
| 1682 | return regcache_sync(regs); |
| 1683 | } |
| 1684 | #endif /* CONFIG_PM_SLEEP */ |
| 1685 | |
| 1686 | static const struct dev_pm_ops fsl_ssi_pm = { |
| 1687 | SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) |
| 1688 | }; |
| 1689 | |
| 1690 | static struct platform_driver fsl_ssi_driver = { |
| 1691 | .driver = { |
| 1692 | .name = "fsl-ssi-dai", |
| 1693 | .of_match_table = fsl_ssi_ids, |
| 1694 | .pm = &fsl_ssi_pm, |
| 1695 | }, |
| 1696 | .probe = fsl_ssi_probe, |
| 1697 | .remove = fsl_ssi_remove, |
| 1698 | }; |
| 1699 | |
| 1700 | module_platform_driver(fsl_ssi_driver); |
| 1701 | |
| 1702 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
| 1703 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
| 1704 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); |
| 1705 | MODULE_LICENSE("GPL v2"); |