| 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * es8328.c -- ES8328 ALSA SoC Audio driver |
| 4 | * |
| 5 | * Copyright 2014 Sutajio Ko-Usagi PTE LTD |
| 6 | * |
| 7 | * Author: Sean Cross <xobs@kosagi.com> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/of_device.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/pm.h> |
| 15 | #include <linux/regmap.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/regulator/consumer.h> |
| 18 | #include <sound/core.h> |
| 19 | #include <sound/initval.h> |
| 20 | #include <sound/pcm.h> |
| 21 | #include <sound/pcm_params.h> |
| 22 | #include <sound/soc.h> |
| 23 | #include <sound/tlv.h> |
| 24 | #include "es8328.h" |
| 25 | |
| 26 | static const unsigned int rates_12288[] = { |
| 27 | 8000, 12000, 16000, 24000, 32000, 48000, 96000, |
| 28 | }; |
| 29 | |
| 30 | static const int ratios_12288[] = { |
| 31 | 10, 7, 6, 4, 3, 2, 0, |
| 32 | }; |
| 33 | |
| 34 | static const struct snd_pcm_hw_constraint_list constraints_12288 = { |
| 35 | .count = ARRAY_SIZE(rates_12288), |
| 36 | .list = rates_12288, |
| 37 | }; |
| 38 | |
| 39 | static const unsigned int rates_11289[] = { |
| 40 | 8018, 11025, 22050, 44100, 88200, |
| 41 | }; |
| 42 | |
| 43 | static const int ratios_11289[] = { |
| 44 | 9, 7, 4, 2, 0, |
| 45 | }; |
| 46 | |
| 47 | static const struct snd_pcm_hw_constraint_list constraints_11289 = { |
| 48 | .count = ARRAY_SIZE(rates_11289), |
| 49 | .list = rates_11289, |
| 50 | }; |
| 51 | |
| 52 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ |
| 53 | enum sgtl5000_regulator_supplies { |
| 54 | DVDD, |
| 55 | AVDD, |
| 56 | PVDD, |
| 57 | HPVDD, |
| 58 | ES8328_SUPPLY_NUM |
| 59 | }; |
| 60 | |
| 61 | /* vddd is optional supply */ |
| 62 | static const char * const supply_names[ES8328_SUPPLY_NUM] = { |
| 63 | "DVDD", |
| 64 | "AVDD", |
| 65 | "PVDD", |
| 66 | "HPVDD", |
| 67 | }; |
| 68 | |
| 69 | #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \ |
| 70 | SNDRV_PCM_RATE_96000 | \ |
| 71 | SNDRV_PCM_RATE_88200 | \ |
| 72 | SNDRV_PCM_RATE_8000_48000) |
| 73 | #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
| 74 | SNDRV_PCM_FMTBIT_S18_3LE | \ |
| 75 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 76 | SNDRV_PCM_FMTBIT_S24_LE | \ |
| 77 | SNDRV_PCM_FMTBIT_S32_LE) |
| 78 | |
| 79 | struct es8328_priv { |
| 80 | struct regmap *regmap; |
| 81 | struct clk *clk; |
| 82 | int playback_fs; |
| 83 | bool deemph; |
| 84 | int mclkdiv2; |
| 85 | const struct snd_pcm_hw_constraint_list *sysclk_constraints; |
| 86 | const int *mclk_ratios; |
| 87 | bool master; |
| 88 | struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; |
| 89 | }; |
| 90 | |
| 91 | /* |
| 92 | * ES8328 Controls |
| 93 | */ |
| 94 | |
| 95 | static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", |
| 96 | "L + R Invert"}; |
| 97 | static SOC_ENUM_SINGLE_DECL(adcpol, |
| 98 | ES8328_ADCCONTROL6, 6, adcpol_txt); |
| 99 | |
| 100 | static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); |
| 101 | static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); |
| 102 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); |
| 103 | static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); |
| 104 | |
| 105 | static const struct { |
| 106 | int rate; |
| 107 | unsigned int val; |
| 108 | } deemph_settings[] = { |
| 109 | { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, |
| 110 | { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, |
| 111 | { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, |
| 112 | { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, |
| 113 | }; |
| 114 | |
| 115 | static int es8328_set_deemph(struct snd_soc_component *component) |
| 116 | { |
| 117 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 118 | int val, i, best; |
| 119 | |
| 120 | /* |
| 121 | * If we're using deemphasis select the nearest available sample |
| 122 | * rate. |
| 123 | */ |
| 124 | if (es8328->deemph) { |
| 125 | best = 0; |
| 126 | for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { |
| 127 | if (abs(deemph_settings[i].rate - es8328->playback_fs) < |
| 128 | abs(deemph_settings[best].rate - es8328->playback_fs)) |
| 129 | best = i; |
| 130 | } |
| 131 | |
| 132 | val = deemph_settings[best].val; |
| 133 | } else { |
| 134 | val = ES8328_DACCONTROL6_DEEMPH_OFF; |
| 135 | } |
| 136 | |
| 137 | dev_dbg(component->dev, "Set deemphasis %d\n", val); |
| 138 | |
| 139 | return snd_soc_component_update_bits(component, ES8328_DACCONTROL6, |
| 140 | ES8328_DACCONTROL6_DEEMPH_MASK, val); |
| 141 | } |
| 142 | |
| 143 | static int es8328_get_deemph(struct snd_kcontrol *kcontrol, |
| 144 | struct snd_ctl_elem_value *ucontrol) |
| 145 | { |
| 146 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
| 147 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 148 | |
| 149 | ucontrol->value.integer.value[0] = es8328->deemph; |
| 150 | return 0; |
| 151 | } |
| 152 | |
| 153 | static int es8328_put_deemph(struct snd_kcontrol *kcontrol, |
| 154 | struct snd_ctl_elem_value *ucontrol) |
| 155 | { |
| 156 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
| 157 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 158 | unsigned int deemph = ucontrol->value.integer.value[0]; |
| 159 | int ret; |
| 160 | |
| 161 | if (deemph > 1) |
| 162 | return -EINVAL; |
| 163 | |
| 164 | ret = es8328_set_deemph(component); |
| 165 | if (ret < 0) |
| 166 | return ret; |
| 167 | |
| 168 | es8328->deemph = deemph; |
| 169 | |
| 170 | return 0; |
| 171 | } |
| 172 | |
| 173 | |
| 174 | |
| 175 | static const struct snd_kcontrol_new es8328_snd_controls[] = { |
| 176 | SOC_DOUBLE_R_TLV("Capture Digital Volume", |
| 177 | ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, |
| 178 | 0, 0xc0, 1, dac_adc_tlv), |
| 179 | SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), |
| 180 | |
| 181 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, |
| 182 | es8328_get_deemph, es8328_put_deemph), |
| 183 | |
| 184 | SOC_ENUM("Capture Polarity", adcpol), |
| 185 | |
| 186 | SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", |
| 187 | ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), |
| 188 | SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", |
| 189 | ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), |
| 190 | SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", |
| 191 | ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), |
| 192 | SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", |
| 193 | ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), |
| 194 | |
| 195 | SOC_DOUBLE_R_TLV("PCM Volume", |
| 196 | ES8328_LDACVOL, ES8328_RDACVOL, |
| 197 | 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), |
| 198 | |
| 199 | SOC_DOUBLE_R_TLV("Output 1 Playback Volume", |
| 200 | ES8328_LOUT1VOL, ES8328_ROUT1VOL, |
| 201 | 0, ES8328_OUT1VOL_MAX, 0, play_tlv), |
| 202 | |
| 203 | SOC_DOUBLE_R_TLV("Output 2 Playback Volume", |
| 204 | ES8328_LOUT2VOL, ES8328_ROUT2VOL, |
| 205 | 0, ES8328_OUT2VOL_MAX, 0, play_tlv), |
| 206 | |
| 207 | SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, |
| 208 | 4, 0, 8, 0, mic_tlv), |
| 209 | }; |
| 210 | |
| 211 | /* |
| 212 | * DAPM Controls |
| 213 | */ |
| 214 | |
| 215 | static const char * const es8328_line_texts[] = { |
| 216 | "Line 1", "Line 2", "PGA", "Differential"}; |
| 217 | |
| 218 | static const struct soc_enum es8328_lline_enum = |
| 219 | SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, |
| 220 | ARRAY_SIZE(es8328_line_texts), |
| 221 | es8328_line_texts); |
| 222 | static const struct snd_kcontrol_new es8328_left_line_controls = |
| 223 | SOC_DAPM_ENUM("Route", es8328_lline_enum); |
| 224 | |
| 225 | static const struct soc_enum es8328_rline_enum = |
| 226 | SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, |
| 227 | ARRAY_SIZE(es8328_line_texts), |
| 228 | es8328_line_texts); |
| 229 | static const struct snd_kcontrol_new es8328_right_line_controls = |
| 230 | SOC_DAPM_ENUM("Route", es8328_rline_enum); |
| 231 | |
| 232 | /* Left Mixer */ |
| 233 | static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { |
| 234 | SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0), |
| 235 | SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), |
| 236 | SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), |
| 237 | SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), |
| 238 | }; |
| 239 | |
| 240 | /* Right Mixer */ |
| 241 | static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { |
| 242 | SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), |
| 243 | SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), |
| 244 | SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0), |
| 245 | SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), |
| 246 | }; |
| 247 | |
| 248 | static const char * const es8328_pga_sel[] = { |
| 249 | "Line 1", "Line 2", "Line 3", "Differential"}; |
| 250 | |
| 251 | /* Left PGA Mux */ |
| 252 | static const struct soc_enum es8328_lpga_enum = |
| 253 | SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, |
| 254 | ARRAY_SIZE(es8328_pga_sel), |
| 255 | es8328_pga_sel); |
| 256 | static const struct snd_kcontrol_new es8328_left_pga_controls = |
| 257 | SOC_DAPM_ENUM("Route", es8328_lpga_enum); |
| 258 | |
| 259 | /* Right PGA Mux */ |
| 260 | static const struct soc_enum es8328_rpga_enum = |
| 261 | SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, |
| 262 | ARRAY_SIZE(es8328_pga_sel), |
| 263 | es8328_pga_sel); |
| 264 | static const struct snd_kcontrol_new es8328_right_pga_controls = |
| 265 | SOC_DAPM_ENUM("Route", es8328_rpga_enum); |
| 266 | |
| 267 | /* Differential Mux */ |
| 268 | static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; |
| 269 | static SOC_ENUM_SINGLE_DECL(diffmux, |
| 270 | ES8328_ADCCONTROL3, 7, es8328_diff_sel); |
| 271 | static const struct snd_kcontrol_new es8328_diffmux_controls = |
| 272 | SOC_DAPM_ENUM("Route", diffmux); |
| 273 | |
| 274 | /* Mono ADC Mux */ |
| 275 | static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", |
| 276 | "Mono (Right)", "Digital Mono"}; |
| 277 | static SOC_ENUM_SINGLE_DECL(monomux, |
| 278 | ES8328_ADCCONTROL3, 3, es8328_mono_mux); |
| 279 | static const struct snd_kcontrol_new es8328_monomux_controls = |
| 280 | SOC_DAPM_ENUM("Route", monomux); |
| 281 | |
| 282 | static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { |
| 283 | SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, |
| 284 | &es8328_diffmux_controls), |
| 285 | SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, |
| 286 | &es8328_monomux_controls), |
| 287 | SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, |
| 288 | &es8328_monomux_controls), |
| 289 | |
| 290 | SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, |
| 291 | ES8328_ADCPOWER_AINL_OFF, 1, |
| 292 | &es8328_left_pga_controls), |
| 293 | SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, |
| 294 | ES8328_ADCPOWER_AINR_OFF, 1, |
| 295 | &es8328_right_pga_controls), |
| 296 | |
| 297 | SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, |
| 298 | &es8328_left_line_controls), |
| 299 | SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, |
| 300 | &es8328_right_line_controls), |
| 301 | |
| 302 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, |
| 303 | ES8328_ADCPOWER_ADCR_OFF, 1), |
| 304 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, |
| 305 | ES8328_ADCPOWER_ADCL_OFF, 1), |
| 306 | |
| 307 | SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, |
| 308 | ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), |
| 309 | SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, |
| 310 | ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), |
| 311 | |
| 312 | SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, |
| 313 | ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), |
| 314 | SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, |
| 315 | ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), |
| 316 | |
| 317 | SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, |
| 318 | ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), |
| 319 | SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, |
| 320 | ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), |
| 321 | |
| 322 | SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, |
| 323 | ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), |
| 324 | SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, |
| 325 | ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), |
| 326 | |
| 327 | SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, |
| 328 | ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), |
| 329 | SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, |
| 330 | ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), |
| 331 | |
| 332 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, |
| 333 | ES8328_DACPOWER_RDAC_OFF, 1), |
| 334 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, |
| 335 | ES8328_DACPOWER_LDAC_OFF, 1), |
| 336 | |
| 337 | SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, |
| 338 | &es8328_left_mixer_controls[0], |
| 339 | ARRAY_SIZE(es8328_left_mixer_controls)), |
| 340 | SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, |
| 341 | &es8328_right_mixer_controls[0], |
| 342 | ARRAY_SIZE(es8328_right_mixer_controls)), |
| 343 | |
| 344 | SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, |
| 345 | ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), |
| 346 | SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, |
| 347 | ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), |
| 348 | SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, |
| 349 | ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), |
| 350 | SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, |
| 351 | ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), |
| 352 | |
| 353 | SND_SOC_DAPM_OUTPUT("LOUT1"), |
| 354 | SND_SOC_DAPM_OUTPUT("ROUT1"), |
| 355 | SND_SOC_DAPM_OUTPUT("LOUT2"), |
| 356 | SND_SOC_DAPM_OUTPUT("ROUT2"), |
| 357 | |
| 358 | SND_SOC_DAPM_INPUT("LINPUT1"), |
| 359 | SND_SOC_DAPM_INPUT("LINPUT2"), |
| 360 | SND_SOC_DAPM_INPUT("RINPUT1"), |
| 361 | SND_SOC_DAPM_INPUT("RINPUT2"), |
| 362 | }; |
| 363 | |
| 364 | static const struct snd_soc_dapm_route es8328_dapm_routes[] = { |
| 365 | |
| 366 | { "Left Line Mux", "Line 1", "LINPUT1" }, |
| 367 | { "Left Line Mux", "Line 2", "LINPUT2" }, |
| 368 | { "Left Line Mux", "PGA", "Left PGA Mux" }, |
| 369 | { "Left Line Mux", "Differential", "Differential Mux" }, |
| 370 | |
| 371 | { "Right Line Mux", "Line 1", "RINPUT1" }, |
| 372 | { "Right Line Mux", "Line 2", "RINPUT2" }, |
| 373 | { "Right Line Mux", "PGA", "Right PGA Mux" }, |
| 374 | { "Right Line Mux", "Differential", "Differential Mux" }, |
| 375 | |
| 376 | { "Left PGA Mux", "Line 1", "LINPUT1" }, |
| 377 | { "Left PGA Mux", "Line 2", "LINPUT2" }, |
| 378 | { "Left PGA Mux", "Differential", "Differential Mux" }, |
| 379 | |
| 380 | { "Right PGA Mux", "Line 1", "RINPUT1" }, |
| 381 | { "Right PGA Mux", "Line 2", "RINPUT2" }, |
| 382 | { "Right PGA Mux", "Differential", "Differential Mux" }, |
| 383 | |
| 384 | { "Differential Mux", "Line 1", "LINPUT1" }, |
| 385 | { "Differential Mux", "Line 1", "RINPUT1" }, |
| 386 | { "Differential Mux", "Line 2", "LINPUT2" }, |
| 387 | { "Differential Mux", "Line 2", "RINPUT2" }, |
| 388 | |
| 389 | { "Left ADC Mux", "Stereo", "Left PGA Mux" }, |
| 390 | { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, |
| 391 | { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, |
| 392 | |
| 393 | { "Right ADC Mux", "Stereo", "Right PGA Mux" }, |
| 394 | { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, |
| 395 | { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, |
| 396 | |
| 397 | { "Left ADC", NULL, "Left ADC Mux" }, |
| 398 | { "Right ADC", NULL, "Right ADC Mux" }, |
| 399 | |
| 400 | { "ADC DIG", NULL, "ADC STM" }, |
| 401 | { "ADC DIG", NULL, "ADC Vref" }, |
| 402 | { "ADC DIG", NULL, "ADC DLL" }, |
| 403 | |
| 404 | { "Left ADC", NULL, "ADC DIG" }, |
| 405 | { "Right ADC", NULL, "ADC DIG" }, |
| 406 | |
| 407 | { "Mic Bias", NULL, "Mic Bias Gen" }, |
| 408 | |
| 409 | { "Left Line Mux", "Line 1", "LINPUT1" }, |
| 410 | { "Left Line Mux", "Line 2", "LINPUT2" }, |
| 411 | { "Left Line Mux", "PGA", "Left PGA Mux" }, |
| 412 | { "Left Line Mux", "Differential", "Differential Mux" }, |
| 413 | |
| 414 | { "Right Line Mux", "Line 1", "RINPUT1" }, |
| 415 | { "Right Line Mux", "Line 2", "RINPUT2" }, |
| 416 | { "Right Line Mux", "PGA", "Right PGA Mux" }, |
| 417 | { "Right Line Mux", "Differential", "Differential Mux" }, |
| 418 | |
| 419 | { "Left Out 1", NULL, "Left DAC" }, |
| 420 | { "Right Out 1", NULL, "Right DAC" }, |
| 421 | { "Left Out 2", NULL, "Left DAC" }, |
| 422 | { "Right Out 2", NULL, "Right DAC" }, |
| 423 | |
| 424 | { "Left Mixer", "Playback Switch", "Left DAC" }, |
| 425 | { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, |
| 426 | { "Left Mixer", "Right Playback Switch", "Right DAC" }, |
| 427 | { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, |
| 428 | |
| 429 | { "Right Mixer", "Left Playback Switch", "Left DAC" }, |
| 430 | { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, |
| 431 | { "Right Mixer", "Playback Switch", "Right DAC" }, |
| 432 | { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, |
| 433 | |
| 434 | { "DAC DIG", NULL, "DAC STM" }, |
| 435 | { "DAC DIG", NULL, "DAC Vref" }, |
| 436 | { "DAC DIG", NULL, "DAC DLL" }, |
| 437 | |
| 438 | { "Left DAC", NULL, "DAC DIG" }, |
| 439 | { "Right DAC", NULL, "DAC DIG" }, |
| 440 | |
| 441 | { "Left Out 1", NULL, "Left Mixer" }, |
| 442 | { "LOUT1", NULL, "Left Out 1" }, |
| 443 | { "Right Out 1", NULL, "Right Mixer" }, |
| 444 | { "ROUT1", NULL, "Right Out 1" }, |
| 445 | |
| 446 | { "Left Out 2", NULL, "Left Mixer" }, |
| 447 | { "LOUT2", NULL, "Left Out 2" }, |
| 448 | { "Right Out 2", NULL, "Right Mixer" }, |
| 449 | { "ROUT2", NULL, "Right Out 2" }, |
| 450 | }; |
| 451 | |
| 452 | static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction) |
| 453 | { |
| 454 | return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, |
| 455 | ES8328_DACCONTROL3_DACMUTE, |
| 456 | mute ? ES8328_DACCONTROL3_DACMUTE : 0); |
| 457 | } |
| 458 | |
| 459 | static int es8328_startup(struct snd_pcm_substream *substream, |
| 460 | struct snd_soc_dai *dai) |
| 461 | { |
| 462 | struct snd_soc_component *component = dai->component; |
| 463 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 464 | |
| 465 | if (es8328->master && es8328->sysclk_constraints) |
| 466 | snd_pcm_hw_constraint_list(substream->runtime, 0, |
| 467 | SNDRV_PCM_HW_PARAM_RATE, |
| 468 | es8328->sysclk_constraints); |
| 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | static int es8328_hw_params(struct snd_pcm_substream *substream, |
| 474 | struct snd_pcm_hw_params *params, |
| 475 | struct snd_soc_dai *dai) |
| 476 | { |
| 477 | struct snd_soc_component *component = dai->component; |
| 478 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 479 | int i; |
| 480 | int reg; |
| 481 | int wl; |
| 482 | int ratio; |
| 483 | |
| 484 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 485 | reg = ES8328_DACCONTROL2; |
| 486 | else |
| 487 | reg = ES8328_ADCCONTROL5; |
| 488 | |
| 489 | if (es8328->master) { |
| 490 | if (!es8328->sysclk_constraints) { |
| 491 | dev_err(component->dev, "No MCLK configured\n"); |
| 492 | return -EINVAL; |
| 493 | } |
| 494 | |
| 495 | for (i = 0; i < es8328->sysclk_constraints->count; i++) |
| 496 | if (es8328->sysclk_constraints->list[i] == |
| 497 | params_rate(params)) |
| 498 | break; |
| 499 | |
| 500 | if (i == es8328->sysclk_constraints->count) { |
| 501 | dev_err(component->dev, |
| 502 | "LRCLK %d unsupported with current clock\n", |
| 503 | params_rate(params)); |
| 504 | return -EINVAL; |
| 505 | } |
| 506 | ratio = es8328->mclk_ratios[i]; |
| 507 | } else { |
| 508 | ratio = 0; |
| 509 | es8328->mclkdiv2 = 0; |
| 510 | } |
| 511 | |
| 512 | snd_soc_component_update_bits(component, ES8328_MASTERMODE, |
| 513 | ES8328_MASTERMODE_MCLKDIV2, |
| 514 | es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); |
| 515 | |
| 516 | switch (params_width(params)) { |
| 517 | case 16: |
| 518 | wl = 3; |
| 519 | break; |
| 520 | case 18: |
| 521 | wl = 2; |
| 522 | break; |
| 523 | case 20: |
| 524 | wl = 1; |
| 525 | break; |
| 526 | case 24: |
| 527 | wl = 0; |
| 528 | break; |
| 529 | case 32: |
| 530 | wl = 4; |
| 531 | break; |
| 532 | default: |
| 533 | return -EINVAL; |
| 534 | } |
| 535 | |
| 536 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 537 | snd_soc_component_update_bits(component, ES8328_DACCONTROL1, |
| 538 | ES8328_DACCONTROL1_DACWL_MASK, |
| 539 | wl << ES8328_DACCONTROL1_DACWL_SHIFT); |
| 540 | |
| 541 | es8328->playback_fs = params_rate(params); |
| 542 | es8328_set_deemph(component); |
| 543 | } else |
| 544 | snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, |
| 545 | ES8328_ADCCONTROL4_ADCWL_MASK, |
| 546 | wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); |
| 547 | |
| 548 | return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio); |
| 549 | } |
| 550 | |
| 551 | static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, |
| 552 | int clk_id, unsigned int freq, int dir) |
| 553 | { |
| 554 | struct snd_soc_component *component = codec_dai->component; |
| 555 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 556 | int mclkdiv2 = 0; |
| 557 | |
| 558 | switch (freq) { |
| 559 | case 0: |
| 560 | es8328->sysclk_constraints = NULL; |
| 561 | es8328->mclk_ratios = NULL; |
| 562 | break; |
| 563 | case 22579200: |
| 564 | mclkdiv2 = 1; |
| 565 | fallthrough; |
| 566 | case 11289600: |
| 567 | es8328->sysclk_constraints = &constraints_11289; |
| 568 | es8328->mclk_ratios = ratios_11289; |
| 569 | break; |
| 570 | case 24576000: |
| 571 | mclkdiv2 = 1; |
| 572 | fallthrough; |
| 573 | case 12288000: |
| 574 | es8328->sysclk_constraints = &constraints_12288; |
| 575 | es8328->mclk_ratios = ratios_12288; |
| 576 | break; |
| 577 | default: |
| 578 | return -EINVAL; |
| 579 | } |
| 580 | |
| 581 | es8328->mclkdiv2 = mclkdiv2; |
| 582 | return 0; |
| 583 | } |
| 584 | |
| 585 | static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, |
| 586 | unsigned int fmt) |
| 587 | { |
| 588 | struct snd_soc_component *component = codec_dai->component; |
| 589 | struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); |
| 590 | u8 dac_mode = 0; |
| 591 | u8 adc_mode = 0; |
| 592 | |
| 593 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 594 | case SND_SOC_DAIFMT_CBM_CFM: |
| 595 | /* Master serial port mode, with BCLK generated automatically */ |
| 596 | snd_soc_component_update_bits(component, ES8328_MASTERMODE, |
| 597 | ES8328_MASTERMODE_MSC, |
| 598 | ES8328_MASTERMODE_MSC); |
| 599 | es8328->master = true; |
| 600 | break; |
| 601 | case SND_SOC_DAIFMT_CBS_CFS: |
| 602 | /* Slave serial port mode */ |
| 603 | snd_soc_component_update_bits(component, ES8328_MASTERMODE, |
| 604 | ES8328_MASTERMODE_MSC, 0); |
| 605 | es8328->master = false; |
| 606 | break; |
| 607 | default: |
| 608 | return -EINVAL; |
| 609 | } |
| 610 | |
| 611 | /* interface format */ |
| 612 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 613 | case SND_SOC_DAIFMT_I2S: |
| 614 | dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; |
| 615 | adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; |
| 616 | break; |
| 617 | case SND_SOC_DAIFMT_RIGHT_J: |
| 618 | dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; |
| 619 | adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; |
| 620 | break; |
| 621 | case SND_SOC_DAIFMT_LEFT_J: |
| 622 | dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; |
| 623 | adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; |
| 624 | break; |
| 625 | default: |
| 626 | return -EINVAL; |
| 627 | } |
| 628 | |
| 629 | /* clock inversion */ |
| 630 | if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) |
| 631 | return -EINVAL; |
| 632 | |
| 633 | snd_soc_component_update_bits(component, ES8328_DACCONTROL1, |
| 634 | ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode); |
| 635 | snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, |
| 636 | ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode); |
| 637 | |
| 638 | return 0; |
| 639 | } |
| 640 | |
| 641 | static int es8328_set_bias_level(struct snd_soc_component *component, |
| 642 | enum snd_soc_bias_level level) |
| 643 | { |
| 644 | switch (level) { |
| 645 | case SND_SOC_BIAS_ON: |
| 646 | break; |
| 647 | |
| 648 | case SND_SOC_BIAS_PREPARE: |
| 649 | /* VREF, VMID=2x50k, digital enabled */ |
| 650 | snd_soc_component_write(component, ES8328_CHIPPOWER, 0); |
| 651 | snd_soc_component_update_bits(component, ES8328_CONTROL1, |
| 652 | ES8328_CONTROL1_VMIDSEL_MASK | |
| 653 | ES8328_CONTROL1_ENREF, |
| 654 | ES8328_CONTROL1_VMIDSEL_50k | |
| 655 | ES8328_CONTROL1_ENREF); |
| 656 | break; |
| 657 | |
| 658 | case SND_SOC_BIAS_STANDBY: |
| 659 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
| 660 | snd_soc_component_update_bits(component, ES8328_CONTROL1, |
| 661 | ES8328_CONTROL1_VMIDSEL_MASK | |
| 662 | ES8328_CONTROL1_ENREF, |
| 663 | ES8328_CONTROL1_VMIDSEL_5k | |
| 664 | ES8328_CONTROL1_ENREF); |
| 665 | |
| 666 | /* Charge caps */ |
| 667 | msleep(100); |
| 668 | } |
| 669 | |
| 670 | snd_soc_component_write(component, ES8328_CONTROL2, |
| 671 | ES8328_CONTROL2_OVERCURRENT_ON | |
| 672 | ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); |
| 673 | |
| 674 | /* VREF, VMID=2*500k, digital stopped */ |
| 675 | snd_soc_component_update_bits(component, ES8328_CONTROL1, |
| 676 | ES8328_CONTROL1_VMIDSEL_MASK | |
| 677 | ES8328_CONTROL1_ENREF, |
| 678 | ES8328_CONTROL1_VMIDSEL_500k | |
| 679 | ES8328_CONTROL1_ENREF); |
| 680 | break; |
| 681 | |
| 682 | case SND_SOC_BIAS_OFF: |
| 683 | snd_soc_component_update_bits(component, ES8328_CONTROL1, |
| 684 | ES8328_CONTROL1_VMIDSEL_MASK | |
| 685 | ES8328_CONTROL1_ENREF, |
| 686 | 0); |
| 687 | break; |
| 688 | } |
| 689 | return 0; |
| 690 | } |
| 691 | |
| 692 | static const struct snd_soc_dai_ops es8328_dai_ops = { |
| 693 | .startup = es8328_startup, |
| 694 | .hw_params = es8328_hw_params, |
| 695 | .mute_stream = es8328_mute, |
| 696 | .set_sysclk = es8328_set_sysclk, |
| 697 | .set_fmt = es8328_set_dai_fmt, |
| 698 | .no_capture_mute = 1, |
| 699 | }; |
| 700 | |
| 701 | static struct snd_soc_dai_driver es8328_dai = { |
| 702 | .name = "es8328-hifi-analog", |
| 703 | .playback = { |
| 704 | .stream_name = "Playback", |
| 705 | .channels_min = 2, |
| 706 | .channels_max = 2, |
| 707 | .rates = ES8328_RATES, |
| 708 | .formats = ES8328_FORMATS, |
| 709 | }, |
| 710 | .capture = { |
| 711 | .stream_name = "Capture", |
| 712 | .channels_min = 2, |
| 713 | .channels_max = 2, |
| 714 | .rates = ES8328_RATES, |
| 715 | .formats = ES8328_FORMATS, |
| 716 | }, |
| 717 | .ops = &es8328_dai_ops, |
| 718 | .symmetric_rate = 1, |
| 719 | }; |
| 720 | |
| 721 | static int es8328_suspend(struct snd_soc_component *component) |
| 722 | { |
| 723 | struct es8328_priv *es8328; |
| 724 | int ret; |
| 725 | |
| 726 | es8328 = snd_soc_component_get_drvdata(component); |
| 727 | |
| 728 | clk_disable_unprepare(es8328->clk); |
| 729 | |
| 730 | ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), |
| 731 | es8328->supplies); |
| 732 | if (ret) { |
| 733 | dev_err(component->dev, "unable to disable regulators\n"); |
| 734 | return ret; |
| 735 | } |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | static int es8328_resume(struct snd_soc_component *component) |
| 740 | { |
| 741 | struct regmap *regmap = dev_get_regmap(component->dev, NULL); |
| 742 | struct es8328_priv *es8328; |
| 743 | int ret; |
| 744 | |
| 745 | es8328 = snd_soc_component_get_drvdata(component); |
| 746 | |
| 747 | ret = clk_prepare_enable(es8328->clk); |
| 748 | if (ret) { |
| 749 | dev_err(component->dev, "unable to enable clock\n"); |
| 750 | return ret; |
| 751 | } |
| 752 | |
| 753 | ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), |
| 754 | es8328->supplies); |
| 755 | if (ret) { |
| 756 | dev_err(component->dev, "unable to enable regulators\n"); |
| 757 | return ret; |
| 758 | } |
| 759 | |
| 760 | regcache_mark_dirty(regmap); |
| 761 | ret = regcache_sync(regmap); |
| 762 | if (ret) { |
| 763 | dev_err(component->dev, "unable to sync regcache\n"); |
| 764 | return ret; |
| 765 | } |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
| 770 | static int es8328_component_probe(struct snd_soc_component *component) |
| 771 | { |
| 772 | struct es8328_priv *es8328; |
| 773 | int ret; |
| 774 | |
| 775 | es8328 = snd_soc_component_get_drvdata(component); |
| 776 | |
| 777 | ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), |
| 778 | es8328->supplies); |
| 779 | if (ret) { |
| 780 | dev_err(component->dev, "unable to enable regulators\n"); |
| 781 | return ret; |
| 782 | } |
| 783 | |
| 784 | /* Setup clocks */ |
| 785 | es8328->clk = devm_clk_get(component->dev, NULL); |
| 786 | if (IS_ERR(es8328->clk)) { |
| 787 | dev_err(component->dev, "codec clock missing or invalid\n"); |
| 788 | ret = PTR_ERR(es8328->clk); |
| 789 | goto clk_fail; |
| 790 | } |
| 791 | |
| 792 | ret = clk_prepare_enable(es8328->clk); |
| 793 | if (ret) { |
| 794 | dev_err(component->dev, "unable to prepare codec clk\n"); |
| 795 | goto clk_fail; |
| 796 | } |
| 797 | |
| 798 | return 0; |
| 799 | |
| 800 | clk_fail: |
| 801 | regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), |
| 802 | es8328->supplies); |
| 803 | return ret; |
| 804 | } |
| 805 | |
| 806 | static void es8328_remove(struct snd_soc_component *component) |
| 807 | { |
| 808 | struct es8328_priv *es8328; |
| 809 | |
| 810 | es8328 = snd_soc_component_get_drvdata(component); |
| 811 | |
| 812 | clk_disable_unprepare(es8328->clk); |
| 813 | |
| 814 | regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), |
| 815 | es8328->supplies); |
| 816 | } |
| 817 | |
| 818 | const struct regmap_config es8328_regmap_config = { |
| 819 | .reg_bits = 8, |
| 820 | .val_bits = 8, |
| 821 | .max_register = ES8328_REG_MAX, |
| 822 | .cache_type = REGCACHE_RBTREE, |
| 823 | .use_single_read = true, |
| 824 | .use_single_write = true, |
| 825 | }; |
| 826 | EXPORT_SYMBOL_GPL(es8328_regmap_config); |
| 827 | |
| 828 | static const struct snd_soc_component_driver es8328_component_driver = { |
| 829 | .probe = es8328_component_probe, |
| 830 | .remove = es8328_remove, |
| 831 | .suspend = es8328_suspend, |
| 832 | .resume = es8328_resume, |
| 833 | .set_bias_level = es8328_set_bias_level, |
| 834 | .controls = es8328_snd_controls, |
| 835 | .num_controls = ARRAY_SIZE(es8328_snd_controls), |
| 836 | .dapm_widgets = es8328_dapm_widgets, |
| 837 | .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), |
| 838 | .dapm_routes = es8328_dapm_routes, |
| 839 | .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), |
| 840 | .suspend_bias_off = 1, |
| 841 | .idle_bias_on = 1, |
| 842 | .use_pmdown_time = 1, |
| 843 | .endianness = 1, |
| 844 | .non_legacy_dai_naming = 1, |
| 845 | }; |
| 846 | |
| 847 | int es8328_probe(struct device *dev, struct regmap *regmap) |
| 848 | { |
| 849 | struct es8328_priv *es8328; |
| 850 | int ret; |
| 851 | int i; |
| 852 | |
| 853 | if (IS_ERR(regmap)) |
| 854 | return PTR_ERR(regmap); |
| 855 | |
| 856 | es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); |
| 857 | if (es8328 == NULL) |
| 858 | return -ENOMEM; |
| 859 | |
| 860 | es8328->regmap = regmap; |
| 861 | |
| 862 | for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) |
| 863 | es8328->supplies[i].supply = supply_names[i]; |
| 864 | |
| 865 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), |
| 866 | es8328->supplies); |
| 867 | if (ret) { |
| 868 | dev_err(dev, "unable to get regulators\n"); |
| 869 | return ret; |
| 870 | } |
| 871 | |
| 872 | dev_set_drvdata(dev, es8328); |
| 873 | |
| 874 | return devm_snd_soc_register_component(dev, |
| 875 | &es8328_component_driver, &es8328_dai, 1); |
| 876 | } |
| 877 | EXPORT_SYMBOL_GPL(es8328_probe); |
| 878 | |
| 879 | MODULE_DESCRIPTION("ASoC ES8328 driver"); |
| 880 | MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); |
| 881 | MODULE_LICENSE("GPL"); |