| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces |
| 4 | * |
| 5 | * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>, |
| 6 | * Pilo Chambert <pilo.c@wanadoo.fr> |
| 7 | * |
| 8 | * Thanks to : Anders Torger <torger@ludd.luth.se>, |
| 9 | * Henk Hesselink <henk@anda.nl> |
| 10 | * for writing the digi96-driver |
| 11 | * and RME for all informations. |
| 12 | * |
| 13 | * **************************************************************************** |
| 14 | * |
| 15 | * Note #1 "Sek'd models" ................................... martin 2002-12-07 |
| 16 | * |
| 17 | * Identical soundcards by Sek'd were labeled: |
| 18 | * RME Digi 32 = Sek'd Prodif 32 |
| 19 | * RME Digi 32 Pro = Sek'd Prodif 96 |
| 20 | * RME Digi 32/8 = Sek'd Prodif Gold |
| 21 | * |
| 22 | * **************************************************************************** |
| 23 | * |
| 24 | * Note #2 "full duplex mode" ............................... martin 2002-12-07 |
| 25 | * |
| 26 | * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical |
| 27 | * in this mode. Rec data and play data are using the same buffer therefore. At |
| 28 | * first you have got the playing bits in the buffer and then (after playing |
| 29 | * them) they were overwitten by the captured sound of the CS8412/14. Both |
| 30 | * modes (play/record) are running harmonically hand in hand in the same buffer |
| 31 | * and you have only one start bit plus one interrupt bit to control this |
| 32 | * paired action. |
| 33 | * This is opposite to the latter rme96 where playing and capturing is totally |
| 34 | * separated and so their full duplex mode is supported by alsa (using two |
| 35 | * start bits and two interrupts for two different buffers). |
| 36 | * But due to the wrong sequence of playing and capturing ALSA shows no solved |
| 37 | * full duplex support for the rme32 at the moment. That's bad, but I'm not |
| 38 | * able to solve it. Are you motivated enough to solve this problem now? Your |
| 39 | * patch would be welcome! |
| 40 | * |
| 41 | * **************************************************************************** |
| 42 | * |
| 43 | * "The story after the long seeking" -- tiwai |
| 44 | * |
| 45 | * Ok, the situation regarding the full duplex is now improved a bit. |
| 46 | * In the fullduplex mode (given by the module parameter), the hardware buffer |
| 47 | * is split to halves for read and write directions at the DMA pointer. |
| 48 | * That is, the half above the current DMA pointer is used for write, and |
| 49 | * the half below is used for read. To mangle this strange behavior, an |
| 50 | * software intermediate buffer is introduced. This is, of course, not good |
| 51 | * from the viewpoint of the data transfer efficiency. However, this allows |
| 52 | * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. |
| 53 | * |
| 54 | * **************************************************************************** |
| 55 | */ |
| 56 | |
| 57 | |
| 58 | #include <linux/delay.h> |
| 59 | #include <linux/gfp.h> |
| 60 | #include <linux/init.h> |
| 61 | #include <linux/interrupt.h> |
| 62 | #include <linux/pci.h> |
| 63 | #include <linux/module.h> |
| 64 | #include <linux/io.h> |
| 65 | |
| 66 | #include <sound/core.h> |
| 67 | #include <sound/info.h> |
| 68 | #include <sound/control.h> |
| 69 | #include <sound/pcm.h> |
| 70 | #include <sound/pcm_params.h> |
| 71 | #include <sound/pcm-indirect.h> |
| 72 | #include <sound/asoundef.h> |
| 73 | #include <sound/initval.h> |
| 74 | |
| 75 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
| 76 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
| 77 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
| 78 | static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; |
| 79 | |
| 80 | module_param_array(index, int, NULL, 0444); |
| 81 | MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); |
| 82 | module_param_array(id, charp, NULL, 0444); |
| 83 | MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); |
| 84 | module_param_array(enable, bool, NULL, 0444); |
| 85 | MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); |
| 86 | module_param_array(fullduplex, bool, NULL, 0444); |
| 87 | MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); |
| 88 | MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>"); |
| 89 | MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); |
| 90 | MODULE_LICENSE("GPL"); |
| 91 | |
| 92 | /* Defines for RME Digi32 series */ |
| 93 | #define RME32_SPDIF_NCHANNELS 2 |
| 94 | |
| 95 | /* Playback and capture buffer size */ |
| 96 | #define RME32_BUFFER_SIZE 0x20000 |
| 97 | |
| 98 | /* IO area size */ |
| 99 | #define RME32_IO_SIZE 0x30000 |
| 100 | |
| 101 | /* IO area offsets */ |
| 102 | #define RME32_IO_DATA_BUFFER 0x0 |
| 103 | #define RME32_IO_CONTROL_REGISTER 0x20000 |
| 104 | #define RME32_IO_GET_POS 0x20000 |
| 105 | #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 |
| 106 | #define RME32_IO_RESET_POS 0x20100 |
| 107 | |
| 108 | /* Write control register bits */ |
| 109 | #define RME32_WCR_START (1 << 0) /* startbit */ |
| 110 | #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono |
| 111 | Setting the whole card to mono |
| 112 | doesn't seem to be very useful. |
| 113 | A software-solution can handle |
| 114 | full-duplex with one direction in |
| 115 | stereo and the other way in mono. |
| 116 | So, the hardware should work all |
| 117 | the time in stereo! */ |
| 118 | #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ |
| 119 | #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ |
| 120 | #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ |
| 121 | #define RME32_WCR_FREQ_1 (1 << 5) |
| 122 | #define RME32_WCR_INP_0 (1 << 6) /* input switch */ |
| 123 | #define RME32_WCR_INP_1 (1 << 7) |
| 124 | #define RME32_WCR_RESET (1 << 8) /* Reset address */ |
| 125 | #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ |
| 126 | #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ |
| 127 | #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ |
| 128 | #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ |
| 129 | #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ |
| 130 | #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ |
| 131 | #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ |
| 132 | |
| 133 | #define RME32_WCR_BITPOS_FREQ_0 4 |
| 134 | #define RME32_WCR_BITPOS_FREQ_1 5 |
| 135 | #define RME32_WCR_BITPOS_INP_0 6 |
| 136 | #define RME32_WCR_BITPOS_INP_1 7 |
| 137 | |
| 138 | /* Read control register bits */ |
| 139 | #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff |
| 140 | #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ |
| 141 | #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ |
| 142 | #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ |
| 143 | #define RME32_RCR_FREQ_1 (1 << 28) |
| 144 | #define RME32_RCR_FREQ_2 (1 << 29) |
| 145 | #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ |
| 146 | #define RME32_RCR_IRQ (1 << 31) /* interrupt */ |
| 147 | |
| 148 | #define RME32_RCR_BITPOS_F0 27 |
| 149 | #define RME32_RCR_BITPOS_F1 28 |
| 150 | #define RME32_RCR_BITPOS_F2 29 |
| 151 | |
| 152 | /* Input types */ |
| 153 | #define RME32_INPUT_OPTICAL 0 |
| 154 | #define RME32_INPUT_COAXIAL 1 |
| 155 | #define RME32_INPUT_INTERNAL 2 |
| 156 | #define RME32_INPUT_XLR 3 |
| 157 | |
| 158 | /* Clock modes */ |
| 159 | #define RME32_CLOCKMODE_SLAVE 0 |
| 160 | #define RME32_CLOCKMODE_MASTER_32 1 |
| 161 | #define RME32_CLOCKMODE_MASTER_44 2 |
| 162 | #define RME32_CLOCKMODE_MASTER_48 3 |
| 163 | |
| 164 | /* Block sizes in bytes */ |
| 165 | #define RME32_BLOCK_SIZE 8192 |
| 166 | |
| 167 | /* Software intermediate buffer (max) size */ |
| 168 | #define RME32_MID_BUFFER_SIZE (1024*1024) |
| 169 | |
| 170 | /* Hardware revisions */ |
| 171 | #define RME32_32_REVISION 192 |
| 172 | #define RME32_328_REVISION_OLD 100 |
| 173 | #define RME32_328_REVISION_NEW 101 |
| 174 | #define RME32_PRO_REVISION_WITH_8412 192 |
| 175 | #define RME32_PRO_REVISION_WITH_8414 150 |
| 176 | |
| 177 | |
| 178 | struct rme32 { |
| 179 | spinlock_t lock; |
| 180 | int irq; |
| 181 | unsigned long port; |
| 182 | void __iomem *iobase; |
| 183 | |
| 184 | u32 wcreg; /* cached write control register value */ |
| 185 | u32 wcreg_spdif; /* S/PDIF setup */ |
| 186 | u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ |
| 187 | u32 rcreg; /* cached read control register value */ |
| 188 | |
| 189 | u8 rev; /* card revision number */ |
| 190 | |
| 191 | struct snd_pcm_substream *playback_substream; |
| 192 | struct snd_pcm_substream *capture_substream; |
| 193 | |
| 194 | int playback_frlog; /* log2 of framesize */ |
| 195 | int capture_frlog; |
| 196 | |
| 197 | size_t playback_periodsize; /* in bytes, zero if not used */ |
| 198 | size_t capture_periodsize; /* in bytes, zero if not used */ |
| 199 | |
| 200 | unsigned int fullduplex_mode; |
| 201 | int running; |
| 202 | |
| 203 | struct snd_pcm_indirect playback_pcm; |
| 204 | struct snd_pcm_indirect capture_pcm; |
| 205 | |
| 206 | struct snd_card *card; |
| 207 | struct snd_pcm *spdif_pcm; |
| 208 | struct snd_pcm *adat_pcm; |
| 209 | struct pci_dev *pci; |
| 210 | struct snd_kcontrol *spdif_ctl; |
| 211 | }; |
| 212 | |
| 213 | static const struct pci_device_id snd_rme32_ids[] = { |
| 214 | {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,}, |
| 215 | {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,}, |
| 216 | {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,}, |
| 217 | {0,} |
| 218 | }; |
| 219 | |
| 220 | MODULE_DEVICE_TABLE(pci, snd_rme32_ids); |
| 221 | |
| 222 | #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) |
| 223 | #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) |
| 224 | |
| 225 | static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); |
| 226 | |
| 227 | static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); |
| 228 | |
| 229 | static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); |
| 230 | |
| 231 | static void snd_rme32_proc_init(struct rme32 * rme32); |
| 232 | |
| 233 | static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); |
| 234 | |
| 235 | static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) |
| 236 | { |
| 237 | return (readl(rme32->iobase + RME32_IO_GET_POS) |
| 238 | & RME32_RCR_AUDIO_ADDR_MASK); |
| 239 | } |
| 240 | |
| 241 | /* silence callback for halfduplex mode */ |
| 242 | static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, |
| 243 | int channel, unsigned long pos, |
| 244 | unsigned long count) |
| 245 | { |
| 246 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 247 | |
| 248 | memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | /* copy callback for halfduplex mode */ |
| 253 | static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, |
| 254 | int channel, unsigned long pos, |
| 255 | struct iov_iter *src, unsigned long count) |
| 256 | { |
| 257 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 258 | |
| 259 | return copy_from_iter_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, |
| 260 | src, count); |
| 261 | } |
| 262 | |
| 263 | /* copy callback for halfduplex mode */ |
| 264 | static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, |
| 265 | int channel, unsigned long pos, |
| 266 | struct iov_iter *dst, unsigned long count) |
| 267 | { |
| 268 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 269 | |
| 270 | return copy_to_iter_fromio(dst, |
| 271 | rme32->iobase + RME32_IO_DATA_BUFFER + pos, |
| 272 | count); |
| 273 | } |
| 274 | |
| 275 | /* |
| 276 | * SPDIF I/O capabilities (half-duplex mode) |
| 277 | */ |
| 278 | static const struct snd_pcm_hardware snd_rme32_spdif_info = { |
| 279 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
| 280 | SNDRV_PCM_INFO_MMAP_VALID | |
| 281 | SNDRV_PCM_INFO_INTERLEAVED | |
| 282 | SNDRV_PCM_INFO_PAUSE | |
| 283 | SNDRV_PCM_INFO_SYNC_START | |
| 284 | SNDRV_PCM_INFO_SYNC_APPLPTR), |
| 285 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
| 286 | SNDRV_PCM_FMTBIT_S32_LE), |
| 287 | .rates = (SNDRV_PCM_RATE_32000 | |
| 288 | SNDRV_PCM_RATE_44100 | |
| 289 | SNDRV_PCM_RATE_48000), |
| 290 | .rate_min = 32000, |
| 291 | .rate_max = 48000, |
| 292 | .channels_min = 2, |
| 293 | .channels_max = 2, |
| 294 | .buffer_bytes_max = RME32_BUFFER_SIZE, |
| 295 | .period_bytes_min = RME32_BLOCK_SIZE, |
| 296 | .period_bytes_max = RME32_BLOCK_SIZE, |
| 297 | .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, |
| 298 | .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, |
| 299 | .fifo_size = 0, |
| 300 | }; |
| 301 | |
| 302 | /* |
| 303 | * ADAT I/O capabilities (half-duplex mode) |
| 304 | */ |
| 305 | static const struct snd_pcm_hardware snd_rme32_adat_info = |
| 306 | { |
| 307 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
| 308 | SNDRV_PCM_INFO_MMAP_VALID | |
| 309 | SNDRV_PCM_INFO_INTERLEAVED | |
| 310 | SNDRV_PCM_INFO_PAUSE | |
| 311 | SNDRV_PCM_INFO_SYNC_START | |
| 312 | SNDRV_PCM_INFO_SYNC_APPLPTR), |
| 313 | .formats= SNDRV_PCM_FMTBIT_S16_LE, |
| 314 | .rates = (SNDRV_PCM_RATE_44100 | |
| 315 | SNDRV_PCM_RATE_48000), |
| 316 | .rate_min = 44100, |
| 317 | .rate_max = 48000, |
| 318 | .channels_min = 8, |
| 319 | .channels_max = 8, |
| 320 | .buffer_bytes_max = RME32_BUFFER_SIZE, |
| 321 | .period_bytes_min = RME32_BLOCK_SIZE, |
| 322 | .period_bytes_max = RME32_BLOCK_SIZE, |
| 323 | .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, |
| 324 | .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, |
| 325 | .fifo_size = 0, |
| 326 | }; |
| 327 | |
| 328 | /* |
| 329 | * SPDIF I/O capabilities (full-duplex mode) |
| 330 | */ |
| 331 | static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = { |
| 332 | .info = (SNDRV_PCM_INFO_MMAP | |
| 333 | SNDRV_PCM_INFO_MMAP_VALID | |
| 334 | SNDRV_PCM_INFO_INTERLEAVED | |
| 335 | SNDRV_PCM_INFO_PAUSE | |
| 336 | SNDRV_PCM_INFO_SYNC_START | |
| 337 | SNDRV_PCM_INFO_SYNC_APPLPTR), |
| 338 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
| 339 | SNDRV_PCM_FMTBIT_S32_LE), |
| 340 | .rates = (SNDRV_PCM_RATE_32000 | |
| 341 | SNDRV_PCM_RATE_44100 | |
| 342 | SNDRV_PCM_RATE_48000), |
| 343 | .rate_min = 32000, |
| 344 | .rate_max = 48000, |
| 345 | .channels_min = 2, |
| 346 | .channels_max = 2, |
| 347 | .buffer_bytes_max = RME32_MID_BUFFER_SIZE, |
| 348 | .period_bytes_min = RME32_BLOCK_SIZE, |
| 349 | .period_bytes_max = RME32_BLOCK_SIZE, |
| 350 | .periods_min = 2, |
| 351 | .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, |
| 352 | .fifo_size = 0, |
| 353 | }; |
| 354 | |
| 355 | /* |
| 356 | * ADAT I/O capabilities (full-duplex mode) |
| 357 | */ |
| 358 | static const struct snd_pcm_hardware snd_rme32_adat_fd_info = |
| 359 | { |
| 360 | .info = (SNDRV_PCM_INFO_MMAP | |
| 361 | SNDRV_PCM_INFO_MMAP_VALID | |
| 362 | SNDRV_PCM_INFO_INTERLEAVED | |
| 363 | SNDRV_PCM_INFO_PAUSE | |
| 364 | SNDRV_PCM_INFO_SYNC_START | |
| 365 | SNDRV_PCM_INFO_SYNC_APPLPTR), |
| 366 | .formats= SNDRV_PCM_FMTBIT_S16_LE, |
| 367 | .rates = (SNDRV_PCM_RATE_44100 | |
| 368 | SNDRV_PCM_RATE_48000), |
| 369 | .rate_min = 44100, |
| 370 | .rate_max = 48000, |
| 371 | .channels_min = 8, |
| 372 | .channels_max = 8, |
| 373 | .buffer_bytes_max = RME32_MID_BUFFER_SIZE, |
| 374 | .period_bytes_min = RME32_BLOCK_SIZE, |
| 375 | .period_bytes_max = RME32_BLOCK_SIZE, |
| 376 | .periods_min = 2, |
| 377 | .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, |
| 378 | .fifo_size = 0, |
| 379 | }; |
| 380 | |
| 381 | static void snd_rme32_reset_dac(struct rme32 *rme32) |
| 382 | { |
| 383 | writel(rme32->wcreg | RME32_WCR_PD, |
| 384 | rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 385 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 386 | } |
| 387 | |
| 388 | static int snd_rme32_playback_getrate(struct rme32 * rme32) |
| 389 | { |
| 390 | int rate; |
| 391 | |
| 392 | rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + |
| 393 | (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); |
| 394 | switch (rate) { |
| 395 | case 1: |
| 396 | rate = 32000; |
| 397 | break; |
| 398 | case 2: |
| 399 | rate = 44100; |
| 400 | break; |
| 401 | case 3: |
| 402 | rate = 48000; |
| 403 | break; |
| 404 | default: |
| 405 | return -1; |
| 406 | } |
| 407 | return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; |
| 408 | } |
| 409 | |
| 410 | static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) |
| 411 | { |
| 412 | int n; |
| 413 | |
| 414 | *is_adat = 0; |
| 415 | if (rme32->rcreg & RME32_RCR_LOCK) { |
| 416 | /* ADAT rate */ |
| 417 | *is_adat = 1; |
| 418 | } |
| 419 | if (rme32->rcreg & RME32_RCR_ERF) { |
| 420 | return -1; |
| 421 | } |
| 422 | |
| 423 | /* S/PDIF rate */ |
| 424 | n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + |
| 425 | (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + |
| 426 | (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); |
| 427 | |
| 428 | if (RME32_PRO_WITH_8414(rme32)) |
| 429 | switch (n) { /* supporting the CS8414 */ |
| 430 | case 0: |
| 431 | case 1: |
| 432 | case 2: |
| 433 | return -1; |
| 434 | case 3: |
| 435 | return 96000; |
| 436 | case 4: |
| 437 | return 88200; |
| 438 | case 5: |
| 439 | return 48000; |
| 440 | case 6: |
| 441 | return 44100; |
| 442 | case 7: |
| 443 | return 32000; |
| 444 | default: |
| 445 | return -1; |
| 446 | } |
| 447 | else |
| 448 | switch (n) { /* supporting the CS8412 */ |
| 449 | case 0: |
| 450 | return -1; |
| 451 | case 1: |
| 452 | return 48000; |
| 453 | case 2: |
| 454 | return 44100; |
| 455 | case 3: |
| 456 | return 32000; |
| 457 | case 4: |
| 458 | return 48000; |
| 459 | case 5: |
| 460 | return 44100; |
| 461 | case 6: |
| 462 | return 44056; |
| 463 | case 7: |
| 464 | return 32000; |
| 465 | default: |
| 466 | break; |
| 467 | } |
| 468 | return -1; |
| 469 | } |
| 470 | |
| 471 | static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) |
| 472 | { |
| 473 | int ds; |
| 474 | |
| 475 | ds = rme32->wcreg & RME32_WCR_DS_BM; |
| 476 | switch (rate) { |
| 477 | case 32000: |
| 478 | rme32->wcreg &= ~RME32_WCR_DS_BM; |
| 479 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & |
| 480 | ~RME32_WCR_FREQ_1; |
| 481 | break; |
| 482 | case 44100: |
| 483 | rme32->wcreg &= ~RME32_WCR_DS_BM; |
| 484 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & |
| 485 | ~RME32_WCR_FREQ_0; |
| 486 | break; |
| 487 | case 48000: |
| 488 | rme32->wcreg &= ~RME32_WCR_DS_BM; |
| 489 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | |
| 490 | RME32_WCR_FREQ_1; |
| 491 | break; |
| 492 | case 64000: |
| 493 | if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) |
| 494 | return -EINVAL; |
| 495 | rme32->wcreg |= RME32_WCR_DS_BM; |
| 496 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & |
| 497 | ~RME32_WCR_FREQ_1; |
| 498 | break; |
| 499 | case 88200: |
| 500 | if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) |
| 501 | return -EINVAL; |
| 502 | rme32->wcreg |= RME32_WCR_DS_BM; |
| 503 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & |
| 504 | ~RME32_WCR_FREQ_0; |
| 505 | break; |
| 506 | case 96000: |
| 507 | if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) |
| 508 | return -EINVAL; |
| 509 | rme32->wcreg |= RME32_WCR_DS_BM; |
| 510 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | |
| 511 | RME32_WCR_FREQ_1; |
| 512 | break; |
| 513 | default: |
| 514 | return -EINVAL; |
| 515 | } |
| 516 | if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || |
| 517 | (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) |
| 518 | { |
| 519 | /* change to/from double-speed: reset the DAC (if available) */ |
| 520 | snd_rme32_reset_dac(rme32); |
| 521 | } else { |
| 522 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 523 | } |
| 524 | return 0; |
| 525 | } |
| 526 | |
| 527 | static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) |
| 528 | { |
| 529 | switch (mode) { |
| 530 | case RME32_CLOCKMODE_SLAVE: |
| 531 | /* AutoSync */ |
| 532 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & |
| 533 | ~RME32_WCR_FREQ_1; |
| 534 | break; |
| 535 | case RME32_CLOCKMODE_MASTER_32: |
| 536 | /* Internal 32.0kHz */ |
| 537 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & |
| 538 | ~RME32_WCR_FREQ_1; |
| 539 | break; |
| 540 | case RME32_CLOCKMODE_MASTER_44: |
| 541 | /* Internal 44.1kHz */ |
| 542 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | |
| 543 | RME32_WCR_FREQ_1; |
| 544 | break; |
| 545 | case RME32_CLOCKMODE_MASTER_48: |
| 546 | /* Internal 48.0kHz */ |
| 547 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | |
| 548 | RME32_WCR_FREQ_1; |
| 549 | break; |
| 550 | default: |
| 551 | return -EINVAL; |
| 552 | } |
| 553 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | static int snd_rme32_getclockmode(struct rme32 * rme32) |
| 558 | { |
| 559 | return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + |
| 560 | (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); |
| 561 | } |
| 562 | |
| 563 | static int snd_rme32_setinputtype(struct rme32 * rme32, int type) |
| 564 | { |
| 565 | switch (type) { |
| 566 | case RME32_INPUT_OPTICAL: |
| 567 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & |
| 568 | ~RME32_WCR_INP_1; |
| 569 | break; |
| 570 | case RME32_INPUT_COAXIAL: |
| 571 | rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & |
| 572 | ~RME32_WCR_INP_1; |
| 573 | break; |
| 574 | case RME32_INPUT_INTERNAL: |
| 575 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | |
| 576 | RME32_WCR_INP_1; |
| 577 | break; |
| 578 | case RME32_INPUT_XLR: |
| 579 | rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | |
| 580 | RME32_WCR_INP_1; |
| 581 | break; |
| 582 | default: |
| 583 | return -EINVAL; |
| 584 | } |
| 585 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | static int snd_rme32_getinputtype(struct rme32 * rme32) |
| 590 | { |
| 591 | return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + |
| 592 | (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); |
| 593 | } |
| 594 | |
| 595 | static void |
| 596 | snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) |
| 597 | { |
| 598 | int frlog; |
| 599 | |
| 600 | if (n_channels == 2) { |
| 601 | frlog = 1; |
| 602 | } else { |
| 603 | /* assume 8 channels */ |
| 604 | frlog = 3; |
| 605 | } |
| 606 | if (is_playback) { |
| 607 | frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; |
| 608 | rme32->playback_frlog = frlog; |
| 609 | } else { |
| 610 | frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; |
| 611 | rme32->capture_frlog = frlog; |
| 612 | } |
| 613 | } |
| 614 | |
| 615 | static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format) |
| 616 | { |
| 617 | switch (format) { |
| 618 | case SNDRV_PCM_FORMAT_S16_LE: |
| 619 | rme32->wcreg &= ~RME32_WCR_MODE24; |
| 620 | break; |
| 621 | case SNDRV_PCM_FORMAT_S32_LE: |
| 622 | rme32->wcreg |= RME32_WCR_MODE24; |
| 623 | break; |
| 624 | default: |
| 625 | return -EINVAL; |
| 626 | } |
| 627 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 628 | return 0; |
| 629 | } |
| 630 | |
| 631 | static int |
| 632 | snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, |
| 633 | struct snd_pcm_hw_params *params) |
| 634 | { |
| 635 | int err, rate, dummy; |
| 636 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 637 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 638 | |
| 639 | if (!rme32->fullduplex_mode) { |
| 640 | runtime->dma_area = (void __force *)(rme32->iobase + |
| 641 | RME32_IO_DATA_BUFFER); |
| 642 | runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; |
| 643 | runtime->dma_bytes = RME32_BUFFER_SIZE; |
| 644 | } |
| 645 | |
| 646 | spin_lock_irq(&rme32->lock); |
| 647 | rate = 0; |
| 648 | if (rme32->rcreg & RME32_RCR_KMODE) |
| 649 | rate = snd_rme32_capture_getrate(rme32, &dummy); |
| 650 | if (rate > 0) { |
| 651 | /* AutoSync */ |
| 652 | if ((int)params_rate(params) != rate) { |
| 653 | spin_unlock_irq(&rme32->lock); |
| 654 | return -EIO; |
| 655 | } |
| 656 | } else { |
| 657 | err = snd_rme32_playback_setrate(rme32, params_rate(params)); |
| 658 | if (err < 0) { |
| 659 | spin_unlock_irq(&rme32->lock); |
| 660 | return err; |
| 661 | } |
| 662 | } |
| 663 | err = snd_rme32_setformat(rme32, params_format(params)); |
| 664 | if (err < 0) { |
| 665 | spin_unlock_irq(&rme32->lock); |
| 666 | return err; |
| 667 | } |
| 668 | |
| 669 | snd_rme32_setframelog(rme32, params_channels(params), 1); |
| 670 | if (rme32->capture_periodsize != 0) { |
| 671 | if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) { |
| 672 | spin_unlock_irq(&rme32->lock); |
| 673 | return -EBUSY; |
| 674 | } |
| 675 | } |
| 676 | rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; |
| 677 | /* S/PDIF setup */ |
| 678 | if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { |
| 679 | rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); |
| 680 | rme32->wcreg |= rme32->wcreg_spdif_stream; |
| 681 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 682 | } |
| 683 | spin_unlock_irq(&rme32->lock); |
| 684 | |
| 685 | return 0; |
| 686 | } |
| 687 | |
| 688 | static int |
| 689 | snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, |
| 690 | struct snd_pcm_hw_params *params) |
| 691 | { |
| 692 | int err, isadat, rate; |
| 693 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 694 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 695 | |
| 696 | if (!rme32->fullduplex_mode) { |
| 697 | runtime->dma_area = (void __force *)rme32->iobase + |
| 698 | RME32_IO_DATA_BUFFER; |
| 699 | runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; |
| 700 | runtime->dma_bytes = RME32_BUFFER_SIZE; |
| 701 | } |
| 702 | |
| 703 | spin_lock_irq(&rme32->lock); |
| 704 | /* enable AutoSync for record-preparing */ |
| 705 | rme32->wcreg |= RME32_WCR_AUTOSYNC; |
| 706 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 707 | |
| 708 | err = snd_rme32_setformat(rme32, params_format(params)); |
| 709 | if (err < 0) { |
| 710 | spin_unlock_irq(&rme32->lock); |
| 711 | return err; |
| 712 | } |
| 713 | err = snd_rme32_playback_setrate(rme32, params_rate(params)); |
| 714 | if (err < 0) { |
| 715 | spin_unlock_irq(&rme32->lock); |
| 716 | return err; |
| 717 | } |
| 718 | rate = snd_rme32_capture_getrate(rme32, &isadat); |
| 719 | if (rate > 0) { |
| 720 | if ((int)params_rate(params) != rate) { |
| 721 | spin_unlock_irq(&rme32->lock); |
| 722 | return -EIO; |
| 723 | } |
| 724 | if ((isadat && runtime->hw.channels_min == 2) || |
| 725 | (!isadat && runtime->hw.channels_min == 8)) { |
| 726 | spin_unlock_irq(&rme32->lock); |
| 727 | return -EIO; |
| 728 | } |
| 729 | } |
| 730 | /* AutoSync off for recording */ |
| 731 | rme32->wcreg &= ~RME32_WCR_AUTOSYNC; |
| 732 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 733 | |
| 734 | snd_rme32_setframelog(rme32, params_channels(params), 0); |
| 735 | if (rme32->playback_periodsize != 0) { |
| 736 | if (params_period_size(params) << rme32->capture_frlog != |
| 737 | rme32->playback_periodsize) { |
| 738 | spin_unlock_irq(&rme32->lock); |
| 739 | return -EBUSY; |
| 740 | } |
| 741 | } |
| 742 | rme32->capture_periodsize = |
| 743 | params_period_size(params) << rme32->capture_frlog; |
| 744 | spin_unlock_irq(&rme32->lock); |
| 745 | |
| 746 | return 0; |
| 747 | } |
| 748 | |
| 749 | static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) |
| 750 | { |
| 751 | if (!from_pause) { |
| 752 | writel(0, rme32->iobase + RME32_IO_RESET_POS); |
| 753 | } |
| 754 | |
| 755 | rme32->wcreg |= RME32_WCR_START; |
| 756 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 757 | } |
| 758 | |
| 759 | static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) |
| 760 | { |
| 761 | /* |
| 762 | * Check if there is an unconfirmed IRQ, if so confirm it, or else |
| 763 | * the hardware will not stop generating interrupts |
| 764 | */ |
| 765 | rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 766 | if (rme32->rcreg & RME32_RCR_IRQ) { |
| 767 | writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); |
| 768 | } |
| 769 | rme32->wcreg &= ~RME32_WCR_START; |
| 770 | if (rme32->wcreg & RME32_WCR_SEL) |
| 771 | rme32->wcreg |= RME32_WCR_MUTE; |
| 772 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 773 | if (! to_pause) |
| 774 | writel(0, rme32->iobase + RME32_IO_RESET_POS); |
| 775 | } |
| 776 | |
| 777 | static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) |
| 778 | { |
| 779 | struct rme32 *rme32 = (struct rme32 *) dev_id; |
| 780 | |
| 781 | rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 782 | if (!(rme32->rcreg & RME32_RCR_IRQ)) { |
| 783 | return IRQ_NONE; |
| 784 | } else { |
| 785 | if (rme32->capture_substream) { |
| 786 | snd_pcm_period_elapsed(rme32->capture_substream); |
| 787 | } |
| 788 | if (rme32->playback_substream) { |
| 789 | snd_pcm_period_elapsed(rme32->playback_substream); |
| 790 | } |
| 791 | writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); |
| 792 | } |
| 793 | return IRQ_HANDLED; |
| 794 | } |
| 795 | |
| 796 | static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; |
| 797 | |
| 798 | static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { |
| 799 | .count = ARRAY_SIZE(period_bytes), |
| 800 | .list = period_bytes, |
| 801 | .mask = 0 |
| 802 | }; |
| 803 | |
| 804 | static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) |
| 805 | { |
| 806 | if (! rme32->fullduplex_mode) { |
| 807 | snd_pcm_hw_constraint_single(runtime, |
| 808 | SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
| 809 | RME32_BUFFER_SIZE); |
| 810 | snd_pcm_hw_constraint_list(runtime, 0, |
| 811 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
| 812 | &hw_constraints_period_bytes); |
| 813 | } |
| 814 | } |
| 815 | |
| 816 | static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) |
| 817 | { |
| 818 | int rate, dummy; |
| 819 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 820 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 821 | |
| 822 | snd_pcm_set_sync(substream); |
| 823 | |
| 824 | spin_lock_irq(&rme32->lock); |
| 825 | if (rme32->playback_substream != NULL) { |
| 826 | spin_unlock_irq(&rme32->lock); |
| 827 | return -EBUSY; |
| 828 | } |
| 829 | rme32->wcreg &= ~RME32_WCR_ADAT; |
| 830 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 831 | rme32->playback_substream = substream; |
| 832 | spin_unlock_irq(&rme32->lock); |
| 833 | |
| 834 | if (rme32->fullduplex_mode) |
| 835 | runtime->hw = snd_rme32_spdif_fd_info; |
| 836 | else |
| 837 | runtime->hw = snd_rme32_spdif_info; |
| 838 | if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { |
| 839 | runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; |
| 840 | runtime->hw.rate_max = 96000; |
| 841 | } |
| 842 | rate = 0; |
| 843 | if (rme32->rcreg & RME32_RCR_KMODE) |
| 844 | rate = snd_rme32_capture_getrate(rme32, &dummy); |
| 845 | if (rate > 0) { |
| 846 | /* AutoSync */ |
| 847 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
| 848 | runtime->hw.rate_min = rate; |
| 849 | runtime->hw.rate_max = rate; |
| 850 | } |
| 851 | |
| 852 | snd_rme32_set_buffer_constraint(rme32, runtime); |
| 853 | |
| 854 | rme32->wcreg_spdif_stream = rme32->wcreg_spdif; |
| 855 | rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; |
| 856 | snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | |
| 857 | SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) |
| 862 | { |
| 863 | int isadat, rate; |
| 864 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 865 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 866 | |
| 867 | snd_pcm_set_sync(substream); |
| 868 | |
| 869 | spin_lock_irq(&rme32->lock); |
| 870 | if (rme32->capture_substream != NULL) { |
| 871 | spin_unlock_irq(&rme32->lock); |
| 872 | return -EBUSY; |
| 873 | } |
| 874 | rme32->capture_substream = substream; |
| 875 | spin_unlock_irq(&rme32->lock); |
| 876 | |
| 877 | if (rme32->fullduplex_mode) |
| 878 | runtime->hw = snd_rme32_spdif_fd_info; |
| 879 | else |
| 880 | runtime->hw = snd_rme32_spdif_info; |
| 881 | if (RME32_PRO_WITH_8414(rme32)) { |
| 882 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; |
| 883 | runtime->hw.rate_max = 96000; |
| 884 | } |
| 885 | rate = snd_rme32_capture_getrate(rme32, &isadat); |
| 886 | if (rate > 0) { |
| 887 | if (isadat) { |
| 888 | return -EIO; |
| 889 | } |
| 890 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
| 891 | runtime->hw.rate_min = rate; |
| 892 | runtime->hw.rate_max = rate; |
| 893 | } |
| 894 | |
| 895 | snd_rme32_set_buffer_constraint(rme32, runtime); |
| 896 | |
| 897 | return 0; |
| 898 | } |
| 899 | |
| 900 | static int |
| 901 | snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) |
| 902 | { |
| 903 | int rate, dummy; |
| 904 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 905 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 906 | |
| 907 | snd_pcm_set_sync(substream); |
| 908 | |
| 909 | spin_lock_irq(&rme32->lock); |
| 910 | if (rme32->playback_substream != NULL) { |
| 911 | spin_unlock_irq(&rme32->lock); |
| 912 | return -EBUSY; |
| 913 | } |
| 914 | rme32->wcreg |= RME32_WCR_ADAT; |
| 915 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 916 | rme32->playback_substream = substream; |
| 917 | spin_unlock_irq(&rme32->lock); |
| 918 | |
| 919 | if (rme32->fullduplex_mode) |
| 920 | runtime->hw = snd_rme32_adat_fd_info; |
| 921 | else |
| 922 | runtime->hw = snd_rme32_adat_info; |
| 923 | rate = 0; |
| 924 | if (rme32->rcreg & RME32_RCR_KMODE) |
| 925 | rate = snd_rme32_capture_getrate(rme32, &dummy); |
| 926 | if (rate > 0) { |
| 927 | /* AutoSync */ |
| 928 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
| 929 | runtime->hw.rate_min = rate; |
| 930 | runtime->hw.rate_max = rate; |
| 931 | } |
| 932 | |
| 933 | snd_rme32_set_buffer_constraint(rme32, runtime); |
| 934 | return 0; |
| 935 | } |
| 936 | |
| 937 | static int |
| 938 | snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) |
| 939 | { |
| 940 | int isadat, rate; |
| 941 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 942 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 943 | |
| 944 | if (rme32->fullduplex_mode) |
| 945 | runtime->hw = snd_rme32_adat_fd_info; |
| 946 | else |
| 947 | runtime->hw = snd_rme32_adat_info; |
| 948 | rate = snd_rme32_capture_getrate(rme32, &isadat); |
| 949 | if (rate > 0) { |
| 950 | if (!isadat) { |
| 951 | return -EIO; |
| 952 | } |
| 953 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
| 954 | runtime->hw.rate_min = rate; |
| 955 | runtime->hw.rate_max = rate; |
| 956 | } |
| 957 | |
| 958 | snd_pcm_set_sync(substream); |
| 959 | |
| 960 | spin_lock_irq(&rme32->lock); |
| 961 | if (rme32->capture_substream != NULL) { |
| 962 | spin_unlock_irq(&rme32->lock); |
| 963 | return -EBUSY; |
| 964 | } |
| 965 | rme32->capture_substream = substream; |
| 966 | spin_unlock_irq(&rme32->lock); |
| 967 | |
| 968 | snd_rme32_set_buffer_constraint(rme32, runtime); |
| 969 | return 0; |
| 970 | } |
| 971 | |
| 972 | static int snd_rme32_playback_close(struct snd_pcm_substream *substream) |
| 973 | { |
| 974 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 975 | int spdif = 0; |
| 976 | |
| 977 | spin_lock_irq(&rme32->lock); |
| 978 | rme32->playback_substream = NULL; |
| 979 | rme32->playback_periodsize = 0; |
| 980 | spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; |
| 981 | spin_unlock_irq(&rme32->lock); |
| 982 | if (spdif) { |
| 983 | rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; |
| 984 | snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | |
| 985 | SNDRV_CTL_EVENT_MASK_INFO, |
| 986 | &rme32->spdif_ctl->id); |
| 987 | } |
| 988 | return 0; |
| 989 | } |
| 990 | |
| 991 | static int snd_rme32_capture_close(struct snd_pcm_substream *substream) |
| 992 | { |
| 993 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 994 | |
| 995 | spin_lock_irq(&rme32->lock); |
| 996 | rme32->capture_substream = NULL; |
| 997 | rme32->capture_periodsize = 0; |
| 998 | spin_unlock_irq(&rme32->lock); |
| 999 | return 0; |
| 1000 | } |
| 1001 | |
| 1002 | static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) |
| 1003 | { |
| 1004 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1005 | |
| 1006 | spin_lock_irq(&rme32->lock); |
| 1007 | if (rme32->fullduplex_mode) { |
| 1008 | memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); |
| 1009 | rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; |
| 1010 | rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); |
| 1011 | } else { |
| 1012 | writel(0, rme32->iobase + RME32_IO_RESET_POS); |
| 1013 | } |
| 1014 | if (rme32->wcreg & RME32_WCR_SEL) |
| 1015 | rme32->wcreg &= ~RME32_WCR_MUTE; |
| 1016 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 1017 | spin_unlock_irq(&rme32->lock); |
| 1018 | return 0; |
| 1019 | } |
| 1020 | |
| 1021 | static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) |
| 1022 | { |
| 1023 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1024 | |
| 1025 | spin_lock_irq(&rme32->lock); |
| 1026 | if (rme32->fullduplex_mode) { |
| 1027 | memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); |
| 1028 | rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; |
| 1029 | rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; |
| 1030 | rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); |
| 1031 | } else { |
| 1032 | writel(0, rme32->iobase + RME32_IO_RESET_POS); |
| 1033 | } |
| 1034 | spin_unlock_irq(&rme32->lock); |
| 1035 | return 0; |
| 1036 | } |
| 1037 | |
| 1038 | static int |
| 1039 | snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
| 1040 | { |
| 1041 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1042 | struct snd_pcm_substream *s; |
| 1043 | |
| 1044 | spin_lock(&rme32->lock); |
| 1045 | snd_pcm_group_for_each_entry(s, substream) { |
| 1046 | if (s != rme32->playback_substream && |
| 1047 | s != rme32->capture_substream) |
| 1048 | continue; |
| 1049 | switch (cmd) { |
| 1050 | case SNDRV_PCM_TRIGGER_START: |
| 1051 | rme32->running |= (1 << s->stream); |
| 1052 | if (rme32->fullduplex_mode) { |
| 1053 | /* remember the current DMA position */ |
| 1054 | if (s == rme32->playback_substream) { |
| 1055 | rme32->playback_pcm.hw_io = |
| 1056 | rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); |
| 1057 | } else { |
| 1058 | rme32->capture_pcm.hw_io = |
| 1059 | rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); |
| 1060 | } |
| 1061 | } |
| 1062 | break; |
| 1063 | case SNDRV_PCM_TRIGGER_STOP: |
| 1064 | rme32->running &= ~(1 << s->stream); |
| 1065 | break; |
| 1066 | } |
| 1067 | snd_pcm_trigger_done(s, substream); |
| 1068 | } |
| 1069 | |
| 1070 | switch (cmd) { |
| 1071 | case SNDRV_PCM_TRIGGER_START: |
| 1072 | if (rme32->running && ! RME32_ISWORKING(rme32)) |
| 1073 | snd_rme32_pcm_start(rme32, 0); |
| 1074 | break; |
| 1075 | case SNDRV_PCM_TRIGGER_STOP: |
| 1076 | if (! rme32->running && RME32_ISWORKING(rme32)) |
| 1077 | snd_rme32_pcm_stop(rme32, 0); |
| 1078 | break; |
| 1079 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 1080 | if (rme32->running && RME32_ISWORKING(rme32)) |
| 1081 | snd_rme32_pcm_stop(rme32, 1); |
| 1082 | break; |
| 1083 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 1084 | if (rme32->running && ! RME32_ISWORKING(rme32)) |
| 1085 | snd_rme32_pcm_start(rme32, 1); |
| 1086 | break; |
| 1087 | } |
| 1088 | spin_unlock(&rme32->lock); |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | /* pointer callback for halfduplex mode */ |
| 1093 | static snd_pcm_uframes_t |
| 1094 | snd_rme32_playback_pointer(struct snd_pcm_substream *substream) |
| 1095 | { |
| 1096 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1097 | return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; |
| 1098 | } |
| 1099 | |
| 1100 | static snd_pcm_uframes_t |
| 1101 | snd_rme32_capture_pointer(struct snd_pcm_substream *substream) |
| 1102 | { |
| 1103 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1104 | return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; |
| 1105 | } |
| 1106 | |
| 1107 | |
| 1108 | /* ack and pointer callbacks for fullduplex mode */ |
| 1109 | static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, |
| 1110 | struct snd_pcm_indirect *rec, size_t bytes) |
| 1111 | { |
| 1112 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1113 | memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, |
| 1114 | substream->runtime->dma_area + rec->sw_data, bytes); |
| 1115 | } |
| 1116 | |
| 1117 | static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) |
| 1118 | { |
| 1119 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1120 | struct snd_pcm_indirect *rec, *cprec; |
| 1121 | |
| 1122 | rec = &rme32->playback_pcm; |
| 1123 | cprec = &rme32->capture_pcm; |
| 1124 | spin_lock(&rme32->lock); |
| 1125 | rec->hw_queue_size = RME32_BUFFER_SIZE; |
| 1126 | if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) |
| 1127 | rec->hw_queue_size -= cprec->hw_ready; |
| 1128 | spin_unlock(&rme32->lock); |
| 1129 | return snd_pcm_indirect_playback_transfer(substream, rec, |
| 1130 | snd_rme32_pb_trans_copy); |
| 1131 | } |
| 1132 | |
| 1133 | static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, |
| 1134 | struct snd_pcm_indirect *rec, size_t bytes) |
| 1135 | { |
| 1136 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1137 | memcpy_fromio(substream->runtime->dma_area + rec->sw_data, |
| 1138 | rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, |
| 1139 | bytes); |
| 1140 | } |
| 1141 | |
| 1142 | static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) |
| 1143 | { |
| 1144 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1145 | return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, |
| 1146 | snd_rme32_cp_trans_copy); |
| 1147 | } |
| 1148 | |
| 1149 | static snd_pcm_uframes_t |
| 1150 | snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) |
| 1151 | { |
| 1152 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1153 | return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, |
| 1154 | snd_rme32_pcm_byteptr(rme32)); |
| 1155 | } |
| 1156 | |
| 1157 | static snd_pcm_uframes_t |
| 1158 | snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) |
| 1159 | { |
| 1160 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
| 1161 | return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, |
| 1162 | snd_rme32_pcm_byteptr(rme32)); |
| 1163 | } |
| 1164 | |
| 1165 | /* for halfduplex mode */ |
| 1166 | static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = { |
| 1167 | .open = snd_rme32_playback_spdif_open, |
| 1168 | .close = snd_rme32_playback_close, |
| 1169 | .hw_params = snd_rme32_playback_hw_params, |
| 1170 | .prepare = snd_rme32_playback_prepare, |
| 1171 | .trigger = snd_rme32_pcm_trigger, |
| 1172 | .pointer = snd_rme32_playback_pointer, |
| 1173 | .copy = snd_rme32_playback_copy, |
| 1174 | .fill_silence = snd_rme32_playback_silence, |
| 1175 | .mmap = snd_pcm_lib_mmap_iomem, |
| 1176 | }; |
| 1177 | |
| 1178 | static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = { |
| 1179 | .open = snd_rme32_capture_spdif_open, |
| 1180 | .close = snd_rme32_capture_close, |
| 1181 | .hw_params = snd_rme32_capture_hw_params, |
| 1182 | .prepare = snd_rme32_capture_prepare, |
| 1183 | .trigger = snd_rme32_pcm_trigger, |
| 1184 | .pointer = snd_rme32_capture_pointer, |
| 1185 | .copy = snd_rme32_capture_copy, |
| 1186 | .mmap = snd_pcm_lib_mmap_iomem, |
| 1187 | }; |
| 1188 | |
| 1189 | static const struct snd_pcm_ops snd_rme32_playback_adat_ops = { |
| 1190 | .open = snd_rme32_playback_adat_open, |
| 1191 | .close = snd_rme32_playback_close, |
| 1192 | .hw_params = snd_rme32_playback_hw_params, |
| 1193 | .prepare = snd_rme32_playback_prepare, |
| 1194 | .trigger = snd_rme32_pcm_trigger, |
| 1195 | .pointer = snd_rme32_playback_pointer, |
| 1196 | .copy = snd_rme32_playback_copy, |
| 1197 | .fill_silence = snd_rme32_playback_silence, |
| 1198 | .mmap = snd_pcm_lib_mmap_iomem, |
| 1199 | }; |
| 1200 | |
| 1201 | static const struct snd_pcm_ops snd_rme32_capture_adat_ops = { |
| 1202 | .open = snd_rme32_capture_adat_open, |
| 1203 | .close = snd_rme32_capture_close, |
| 1204 | .hw_params = snd_rme32_capture_hw_params, |
| 1205 | .prepare = snd_rme32_capture_prepare, |
| 1206 | .trigger = snd_rme32_pcm_trigger, |
| 1207 | .pointer = snd_rme32_capture_pointer, |
| 1208 | .copy = snd_rme32_capture_copy, |
| 1209 | .mmap = snd_pcm_lib_mmap_iomem, |
| 1210 | }; |
| 1211 | |
| 1212 | /* for fullduplex mode */ |
| 1213 | static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { |
| 1214 | .open = snd_rme32_playback_spdif_open, |
| 1215 | .close = snd_rme32_playback_close, |
| 1216 | .hw_params = snd_rme32_playback_hw_params, |
| 1217 | .prepare = snd_rme32_playback_prepare, |
| 1218 | .trigger = snd_rme32_pcm_trigger, |
| 1219 | .pointer = snd_rme32_playback_fd_pointer, |
| 1220 | .ack = snd_rme32_playback_fd_ack, |
| 1221 | }; |
| 1222 | |
| 1223 | static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { |
| 1224 | .open = snd_rme32_capture_spdif_open, |
| 1225 | .close = snd_rme32_capture_close, |
| 1226 | .hw_params = snd_rme32_capture_hw_params, |
| 1227 | .prepare = snd_rme32_capture_prepare, |
| 1228 | .trigger = snd_rme32_pcm_trigger, |
| 1229 | .pointer = snd_rme32_capture_fd_pointer, |
| 1230 | .ack = snd_rme32_capture_fd_ack, |
| 1231 | }; |
| 1232 | |
| 1233 | static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { |
| 1234 | .open = snd_rme32_playback_adat_open, |
| 1235 | .close = snd_rme32_playback_close, |
| 1236 | .hw_params = snd_rme32_playback_hw_params, |
| 1237 | .prepare = snd_rme32_playback_prepare, |
| 1238 | .trigger = snd_rme32_pcm_trigger, |
| 1239 | .pointer = snd_rme32_playback_fd_pointer, |
| 1240 | .ack = snd_rme32_playback_fd_ack, |
| 1241 | }; |
| 1242 | |
| 1243 | static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { |
| 1244 | .open = snd_rme32_capture_adat_open, |
| 1245 | .close = snd_rme32_capture_close, |
| 1246 | .hw_params = snd_rme32_capture_hw_params, |
| 1247 | .prepare = snd_rme32_capture_prepare, |
| 1248 | .trigger = snd_rme32_pcm_trigger, |
| 1249 | .pointer = snd_rme32_capture_fd_pointer, |
| 1250 | .ack = snd_rme32_capture_fd_ack, |
| 1251 | }; |
| 1252 | |
| 1253 | static void snd_rme32_free(struct rme32 *rme32) |
| 1254 | { |
| 1255 | if (rme32->irq >= 0) |
| 1256 | snd_rme32_pcm_stop(rme32, 0); |
| 1257 | } |
| 1258 | |
| 1259 | static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) |
| 1260 | { |
| 1261 | struct rme32 *rme32 = (struct rme32 *) pcm->private_data; |
| 1262 | rme32->spdif_pcm = NULL; |
| 1263 | } |
| 1264 | |
| 1265 | static void |
| 1266 | snd_rme32_free_adat_pcm(struct snd_pcm *pcm) |
| 1267 | { |
| 1268 | struct rme32 *rme32 = (struct rme32 *) pcm->private_data; |
| 1269 | rme32->adat_pcm = NULL; |
| 1270 | } |
| 1271 | |
| 1272 | static int snd_rme32_create(struct rme32 *rme32) |
| 1273 | { |
| 1274 | struct pci_dev *pci = rme32->pci; |
| 1275 | int err; |
| 1276 | |
| 1277 | rme32->irq = -1; |
| 1278 | spin_lock_init(&rme32->lock); |
| 1279 | |
| 1280 | err = pcim_enable_device(pci); |
| 1281 | if (err < 0) |
| 1282 | return err; |
| 1283 | |
| 1284 | err = pci_request_regions(pci, "RME32"); |
| 1285 | if (err < 0) |
| 1286 | return err; |
| 1287 | rme32->port = pci_resource_start(rme32->pci, 0); |
| 1288 | |
| 1289 | rme32->iobase = devm_ioremap(&pci->dev, rme32->port, RME32_IO_SIZE); |
| 1290 | if (!rme32->iobase) { |
| 1291 | dev_err(rme32->card->dev, |
| 1292 | "unable to remap memory region 0x%lx-0x%lx\n", |
| 1293 | rme32->port, rme32->port + RME32_IO_SIZE - 1); |
| 1294 | return -ENOMEM; |
| 1295 | } |
| 1296 | |
| 1297 | if (devm_request_irq(&pci->dev, pci->irq, snd_rme32_interrupt, |
| 1298 | IRQF_SHARED, KBUILD_MODNAME, rme32)) { |
| 1299 | dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq); |
| 1300 | return -EBUSY; |
| 1301 | } |
| 1302 | rme32->irq = pci->irq; |
| 1303 | rme32->card->sync_irq = rme32->irq; |
| 1304 | |
| 1305 | /* read the card's revision number */ |
| 1306 | pci_read_config_byte(pci, 8, &rme32->rev); |
| 1307 | |
| 1308 | /* set up ALSA pcm device for S/PDIF */ |
| 1309 | err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm); |
| 1310 | if (err < 0) |
| 1311 | return err; |
| 1312 | rme32->spdif_pcm->private_data = rme32; |
| 1313 | rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; |
| 1314 | strcpy(rme32->spdif_pcm->name, "Digi32 IEC958"); |
| 1315 | if (rme32->fullduplex_mode) { |
| 1316 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, |
| 1317 | &snd_rme32_playback_spdif_fd_ops); |
| 1318 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, |
| 1319 | &snd_rme32_capture_spdif_fd_ops); |
| 1320 | snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, |
| 1321 | NULL, 0, RME32_MID_BUFFER_SIZE); |
| 1322 | rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; |
| 1323 | } else { |
| 1324 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, |
| 1325 | &snd_rme32_playback_spdif_ops); |
| 1326 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, |
| 1327 | &snd_rme32_capture_spdif_ops); |
| 1328 | rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; |
| 1329 | } |
| 1330 | |
| 1331 | /* set up ALSA pcm device for ADAT */ |
| 1332 | if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || |
| 1333 | (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { |
| 1334 | /* ADAT is not available on DIGI32 and DIGI32 Pro */ |
| 1335 | rme32->adat_pcm = NULL; |
| 1336 | } |
| 1337 | else { |
| 1338 | err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, |
| 1339 | 1, 1, &rme32->adat_pcm); |
| 1340 | if (err < 0) |
| 1341 | return err; |
| 1342 | rme32->adat_pcm->private_data = rme32; |
| 1343 | rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; |
| 1344 | strcpy(rme32->adat_pcm->name, "Digi32 ADAT"); |
| 1345 | if (rme32->fullduplex_mode) { |
| 1346 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, |
| 1347 | &snd_rme32_playback_adat_fd_ops); |
| 1348 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, |
| 1349 | &snd_rme32_capture_adat_fd_ops); |
| 1350 | snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, |
| 1351 | NULL, |
| 1352 | 0, RME32_MID_BUFFER_SIZE); |
| 1353 | rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; |
| 1354 | } else { |
| 1355 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, |
| 1356 | &snd_rme32_playback_adat_ops); |
| 1357 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, |
| 1358 | &snd_rme32_capture_adat_ops); |
| 1359 | rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; |
| 1360 | } |
| 1361 | } |
| 1362 | |
| 1363 | |
| 1364 | rme32->playback_periodsize = 0; |
| 1365 | rme32->capture_periodsize = 0; |
| 1366 | |
| 1367 | /* make sure playback/capture is stopped, if by some reason active */ |
| 1368 | snd_rme32_pcm_stop(rme32, 0); |
| 1369 | |
| 1370 | /* reset DAC */ |
| 1371 | snd_rme32_reset_dac(rme32); |
| 1372 | |
| 1373 | /* reset buffer pointer */ |
| 1374 | writel(0, rme32->iobase + RME32_IO_RESET_POS); |
| 1375 | |
| 1376 | /* set default values in registers */ |
| 1377 | rme32->wcreg = RME32_WCR_SEL | /* normal playback */ |
| 1378 | RME32_WCR_INP_0 | /* input select */ |
| 1379 | RME32_WCR_MUTE; /* muting on */ |
| 1380 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 1381 | |
| 1382 | |
| 1383 | /* init switch interface */ |
| 1384 | err = snd_rme32_create_switches(rme32->card, rme32); |
| 1385 | if (err < 0) |
| 1386 | return err; |
| 1387 | |
| 1388 | /* init proc interface */ |
| 1389 | snd_rme32_proc_init(rme32); |
| 1390 | |
| 1391 | rme32->capture_substream = NULL; |
| 1392 | rme32->playback_substream = NULL; |
| 1393 | |
| 1394 | return 0; |
| 1395 | } |
| 1396 | |
| 1397 | /* |
| 1398 | * proc interface |
| 1399 | */ |
| 1400 | |
| 1401 | static void |
| 1402 | snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) |
| 1403 | { |
| 1404 | int n; |
| 1405 | struct rme32 *rme32 = (struct rme32 *) entry->private_data; |
| 1406 | |
| 1407 | rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 1408 | |
| 1409 | snd_iprintf(buffer, rme32->card->longname); |
| 1410 | snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); |
| 1411 | |
| 1412 | snd_iprintf(buffer, "\nGeneral settings\n"); |
| 1413 | if (rme32->fullduplex_mode) |
| 1414 | snd_iprintf(buffer, " Full-duplex mode\n"); |
| 1415 | else |
| 1416 | snd_iprintf(buffer, " Half-duplex mode\n"); |
| 1417 | if (RME32_PRO_WITH_8414(rme32)) { |
| 1418 | snd_iprintf(buffer, " receiver: CS8414\n"); |
| 1419 | } else { |
| 1420 | snd_iprintf(buffer, " receiver: CS8412\n"); |
| 1421 | } |
| 1422 | if (rme32->wcreg & RME32_WCR_MODE24) { |
| 1423 | snd_iprintf(buffer, " format: 24 bit"); |
| 1424 | } else { |
| 1425 | snd_iprintf(buffer, " format: 16 bit"); |
| 1426 | } |
| 1427 | if (rme32->wcreg & RME32_WCR_MONO) { |
| 1428 | snd_iprintf(buffer, ", Mono\n"); |
| 1429 | } else { |
| 1430 | snd_iprintf(buffer, ", Stereo\n"); |
| 1431 | } |
| 1432 | |
| 1433 | snd_iprintf(buffer, "\nInput settings\n"); |
| 1434 | switch (snd_rme32_getinputtype(rme32)) { |
| 1435 | case RME32_INPUT_OPTICAL: |
| 1436 | snd_iprintf(buffer, " input: optical"); |
| 1437 | break; |
| 1438 | case RME32_INPUT_COAXIAL: |
| 1439 | snd_iprintf(buffer, " input: coaxial"); |
| 1440 | break; |
| 1441 | case RME32_INPUT_INTERNAL: |
| 1442 | snd_iprintf(buffer, " input: internal"); |
| 1443 | break; |
| 1444 | case RME32_INPUT_XLR: |
| 1445 | snd_iprintf(buffer, " input: XLR"); |
| 1446 | break; |
| 1447 | } |
| 1448 | if (snd_rme32_capture_getrate(rme32, &n) < 0) { |
| 1449 | snd_iprintf(buffer, "\n sample rate: no valid signal\n"); |
| 1450 | } else { |
| 1451 | if (n) { |
| 1452 | snd_iprintf(buffer, " (8 channels)\n"); |
| 1453 | } else { |
| 1454 | snd_iprintf(buffer, " (2 channels)\n"); |
| 1455 | } |
| 1456 | snd_iprintf(buffer, " sample rate: %d Hz\n", |
| 1457 | snd_rme32_capture_getrate(rme32, &n)); |
| 1458 | } |
| 1459 | |
| 1460 | snd_iprintf(buffer, "\nOutput settings\n"); |
| 1461 | if (rme32->wcreg & RME32_WCR_SEL) { |
| 1462 | snd_iprintf(buffer, " output signal: normal playback"); |
| 1463 | } else { |
| 1464 | snd_iprintf(buffer, " output signal: same as input"); |
| 1465 | } |
| 1466 | if (rme32->wcreg & RME32_WCR_MUTE) { |
| 1467 | snd_iprintf(buffer, " (muted)\n"); |
| 1468 | } else { |
| 1469 | snd_iprintf(buffer, "\n"); |
| 1470 | } |
| 1471 | |
| 1472 | /* master output frequency */ |
| 1473 | if (! |
| 1474 | ((!(rme32->wcreg & RME32_WCR_FREQ_0)) |
| 1475 | && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { |
| 1476 | snd_iprintf(buffer, " sample rate: %d Hz\n", |
| 1477 | snd_rme32_playback_getrate(rme32)); |
| 1478 | } |
| 1479 | if (rme32->rcreg & RME32_RCR_KMODE) { |
| 1480 | snd_iprintf(buffer, " sample clock source: AutoSync\n"); |
| 1481 | } else { |
| 1482 | snd_iprintf(buffer, " sample clock source: Internal\n"); |
| 1483 | } |
| 1484 | if (rme32->wcreg & RME32_WCR_PRO) { |
| 1485 | snd_iprintf(buffer, " format: AES/EBU (professional)\n"); |
| 1486 | } else { |
| 1487 | snd_iprintf(buffer, " format: IEC958 (consumer)\n"); |
| 1488 | } |
| 1489 | if (rme32->wcreg & RME32_WCR_EMP) { |
| 1490 | snd_iprintf(buffer, " emphasis: on\n"); |
| 1491 | } else { |
| 1492 | snd_iprintf(buffer, " emphasis: off\n"); |
| 1493 | } |
| 1494 | } |
| 1495 | |
| 1496 | static void snd_rme32_proc_init(struct rme32 *rme32) |
| 1497 | { |
| 1498 | snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read); |
| 1499 | } |
| 1500 | |
| 1501 | /* |
| 1502 | * control interface |
| 1503 | */ |
| 1504 | |
| 1505 | #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info |
| 1506 | |
| 1507 | static int |
| 1508 | snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, |
| 1509 | struct snd_ctl_elem_value *ucontrol) |
| 1510 | { |
| 1511 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1512 | |
| 1513 | spin_lock_irq(&rme32->lock); |
| 1514 | ucontrol->value.integer.value[0] = |
| 1515 | rme32->wcreg & RME32_WCR_SEL ? 0 : 1; |
| 1516 | spin_unlock_irq(&rme32->lock); |
| 1517 | return 0; |
| 1518 | } |
| 1519 | static int |
| 1520 | snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, |
| 1521 | struct snd_ctl_elem_value *ucontrol) |
| 1522 | { |
| 1523 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1524 | unsigned int val; |
| 1525 | int change; |
| 1526 | |
| 1527 | val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; |
| 1528 | spin_lock_irq(&rme32->lock); |
| 1529 | val = (rme32->wcreg & ~RME32_WCR_SEL) | val; |
| 1530 | change = val != rme32->wcreg; |
| 1531 | if (ucontrol->value.integer.value[0]) |
| 1532 | val &= ~RME32_WCR_MUTE; |
| 1533 | else |
| 1534 | val |= RME32_WCR_MUTE; |
| 1535 | rme32->wcreg = val; |
| 1536 | writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 1537 | spin_unlock_irq(&rme32->lock); |
| 1538 | return change; |
| 1539 | } |
| 1540 | |
| 1541 | static int |
| 1542 | snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, |
| 1543 | struct snd_ctl_elem_info *uinfo) |
| 1544 | { |
| 1545 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1546 | static const char * const texts[4] = { |
| 1547 | "Optical", "Coaxial", "Internal", "XLR" |
| 1548 | }; |
| 1549 | int num_items; |
| 1550 | |
| 1551 | switch (rme32->pci->device) { |
| 1552 | case PCI_DEVICE_ID_RME_DIGI32: |
| 1553 | case PCI_DEVICE_ID_RME_DIGI32_8: |
| 1554 | num_items = 3; |
| 1555 | break; |
| 1556 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
| 1557 | num_items = 4; |
| 1558 | break; |
| 1559 | default: |
| 1560 | snd_BUG(); |
| 1561 | return -EINVAL; |
| 1562 | } |
| 1563 | return snd_ctl_enum_info(uinfo, 1, num_items, texts); |
| 1564 | } |
| 1565 | static int |
| 1566 | snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, |
| 1567 | struct snd_ctl_elem_value *ucontrol) |
| 1568 | { |
| 1569 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1570 | unsigned int items = 3; |
| 1571 | |
| 1572 | spin_lock_irq(&rme32->lock); |
| 1573 | ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); |
| 1574 | |
| 1575 | switch (rme32->pci->device) { |
| 1576 | case PCI_DEVICE_ID_RME_DIGI32: |
| 1577 | case PCI_DEVICE_ID_RME_DIGI32_8: |
| 1578 | items = 3; |
| 1579 | break; |
| 1580 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
| 1581 | items = 4; |
| 1582 | break; |
| 1583 | default: |
| 1584 | snd_BUG(); |
| 1585 | break; |
| 1586 | } |
| 1587 | if (ucontrol->value.enumerated.item[0] >= items) { |
| 1588 | ucontrol->value.enumerated.item[0] = items - 1; |
| 1589 | } |
| 1590 | |
| 1591 | spin_unlock_irq(&rme32->lock); |
| 1592 | return 0; |
| 1593 | } |
| 1594 | static int |
| 1595 | snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, |
| 1596 | struct snd_ctl_elem_value *ucontrol) |
| 1597 | { |
| 1598 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1599 | unsigned int val; |
| 1600 | int change, items = 3; |
| 1601 | |
| 1602 | switch (rme32->pci->device) { |
| 1603 | case PCI_DEVICE_ID_RME_DIGI32: |
| 1604 | case PCI_DEVICE_ID_RME_DIGI32_8: |
| 1605 | items = 3; |
| 1606 | break; |
| 1607 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
| 1608 | items = 4; |
| 1609 | break; |
| 1610 | default: |
| 1611 | snd_BUG(); |
| 1612 | break; |
| 1613 | } |
| 1614 | val = ucontrol->value.enumerated.item[0] % items; |
| 1615 | |
| 1616 | spin_lock_irq(&rme32->lock); |
| 1617 | change = val != (unsigned int)snd_rme32_getinputtype(rme32); |
| 1618 | snd_rme32_setinputtype(rme32, val); |
| 1619 | spin_unlock_irq(&rme32->lock); |
| 1620 | return change; |
| 1621 | } |
| 1622 | |
| 1623 | static int |
| 1624 | snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, |
| 1625 | struct snd_ctl_elem_info *uinfo) |
| 1626 | { |
| 1627 | static const char * const texts[4] = { "AutoSync", |
| 1628 | "Internal 32.0kHz", |
| 1629 | "Internal 44.1kHz", |
| 1630 | "Internal 48.0kHz" }; |
| 1631 | |
| 1632 | return snd_ctl_enum_info(uinfo, 1, 4, texts); |
| 1633 | } |
| 1634 | static int |
| 1635 | snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, |
| 1636 | struct snd_ctl_elem_value *ucontrol) |
| 1637 | { |
| 1638 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1639 | |
| 1640 | spin_lock_irq(&rme32->lock); |
| 1641 | ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); |
| 1642 | spin_unlock_irq(&rme32->lock); |
| 1643 | return 0; |
| 1644 | } |
| 1645 | static int |
| 1646 | snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, |
| 1647 | struct snd_ctl_elem_value *ucontrol) |
| 1648 | { |
| 1649 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1650 | unsigned int val; |
| 1651 | int change; |
| 1652 | |
| 1653 | val = ucontrol->value.enumerated.item[0] % 3; |
| 1654 | spin_lock_irq(&rme32->lock); |
| 1655 | change = val != (unsigned int)snd_rme32_getclockmode(rme32); |
| 1656 | snd_rme32_setclockmode(rme32, val); |
| 1657 | spin_unlock_irq(&rme32->lock); |
| 1658 | return change; |
| 1659 | } |
| 1660 | |
| 1661 | static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) |
| 1662 | { |
| 1663 | u32 val = 0; |
| 1664 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; |
| 1665 | if (val & RME32_WCR_PRO) |
| 1666 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; |
| 1667 | else |
| 1668 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; |
| 1669 | return val; |
| 1670 | } |
| 1671 | |
| 1672 | static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) |
| 1673 | { |
| 1674 | aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); |
| 1675 | if (val & RME32_WCR_PRO) |
| 1676 | aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; |
| 1677 | else |
| 1678 | aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; |
| 1679 | } |
| 1680 | |
| 1681 | static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, |
| 1682 | struct snd_ctl_elem_info *uinfo) |
| 1683 | { |
| 1684 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
| 1685 | uinfo->count = 1; |
| 1686 | return 0; |
| 1687 | } |
| 1688 | |
| 1689 | static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, |
| 1690 | struct snd_ctl_elem_value *ucontrol) |
| 1691 | { |
| 1692 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1693 | |
| 1694 | snd_rme32_convert_to_aes(&ucontrol->value.iec958, |
| 1695 | rme32->wcreg_spdif); |
| 1696 | return 0; |
| 1697 | } |
| 1698 | |
| 1699 | static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, |
| 1700 | struct snd_ctl_elem_value *ucontrol) |
| 1701 | { |
| 1702 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1703 | int change; |
| 1704 | u32 val; |
| 1705 | |
| 1706 | val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); |
| 1707 | spin_lock_irq(&rme32->lock); |
| 1708 | change = val != rme32->wcreg_spdif; |
| 1709 | rme32->wcreg_spdif = val; |
| 1710 | spin_unlock_irq(&rme32->lock); |
| 1711 | return change; |
| 1712 | } |
| 1713 | |
| 1714 | static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, |
| 1715 | struct snd_ctl_elem_info *uinfo) |
| 1716 | { |
| 1717 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
| 1718 | uinfo->count = 1; |
| 1719 | return 0; |
| 1720 | } |
| 1721 | |
| 1722 | static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, |
| 1723 | struct snd_ctl_elem_value * |
| 1724 | ucontrol) |
| 1725 | { |
| 1726 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1727 | |
| 1728 | snd_rme32_convert_to_aes(&ucontrol->value.iec958, |
| 1729 | rme32->wcreg_spdif_stream); |
| 1730 | return 0; |
| 1731 | } |
| 1732 | |
| 1733 | static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, |
| 1734 | struct snd_ctl_elem_value * |
| 1735 | ucontrol) |
| 1736 | { |
| 1737 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
| 1738 | int change; |
| 1739 | u32 val; |
| 1740 | |
| 1741 | val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); |
| 1742 | spin_lock_irq(&rme32->lock); |
| 1743 | change = val != rme32->wcreg_spdif_stream; |
| 1744 | rme32->wcreg_spdif_stream = val; |
| 1745 | rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); |
| 1746 | rme32->wcreg |= val; |
| 1747 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); |
| 1748 | spin_unlock_irq(&rme32->lock); |
| 1749 | return change; |
| 1750 | } |
| 1751 | |
| 1752 | static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, |
| 1753 | struct snd_ctl_elem_info *uinfo) |
| 1754 | { |
| 1755 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
| 1756 | uinfo->count = 1; |
| 1757 | return 0; |
| 1758 | } |
| 1759 | |
| 1760 | static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, |
| 1761 | struct snd_ctl_elem_value * |
| 1762 | ucontrol) |
| 1763 | { |
| 1764 | ucontrol->value.iec958.status[0] = kcontrol->private_value; |
| 1765 | return 0; |
| 1766 | } |
| 1767 | |
| 1768 | static const struct snd_kcontrol_new snd_rme32_controls[] = { |
| 1769 | { |
| 1770 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 1771 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), |
| 1772 | .info = snd_rme32_control_spdif_info, |
| 1773 | .get = snd_rme32_control_spdif_get, |
| 1774 | .put = snd_rme32_control_spdif_put |
| 1775 | }, |
| 1776 | { |
| 1777 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, |
| 1778 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 1779 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), |
| 1780 | .info = snd_rme32_control_spdif_stream_info, |
| 1781 | .get = snd_rme32_control_spdif_stream_get, |
| 1782 | .put = snd_rme32_control_spdif_stream_put |
| 1783 | }, |
| 1784 | { |
| 1785 | .access = SNDRV_CTL_ELEM_ACCESS_READ, |
| 1786 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 1787 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), |
| 1788 | .info = snd_rme32_control_spdif_mask_info, |
| 1789 | .get = snd_rme32_control_spdif_mask_get, |
| 1790 | .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS |
| 1791 | }, |
| 1792 | { |
| 1793 | .access = SNDRV_CTL_ELEM_ACCESS_READ, |
| 1794 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 1795 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), |
| 1796 | .info = snd_rme32_control_spdif_mask_info, |
| 1797 | .get = snd_rme32_control_spdif_mask_get, |
| 1798 | .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS |
| 1799 | }, |
| 1800 | { |
| 1801 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 1802 | .name = "Input Connector", |
| 1803 | .info = snd_rme32_info_inputtype_control, |
| 1804 | .get = snd_rme32_get_inputtype_control, |
| 1805 | .put = snd_rme32_put_inputtype_control |
| 1806 | }, |
| 1807 | { |
| 1808 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 1809 | .name = "Loopback Input", |
| 1810 | .info = snd_rme32_info_loopback_control, |
| 1811 | .get = snd_rme32_get_loopback_control, |
| 1812 | .put = snd_rme32_put_loopback_control |
| 1813 | }, |
| 1814 | { |
| 1815 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 1816 | .name = "Sample Clock Source", |
| 1817 | .info = snd_rme32_info_clockmode_control, |
| 1818 | .get = snd_rme32_get_clockmode_control, |
| 1819 | .put = snd_rme32_put_clockmode_control |
| 1820 | } |
| 1821 | }; |
| 1822 | |
| 1823 | static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) |
| 1824 | { |
| 1825 | int idx, err; |
| 1826 | struct snd_kcontrol *kctl; |
| 1827 | |
| 1828 | for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { |
| 1829 | kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32); |
| 1830 | err = snd_ctl_add(card, kctl); |
| 1831 | if (err < 0) |
| 1832 | return err; |
| 1833 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ |
| 1834 | rme32->spdif_ctl = kctl; |
| 1835 | } |
| 1836 | |
| 1837 | return 0; |
| 1838 | } |
| 1839 | |
| 1840 | /* |
| 1841 | * Card initialisation |
| 1842 | */ |
| 1843 | |
| 1844 | static void snd_rme32_card_free(struct snd_card *card) |
| 1845 | { |
| 1846 | snd_rme32_free(card->private_data); |
| 1847 | } |
| 1848 | |
| 1849 | static int |
| 1850 | __snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
| 1851 | { |
| 1852 | static int dev; |
| 1853 | struct rme32 *rme32; |
| 1854 | struct snd_card *card; |
| 1855 | int err; |
| 1856 | |
| 1857 | if (dev >= SNDRV_CARDS) { |
| 1858 | return -ENODEV; |
| 1859 | } |
| 1860 | if (!enable[dev]) { |
| 1861 | dev++; |
| 1862 | return -ENOENT; |
| 1863 | } |
| 1864 | |
| 1865 | err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
| 1866 | sizeof(*rme32), &card); |
| 1867 | if (err < 0) |
| 1868 | return err; |
| 1869 | card->private_free = snd_rme32_card_free; |
| 1870 | rme32 = (struct rme32 *) card->private_data; |
| 1871 | rme32->card = card; |
| 1872 | rme32->pci = pci; |
| 1873 | if (fullduplex[dev]) |
| 1874 | rme32->fullduplex_mode = 1; |
| 1875 | err = snd_rme32_create(rme32); |
| 1876 | if (err < 0) |
| 1877 | return err; |
| 1878 | |
| 1879 | strcpy(card->driver, "Digi32"); |
| 1880 | switch (rme32->pci->device) { |
| 1881 | case PCI_DEVICE_ID_RME_DIGI32: |
| 1882 | strcpy(card->shortname, "RME Digi32"); |
| 1883 | break; |
| 1884 | case PCI_DEVICE_ID_RME_DIGI32_8: |
| 1885 | strcpy(card->shortname, "RME Digi32/8"); |
| 1886 | break; |
| 1887 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
| 1888 | strcpy(card->shortname, "RME Digi32 PRO"); |
| 1889 | break; |
| 1890 | } |
| 1891 | sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", |
| 1892 | card->shortname, rme32->rev, rme32->port, rme32->irq); |
| 1893 | |
| 1894 | err = snd_card_register(card); |
| 1895 | if (err < 0) |
| 1896 | return err; |
| 1897 | pci_set_drvdata(pci, card); |
| 1898 | dev++; |
| 1899 | return 0; |
| 1900 | } |
| 1901 | |
| 1902 | static int |
| 1903 | snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
| 1904 | { |
| 1905 | return snd_card_free_on_error(&pci->dev, __snd_rme32_probe(pci, pci_id)); |
| 1906 | } |
| 1907 | |
| 1908 | static struct pci_driver rme32_driver = { |
| 1909 | .name = KBUILD_MODNAME, |
| 1910 | .id_table = snd_rme32_ids, |
| 1911 | .probe = snd_rme32_probe, |
| 1912 | }; |
| 1913 | |
| 1914 | module_pci_driver(rme32_driver); |