| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * |
| 4 | * hda_intel.c - Implementation of primary alsa driver code base |
| 5 | * for Intel HD Audio. |
| 6 | * |
| 7 | * Copyright(c) 2004 Intel Corporation. All rights reserved. |
| 8 | * |
| 9 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> |
| 10 | * PeiSen Hou <pshou@realtek.com.tw> |
| 11 | * |
| 12 | * CONTACTS: |
| 13 | * |
| 14 | * Matt Jared matt.jared@intel.com |
| 15 | * Andy Kopp andy.kopp@intel.com |
| 16 | * Dan Kogan dan.d.kogan@intel.com |
| 17 | * |
| 18 | * CHANGES: |
| 19 | * |
| 20 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou |
| 21 | */ |
| 22 | |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/dma-mapping.h> |
| 28 | #include <linux/moduleparam.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/pci.h> |
| 32 | #include <linux/mutex.h> |
| 33 | #include <linux/io.h> |
| 34 | #include <linux/pm_runtime.h> |
| 35 | #include <linux/clocksource.h> |
| 36 | #include <linux/time.h> |
| 37 | #include <linux/completion.h> |
| 38 | #include <linux/acpi.h> |
| 39 | #include <linux/pgtable.h> |
| 40 | |
| 41 | #ifdef CONFIG_X86 |
| 42 | /* for snoop control */ |
| 43 | #include <asm/set_memory.h> |
| 44 | #include <asm/cpufeature.h> |
| 45 | #endif |
| 46 | #include <sound/core.h> |
| 47 | #include <sound/initval.h> |
| 48 | #include <sound/hdaudio.h> |
| 49 | #include <sound/hda_i915.h> |
| 50 | #include <sound/intel-dsp-config.h> |
| 51 | #include <linux/vgaarb.h> |
| 52 | #include <linux/vga_switcheroo.h> |
| 53 | #include <linux/firmware.h> |
| 54 | #include <sound/hda_codec.h> |
| 55 | #include "hda_controller.h" |
| 56 | #include "hda_intel.h" |
| 57 | |
| 58 | #define CREATE_TRACE_POINTS |
| 59 | #include "hda_intel_trace.h" |
| 60 | |
| 61 | /* position fix mode */ |
| 62 | enum { |
| 63 | POS_FIX_AUTO, |
| 64 | POS_FIX_LPIB, |
| 65 | POS_FIX_POSBUF, |
| 66 | POS_FIX_VIACOMBO, |
| 67 | POS_FIX_COMBO, |
| 68 | POS_FIX_SKL, |
| 69 | POS_FIX_FIFO, |
| 70 | }; |
| 71 | |
| 72 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
| 73 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
| 74 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 |
| 75 | |
| 76 | /* Defines for Nvidia HDA support */ |
| 77 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e |
| 78 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f |
| 79 | #define NVIDIA_HDA_ISTRM_COH 0x4d |
| 80 | #define NVIDIA_HDA_OSTRM_COH 0x4c |
| 81 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 |
| 82 | |
| 83 | /* Defines for Intel SCH HDA snoop control */ |
| 84 | #define INTEL_HDA_CGCTL 0x48 |
| 85 | #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) |
| 86 | #define INTEL_SCH_HDA_DEVC 0x78 |
| 87 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) |
| 88 | |
| 89 | /* Define VIA HD Audio Device ID*/ |
| 90 | #define VIA_HDAC_DEVICE_ID 0x3288 |
| 91 | |
| 92 | /* max number of SDs */ |
| 93 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
| 94 | #define ICH6_NUM_CAPTURE 4 |
| 95 | #define ICH6_NUM_PLAYBACK 4 |
| 96 | |
| 97 | /* ULI has 6 playback and 5 capture */ |
| 98 | #define ULI_NUM_CAPTURE 5 |
| 99 | #define ULI_NUM_PLAYBACK 6 |
| 100 | |
| 101 | /* ATI HDMI may have up to 8 playbacks and 0 capture */ |
| 102 | #define ATIHDMI_NUM_CAPTURE 0 |
| 103 | #define ATIHDMI_NUM_PLAYBACK 8 |
| 104 | |
| 105 | /* TERA has 4 playback and 3 capture */ |
| 106 | #define TERA_NUM_CAPTURE 3 |
| 107 | #define TERA_NUM_PLAYBACK 4 |
| 108 | |
| 109 | |
| 110 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
| 111 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; |
| 112 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
| 113 | static char *model[SNDRV_CARDS]; |
| 114 | static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
| 115 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
| 116 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
| 117 | static int probe_only[SNDRV_CARDS]; |
| 118 | static int jackpoll_ms[SNDRV_CARDS]; |
| 119 | static int single_cmd = -1; |
| 120 | static int enable_msi = -1; |
| 121 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
| 122 | static char *patch[SNDRV_CARDS]; |
| 123 | #endif |
| 124 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
| 125 | static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = |
| 126 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; |
| 127 | #endif |
| 128 | static bool dmic_detect = 1; |
| 129 | |
| 130 | module_param_array(index, int, NULL, 0444); |
| 131 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
| 132 | module_param_array(id, charp, NULL, 0444); |
| 133 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
| 134 | module_param_array(enable, bool, NULL, 0444); |
| 135 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); |
| 136 | module_param_array(model, charp, NULL, 0444); |
| 137 | MODULE_PARM_DESC(model, "Use the given board model."); |
| 138 | module_param_array(position_fix, int, NULL, 0444); |
| 139 | MODULE_PARM_DESC(position_fix, "DMA pointer read method." |
| 140 | "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); |
| 141 | module_param_array(bdl_pos_adj, int, NULL, 0644); |
| 142 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); |
| 143 | module_param_array(probe_mask, int, NULL, 0444); |
| 144 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); |
| 145 | module_param_array(probe_only, int, NULL, 0444); |
| 146 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); |
| 147 | module_param_array(jackpoll_ms, int, NULL, 0444); |
| 148 | MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); |
| 149 | module_param(single_cmd, bint, 0444); |
| 150 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " |
| 151 | "(for debugging only)."); |
| 152 | module_param(enable_msi, bint, 0444); |
| 153 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); |
| 154 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
| 155 | module_param_array(patch, charp, NULL, 0444); |
| 156 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); |
| 157 | #endif |
| 158 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
| 159 | module_param_array(beep_mode, bool, NULL, 0444); |
| 160 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " |
| 161 | "(0=off, 1=on) (default=1)."); |
| 162 | #endif |
| 163 | module_param(dmic_detect, bool, 0444); |
| 164 | MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " |
| 165 | "(0=off, 1=on) (default=1); " |
| 166 | "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); |
| 167 | |
| 168 | #ifdef CONFIG_PM |
| 169 | static int param_set_xint(const char *val, const struct kernel_param *kp); |
| 170 | static const struct kernel_param_ops param_ops_xint = { |
| 171 | .set = param_set_xint, |
| 172 | .get = param_get_int, |
| 173 | }; |
| 174 | #define param_check_xint param_check_int |
| 175 | |
| 176 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
| 177 | module_param(power_save, xint, 0644); |
| 178 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " |
| 179 | "(in second, 0 = disable)."); |
| 180 | |
| 181 | static bool pm_blacklist = true; |
| 182 | module_param(pm_blacklist, bool, 0644); |
| 183 | MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); |
| 184 | |
| 185 | /* reset the HD-audio controller in power save mode. |
| 186 | * this may give more power-saving, but will take longer time to |
| 187 | * wake up. |
| 188 | */ |
| 189 | static bool power_save_controller = 1; |
| 190 | module_param(power_save_controller, bool, 0644); |
| 191 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); |
| 192 | #else |
| 193 | #define power_save 0 |
| 194 | #endif /* CONFIG_PM */ |
| 195 | |
| 196 | static int align_buffer_size = -1; |
| 197 | module_param(align_buffer_size, bint, 0644); |
| 198 | MODULE_PARM_DESC(align_buffer_size, |
| 199 | "Force buffer and period sizes to be multiple of 128 bytes."); |
| 200 | |
| 201 | #ifdef CONFIG_X86 |
| 202 | static int hda_snoop = -1; |
| 203 | module_param_named(snoop, hda_snoop, bint, 0444); |
| 204 | MODULE_PARM_DESC(snoop, "Enable/disable snooping"); |
| 205 | #else |
| 206 | #define hda_snoop true |
| 207 | #endif |
| 208 | |
| 209 | |
| 210 | MODULE_LICENSE("GPL"); |
| 211 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," |
| 212 | "{Intel, ICH6M}," |
| 213 | "{Intel, ICH7}," |
| 214 | "{Intel, ESB2}," |
| 215 | "{Intel, ICH8}," |
| 216 | "{Intel, ICH9}," |
| 217 | "{Intel, ICH10}," |
| 218 | "{Intel, PCH}," |
| 219 | "{Intel, CPT}," |
| 220 | "{Intel, PPT}," |
| 221 | "{Intel, LPT}," |
| 222 | "{Intel, LPT_LP}," |
| 223 | "{Intel, WPT_LP}," |
| 224 | "{Intel, SPT}," |
| 225 | "{Intel, SPT_LP}," |
| 226 | "{Intel, HPT}," |
| 227 | "{Intel, PBG}," |
| 228 | "{Intel, SCH}," |
| 229 | "{ATI, SB450}," |
| 230 | "{ATI, SB600}," |
| 231 | "{ATI, RS600}," |
| 232 | "{ATI, RS690}," |
| 233 | "{ATI, RS780}," |
| 234 | "{ATI, R600}," |
| 235 | "{ATI, RV630}," |
| 236 | "{ATI, RV610}," |
| 237 | "{ATI, RV670}," |
| 238 | "{ATI, RV635}," |
| 239 | "{ATI, RV620}," |
| 240 | "{ATI, RV770}," |
| 241 | "{VIA, VT8251}," |
| 242 | "{VIA, VT8237A}," |
| 243 | "{SiS, SIS966}," |
| 244 | "{ULI, M5461}}"); |
| 245 | MODULE_DESCRIPTION("Intel HDA driver"); |
| 246 | |
| 247 | #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) |
| 248 | #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) |
| 249 | #define SUPPORT_VGA_SWITCHEROO |
| 250 | #endif |
| 251 | #endif |
| 252 | |
| 253 | |
| 254 | /* |
| 255 | */ |
| 256 | |
| 257 | /* driver types */ |
| 258 | enum { |
| 259 | AZX_DRIVER_ICH, |
| 260 | AZX_DRIVER_PCH, |
| 261 | AZX_DRIVER_SCH, |
| 262 | AZX_DRIVER_SKL, |
| 263 | AZX_DRIVER_HDMI, |
| 264 | AZX_DRIVER_ATI, |
| 265 | AZX_DRIVER_ATIHDMI, |
| 266 | AZX_DRIVER_ATIHDMI_NS, |
| 267 | AZX_DRIVER_VIA, |
| 268 | AZX_DRIVER_SIS, |
| 269 | AZX_DRIVER_ULI, |
| 270 | AZX_DRIVER_NVIDIA, |
| 271 | AZX_DRIVER_TERA, |
| 272 | AZX_DRIVER_CTX, |
| 273 | AZX_DRIVER_CTHDA, |
| 274 | AZX_DRIVER_CMEDIA, |
| 275 | AZX_DRIVER_ZHAOXIN, |
| 276 | AZX_DRIVER_GENERIC, |
| 277 | AZX_NUM_DRIVERS, /* keep this as last entry */ |
| 278 | }; |
| 279 | |
| 280 | #define azx_get_snoop_type(chip) \ |
| 281 | (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) |
| 282 | #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) |
| 283 | |
| 284 | /* quirks for old Intel chipsets */ |
| 285 | #define AZX_DCAPS_INTEL_ICH \ |
| 286 | (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) |
| 287 | |
| 288 | /* quirks for Intel PCH */ |
| 289 | #define AZX_DCAPS_INTEL_PCH_BASE \ |
| 290 | (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ |
| 291 | AZX_DCAPS_SNOOP_TYPE(SCH)) |
| 292 | |
| 293 | /* PCH up to IVB; no runtime PM; bind with i915 gfx */ |
| 294 | #define AZX_DCAPS_INTEL_PCH_NOPM \ |
| 295 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) |
| 296 | |
| 297 | /* PCH for HSW/BDW; with runtime PM */ |
| 298 | /* no i915 binding for this as HSW/BDW has another controller for HDMI */ |
| 299 | #define AZX_DCAPS_INTEL_PCH \ |
| 300 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) |
| 301 | |
| 302 | /* HSW HDMI */ |
| 303 | #define AZX_DCAPS_INTEL_HASWELL \ |
| 304 | (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ |
| 305 | AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ |
| 306 | AZX_DCAPS_SNOOP_TYPE(SCH)) |
| 307 | |
| 308 | /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ |
| 309 | #define AZX_DCAPS_INTEL_BROADWELL \ |
| 310 | (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ |
| 311 | AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ |
| 312 | AZX_DCAPS_SNOOP_TYPE(SCH)) |
| 313 | |
| 314 | #define AZX_DCAPS_INTEL_BAYTRAIL \ |
| 315 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) |
| 316 | |
| 317 | #define AZX_DCAPS_INTEL_BRASWELL \ |
| 318 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ |
| 319 | AZX_DCAPS_I915_COMPONENT) |
| 320 | |
| 321 | #define AZX_DCAPS_INTEL_SKYLAKE \ |
| 322 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ |
| 323 | AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) |
| 324 | |
| 325 | #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE |
| 326 | |
| 327 | /* quirks for ATI SB / AMD Hudson */ |
| 328 | #define AZX_DCAPS_PRESET_ATI_SB \ |
| 329 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ |
| 330 | AZX_DCAPS_SNOOP_TYPE(ATI)) |
| 331 | |
| 332 | /* quirks for ATI/AMD HDMI */ |
| 333 | #define AZX_DCAPS_PRESET_ATI_HDMI \ |
| 334 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ |
| 335 | AZX_DCAPS_NO_MSI64) |
| 336 | |
| 337 | /* quirks for ATI HDMI with snoop off */ |
| 338 | #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ |
| 339 | (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) |
| 340 | |
| 341 | /* quirks for AMD SB */ |
| 342 | #define AZX_DCAPS_PRESET_AMD_SB \ |
| 343 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ |
| 344 | AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) |
| 345 | |
| 346 | /* quirks for Nvidia */ |
| 347 | #define AZX_DCAPS_PRESET_NVIDIA \ |
| 348 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ |
| 349 | AZX_DCAPS_SNOOP_TYPE(NVIDIA)) |
| 350 | |
| 351 | #define AZX_DCAPS_PRESET_CTHDA \ |
| 352 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ |
| 353 | AZX_DCAPS_NO_64BIT |\ |
| 354 | AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) |
| 355 | |
| 356 | /* |
| 357 | * vga_switcheroo support |
| 358 | */ |
| 359 | #ifdef SUPPORT_VGA_SWITCHEROO |
| 360 | #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) |
| 361 | #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) |
| 362 | #else |
| 363 | #define use_vga_switcheroo(chip) 0 |
| 364 | #define needs_eld_notify_link(chip) false |
| 365 | #endif |
| 366 | |
| 367 | #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ |
| 368 | ((pci)->device == 0x0c0c) || \ |
| 369 | ((pci)->device == 0x0d0c) || \ |
| 370 | ((pci)->device == 0x160c) || \ |
| 371 | ((pci)->device == 0x490d)) |
| 372 | |
| 373 | #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) |
| 374 | |
| 375 | static const char * const driver_short_names[] = { |
| 376 | [AZX_DRIVER_ICH] = "HDA Intel", |
| 377 | [AZX_DRIVER_PCH] = "HDA Intel PCH", |
| 378 | [AZX_DRIVER_SCH] = "HDA Intel MID", |
| 379 | [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ |
| 380 | [AZX_DRIVER_HDMI] = "HDA Intel HDMI", |
| 381 | [AZX_DRIVER_ATI] = "HDA ATI SB", |
| 382 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
| 383 | [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", |
| 384 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
| 385 | [AZX_DRIVER_SIS] = "HDA SIS966", |
| 386 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
| 387 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", |
| 388 | [AZX_DRIVER_TERA] = "HDA Teradici", |
| 389 | [AZX_DRIVER_CTX] = "HDA Creative", |
| 390 | [AZX_DRIVER_CTHDA] = "HDA Creative", |
| 391 | [AZX_DRIVER_CMEDIA] = "HDA C-Media", |
| 392 | [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", |
| 393 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", |
| 394 | }; |
| 395 | |
| 396 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
| 397 | static void set_default_power_save(struct azx *chip); |
| 398 | |
| 399 | /* |
| 400 | * initialize the PCI registers |
| 401 | */ |
| 402 | /* update bits in a PCI register byte */ |
| 403 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, |
| 404 | unsigned char mask, unsigned char val) |
| 405 | { |
| 406 | unsigned char data; |
| 407 | |
| 408 | pci_read_config_byte(pci, reg, &data); |
| 409 | data &= ~mask; |
| 410 | data |= (val & mask); |
| 411 | pci_write_config_byte(pci, reg, data); |
| 412 | } |
| 413 | |
| 414 | static void azx_init_pci(struct azx *chip) |
| 415 | { |
| 416 | int snoop_type = azx_get_snoop_type(chip); |
| 417 | |
| 418 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
| 419 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS |
| 420 | * Ensuring these bits are 0 clears playback static on some HD Audio |
| 421 | * codecs. |
| 422 | * The PCI register TCSEL is defined in the Intel manuals. |
| 423 | */ |
| 424 | if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { |
| 425 | dev_dbg(chip->card->dev, "Clearing TCSEL\n"); |
| 426 | update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); |
| 427 | } |
| 428 | |
| 429 | /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, |
| 430 | * we need to enable snoop. |
| 431 | */ |
| 432 | if (snoop_type == AZX_SNOOP_TYPE_ATI) { |
| 433 | dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", |
| 434 | azx_snoop(chip)); |
| 435 | update_pci_byte(chip->pci, |
| 436 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, |
| 437 | azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); |
| 438 | } |
| 439 | |
| 440 | /* For NVIDIA HDA, enable snoop */ |
| 441 | if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { |
| 442 | dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", |
| 443 | azx_snoop(chip)); |
| 444 | update_pci_byte(chip->pci, |
| 445 | NVIDIA_HDA_TRANSREG_ADDR, |
| 446 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); |
| 447 | update_pci_byte(chip->pci, |
| 448 | NVIDIA_HDA_ISTRM_COH, |
| 449 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); |
| 450 | update_pci_byte(chip->pci, |
| 451 | NVIDIA_HDA_OSTRM_COH, |
| 452 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); |
| 453 | } |
| 454 | |
| 455 | /* Enable SCH/PCH snoop if needed */ |
| 456 | if (snoop_type == AZX_SNOOP_TYPE_SCH) { |
| 457 | unsigned short snoop; |
| 458 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); |
| 459 | if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || |
| 460 | (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { |
| 461 | snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; |
| 462 | if (!azx_snoop(chip)) |
| 463 | snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; |
| 464 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); |
| 465 | pci_read_config_word(chip->pci, |
| 466 | INTEL_SCH_HDA_DEVC, &snoop); |
| 467 | } |
| 468 | dev_dbg(chip->card->dev, "SCH snoop: %s\n", |
| 469 | (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? |
| 470 | "Disabled" : "Enabled"); |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | /* |
| 475 | * In BXT-P A0, HD-Audio DMA requests is later than expected, |
| 476 | * and makes an audio stream sensitive to system latencies when |
| 477 | * 24/32 bits are playing. |
| 478 | * Adjusting threshold of DMA fifo to force the DMA request |
| 479 | * sooner to improve latency tolerance at the expense of power. |
| 480 | */ |
| 481 | static void bxt_reduce_dma_latency(struct azx *chip) |
| 482 | { |
| 483 | u32 val; |
| 484 | |
| 485 | val = azx_readl(chip, VS_EM4L); |
| 486 | val &= (0x3 << 20); |
| 487 | azx_writel(chip, VS_EM4L, val); |
| 488 | } |
| 489 | |
| 490 | /* |
| 491 | * ML_LCAP bits: |
| 492 | * bit 0: 6 MHz Supported |
| 493 | * bit 1: 12 MHz Supported |
| 494 | * bit 2: 24 MHz Supported |
| 495 | * bit 3: 48 MHz Supported |
| 496 | * bit 4: 96 MHz Supported |
| 497 | * bit 5: 192 MHz Supported |
| 498 | */ |
| 499 | static int intel_get_lctl_scf(struct azx *chip) |
| 500 | { |
| 501 | struct hdac_bus *bus = azx_bus(chip); |
| 502 | static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; |
| 503 | u32 val, t; |
| 504 | int i; |
| 505 | |
| 506 | val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); |
| 507 | |
| 508 | for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { |
| 509 | t = preferred_bits[i]; |
| 510 | if (val & (1 << t)) |
| 511 | return t; |
| 512 | } |
| 513 | |
| 514 | dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static int intel_ml_lctl_set_power(struct azx *chip, int state) |
| 519 | { |
| 520 | struct hdac_bus *bus = azx_bus(chip); |
| 521 | u32 val; |
| 522 | int timeout; |
| 523 | |
| 524 | /* |
| 525 | * the codecs are sharing the first link setting by default |
| 526 | * If other links are enabled for stream, they need similar fix |
| 527 | */ |
| 528 | val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); |
| 529 | val &= ~AZX_MLCTL_SPA; |
| 530 | val |= state << AZX_MLCTL_SPA_SHIFT; |
| 531 | writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); |
| 532 | /* wait for CPA */ |
| 533 | timeout = 50; |
| 534 | while (timeout) { |
| 535 | if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & |
| 536 | AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) |
| 537 | return 0; |
| 538 | timeout--; |
| 539 | udelay(10); |
| 540 | } |
| 541 | |
| 542 | return -1; |
| 543 | } |
| 544 | |
| 545 | static void intel_init_lctl(struct azx *chip) |
| 546 | { |
| 547 | struct hdac_bus *bus = azx_bus(chip); |
| 548 | u32 val; |
| 549 | int ret; |
| 550 | |
| 551 | /* 0. check lctl register value is correct or not */ |
| 552 | val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); |
| 553 | /* if SCF is already set, let's use it */ |
| 554 | if ((val & ML_LCTL_SCF_MASK) != 0) |
| 555 | return; |
| 556 | |
| 557 | /* |
| 558 | * Before operating on SPA, CPA must match SPA. |
| 559 | * Any deviation may result in undefined behavior. |
| 560 | */ |
| 561 | if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != |
| 562 | ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) |
| 563 | return; |
| 564 | |
| 565 | /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ |
| 566 | ret = intel_ml_lctl_set_power(chip, 0); |
| 567 | udelay(100); |
| 568 | if (ret) |
| 569 | goto set_spa; |
| 570 | |
| 571 | /* 2. update SCF to select a properly audio clock*/ |
| 572 | val &= ~ML_LCTL_SCF_MASK; |
| 573 | val |= intel_get_lctl_scf(chip); |
| 574 | writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); |
| 575 | |
| 576 | set_spa: |
| 577 | /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ |
| 578 | intel_ml_lctl_set_power(chip, 1); |
| 579 | udelay(100); |
| 580 | } |
| 581 | |
| 582 | static void hda_intel_init_chip(struct azx *chip, bool full_reset) |
| 583 | { |
| 584 | struct hdac_bus *bus = azx_bus(chip); |
| 585 | struct pci_dev *pci = chip->pci; |
| 586 | u32 val; |
| 587 | |
| 588 | snd_hdac_set_codec_wakeup(bus, true); |
| 589 | if (chip->driver_type == AZX_DRIVER_SKL) { |
| 590 | pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); |
| 591 | val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; |
| 592 | pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); |
| 593 | } |
| 594 | azx_init_chip(chip, full_reset); |
| 595 | if (chip->driver_type == AZX_DRIVER_SKL) { |
| 596 | pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); |
| 597 | val = val | INTEL_HDA_CGCTL_MISCBDCGE; |
| 598 | pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); |
| 599 | } |
| 600 | |
| 601 | snd_hdac_set_codec_wakeup(bus, false); |
| 602 | |
| 603 | /* reduce dma latency to avoid noise */ |
| 604 | if (IS_BXT(pci)) |
| 605 | bxt_reduce_dma_latency(chip); |
| 606 | |
| 607 | if (bus->mlcap != NULL) |
| 608 | intel_init_lctl(chip); |
| 609 | } |
| 610 | |
| 611 | /* calculate runtime delay from LPIB */ |
| 612 | static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, |
| 613 | unsigned int pos) |
| 614 | { |
| 615 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
| 616 | int stream = substream->stream; |
| 617 | unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); |
| 618 | int delay; |
| 619 | |
| 620 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 621 | delay = pos - lpib_pos; |
| 622 | else |
| 623 | delay = lpib_pos - pos; |
| 624 | if (delay < 0) { |
| 625 | if (delay >= azx_dev->core.delay_negative_threshold) |
| 626 | delay = 0; |
| 627 | else |
| 628 | delay += azx_dev->core.bufsize; |
| 629 | } |
| 630 | |
| 631 | if (delay >= azx_dev->core.period_bytes) { |
| 632 | dev_info(chip->card->dev, |
| 633 | "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", |
| 634 | delay, azx_dev->core.period_bytes); |
| 635 | delay = 0; |
| 636 | chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; |
| 637 | chip->get_delay[stream] = NULL; |
| 638 | } |
| 639 | |
| 640 | return bytes_to_frames(substream->runtime, delay); |
| 641 | } |
| 642 | |
| 643 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); |
| 644 | |
| 645 | /* called from IRQ */ |
| 646 | static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) |
| 647 | { |
| 648 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 649 | int ok; |
| 650 | |
| 651 | ok = azx_position_ok(chip, azx_dev); |
| 652 | if (ok == 1) { |
| 653 | azx_dev->irq_pending = 0; |
| 654 | return ok; |
| 655 | } else if (ok == 0) { |
| 656 | /* bogus IRQ, process it later */ |
| 657 | azx_dev->irq_pending = 1; |
| 658 | schedule_work(&hda->irq_pending_work); |
| 659 | } |
| 660 | return 0; |
| 661 | } |
| 662 | |
| 663 | #define display_power(chip, enable) \ |
| 664 | snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) |
| 665 | |
| 666 | /* |
| 667 | * Check whether the current DMA position is acceptable for updating |
| 668 | * periods. Returns non-zero if it's OK. |
| 669 | * |
| 670 | * Many HD-audio controllers appear pretty inaccurate about |
| 671 | * the update-IRQ timing. The IRQ is issued before actually the |
| 672 | * data is processed. So, we need to process it afterwords in a |
| 673 | * workqueue. |
| 674 | */ |
| 675 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) |
| 676 | { |
| 677 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
| 678 | int stream = substream->stream; |
| 679 | u32 wallclk; |
| 680 | unsigned int pos; |
| 681 | |
| 682 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; |
| 683 | if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) |
| 684 | return -1; /* bogus (too early) interrupt */ |
| 685 | |
| 686 | if (chip->get_position[stream]) |
| 687 | pos = chip->get_position[stream](chip, azx_dev); |
| 688 | else { /* use the position buffer as default */ |
| 689 | pos = azx_get_pos_posbuf(chip, azx_dev); |
| 690 | if (!pos || pos == (u32)-1) { |
| 691 | dev_info(chip->card->dev, |
| 692 | "Invalid position buffer, using LPIB read method instead.\n"); |
| 693 | chip->get_position[stream] = azx_get_pos_lpib; |
| 694 | if (chip->get_position[0] == azx_get_pos_lpib && |
| 695 | chip->get_position[1] == azx_get_pos_lpib) |
| 696 | azx_bus(chip)->use_posbuf = false; |
| 697 | pos = azx_get_pos_lpib(chip, azx_dev); |
| 698 | chip->get_delay[stream] = NULL; |
| 699 | } else { |
| 700 | chip->get_position[stream] = azx_get_pos_posbuf; |
| 701 | if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) |
| 702 | chip->get_delay[stream] = azx_get_delay_from_lpib; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | if (pos >= azx_dev->core.bufsize) |
| 707 | pos = 0; |
| 708 | |
| 709 | if (WARN_ONCE(!azx_dev->core.period_bytes, |
| 710 | "hda-intel: zero azx_dev->period_bytes")) |
| 711 | return -1; /* this shouldn't happen! */ |
| 712 | if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && |
| 713 | pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) |
| 714 | /* NG - it's below the first next period boundary */ |
| 715 | return chip->bdl_pos_adj ? 0 : -1; |
| 716 | azx_dev->core.start_wallclk += wallclk; |
| 717 | return 1; /* OK, it's fine */ |
| 718 | } |
| 719 | |
| 720 | /* |
| 721 | * The work for pending PCM period updates. |
| 722 | */ |
| 723 | static void azx_irq_pending_work(struct work_struct *work) |
| 724 | { |
| 725 | struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); |
| 726 | struct azx *chip = &hda->chip; |
| 727 | struct hdac_bus *bus = azx_bus(chip); |
| 728 | struct hdac_stream *s; |
| 729 | int pending, ok; |
| 730 | |
| 731 | if (!hda->irq_pending_warned) { |
| 732 | dev_info(chip->card->dev, |
| 733 | "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", |
| 734 | chip->card->number); |
| 735 | hda->irq_pending_warned = 1; |
| 736 | } |
| 737 | |
| 738 | for (;;) { |
| 739 | pending = 0; |
| 740 | spin_lock_irq(&bus->reg_lock); |
| 741 | list_for_each_entry(s, &bus->stream_list, list) { |
| 742 | struct azx_dev *azx_dev = stream_to_azx_dev(s); |
| 743 | if (!azx_dev->irq_pending || |
| 744 | !s->substream || |
| 745 | !s->running) |
| 746 | continue; |
| 747 | ok = azx_position_ok(chip, azx_dev); |
| 748 | if (ok > 0) { |
| 749 | azx_dev->irq_pending = 0; |
| 750 | spin_unlock(&bus->reg_lock); |
| 751 | snd_pcm_period_elapsed(s->substream); |
| 752 | spin_lock(&bus->reg_lock); |
| 753 | } else if (ok < 0) { |
| 754 | pending = 0; /* too early */ |
| 755 | } else |
| 756 | pending++; |
| 757 | } |
| 758 | spin_unlock_irq(&bus->reg_lock); |
| 759 | if (!pending) |
| 760 | return; |
| 761 | msleep(1); |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | /* clear irq_pending flags and assure no on-going workq */ |
| 766 | static void azx_clear_irq_pending(struct azx *chip) |
| 767 | { |
| 768 | struct hdac_bus *bus = azx_bus(chip); |
| 769 | struct hdac_stream *s; |
| 770 | |
| 771 | spin_lock_irq(&bus->reg_lock); |
| 772 | list_for_each_entry(s, &bus->stream_list, list) { |
| 773 | struct azx_dev *azx_dev = stream_to_azx_dev(s); |
| 774 | azx_dev->irq_pending = 0; |
| 775 | } |
| 776 | spin_unlock_irq(&bus->reg_lock); |
| 777 | } |
| 778 | |
| 779 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
| 780 | { |
| 781 | struct hdac_bus *bus = azx_bus(chip); |
| 782 | |
| 783 | if (request_irq(chip->pci->irq, azx_interrupt, |
| 784 | chip->msi ? 0 : IRQF_SHARED, |
| 785 | chip->card->irq_descr, chip)) { |
| 786 | dev_err(chip->card->dev, |
| 787 | "unable to grab IRQ %d, disabling device\n", |
| 788 | chip->pci->irq); |
| 789 | if (do_disconnect) |
| 790 | snd_card_disconnect(chip->card); |
| 791 | return -1; |
| 792 | } |
| 793 | bus->irq = chip->pci->irq; |
| 794 | chip->card->sync_irq = bus->irq; |
| 795 | pci_intx(chip->pci, !chip->msi); |
| 796 | return 0; |
| 797 | } |
| 798 | |
| 799 | /* get the current DMA position with correction on VIA chips */ |
| 800 | static unsigned int azx_via_get_position(struct azx *chip, |
| 801 | struct azx_dev *azx_dev) |
| 802 | { |
| 803 | unsigned int link_pos, mini_pos, bound_pos; |
| 804 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; |
| 805 | unsigned int fifo_size; |
| 806 | |
| 807 | link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
| 808 | if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 809 | /* Playback, no problem using link position */ |
| 810 | return link_pos; |
| 811 | } |
| 812 | |
| 813 | /* Capture */ |
| 814 | /* For new chipset, |
| 815 | * use mod to get the DMA position just like old chipset |
| 816 | */ |
| 817 | mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); |
| 818 | mod_dma_pos %= azx_dev->core.period_bytes; |
| 819 | |
| 820 | fifo_size = azx_stream(azx_dev)->fifo_size - 1; |
| 821 | |
| 822 | if (azx_dev->insufficient) { |
| 823 | /* Link position never gather than FIFO size */ |
| 824 | if (link_pos <= fifo_size) |
| 825 | return 0; |
| 826 | |
| 827 | azx_dev->insufficient = 0; |
| 828 | } |
| 829 | |
| 830 | if (link_pos <= fifo_size) |
| 831 | mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; |
| 832 | else |
| 833 | mini_pos = link_pos - fifo_size; |
| 834 | |
| 835 | /* Find nearest previous boudary */ |
| 836 | mod_mini_pos = mini_pos % azx_dev->core.period_bytes; |
| 837 | mod_link_pos = link_pos % azx_dev->core.period_bytes; |
| 838 | if (mod_link_pos >= fifo_size) |
| 839 | bound_pos = link_pos - mod_link_pos; |
| 840 | else if (mod_dma_pos >= mod_mini_pos) |
| 841 | bound_pos = mini_pos - mod_mini_pos; |
| 842 | else { |
| 843 | bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; |
| 844 | if (bound_pos >= azx_dev->core.bufsize) |
| 845 | bound_pos = 0; |
| 846 | } |
| 847 | |
| 848 | /* Calculate real DMA position we want */ |
| 849 | return bound_pos + mod_dma_pos; |
| 850 | } |
| 851 | |
| 852 | #define AMD_FIFO_SIZE 32 |
| 853 | |
| 854 | /* get the current DMA position with FIFO size correction */ |
| 855 | static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) |
| 856 | { |
| 857 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
| 858 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 859 | unsigned int pos, delay; |
| 860 | |
| 861 | pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
| 862 | if (!runtime) |
| 863 | return pos; |
| 864 | |
| 865 | runtime->delay = AMD_FIFO_SIZE; |
| 866 | delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); |
| 867 | if (azx_dev->insufficient) { |
| 868 | if (pos < delay) { |
| 869 | delay = pos; |
| 870 | runtime->delay = bytes_to_frames(runtime, pos); |
| 871 | } else { |
| 872 | azx_dev->insufficient = 0; |
| 873 | } |
| 874 | } |
| 875 | |
| 876 | /* correct the DMA position for capture stream */ |
| 877 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
| 878 | if (pos < delay) |
| 879 | pos += azx_dev->core.bufsize; |
| 880 | pos -= delay; |
| 881 | } |
| 882 | |
| 883 | return pos; |
| 884 | } |
| 885 | |
| 886 | static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, |
| 887 | unsigned int pos) |
| 888 | { |
| 889 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
| 890 | |
| 891 | /* just read back the calculated value in the above */ |
| 892 | return substream->runtime->delay; |
| 893 | } |
| 894 | |
| 895 | static unsigned int azx_skl_get_dpib_pos(struct azx *chip, |
| 896 | struct azx_dev *azx_dev) |
| 897 | { |
| 898 | return _snd_hdac_chip_readl(azx_bus(chip), |
| 899 | AZX_REG_VS_SDXDPIB_XBASE + |
| 900 | (AZX_REG_VS_SDXDPIB_XINTERVAL * |
| 901 | azx_dev->core.index)); |
| 902 | } |
| 903 | |
| 904 | /* get the current DMA position with correction on SKL+ chips */ |
| 905 | static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) |
| 906 | { |
| 907 | /* DPIB register gives a more accurate position for playback */ |
| 908 | if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 909 | return azx_skl_get_dpib_pos(chip, azx_dev); |
| 910 | |
| 911 | /* For capture, we need to read posbuf, but it requires a delay |
| 912 | * for the possible boundary overlap; the read of DPIB fetches the |
| 913 | * actual posbuf |
| 914 | */ |
| 915 | udelay(20); |
| 916 | azx_skl_get_dpib_pos(chip, azx_dev); |
| 917 | return azx_get_pos_posbuf(chip, azx_dev); |
| 918 | } |
| 919 | |
| 920 | #ifdef CONFIG_PM |
| 921 | static DEFINE_MUTEX(card_list_lock); |
| 922 | static LIST_HEAD(card_list); |
| 923 | |
| 924 | static void azx_add_card_list(struct azx *chip) |
| 925 | { |
| 926 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 927 | mutex_lock(&card_list_lock); |
| 928 | list_add(&hda->list, &card_list); |
| 929 | mutex_unlock(&card_list_lock); |
| 930 | } |
| 931 | |
| 932 | static void azx_del_card_list(struct azx *chip) |
| 933 | { |
| 934 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 935 | mutex_lock(&card_list_lock); |
| 936 | list_del_init(&hda->list); |
| 937 | mutex_unlock(&card_list_lock); |
| 938 | } |
| 939 | |
| 940 | /* trigger power-save check at writing parameter */ |
| 941 | static int param_set_xint(const char *val, const struct kernel_param *kp) |
| 942 | { |
| 943 | struct hda_intel *hda; |
| 944 | struct azx *chip; |
| 945 | int prev = power_save; |
| 946 | int ret = param_set_int(val, kp); |
| 947 | |
| 948 | if (ret || prev == power_save) |
| 949 | return ret; |
| 950 | |
| 951 | mutex_lock(&card_list_lock); |
| 952 | list_for_each_entry(hda, &card_list, list) { |
| 953 | chip = &hda->chip; |
| 954 | if (!hda->probe_continued || chip->disabled) |
| 955 | continue; |
| 956 | snd_hda_set_power_save(&chip->bus, power_save * 1000); |
| 957 | } |
| 958 | mutex_unlock(&card_list_lock); |
| 959 | return 0; |
| 960 | } |
| 961 | |
| 962 | /* |
| 963 | * power management |
| 964 | */ |
| 965 | static bool azx_is_pm_ready(struct snd_card *card) |
| 966 | { |
| 967 | struct azx *chip; |
| 968 | struct hda_intel *hda; |
| 969 | |
| 970 | if (!card) |
| 971 | return false; |
| 972 | chip = card->private_data; |
| 973 | hda = container_of(chip, struct hda_intel, chip); |
| 974 | if (chip->disabled || hda->init_failed || !chip->running) |
| 975 | return false; |
| 976 | return true; |
| 977 | } |
| 978 | |
| 979 | static void __azx_runtime_suspend(struct azx *chip) |
| 980 | { |
| 981 | azx_stop_chip(chip); |
| 982 | azx_enter_link_reset(chip); |
| 983 | azx_clear_irq_pending(chip); |
| 984 | display_power(chip, false); |
| 985 | } |
| 986 | |
| 987 | static void __azx_runtime_resume(struct azx *chip) |
| 988 | { |
| 989 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 990 | struct hdac_bus *bus = azx_bus(chip); |
| 991 | struct hda_codec *codec; |
| 992 | int status; |
| 993 | |
| 994 | display_power(chip, true); |
| 995 | if (hda->need_i915_power) |
| 996 | snd_hdac_i915_set_bclk(bus); |
| 997 | |
| 998 | /* Read STATESTS before controller reset */ |
| 999 | status = azx_readw(chip, STATESTS); |
| 1000 | |
| 1001 | azx_init_pci(chip); |
| 1002 | hda_intel_init_chip(chip, true); |
| 1003 | |
| 1004 | /* Avoid codec resume if runtime resume is for system suspend */ |
| 1005 | if (!chip->pm_prepared) { |
| 1006 | list_for_each_codec(codec, &chip->bus) { |
| 1007 | if (codec->relaxed_resume) |
| 1008 | continue; |
| 1009 | |
| 1010 | if (codec->forced_resume || (status & (1 << codec->addr))) |
| 1011 | pm_request_resume(hda_codec_dev(codec)); |
| 1012 | } |
| 1013 | } |
| 1014 | |
| 1015 | /* power down again for link-controlled chips */ |
| 1016 | if (!hda->need_i915_power) |
| 1017 | display_power(chip, false); |
| 1018 | } |
| 1019 | |
| 1020 | #ifdef CONFIG_PM_SLEEP |
| 1021 | static int azx_prepare(struct device *dev) |
| 1022 | { |
| 1023 | struct snd_card *card = dev_get_drvdata(dev); |
| 1024 | struct azx *chip; |
| 1025 | |
| 1026 | chip = card->private_data; |
| 1027 | chip->pm_prepared = 1; |
| 1028 | |
| 1029 | /* HDA controller always requires different WAKEEN for runtime suspend |
| 1030 | * and system suspend, so don't use direct-complete here. |
| 1031 | */ |
| 1032 | return 0; |
| 1033 | } |
| 1034 | |
| 1035 | static void azx_complete(struct device *dev) |
| 1036 | { |
| 1037 | struct snd_card *card = dev_get_drvdata(dev); |
| 1038 | struct azx *chip; |
| 1039 | |
| 1040 | chip = card->private_data; |
| 1041 | chip->pm_prepared = 0; |
| 1042 | } |
| 1043 | |
| 1044 | static int azx_suspend(struct device *dev) |
| 1045 | { |
| 1046 | struct snd_card *card = dev_get_drvdata(dev); |
| 1047 | struct azx *chip; |
| 1048 | struct hdac_bus *bus; |
| 1049 | |
| 1050 | if (!azx_is_pm_ready(card)) |
| 1051 | return 0; |
| 1052 | |
| 1053 | chip = card->private_data; |
| 1054 | bus = azx_bus(chip); |
| 1055 | __azx_runtime_suspend(chip); |
| 1056 | if (bus->irq >= 0) { |
| 1057 | free_irq(bus->irq, chip); |
| 1058 | bus->irq = -1; |
| 1059 | chip->card->sync_irq = -1; |
| 1060 | } |
| 1061 | |
| 1062 | if (chip->msi) |
| 1063 | pci_disable_msi(chip->pci); |
| 1064 | |
| 1065 | trace_azx_suspend(chip); |
| 1066 | return 0; |
| 1067 | } |
| 1068 | |
| 1069 | static int azx_resume(struct device *dev) |
| 1070 | { |
| 1071 | struct snd_card *card = dev_get_drvdata(dev); |
| 1072 | struct azx *chip; |
| 1073 | |
| 1074 | if (!azx_is_pm_ready(card)) |
| 1075 | return 0; |
| 1076 | |
| 1077 | chip = card->private_data; |
| 1078 | if (chip->msi) |
| 1079 | if (pci_enable_msi(chip->pci) < 0) |
| 1080 | chip->msi = 0; |
| 1081 | if (azx_acquire_irq(chip, 1) < 0) |
| 1082 | return -EIO; |
| 1083 | |
| 1084 | __azx_runtime_resume(chip); |
| 1085 | |
| 1086 | trace_azx_resume(chip); |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
| 1090 | /* put codec down to D3 at hibernation for Intel SKL+; |
| 1091 | * otherwise BIOS may still access the codec and screw up the driver |
| 1092 | */ |
| 1093 | static int azx_freeze_noirq(struct device *dev) |
| 1094 | { |
| 1095 | struct snd_card *card = dev_get_drvdata(dev); |
| 1096 | struct azx *chip = card->private_data; |
| 1097 | struct pci_dev *pci = to_pci_dev(dev); |
| 1098 | |
| 1099 | if (!azx_is_pm_ready(card)) |
| 1100 | return 0; |
| 1101 | if (chip->driver_type == AZX_DRIVER_SKL) |
| 1102 | pci_set_power_state(pci, PCI_D3hot); |
| 1103 | |
| 1104 | return 0; |
| 1105 | } |
| 1106 | |
| 1107 | static int azx_thaw_noirq(struct device *dev) |
| 1108 | { |
| 1109 | struct snd_card *card = dev_get_drvdata(dev); |
| 1110 | struct azx *chip = card->private_data; |
| 1111 | struct pci_dev *pci = to_pci_dev(dev); |
| 1112 | |
| 1113 | if (!azx_is_pm_ready(card)) |
| 1114 | return 0; |
| 1115 | if (chip->driver_type == AZX_DRIVER_SKL) |
| 1116 | pci_set_power_state(pci, PCI_D0); |
| 1117 | |
| 1118 | return 0; |
| 1119 | } |
| 1120 | #endif /* CONFIG_PM_SLEEP */ |
| 1121 | |
| 1122 | static int azx_runtime_suspend(struct device *dev) |
| 1123 | { |
| 1124 | struct snd_card *card = dev_get_drvdata(dev); |
| 1125 | struct azx *chip; |
| 1126 | |
| 1127 | if (!azx_is_pm_ready(card)) |
| 1128 | return 0; |
| 1129 | chip = card->private_data; |
| 1130 | |
| 1131 | /* enable controller wake up event */ |
| 1132 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); |
| 1133 | |
| 1134 | __azx_runtime_suspend(chip); |
| 1135 | trace_azx_runtime_suspend(chip); |
| 1136 | return 0; |
| 1137 | } |
| 1138 | |
| 1139 | static int azx_runtime_resume(struct device *dev) |
| 1140 | { |
| 1141 | struct snd_card *card = dev_get_drvdata(dev); |
| 1142 | struct azx *chip; |
| 1143 | |
| 1144 | if (!azx_is_pm_ready(card)) |
| 1145 | return 0; |
| 1146 | chip = card->private_data; |
| 1147 | __azx_runtime_resume(chip); |
| 1148 | |
| 1149 | /* disable controller Wake Up event*/ |
| 1150 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); |
| 1151 | |
| 1152 | trace_azx_runtime_resume(chip); |
| 1153 | return 0; |
| 1154 | } |
| 1155 | |
| 1156 | static int azx_runtime_idle(struct device *dev) |
| 1157 | { |
| 1158 | struct snd_card *card = dev_get_drvdata(dev); |
| 1159 | struct azx *chip; |
| 1160 | struct hda_intel *hda; |
| 1161 | |
| 1162 | if (!card) |
| 1163 | return 0; |
| 1164 | |
| 1165 | chip = card->private_data; |
| 1166 | hda = container_of(chip, struct hda_intel, chip); |
| 1167 | if (chip->disabled || hda->init_failed) |
| 1168 | return 0; |
| 1169 | |
| 1170 | if (!power_save_controller || !azx_has_pm_runtime(chip) || |
| 1171 | azx_bus(chip)->codec_powered || !chip->running) |
| 1172 | return -EBUSY; |
| 1173 | |
| 1174 | /* ELD notification gets broken when HD-audio bus is off */ |
| 1175 | if (needs_eld_notify_link(chip)) |
| 1176 | return -EBUSY; |
| 1177 | |
| 1178 | return 0; |
| 1179 | } |
| 1180 | |
| 1181 | static const struct dev_pm_ops azx_pm = { |
| 1182 | SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) |
| 1183 | #ifdef CONFIG_PM_SLEEP |
| 1184 | .prepare = azx_prepare, |
| 1185 | .complete = azx_complete, |
| 1186 | .freeze_noirq = azx_freeze_noirq, |
| 1187 | .thaw_noirq = azx_thaw_noirq, |
| 1188 | #endif |
| 1189 | SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) |
| 1190 | }; |
| 1191 | |
| 1192 | #define AZX_PM_OPS &azx_pm |
| 1193 | #else |
| 1194 | #define azx_add_card_list(chip) /* NOP */ |
| 1195 | #define azx_del_card_list(chip) /* NOP */ |
| 1196 | #define AZX_PM_OPS NULL |
| 1197 | #endif /* CONFIG_PM */ |
| 1198 | |
| 1199 | |
| 1200 | static int azx_probe_continue(struct azx *chip); |
| 1201 | |
| 1202 | #ifdef SUPPORT_VGA_SWITCHEROO |
| 1203 | static struct pci_dev *get_bound_vga(struct pci_dev *pci); |
| 1204 | |
| 1205 | static void azx_vs_set_state(struct pci_dev *pci, |
| 1206 | enum vga_switcheroo_state state) |
| 1207 | { |
| 1208 | struct snd_card *card = pci_get_drvdata(pci); |
| 1209 | struct azx *chip = card->private_data; |
| 1210 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 1211 | struct hda_codec *codec; |
| 1212 | bool disabled; |
| 1213 | |
| 1214 | wait_for_completion(&hda->probe_wait); |
| 1215 | if (hda->init_failed) |
| 1216 | return; |
| 1217 | |
| 1218 | disabled = (state == VGA_SWITCHEROO_OFF); |
| 1219 | if (chip->disabled == disabled) |
| 1220 | return; |
| 1221 | |
| 1222 | if (!hda->probe_continued) { |
| 1223 | chip->disabled = disabled; |
| 1224 | if (!disabled) { |
| 1225 | dev_info(chip->card->dev, |
| 1226 | "Start delayed initialization\n"); |
| 1227 | if (azx_probe_continue(chip) < 0) |
| 1228 | dev_err(chip->card->dev, "initialization error\n"); |
| 1229 | } |
| 1230 | } else { |
| 1231 | dev_info(chip->card->dev, "%s via vga_switcheroo\n", |
| 1232 | disabled ? "Disabling" : "Enabling"); |
| 1233 | if (disabled) { |
| 1234 | list_for_each_codec(codec, &chip->bus) { |
| 1235 | pm_runtime_suspend(hda_codec_dev(codec)); |
| 1236 | pm_runtime_disable(hda_codec_dev(codec)); |
| 1237 | } |
| 1238 | pm_runtime_suspend(card->dev); |
| 1239 | pm_runtime_disable(card->dev); |
| 1240 | /* when we get suspended by vga_switcheroo we end up in D3cold, |
| 1241 | * however we have no ACPI handle, so pci/acpi can't put us there, |
| 1242 | * put ourselves there */ |
| 1243 | pci->current_state = PCI_D3cold; |
| 1244 | chip->disabled = true; |
| 1245 | if (snd_hda_lock_devices(&chip->bus)) |
| 1246 | dev_warn(chip->card->dev, |
| 1247 | "Cannot lock devices!\n"); |
| 1248 | } else { |
| 1249 | snd_hda_unlock_devices(&chip->bus); |
| 1250 | chip->disabled = false; |
| 1251 | pm_runtime_enable(card->dev); |
| 1252 | list_for_each_codec(codec, &chip->bus) { |
| 1253 | pm_runtime_enable(hda_codec_dev(codec)); |
| 1254 | pm_runtime_resume(hda_codec_dev(codec)); |
| 1255 | } |
| 1256 | } |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | static bool azx_vs_can_switch(struct pci_dev *pci) |
| 1261 | { |
| 1262 | struct snd_card *card = pci_get_drvdata(pci); |
| 1263 | struct azx *chip = card->private_data; |
| 1264 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 1265 | |
| 1266 | wait_for_completion(&hda->probe_wait); |
| 1267 | if (hda->init_failed) |
| 1268 | return false; |
| 1269 | if (chip->disabled || !hda->probe_continued) |
| 1270 | return true; |
| 1271 | if (snd_hda_lock_devices(&chip->bus)) |
| 1272 | return false; |
| 1273 | snd_hda_unlock_devices(&chip->bus); |
| 1274 | return true; |
| 1275 | } |
| 1276 | |
| 1277 | /* |
| 1278 | * The discrete GPU cannot power down unless the HDA controller runtime |
| 1279 | * suspends, so activate runtime PM on codecs even if power_save == 0. |
| 1280 | */ |
| 1281 | static void setup_vga_switcheroo_runtime_pm(struct azx *chip) |
| 1282 | { |
| 1283 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 1284 | struct hda_codec *codec; |
| 1285 | |
| 1286 | if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { |
| 1287 | list_for_each_codec(codec, &chip->bus) |
| 1288 | codec->auto_runtime_pm = 1; |
| 1289 | /* reset the power save setup */ |
| 1290 | if (chip->running) |
| 1291 | set_default_power_save(chip); |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | static void azx_vs_gpu_bound(struct pci_dev *pci, |
| 1296 | enum vga_switcheroo_client_id client_id) |
| 1297 | { |
| 1298 | struct snd_card *card = pci_get_drvdata(pci); |
| 1299 | struct azx *chip = card->private_data; |
| 1300 | |
| 1301 | if (client_id == VGA_SWITCHEROO_DIS) |
| 1302 | chip->bus.keep_power = 0; |
| 1303 | setup_vga_switcheroo_runtime_pm(chip); |
| 1304 | } |
| 1305 | |
| 1306 | static void init_vga_switcheroo(struct azx *chip) |
| 1307 | { |
| 1308 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 1309 | struct pci_dev *p = get_bound_vga(chip->pci); |
| 1310 | struct pci_dev *parent; |
| 1311 | if (p) { |
| 1312 | dev_info(chip->card->dev, |
| 1313 | "Handle vga_switcheroo audio client\n"); |
| 1314 | hda->use_vga_switcheroo = 1; |
| 1315 | |
| 1316 | /* cleared in either gpu_bound op or codec probe, or when its |
| 1317 | * upstream port has _PR3 (i.e. dGPU). |
| 1318 | */ |
| 1319 | parent = pci_upstream_bridge(p); |
| 1320 | chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; |
| 1321 | chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; |
| 1322 | pci_dev_put(p); |
| 1323 | } |
| 1324 | } |
| 1325 | |
| 1326 | static const struct vga_switcheroo_client_ops azx_vs_ops = { |
| 1327 | .set_gpu_state = azx_vs_set_state, |
| 1328 | .can_switch = azx_vs_can_switch, |
| 1329 | .gpu_bound = azx_vs_gpu_bound, |
| 1330 | }; |
| 1331 | |
| 1332 | static int register_vga_switcheroo(struct azx *chip) |
| 1333 | { |
| 1334 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 1335 | struct pci_dev *p; |
| 1336 | int err; |
| 1337 | |
| 1338 | if (!hda->use_vga_switcheroo) |
| 1339 | return 0; |
| 1340 | |
| 1341 | p = get_bound_vga(chip->pci); |
| 1342 | err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); |
| 1343 | pci_dev_put(p); |
| 1344 | |
| 1345 | if (err < 0) |
| 1346 | return err; |
| 1347 | hda->vga_switcheroo_registered = 1; |
| 1348 | |
| 1349 | return 0; |
| 1350 | } |
| 1351 | #else |
| 1352 | #define init_vga_switcheroo(chip) /* NOP */ |
| 1353 | #define register_vga_switcheroo(chip) 0 |
| 1354 | #define check_hdmi_disabled(pci) false |
| 1355 | #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ |
| 1356 | #endif /* SUPPORT_VGA_SWITCHER */ |
| 1357 | |
| 1358 | /* |
| 1359 | * destructor |
| 1360 | */ |
| 1361 | static void azx_free(struct azx *chip) |
| 1362 | { |
| 1363 | struct pci_dev *pci = chip->pci; |
| 1364 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 1365 | struct hdac_bus *bus = azx_bus(chip); |
| 1366 | |
| 1367 | if (hda->freed) |
| 1368 | return; |
| 1369 | |
| 1370 | if (azx_has_pm_runtime(chip) && chip->running) |
| 1371 | pm_runtime_get_noresume(&pci->dev); |
| 1372 | chip->running = 0; |
| 1373 | |
| 1374 | azx_del_card_list(chip); |
| 1375 | |
| 1376 | hda->init_failed = 1; /* to be sure */ |
| 1377 | complete_all(&hda->probe_wait); |
| 1378 | |
| 1379 | if (use_vga_switcheroo(hda)) { |
| 1380 | if (chip->disabled && hda->probe_continued) |
| 1381 | snd_hda_unlock_devices(&chip->bus); |
| 1382 | if (hda->vga_switcheroo_registered) |
| 1383 | vga_switcheroo_unregister_client(chip->pci); |
| 1384 | } |
| 1385 | |
| 1386 | if (bus->chip_init) { |
| 1387 | azx_clear_irq_pending(chip); |
| 1388 | azx_stop_all_streams(chip); |
| 1389 | azx_stop_chip(chip); |
| 1390 | } |
| 1391 | |
| 1392 | if (bus->irq >= 0) |
| 1393 | free_irq(bus->irq, (void*)chip); |
| 1394 | if (chip->msi) |
| 1395 | pci_disable_msi(chip->pci); |
| 1396 | iounmap(bus->remap_addr); |
| 1397 | |
| 1398 | azx_free_stream_pages(chip); |
| 1399 | azx_free_streams(chip); |
| 1400 | snd_hdac_bus_exit(bus); |
| 1401 | |
| 1402 | if (chip->region_requested) |
| 1403 | pci_release_regions(chip->pci); |
| 1404 | |
| 1405 | pci_disable_device(chip->pci); |
| 1406 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
| 1407 | release_firmware(chip->fw); |
| 1408 | #endif |
| 1409 | display_power(chip, false); |
| 1410 | |
| 1411 | if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) |
| 1412 | snd_hdac_i915_exit(bus); |
| 1413 | |
| 1414 | hda->freed = 1; |
| 1415 | } |
| 1416 | |
| 1417 | static int azx_dev_disconnect(struct snd_device *device) |
| 1418 | { |
| 1419 | struct azx *chip = device->device_data; |
| 1420 | struct hdac_bus *bus = azx_bus(chip); |
| 1421 | |
| 1422 | chip->bus.shutdown = 1; |
| 1423 | cancel_work_sync(&bus->unsol_work); |
| 1424 | |
| 1425 | return 0; |
| 1426 | } |
| 1427 | |
| 1428 | static int azx_dev_free(struct snd_device *device) |
| 1429 | { |
| 1430 | azx_free(device->device_data); |
| 1431 | return 0; |
| 1432 | } |
| 1433 | |
| 1434 | #ifdef SUPPORT_VGA_SWITCHEROO |
| 1435 | #ifdef CONFIG_ACPI |
| 1436 | /* ATPX is in the integrated GPU's namespace */ |
| 1437 | static bool atpx_present(void) |
| 1438 | { |
| 1439 | struct pci_dev *pdev = NULL; |
| 1440 | acpi_handle dhandle, atpx_handle; |
| 1441 | acpi_status status; |
| 1442 | |
| 1443 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { |
| 1444 | dhandle = ACPI_HANDLE(&pdev->dev); |
| 1445 | if (dhandle) { |
| 1446 | status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); |
| 1447 | if (!ACPI_FAILURE(status)) { |
| 1448 | pci_dev_put(pdev); |
| 1449 | return true; |
| 1450 | } |
| 1451 | } |
| 1452 | } |
| 1453 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { |
| 1454 | dhandle = ACPI_HANDLE(&pdev->dev); |
| 1455 | if (dhandle) { |
| 1456 | status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); |
| 1457 | if (!ACPI_FAILURE(status)) { |
| 1458 | pci_dev_put(pdev); |
| 1459 | return true; |
| 1460 | } |
| 1461 | } |
| 1462 | } |
| 1463 | return false; |
| 1464 | } |
| 1465 | #else |
| 1466 | static bool atpx_present(void) |
| 1467 | { |
| 1468 | return false; |
| 1469 | } |
| 1470 | #endif |
| 1471 | |
| 1472 | /* |
| 1473 | * Check of disabled HDMI controller by vga_switcheroo |
| 1474 | */ |
| 1475 | static struct pci_dev *get_bound_vga(struct pci_dev *pci) |
| 1476 | { |
| 1477 | struct pci_dev *p; |
| 1478 | |
| 1479 | /* check only discrete GPU */ |
| 1480 | switch (pci->vendor) { |
| 1481 | case PCI_VENDOR_ID_ATI: |
| 1482 | case PCI_VENDOR_ID_AMD: |
| 1483 | if (pci->devfn == 1) { |
| 1484 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), |
| 1485 | pci->bus->number, 0); |
| 1486 | if (p) { |
| 1487 | /* ATPX is in the integrated GPU's ACPI namespace |
| 1488 | * rather than the dGPU's namespace. However, |
| 1489 | * the dGPU is the one who is involved in |
| 1490 | * vgaswitcheroo. |
| 1491 | */ |
| 1492 | if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && |
| 1493 | atpx_present()) |
| 1494 | return p; |
| 1495 | pci_dev_put(p); |
| 1496 | } |
| 1497 | } |
| 1498 | break; |
| 1499 | case PCI_VENDOR_ID_NVIDIA: |
| 1500 | if (pci->devfn == 1) { |
| 1501 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), |
| 1502 | pci->bus->number, 0); |
| 1503 | if (p) { |
| 1504 | if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
| 1505 | return p; |
| 1506 | pci_dev_put(p); |
| 1507 | } |
| 1508 | } |
| 1509 | break; |
| 1510 | } |
| 1511 | return NULL; |
| 1512 | } |
| 1513 | |
| 1514 | static bool check_hdmi_disabled(struct pci_dev *pci) |
| 1515 | { |
| 1516 | bool vga_inactive = false; |
| 1517 | struct pci_dev *p = get_bound_vga(pci); |
| 1518 | |
| 1519 | if (p) { |
| 1520 | if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) |
| 1521 | vga_inactive = true; |
| 1522 | pci_dev_put(p); |
| 1523 | } |
| 1524 | return vga_inactive; |
| 1525 | } |
| 1526 | #endif /* SUPPORT_VGA_SWITCHEROO */ |
| 1527 | |
| 1528 | /* |
| 1529 | * allow/deny-listing for position_fix |
| 1530 | */ |
| 1531 | static const struct snd_pci_quirk position_fix_list[] = { |
| 1532 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), |
| 1533 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), |
| 1534 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), |
| 1535 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), |
| 1536 | SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), |
| 1537 | SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), |
| 1538 | SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), |
| 1539 | SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), |
| 1540 | SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), |
| 1541 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), |
| 1542 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), |
| 1543 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), |
| 1544 | SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), |
| 1545 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), |
| 1546 | {} |
| 1547 | }; |
| 1548 | |
| 1549 | static int check_position_fix(struct azx *chip, int fix) |
| 1550 | { |
| 1551 | const struct snd_pci_quirk *q; |
| 1552 | |
| 1553 | switch (fix) { |
| 1554 | case POS_FIX_AUTO: |
| 1555 | case POS_FIX_LPIB: |
| 1556 | case POS_FIX_POSBUF: |
| 1557 | case POS_FIX_VIACOMBO: |
| 1558 | case POS_FIX_COMBO: |
| 1559 | case POS_FIX_SKL: |
| 1560 | case POS_FIX_FIFO: |
| 1561 | return fix; |
| 1562 | } |
| 1563 | |
| 1564 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
| 1565 | if (q) { |
| 1566 | dev_info(chip->card->dev, |
| 1567 | "position_fix set to %d for device %04x:%04x\n", |
| 1568 | q->value, q->subvendor, q->subdevice); |
| 1569 | return q->value; |
| 1570 | } |
| 1571 | |
| 1572 | /* Check VIA/ATI HD Audio Controller exist */ |
| 1573 | if (chip->driver_type == AZX_DRIVER_VIA) { |
| 1574 | dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); |
| 1575 | return POS_FIX_VIACOMBO; |
| 1576 | } |
| 1577 | if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { |
| 1578 | dev_dbg(chip->card->dev, "Using FIFO position fix\n"); |
| 1579 | return POS_FIX_FIFO; |
| 1580 | } |
| 1581 | if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { |
| 1582 | dev_dbg(chip->card->dev, "Using LPIB position fix\n"); |
| 1583 | return POS_FIX_LPIB; |
| 1584 | } |
| 1585 | if (chip->driver_type == AZX_DRIVER_SKL) { |
| 1586 | dev_dbg(chip->card->dev, "Using SKL position fix\n"); |
| 1587 | return POS_FIX_SKL; |
| 1588 | } |
| 1589 | return POS_FIX_AUTO; |
| 1590 | } |
| 1591 | |
| 1592 | static void assign_position_fix(struct azx *chip, int fix) |
| 1593 | { |
| 1594 | static const azx_get_pos_callback_t callbacks[] = { |
| 1595 | [POS_FIX_AUTO] = NULL, |
| 1596 | [POS_FIX_LPIB] = azx_get_pos_lpib, |
| 1597 | [POS_FIX_POSBUF] = azx_get_pos_posbuf, |
| 1598 | [POS_FIX_VIACOMBO] = azx_via_get_position, |
| 1599 | [POS_FIX_COMBO] = azx_get_pos_lpib, |
| 1600 | [POS_FIX_SKL] = azx_get_pos_skl, |
| 1601 | [POS_FIX_FIFO] = azx_get_pos_fifo, |
| 1602 | }; |
| 1603 | |
| 1604 | chip->get_position[0] = chip->get_position[1] = callbacks[fix]; |
| 1605 | |
| 1606 | /* combo mode uses LPIB only for playback */ |
| 1607 | if (fix == POS_FIX_COMBO) |
| 1608 | chip->get_position[1] = NULL; |
| 1609 | |
| 1610 | if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && |
| 1611 | (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { |
| 1612 | chip->get_delay[0] = chip->get_delay[1] = |
| 1613 | azx_get_delay_from_lpib; |
| 1614 | } |
| 1615 | |
| 1616 | if (fix == POS_FIX_FIFO) |
| 1617 | chip->get_delay[0] = chip->get_delay[1] = |
| 1618 | azx_get_delay_from_fifo; |
| 1619 | } |
| 1620 | |
| 1621 | /* |
| 1622 | * deny-lists for probe_mask |
| 1623 | */ |
| 1624 | static const struct snd_pci_quirk probe_mask_list[] = { |
| 1625 | /* Thinkpad often breaks the controller communication when accessing |
| 1626 | * to the non-working (or non-existing) modem codec slot. |
| 1627 | */ |
| 1628 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), |
| 1629 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), |
| 1630 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), |
| 1631 | /* broken BIOS */ |
| 1632 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), |
| 1633 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ |
| 1634 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), |
| 1635 | /* forced codec slots */ |
| 1636 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), |
| 1637 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), |
| 1638 | /* WinFast VP200 H (Teradici) user reported broken communication */ |
| 1639 | SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), |
| 1640 | {} |
| 1641 | }; |
| 1642 | |
| 1643 | #define AZX_FORCE_CODEC_MASK 0x100 |
| 1644 | |
| 1645 | static void check_probe_mask(struct azx *chip, int dev) |
| 1646 | { |
| 1647 | const struct snd_pci_quirk *q; |
| 1648 | |
| 1649 | chip->codec_probe_mask = probe_mask[dev]; |
| 1650 | if (chip->codec_probe_mask == -1) { |
| 1651 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); |
| 1652 | if (q) { |
| 1653 | dev_info(chip->card->dev, |
| 1654 | "probe_mask set to 0x%x for device %04x:%04x\n", |
| 1655 | q->value, q->subvendor, q->subdevice); |
| 1656 | chip->codec_probe_mask = q->value; |
| 1657 | } |
| 1658 | } |
| 1659 | |
| 1660 | /* check forced option */ |
| 1661 | if (chip->codec_probe_mask != -1 && |
| 1662 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { |
| 1663 | azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; |
| 1664 | dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", |
| 1665 | (int)azx_bus(chip)->codec_mask); |
| 1666 | } |
| 1667 | } |
| 1668 | |
| 1669 | /* |
| 1670 | * allow/deny-list for enable_msi |
| 1671 | */ |
| 1672 | static const struct snd_pci_quirk msi_deny_list[] = { |
| 1673 | SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ |
| 1674 | SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ |
| 1675 | SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ |
| 1676 | SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ |
| 1677 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ |
| 1678 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ |
| 1679 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ |
| 1680 | SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ |
| 1681 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ |
| 1682 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ |
| 1683 | {} |
| 1684 | }; |
| 1685 | |
| 1686 | static void check_msi(struct azx *chip) |
| 1687 | { |
| 1688 | const struct snd_pci_quirk *q; |
| 1689 | |
| 1690 | if (enable_msi >= 0) { |
| 1691 | chip->msi = !!enable_msi; |
| 1692 | return; |
| 1693 | } |
| 1694 | chip->msi = 1; /* enable MSI as default */ |
| 1695 | q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); |
| 1696 | if (q) { |
| 1697 | dev_info(chip->card->dev, |
| 1698 | "msi for device %04x:%04x set to %d\n", |
| 1699 | q->subvendor, q->subdevice, q->value); |
| 1700 | chip->msi = q->value; |
| 1701 | return; |
| 1702 | } |
| 1703 | |
| 1704 | /* NVidia chipsets seem to cause troubles with MSI */ |
| 1705 | if (chip->driver_caps & AZX_DCAPS_NO_MSI) { |
| 1706 | dev_info(chip->card->dev, "Disabling MSI\n"); |
| 1707 | chip->msi = 0; |
| 1708 | } |
| 1709 | } |
| 1710 | |
| 1711 | /* check the snoop mode availability */ |
| 1712 | static void azx_check_snoop_available(struct azx *chip) |
| 1713 | { |
| 1714 | int snoop = hda_snoop; |
| 1715 | |
| 1716 | if (snoop >= 0) { |
| 1717 | dev_info(chip->card->dev, "Force to %s mode by module option\n", |
| 1718 | snoop ? "snoop" : "non-snoop"); |
| 1719 | chip->snoop = snoop; |
| 1720 | chip->uc_buffer = !snoop; |
| 1721 | return; |
| 1722 | } |
| 1723 | |
| 1724 | snoop = true; |
| 1725 | if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && |
| 1726 | chip->driver_type == AZX_DRIVER_VIA) { |
| 1727 | /* force to non-snoop mode for a new VIA controller |
| 1728 | * when BIOS is set |
| 1729 | */ |
| 1730 | u8 val; |
| 1731 | pci_read_config_byte(chip->pci, 0x42, &val); |
| 1732 | if (!(val & 0x80) && (chip->pci->revision == 0x30 || |
| 1733 | chip->pci->revision == 0x20)) |
| 1734 | snoop = false; |
| 1735 | } |
| 1736 | |
| 1737 | if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) |
| 1738 | snoop = false; |
| 1739 | |
| 1740 | chip->snoop = snoop; |
| 1741 | if (!snoop) { |
| 1742 | dev_info(chip->card->dev, "Force to non-snoop mode\n"); |
| 1743 | /* C-Media requires non-cached pages only for CORB/RIRB */ |
| 1744 | if (chip->driver_type != AZX_DRIVER_CMEDIA) |
| 1745 | chip->uc_buffer = true; |
| 1746 | } |
| 1747 | } |
| 1748 | |
| 1749 | static void azx_probe_work(struct work_struct *work) |
| 1750 | { |
| 1751 | struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); |
| 1752 | azx_probe_continue(&hda->chip); |
| 1753 | } |
| 1754 | |
| 1755 | static int default_bdl_pos_adj(struct azx *chip) |
| 1756 | { |
| 1757 | /* some exceptions: Atoms seem problematic with value 1 */ |
| 1758 | if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { |
| 1759 | switch (chip->pci->device) { |
| 1760 | case 0x0f04: /* Baytrail */ |
| 1761 | case 0x2284: /* Braswell */ |
| 1762 | return 32; |
| 1763 | } |
| 1764 | } |
| 1765 | |
| 1766 | switch (chip->driver_type) { |
| 1767 | case AZX_DRIVER_ICH: |
| 1768 | case AZX_DRIVER_PCH: |
| 1769 | return 1; |
| 1770 | default: |
| 1771 | return 32; |
| 1772 | } |
| 1773 | } |
| 1774 | |
| 1775 | /* |
| 1776 | * constructor |
| 1777 | */ |
| 1778 | static const struct hda_controller_ops pci_hda_ops; |
| 1779 | |
| 1780 | static int azx_create(struct snd_card *card, struct pci_dev *pci, |
| 1781 | int dev, unsigned int driver_caps, |
| 1782 | struct azx **rchip) |
| 1783 | { |
| 1784 | static const struct snd_device_ops ops = { |
| 1785 | .dev_disconnect = azx_dev_disconnect, |
| 1786 | .dev_free = azx_dev_free, |
| 1787 | }; |
| 1788 | struct hda_intel *hda; |
| 1789 | struct azx *chip; |
| 1790 | int err; |
| 1791 | |
| 1792 | *rchip = NULL; |
| 1793 | |
| 1794 | err = pci_enable_device(pci); |
| 1795 | if (err < 0) |
| 1796 | return err; |
| 1797 | |
| 1798 | hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); |
| 1799 | if (!hda) { |
| 1800 | pci_disable_device(pci); |
| 1801 | return -ENOMEM; |
| 1802 | } |
| 1803 | |
| 1804 | chip = &hda->chip; |
| 1805 | mutex_init(&chip->open_mutex); |
| 1806 | chip->card = card; |
| 1807 | chip->pci = pci; |
| 1808 | chip->ops = &pci_hda_ops; |
| 1809 | chip->driver_caps = driver_caps; |
| 1810 | chip->driver_type = driver_caps & 0xff; |
| 1811 | check_msi(chip); |
| 1812 | chip->dev_index = dev; |
| 1813 | if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) |
| 1814 | chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); |
| 1815 | INIT_LIST_HEAD(&chip->pcm_list); |
| 1816 | INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); |
| 1817 | INIT_LIST_HEAD(&hda->list); |
| 1818 | init_vga_switcheroo(chip); |
| 1819 | init_completion(&hda->probe_wait); |
| 1820 | |
| 1821 | assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); |
| 1822 | |
| 1823 | check_probe_mask(chip, dev); |
| 1824 | |
| 1825 | if (single_cmd < 0) /* allow fallback to single_cmd at errors */ |
| 1826 | chip->fallback_to_single_cmd = 1; |
| 1827 | else /* explicitly set to single_cmd or not */ |
| 1828 | chip->single_cmd = single_cmd; |
| 1829 | |
| 1830 | azx_check_snoop_available(chip); |
| 1831 | |
| 1832 | if (bdl_pos_adj[dev] < 0) |
| 1833 | chip->bdl_pos_adj = default_bdl_pos_adj(chip); |
| 1834 | else |
| 1835 | chip->bdl_pos_adj = bdl_pos_adj[dev]; |
| 1836 | |
| 1837 | err = azx_bus_init(chip, model[dev]); |
| 1838 | if (err < 0) { |
| 1839 | pci_disable_device(pci); |
| 1840 | return err; |
| 1841 | } |
| 1842 | |
| 1843 | /* use the non-cached pages in non-snoop mode */ |
| 1844 | if (!azx_snoop(chip)) |
| 1845 | azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; |
| 1846 | |
| 1847 | if (chip->driver_type == AZX_DRIVER_NVIDIA) { |
| 1848 | dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); |
| 1849 | chip->bus.core.needs_damn_long_delay = 1; |
| 1850 | } |
| 1851 | |
| 1852 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
| 1853 | if (err < 0) { |
| 1854 | dev_err(card->dev, "Error creating device [card]!\n"); |
| 1855 | azx_free(chip); |
| 1856 | return err; |
| 1857 | } |
| 1858 | |
| 1859 | /* continue probing in work context as may trigger request module */ |
| 1860 | INIT_WORK(&hda->probe_work, azx_probe_work); |
| 1861 | |
| 1862 | *rchip = chip; |
| 1863 | |
| 1864 | return 0; |
| 1865 | } |
| 1866 | |
| 1867 | static int azx_first_init(struct azx *chip) |
| 1868 | { |
| 1869 | int dev = chip->dev_index; |
| 1870 | struct pci_dev *pci = chip->pci; |
| 1871 | struct snd_card *card = chip->card; |
| 1872 | struct hdac_bus *bus = azx_bus(chip); |
| 1873 | int err; |
| 1874 | unsigned short gcap; |
| 1875 | unsigned int dma_bits = 64; |
| 1876 | |
| 1877 | #if BITS_PER_LONG != 64 |
| 1878 | /* Fix up base address on ULI M5461 */ |
| 1879 | if (chip->driver_type == AZX_DRIVER_ULI) { |
| 1880 | u16 tmp3; |
| 1881 | pci_read_config_word(pci, 0x40, &tmp3); |
| 1882 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); |
| 1883 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); |
| 1884 | } |
| 1885 | #endif |
| 1886 | |
| 1887 | err = pci_request_regions(pci, "ICH HD audio"); |
| 1888 | if (err < 0) |
| 1889 | return err; |
| 1890 | chip->region_requested = 1; |
| 1891 | |
| 1892 | bus->addr = pci_resource_start(pci, 0); |
| 1893 | bus->remap_addr = pci_ioremap_bar(pci, 0); |
| 1894 | if (bus->remap_addr == NULL) { |
| 1895 | dev_err(card->dev, "ioremap error\n"); |
| 1896 | return -ENXIO; |
| 1897 | } |
| 1898 | |
| 1899 | if (chip->driver_type == AZX_DRIVER_SKL) |
| 1900 | snd_hdac_bus_parse_capabilities(bus); |
| 1901 | |
| 1902 | /* |
| 1903 | * Some Intel CPUs has always running timer (ART) feature and |
| 1904 | * controller may have Global time sync reporting capability, so |
| 1905 | * check both of these before declaring synchronized time reporting |
| 1906 | * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME |
| 1907 | */ |
| 1908 | chip->gts_present = false; |
| 1909 | |
| 1910 | #ifdef CONFIG_X86 |
| 1911 | if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) |
| 1912 | chip->gts_present = true; |
| 1913 | #endif |
| 1914 | |
| 1915 | if (chip->msi) { |
| 1916 | if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { |
| 1917 | dev_dbg(card->dev, "Disabling 64bit MSI\n"); |
| 1918 | pci->no_64bit_msi = true; |
| 1919 | } |
| 1920 | if (pci_enable_msi(pci) < 0) |
| 1921 | chip->msi = 0; |
| 1922 | } |
| 1923 | |
| 1924 | pci_set_master(pci); |
| 1925 | |
| 1926 | gcap = azx_readw(chip, GCAP); |
| 1927 | dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); |
| 1928 | |
| 1929 | /* AMD devices support 40 or 48bit DMA, take the safe one */ |
| 1930 | if (chip->pci->vendor == PCI_VENDOR_ID_AMD) |
| 1931 | dma_bits = 40; |
| 1932 | |
| 1933 | /* disable SB600 64bit support for safety */ |
| 1934 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { |
| 1935 | struct pci_dev *p_smbus; |
| 1936 | dma_bits = 40; |
| 1937 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
| 1938 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
| 1939 | NULL); |
| 1940 | if (p_smbus) { |
| 1941 | if (p_smbus->revision < 0x30) |
| 1942 | gcap &= ~AZX_GCAP_64OK; |
| 1943 | pci_dev_put(p_smbus); |
| 1944 | } |
| 1945 | } |
| 1946 | |
| 1947 | /* NVidia hardware normally only supports up to 40 bits of DMA */ |
| 1948 | if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) |
| 1949 | dma_bits = 40; |
| 1950 | |
| 1951 | /* disable 64bit DMA address on some devices */ |
| 1952 | if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { |
| 1953 | dev_dbg(card->dev, "Disabling 64bit DMA\n"); |
| 1954 | gcap &= ~AZX_GCAP_64OK; |
| 1955 | } |
| 1956 | |
| 1957 | /* disable buffer size rounding to 128-byte multiples if supported */ |
| 1958 | if (align_buffer_size >= 0) |
| 1959 | chip->align_buffer_size = !!align_buffer_size; |
| 1960 | else { |
| 1961 | if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) |
| 1962 | chip->align_buffer_size = 0; |
| 1963 | else |
| 1964 | chip->align_buffer_size = 1; |
| 1965 | } |
| 1966 | |
| 1967 | /* allow 64bit DMA address if supported by H/W */ |
| 1968 | if (!(gcap & AZX_GCAP_64OK)) |
| 1969 | dma_bits = 32; |
| 1970 | if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { |
| 1971 | dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); |
| 1972 | } else { |
| 1973 | dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); |
| 1974 | dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); |
| 1975 | } |
| 1976 | |
| 1977 | /* read number of streams from GCAP register instead of using |
| 1978 | * hardcoded value |
| 1979 | */ |
| 1980 | chip->capture_streams = (gcap >> 8) & 0x0f; |
| 1981 | chip->playback_streams = (gcap >> 12) & 0x0f; |
| 1982 | if (!chip->playback_streams && !chip->capture_streams) { |
| 1983 | /* gcap didn't give any info, switching to old method */ |
| 1984 | |
| 1985 | switch (chip->driver_type) { |
| 1986 | case AZX_DRIVER_ULI: |
| 1987 | chip->playback_streams = ULI_NUM_PLAYBACK; |
| 1988 | chip->capture_streams = ULI_NUM_CAPTURE; |
| 1989 | break; |
| 1990 | case AZX_DRIVER_ATIHDMI: |
| 1991 | case AZX_DRIVER_ATIHDMI_NS: |
| 1992 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; |
| 1993 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; |
| 1994 | break; |
| 1995 | case AZX_DRIVER_GENERIC: |
| 1996 | default: |
| 1997 | chip->playback_streams = ICH6_NUM_PLAYBACK; |
| 1998 | chip->capture_streams = ICH6_NUM_CAPTURE; |
| 1999 | break; |
| 2000 | } |
| 2001 | } |
| 2002 | chip->capture_index_offset = 0; |
| 2003 | chip->playback_index_offset = chip->capture_streams; |
| 2004 | chip->num_streams = chip->playback_streams + chip->capture_streams; |
| 2005 | |
| 2006 | /* sanity check for the SDxCTL.STRM field overflow */ |
| 2007 | if (chip->num_streams > 15 && |
| 2008 | (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { |
| 2009 | dev_warn(chip->card->dev, "number of I/O streams is %d, " |
| 2010 | "forcing separate stream tags", chip->num_streams); |
| 2011 | chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; |
| 2012 | } |
| 2013 | |
| 2014 | /* initialize streams */ |
| 2015 | err = azx_init_streams(chip); |
| 2016 | if (err < 0) |
| 2017 | return err; |
| 2018 | |
| 2019 | err = azx_alloc_stream_pages(chip); |
| 2020 | if (err < 0) |
| 2021 | return err; |
| 2022 | |
| 2023 | /* initialize chip */ |
| 2024 | azx_init_pci(chip); |
| 2025 | |
| 2026 | snd_hdac_i915_set_bclk(bus); |
| 2027 | |
| 2028 | hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); |
| 2029 | |
| 2030 | /* codec detection */ |
| 2031 | if (!azx_bus(chip)->codec_mask) { |
| 2032 | dev_err(card->dev, "no codecs found!\n"); |
| 2033 | /* keep running the rest for the runtime PM */ |
| 2034 | } |
| 2035 | |
| 2036 | if (azx_acquire_irq(chip, 0) < 0) |
| 2037 | return -EBUSY; |
| 2038 | |
| 2039 | strcpy(card->driver, "HDA-Intel"); |
| 2040 | strlcpy(card->shortname, driver_short_names[chip->driver_type], |
| 2041 | sizeof(card->shortname)); |
| 2042 | snprintf(card->longname, sizeof(card->longname), |
| 2043 | "%s at 0x%lx irq %i", |
| 2044 | card->shortname, bus->addr, bus->irq); |
| 2045 | |
| 2046 | return 0; |
| 2047 | } |
| 2048 | |
| 2049 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
| 2050 | /* callback from request_firmware_nowait() */ |
| 2051 | static void azx_firmware_cb(const struct firmware *fw, void *context) |
| 2052 | { |
| 2053 | struct snd_card *card = context; |
| 2054 | struct azx *chip = card->private_data; |
| 2055 | |
| 2056 | if (fw) |
| 2057 | chip->fw = fw; |
| 2058 | else |
| 2059 | dev_err(card->dev, "Cannot load firmware, continue without patching\n"); |
| 2060 | if (!chip->disabled) { |
| 2061 | /* continue probing */ |
| 2062 | azx_probe_continue(chip); |
| 2063 | } |
| 2064 | } |
| 2065 | #endif |
| 2066 | |
| 2067 | static int disable_msi_reset_irq(struct azx *chip) |
| 2068 | { |
| 2069 | struct hdac_bus *bus = azx_bus(chip); |
| 2070 | int err; |
| 2071 | |
| 2072 | free_irq(bus->irq, chip); |
| 2073 | bus->irq = -1; |
| 2074 | chip->card->sync_irq = -1; |
| 2075 | pci_disable_msi(chip->pci); |
| 2076 | chip->msi = 0; |
| 2077 | err = azx_acquire_irq(chip, 1); |
| 2078 | if (err < 0) |
| 2079 | return err; |
| 2080 | |
| 2081 | return 0; |
| 2082 | } |
| 2083 | |
| 2084 | static void pcm_mmap_prepare(struct snd_pcm_substream *substream, |
| 2085 | struct vm_area_struct *area) |
| 2086 | { |
| 2087 | #ifdef CONFIG_X86 |
| 2088 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 2089 | struct azx *chip = apcm->chip; |
| 2090 | if (chip->uc_buffer) |
| 2091 | area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); |
| 2092 | #endif |
| 2093 | } |
| 2094 | |
| 2095 | /* Denylist for skipping the whole probe: |
| 2096 | * some HD-audio PCI entries are exposed without any codecs, and such devices |
| 2097 | * should be ignored from the beginning. |
| 2098 | */ |
| 2099 | static const struct pci_device_id driver_denylist[] = { |
| 2100 | { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ |
| 2101 | { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ |
| 2102 | { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ |
| 2103 | {} |
| 2104 | }; |
| 2105 | |
| 2106 | static const struct hda_controller_ops pci_hda_ops = { |
| 2107 | .disable_msi_reset_irq = disable_msi_reset_irq, |
| 2108 | .pcm_mmap_prepare = pcm_mmap_prepare, |
| 2109 | .position_check = azx_position_check, |
| 2110 | }; |
| 2111 | |
| 2112 | static int azx_probe(struct pci_dev *pci, |
| 2113 | const struct pci_device_id *pci_id) |
| 2114 | { |
| 2115 | static int dev; |
| 2116 | struct snd_card *card; |
| 2117 | struct hda_intel *hda; |
| 2118 | struct azx *chip; |
| 2119 | bool schedule_probe; |
| 2120 | int err; |
| 2121 | |
| 2122 | if (pci_match_id(driver_denylist, pci)) { |
| 2123 | dev_info(&pci->dev, "Skipping the device on the denylist\n"); |
| 2124 | return -ENODEV; |
| 2125 | } |
| 2126 | |
| 2127 | if (dev >= SNDRV_CARDS) |
| 2128 | return -ENODEV; |
| 2129 | if (!enable[dev]) { |
| 2130 | dev++; |
| 2131 | return -ENOENT; |
| 2132 | } |
| 2133 | |
| 2134 | /* |
| 2135 | * stop probe if another Intel's DSP driver should be activated |
| 2136 | */ |
| 2137 | if (dmic_detect) { |
| 2138 | err = snd_intel_dsp_driver_probe(pci); |
| 2139 | if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { |
| 2140 | dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); |
| 2141 | return -ENODEV; |
| 2142 | } |
| 2143 | } else { |
| 2144 | dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); |
| 2145 | } |
| 2146 | |
| 2147 | err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
| 2148 | 0, &card); |
| 2149 | if (err < 0) { |
| 2150 | dev_err(&pci->dev, "Error creating card!\n"); |
| 2151 | return err; |
| 2152 | } |
| 2153 | |
| 2154 | err = azx_create(card, pci, dev, pci_id->driver_data, &chip); |
| 2155 | if (err < 0) |
| 2156 | goto out_free; |
| 2157 | card->private_data = chip; |
| 2158 | hda = container_of(chip, struct hda_intel, chip); |
| 2159 | |
| 2160 | pci_set_drvdata(pci, card); |
| 2161 | |
| 2162 | err = register_vga_switcheroo(chip); |
| 2163 | if (err < 0) { |
| 2164 | dev_err(card->dev, "Error registering vga_switcheroo client\n"); |
| 2165 | goto out_free; |
| 2166 | } |
| 2167 | |
| 2168 | if (check_hdmi_disabled(pci)) { |
| 2169 | dev_info(card->dev, "VGA controller is disabled\n"); |
| 2170 | dev_info(card->dev, "Delaying initialization\n"); |
| 2171 | chip->disabled = true; |
| 2172 | } |
| 2173 | |
| 2174 | schedule_probe = !chip->disabled; |
| 2175 | |
| 2176 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
| 2177 | if (patch[dev] && *patch[dev]) { |
| 2178 | dev_info(card->dev, "Applying patch firmware '%s'\n", |
| 2179 | patch[dev]); |
| 2180 | err = request_firmware_nowait(THIS_MODULE, true, patch[dev], |
| 2181 | &pci->dev, GFP_KERNEL, card, |
| 2182 | azx_firmware_cb); |
| 2183 | if (err < 0) |
| 2184 | goto out_free; |
| 2185 | schedule_probe = false; /* continued in azx_firmware_cb() */ |
| 2186 | } |
| 2187 | #endif /* CONFIG_SND_HDA_PATCH_LOADER */ |
| 2188 | |
| 2189 | #ifndef CONFIG_SND_HDA_I915 |
| 2190 | if (CONTROLLER_IN_GPU(pci)) |
| 2191 | dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); |
| 2192 | #endif |
| 2193 | |
| 2194 | if (schedule_probe) |
| 2195 | schedule_work(&hda->probe_work); |
| 2196 | |
| 2197 | dev++; |
| 2198 | if (chip->disabled) |
| 2199 | complete_all(&hda->probe_wait); |
| 2200 | return 0; |
| 2201 | |
| 2202 | out_free: |
| 2203 | snd_card_free(card); |
| 2204 | return err; |
| 2205 | } |
| 2206 | |
| 2207 | #ifdef CONFIG_PM |
| 2208 | /* On some boards setting power_save to a non 0 value leads to clicking / |
| 2209 | * popping sounds when ever we enter/leave powersaving mode. Ideally we would |
| 2210 | * figure out how to avoid these sounds, but that is not always feasible. |
| 2211 | * So we keep a list of devices where we disable powersaving as its known |
| 2212 | * to causes problems on these devices. |
| 2213 | */ |
| 2214 | static const struct snd_pci_quirk power_save_denylist[] = { |
| 2215 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2216 | SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), |
| 2217 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2218 | SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), |
| 2219 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2220 | SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), |
| 2221 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2222 | SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), |
| 2223 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2224 | SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), |
| 2225 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2226 | SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), |
| 2227 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2228 | /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ |
| 2229 | SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), |
| 2230 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
| 2231 | SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), |
| 2232 | /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ |
| 2233 | SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), |
| 2234 | /* https://bugs.launchpad.net/bugs/1821663 */ |
| 2235 | SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), |
| 2236 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ |
| 2237 | SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), |
| 2238 | /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ |
| 2239 | SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), |
| 2240 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ |
| 2241 | SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), |
| 2242 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ |
| 2243 | SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), |
| 2244 | /* https://bugs.launchpad.net/bugs/1821663 */ |
| 2245 | SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), |
| 2246 | {} |
| 2247 | }; |
| 2248 | #endif /* CONFIG_PM */ |
| 2249 | |
| 2250 | static void set_default_power_save(struct azx *chip) |
| 2251 | { |
| 2252 | int val = power_save; |
| 2253 | |
| 2254 | #ifdef CONFIG_PM |
| 2255 | if (pm_blacklist) { |
| 2256 | const struct snd_pci_quirk *q; |
| 2257 | |
| 2258 | q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); |
| 2259 | if (q && val) { |
| 2260 | dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", |
| 2261 | q->subvendor, q->subdevice); |
| 2262 | val = 0; |
| 2263 | } |
| 2264 | } |
| 2265 | #endif /* CONFIG_PM */ |
| 2266 | snd_hda_set_power_save(&chip->bus, val * 1000); |
| 2267 | } |
| 2268 | |
| 2269 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ |
| 2270 | static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { |
| 2271 | [AZX_DRIVER_NVIDIA] = 8, |
| 2272 | [AZX_DRIVER_TERA] = 1, |
| 2273 | }; |
| 2274 | |
| 2275 | static int azx_probe_continue(struct azx *chip) |
| 2276 | { |
| 2277 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
| 2278 | struct hdac_bus *bus = azx_bus(chip); |
| 2279 | struct pci_dev *pci = chip->pci; |
| 2280 | int dev = chip->dev_index; |
| 2281 | int err; |
| 2282 | |
| 2283 | to_hda_bus(bus)->bus_probing = 1; |
| 2284 | hda->probe_continued = 1; |
| 2285 | |
| 2286 | /* bind with i915 if needed */ |
| 2287 | if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { |
| 2288 | err = snd_hdac_i915_init(bus); |
| 2289 | if (err < 0) { |
| 2290 | /* if the controller is bound only with HDMI/DP |
| 2291 | * (for HSW and BDW), we need to abort the probe; |
| 2292 | * for other chips, still continue probing as other |
| 2293 | * codecs can be on the same link. |
| 2294 | */ |
| 2295 | if (CONTROLLER_IN_GPU(pci)) { |
| 2296 | dev_err(chip->card->dev, |
| 2297 | "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); |
| 2298 | goto out_free; |
| 2299 | } else { |
| 2300 | /* don't bother any longer */ |
| 2301 | chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; |
| 2302 | } |
| 2303 | } |
| 2304 | |
| 2305 | /* HSW/BDW controllers need this power */ |
| 2306 | if (CONTROLLER_IN_GPU(pci)) |
| 2307 | hda->need_i915_power = 1; |
| 2308 | } |
| 2309 | |
| 2310 | /* Request display power well for the HDA controller or codec. For |
| 2311 | * Haswell/Broadwell, both the display HDA controller and codec need |
| 2312 | * this power. For other platforms, like Baytrail/Braswell, only the |
| 2313 | * display codec needs the power and it can be released after probe. |
| 2314 | */ |
| 2315 | display_power(chip, true); |
| 2316 | |
| 2317 | err = azx_first_init(chip); |
| 2318 | if (err < 0) |
| 2319 | goto out_free; |
| 2320 | |
| 2321 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
| 2322 | chip->beep_mode = beep_mode[dev]; |
| 2323 | #endif |
| 2324 | |
| 2325 | /* create codec instances */ |
| 2326 | if (bus->codec_mask) { |
| 2327 | err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); |
| 2328 | if (err < 0) |
| 2329 | goto out_free; |
| 2330 | } |
| 2331 | |
| 2332 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
| 2333 | if (chip->fw) { |
| 2334 | err = snd_hda_load_patch(&chip->bus, chip->fw->size, |
| 2335 | chip->fw->data); |
| 2336 | if (err < 0) |
| 2337 | goto out_free; |
| 2338 | #ifndef CONFIG_PM |
| 2339 | release_firmware(chip->fw); /* no longer needed */ |
| 2340 | chip->fw = NULL; |
| 2341 | #endif |
| 2342 | } |
| 2343 | #endif |
| 2344 | if (bus->codec_mask && !(probe_only[dev] & 1)) { |
| 2345 | err = azx_codec_configure(chip); |
| 2346 | if (err < 0) |
| 2347 | goto out_free; |
| 2348 | } |
| 2349 | |
| 2350 | err = snd_card_register(chip->card); |
| 2351 | if (err < 0) |
| 2352 | goto out_free; |
| 2353 | |
| 2354 | setup_vga_switcheroo_runtime_pm(chip); |
| 2355 | |
| 2356 | chip->running = 1; |
| 2357 | azx_add_card_list(chip); |
| 2358 | |
| 2359 | set_default_power_save(chip); |
| 2360 | |
| 2361 | if (azx_has_pm_runtime(chip)) { |
| 2362 | pm_runtime_use_autosuspend(&pci->dev); |
| 2363 | pm_runtime_allow(&pci->dev); |
| 2364 | pm_runtime_put_autosuspend(&pci->dev); |
| 2365 | } |
| 2366 | |
| 2367 | out_free: |
| 2368 | if (err < 0) { |
| 2369 | azx_free(chip); |
| 2370 | return err; |
| 2371 | } |
| 2372 | |
| 2373 | if (!hda->need_i915_power) |
| 2374 | display_power(chip, false); |
| 2375 | complete_all(&hda->probe_wait); |
| 2376 | to_hda_bus(bus)->bus_probing = 0; |
| 2377 | return 0; |
| 2378 | } |
| 2379 | |
| 2380 | static void azx_remove(struct pci_dev *pci) |
| 2381 | { |
| 2382 | struct snd_card *card = pci_get_drvdata(pci); |
| 2383 | struct azx *chip; |
| 2384 | struct hda_intel *hda; |
| 2385 | |
| 2386 | if (card) { |
| 2387 | /* cancel the pending probing work */ |
| 2388 | chip = card->private_data; |
| 2389 | hda = container_of(chip, struct hda_intel, chip); |
| 2390 | /* FIXME: below is an ugly workaround. |
| 2391 | * Both device_release_driver() and driver_probe_device() |
| 2392 | * take *both* the device's and its parent's lock before |
| 2393 | * calling the remove() and probe() callbacks. The codec |
| 2394 | * probe takes the locks of both the codec itself and its |
| 2395 | * parent, i.e. the PCI controller dev. Meanwhile, when |
| 2396 | * the PCI controller is unbound, it takes its lock, too |
| 2397 | * ==> ouch, a deadlock! |
| 2398 | * As a workaround, we unlock temporarily here the controller |
| 2399 | * device during cancel_work_sync() call. |
| 2400 | */ |
| 2401 | device_unlock(&pci->dev); |
| 2402 | cancel_work_sync(&hda->probe_work); |
| 2403 | device_lock(&pci->dev); |
| 2404 | |
| 2405 | snd_card_free(card); |
| 2406 | } |
| 2407 | } |
| 2408 | |
| 2409 | static void azx_shutdown(struct pci_dev *pci) |
| 2410 | { |
| 2411 | struct snd_card *card = pci_get_drvdata(pci); |
| 2412 | struct azx *chip; |
| 2413 | |
| 2414 | if (!card) |
| 2415 | return; |
| 2416 | chip = card->private_data; |
| 2417 | if (chip && chip->running) |
| 2418 | azx_stop_chip(chip); |
| 2419 | } |
| 2420 | |
| 2421 | /* PCI IDs */ |
| 2422 | static const struct pci_device_id azx_ids[] = { |
| 2423 | /* CPT */ |
| 2424 | { PCI_DEVICE(0x8086, 0x1c20), |
| 2425 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
| 2426 | /* PBG */ |
| 2427 | { PCI_DEVICE(0x8086, 0x1d20), |
| 2428 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
| 2429 | /* Panther Point */ |
| 2430 | { PCI_DEVICE(0x8086, 0x1e20), |
| 2431 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
| 2432 | /* Lynx Point */ |
| 2433 | { PCI_DEVICE(0x8086, 0x8c20), |
| 2434 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2435 | /* 9 Series */ |
| 2436 | { PCI_DEVICE(0x8086, 0x8ca0), |
| 2437 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2438 | /* Wellsburg */ |
| 2439 | { PCI_DEVICE(0x8086, 0x8d20), |
| 2440 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2441 | { PCI_DEVICE(0x8086, 0x8d21), |
| 2442 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2443 | /* Lewisburg */ |
| 2444 | { PCI_DEVICE(0x8086, 0xa1f0), |
| 2445 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2446 | { PCI_DEVICE(0x8086, 0xa270), |
| 2447 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2448 | /* Lynx Point-LP */ |
| 2449 | { PCI_DEVICE(0x8086, 0x9c20), |
| 2450 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2451 | /* Lynx Point-LP */ |
| 2452 | { PCI_DEVICE(0x8086, 0x9c21), |
| 2453 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2454 | /* Wildcat Point-LP */ |
| 2455 | { PCI_DEVICE(0x8086, 0x9ca0), |
| 2456 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
| 2457 | /* Sunrise Point */ |
| 2458 | { PCI_DEVICE(0x8086, 0xa170), |
| 2459 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2460 | /* Sunrise Point-LP */ |
| 2461 | { PCI_DEVICE(0x8086, 0x9d70), |
| 2462 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2463 | /* Kabylake */ |
| 2464 | { PCI_DEVICE(0x8086, 0xa171), |
| 2465 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2466 | /* Kabylake-LP */ |
| 2467 | { PCI_DEVICE(0x8086, 0x9d71), |
| 2468 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2469 | /* Kabylake-H */ |
| 2470 | { PCI_DEVICE(0x8086, 0xa2f0), |
| 2471 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
| 2472 | /* Coffelake */ |
| 2473 | { PCI_DEVICE(0x8086, 0xa348), |
| 2474 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2475 | /* Cannonlake */ |
| 2476 | { PCI_DEVICE(0x8086, 0x9dc8), |
| 2477 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2478 | /* CometLake-LP */ |
| 2479 | { PCI_DEVICE(0x8086, 0x02C8), |
| 2480 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2481 | /* CometLake-H */ |
| 2482 | { PCI_DEVICE(0x8086, 0x06C8), |
| 2483 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2484 | /* CometLake-S */ |
| 2485 | { PCI_DEVICE(0x8086, 0xa3f0), |
| 2486 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2487 | /* Icelake */ |
| 2488 | { PCI_DEVICE(0x8086, 0x34c8), |
| 2489 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2490 | /* Icelake-H */ |
| 2491 | { PCI_DEVICE(0x8086, 0x3dc8), |
| 2492 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2493 | /* Jasperlake */ |
| 2494 | { PCI_DEVICE(0x8086, 0x38c8), |
| 2495 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2496 | { PCI_DEVICE(0x8086, 0x4dc8), |
| 2497 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2498 | /* Tigerlake */ |
| 2499 | { PCI_DEVICE(0x8086, 0xa0c8), |
| 2500 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2501 | /* Tigerlake-H */ |
| 2502 | { PCI_DEVICE(0x8086, 0x43c8), |
| 2503 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2504 | /* DG1 */ |
| 2505 | { PCI_DEVICE(0x8086, 0x490d), |
| 2506 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2507 | /* Alderlake-S */ |
| 2508 | { PCI_DEVICE(0x8086, 0x7ad0), |
| 2509 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2510 | /* Elkhart Lake */ |
| 2511 | { PCI_DEVICE(0x8086, 0x4b55), |
| 2512 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2513 | { PCI_DEVICE(0x8086, 0x4b58), |
| 2514 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
| 2515 | /* Broxton-P(Apollolake) */ |
| 2516 | { PCI_DEVICE(0x8086, 0x5a98), |
| 2517 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, |
| 2518 | /* Broxton-T */ |
| 2519 | { PCI_DEVICE(0x8086, 0x1a98), |
| 2520 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, |
| 2521 | /* Gemini-Lake */ |
| 2522 | { PCI_DEVICE(0x8086, 0x3198), |
| 2523 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, |
| 2524 | /* Haswell */ |
| 2525 | { PCI_DEVICE(0x8086, 0x0a0c), |
| 2526 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
| 2527 | { PCI_DEVICE(0x8086, 0x0c0c), |
| 2528 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
| 2529 | { PCI_DEVICE(0x8086, 0x0d0c), |
| 2530 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
| 2531 | /* Broadwell */ |
| 2532 | { PCI_DEVICE(0x8086, 0x160c), |
| 2533 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, |
| 2534 | /* 5 Series/3400 */ |
| 2535 | { PCI_DEVICE(0x8086, 0x3b56), |
| 2536 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
| 2537 | /* Poulsbo */ |
| 2538 | { PCI_DEVICE(0x8086, 0x811b), |
| 2539 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, |
| 2540 | /* Oaktrail */ |
| 2541 | { PCI_DEVICE(0x8086, 0x080a), |
| 2542 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, |
| 2543 | /* BayTrail */ |
| 2544 | { PCI_DEVICE(0x8086, 0x0f04), |
| 2545 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, |
| 2546 | /* Braswell */ |
| 2547 | { PCI_DEVICE(0x8086, 0x2284), |
| 2548 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, |
| 2549 | /* ICH6 */ |
| 2550 | { PCI_DEVICE(0x8086, 0x2668), |
| 2551 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2552 | /* ICH7 */ |
| 2553 | { PCI_DEVICE(0x8086, 0x27d8), |
| 2554 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2555 | /* ESB2 */ |
| 2556 | { PCI_DEVICE(0x8086, 0x269a), |
| 2557 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2558 | /* ICH8 */ |
| 2559 | { PCI_DEVICE(0x8086, 0x284b), |
| 2560 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2561 | /* ICH9 */ |
| 2562 | { PCI_DEVICE(0x8086, 0x293e), |
| 2563 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2564 | /* ICH9 */ |
| 2565 | { PCI_DEVICE(0x8086, 0x293f), |
| 2566 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2567 | /* ICH10 */ |
| 2568 | { PCI_DEVICE(0x8086, 0x3a3e), |
| 2569 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2570 | /* ICH10 */ |
| 2571 | { PCI_DEVICE(0x8086, 0x3a6e), |
| 2572 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
| 2573 | /* Generic Intel */ |
| 2574 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), |
| 2575 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
| 2576 | .class_mask = 0xffffff, |
| 2577 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, |
| 2578 | /* ATI SB 450/600/700/800/900 */ |
| 2579 | { PCI_DEVICE(0x1002, 0x437b), |
| 2580 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, |
| 2581 | { PCI_DEVICE(0x1002, 0x4383), |
| 2582 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, |
| 2583 | /* AMD Hudson */ |
| 2584 | { PCI_DEVICE(0x1022, 0x780d), |
| 2585 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, |
| 2586 | /* AMD, X370 & co */ |
| 2587 | { PCI_DEVICE(0x1022, 0x1457), |
| 2588 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, |
| 2589 | /* AMD, X570 & co */ |
| 2590 | { PCI_DEVICE(0x1022, 0x1487), |
| 2591 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, |
| 2592 | /* AMD Stoney */ |
| 2593 | { PCI_DEVICE(0x1022, 0x157a), |
| 2594 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | |
| 2595 | AZX_DCAPS_PM_RUNTIME }, |
| 2596 | /* AMD Raven */ |
| 2597 | { PCI_DEVICE(0x1022, 0x15e3), |
| 2598 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, |
| 2599 | /* ATI HDMI */ |
| 2600 | { PCI_DEVICE(0x1002, 0x0002), |
| 2601 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2602 | { PCI_DEVICE(0x1002, 0x1308), |
| 2603 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2604 | { PCI_DEVICE(0x1002, 0x157a), |
| 2605 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2606 | { PCI_DEVICE(0x1002, 0x15b3), |
| 2607 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2608 | { PCI_DEVICE(0x1002, 0x793b), |
| 2609 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2610 | { PCI_DEVICE(0x1002, 0x7919), |
| 2611 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2612 | { PCI_DEVICE(0x1002, 0x960f), |
| 2613 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2614 | { PCI_DEVICE(0x1002, 0x970f), |
| 2615 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2616 | { PCI_DEVICE(0x1002, 0x9840), |
| 2617 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2618 | { PCI_DEVICE(0x1002, 0xaa00), |
| 2619 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2620 | { PCI_DEVICE(0x1002, 0xaa08), |
| 2621 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2622 | { PCI_DEVICE(0x1002, 0xaa10), |
| 2623 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2624 | { PCI_DEVICE(0x1002, 0xaa18), |
| 2625 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2626 | { PCI_DEVICE(0x1002, 0xaa20), |
| 2627 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2628 | { PCI_DEVICE(0x1002, 0xaa28), |
| 2629 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2630 | { PCI_DEVICE(0x1002, 0xaa30), |
| 2631 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2632 | { PCI_DEVICE(0x1002, 0xaa38), |
| 2633 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2634 | { PCI_DEVICE(0x1002, 0xaa40), |
| 2635 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2636 | { PCI_DEVICE(0x1002, 0xaa48), |
| 2637 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2638 | { PCI_DEVICE(0x1002, 0xaa50), |
| 2639 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2640 | { PCI_DEVICE(0x1002, 0xaa58), |
| 2641 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2642 | { PCI_DEVICE(0x1002, 0xaa60), |
| 2643 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2644 | { PCI_DEVICE(0x1002, 0xaa68), |
| 2645 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2646 | { PCI_DEVICE(0x1002, 0xaa80), |
| 2647 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2648 | { PCI_DEVICE(0x1002, 0xaa88), |
| 2649 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2650 | { PCI_DEVICE(0x1002, 0xaa90), |
| 2651 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2652 | { PCI_DEVICE(0x1002, 0xaa98), |
| 2653 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2654 | { PCI_DEVICE(0x1002, 0x9902), |
| 2655 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2656 | { PCI_DEVICE(0x1002, 0xaaa0), |
| 2657 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2658 | { PCI_DEVICE(0x1002, 0xaaa8), |
| 2659 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2660 | { PCI_DEVICE(0x1002, 0xaab0), |
| 2661 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2662 | { PCI_DEVICE(0x1002, 0xaac0), |
| 2663 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2664 | { PCI_DEVICE(0x1002, 0xaac8), |
| 2665 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
| 2666 | { PCI_DEVICE(0x1002, 0xaad8), |
| 2667 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2668 | AZX_DCAPS_PM_RUNTIME }, |
| 2669 | { PCI_DEVICE(0x1002, 0xaae0), |
| 2670 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2671 | AZX_DCAPS_PM_RUNTIME }, |
| 2672 | { PCI_DEVICE(0x1002, 0xaae8), |
| 2673 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2674 | AZX_DCAPS_PM_RUNTIME }, |
| 2675 | { PCI_DEVICE(0x1002, 0xaaf0), |
| 2676 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2677 | AZX_DCAPS_PM_RUNTIME }, |
| 2678 | { PCI_DEVICE(0x1002, 0xaaf8), |
| 2679 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2680 | AZX_DCAPS_PM_RUNTIME }, |
| 2681 | { PCI_DEVICE(0x1002, 0xab00), |
| 2682 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2683 | AZX_DCAPS_PM_RUNTIME }, |
| 2684 | { PCI_DEVICE(0x1002, 0xab08), |
| 2685 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2686 | AZX_DCAPS_PM_RUNTIME }, |
| 2687 | { PCI_DEVICE(0x1002, 0xab10), |
| 2688 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2689 | AZX_DCAPS_PM_RUNTIME }, |
| 2690 | { PCI_DEVICE(0x1002, 0xab18), |
| 2691 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2692 | AZX_DCAPS_PM_RUNTIME }, |
| 2693 | { PCI_DEVICE(0x1002, 0xab20), |
| 2694 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2695 | AZX_DCAPS_PM_RUNTIME }, |
| 2696 | { PCI_DEVICE(0x1002, 0xab28), |
| 2697 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2698 | AZX_DCAPS_PM_RUNTIME }, |
| 2699 | { PCI_DEVICE(0x1002, 0xab38), |
| 2700 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
| 2701 | AZX_DCAPS_PM_RUNTIME }, |
| 2702 | /* VIA VT8251/VT8237A */ |
| 2703 | { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, |
| 2704 | /* VIA GFX VT7122/VX900 */ |
| 2705 | { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, |
| 2706 | /* VIA GFX VT6122/VX11 */ |
| 2707 | { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, |
| 2708 | /* SIS966 */ |
| 2709 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, |
| 2710 | /* ULI M5461 */ |
| 2711 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, |
| 2712 | /* NVIDIA MCP */ |
| 2713 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), |
| 2714 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
| 2715 | .class_mask = 0xffffff, |
| 2716 | .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, |
| 2717 | /* Teradici */ |
| 2718 | { PCI_DEVICE(0x6549, 0x1200), |
| 2719 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, |
| 2720 | { PCI_DEVICE(0x6549, 0x2200), |
| 2721 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, |
| 2722 | /* Creative X-Fi (CA0110-IBG) */ |
| 2723 | /* CTHDA chips */ |
| 2724 | { PCI_DEVICE(0x1102, 0x0010), |
| 2725 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, |
| 2726 | { PCI_DEVICE(0x1102, 0x0012), |
| 2727 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, |
| 2728 | #if !IS_ENABLED(CONFIG_SND_CTXFI) |
| 2729 | /* the following entry conflicts with snd-ctxfi driver, |
| 2730 | * as ctxfi driver mutates from HD-audio to native mode with |
| 2731 | * a special command sequence. |
| 2732 | */ |
| 2733 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), |
| 2734 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
| 2735 | .class_mask = 0xffffff, |
| 2736 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | |
| 2737 | AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, |
| 2738 | #else |
| 2739 | /* this entry seems still valid -- i.e. without emu20kx chip */ |
| 2740 | { PCI_DEVICE(0x1102, 0x0009), |
| 2741 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | |
| 2742 | AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, |
| 2743 | #endif |
| 2744 | /* CM8888 */ |
| 2745 | { PCI_DEVICE(0x13f6, 0x5011), |
| 2746 | .driver_data = AZX_DRIVER_CMEDIA | |
| 2747 | AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, |
| 2748 | /* Vortex86MX */ |
| 2749 | { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, |
| 2750 | /* VMware HDAudio */ |
| 2751 | { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, |
| 2752 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ |
| 2753 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), |
| 2754 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
| 2755 | .class_mask = 0xffffff, |
| 2756 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2757 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), |
| 2758 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
| 2759 | .class_mask = 0xffffff, |
| 2760 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
| 2761 | /* Zhaoxin */ |
| 2762 | { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, |
| 2763 | { 0, } |
| 2764 | }; |
| 2765 | MODULE_DEVICE_TABLE(pci, azx_ids); |
| 2766 | |
| 2767 | /* pci_driver definition */ |
| 2768 | static struct pci_driver azx_driver = { |
| 2769 | .name = KBUILD_MODNAME, |
| 2770 | .id_table = azx_ids, |
| 2771 | .probe = azx_probe, |
| 2772 | .remove = azx_remove, |
| 2773 | .shutdown = azx_shutdown, |
| 2774 | .driver = { |
| 2775 | .pm = AZX_PM_OPS, |
| 2776 | }, |
| 2777 | }; |
| 2778 | |
| 2779 | module_pci_driver(azx_driver); |