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Merge tag 'erofs-for-6.10-rc7-fixes' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / pgtable.h
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1/*
2 * S390 version
3 * Copyright IBM Corp. 1999, 2000
4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
30#include <linux/sched.h>
31#include <linux/mm_types.h>
32#include <linux/page-flags.h>
33#include <asm/bug.h>
34#include <asm/page.h>
35
36extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
37extern void paging_init(void);
38extern void vmem_map_init(void);
39
40/*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
44#define update_mmu_cache(vma, address, ptep) do { } while (0)
45#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
46
47/*
48 * ZERO_PAGE is a global shared page that is always zero; used
49 * for zero-mapped memory areas etc..
50 */
51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + \
57 (((unsigned long)(vaddr)) &zero_page_mask))))
58#define __HAVE_COLOR_ZERO_PAGE
59
60/* TODO: s390 cannot support io_remap_pfn_range... */
61#endif /* !__ASSEMBLY__ */
62
63/*
64 * PMD_SHIFT determines the size of the area a second-level page
65 * table can map
66 * PGDIR_SHIFT determines what a third-level page table entry can map
67 */
68#ifndef CONFIG_64BIT
69# define PMD_SHIFT 20
70# define PUD_SHIFT 20
71# define PGDIR_SHIFT 20
72#else /* CONFIG_64BIT */
73# define PMD_SHIFT 20
74# define PUD_SHIFT 31
75# define PGDIR_SHIFT 42
76#endif /* CONFIG_64BIT */
77
78#define PMD_SIZE (1UL << PMD_SHIFT)
79#define PMD_MASK (~(PMD_SIZE-1))
80#define PUD_SIZE (1UL << PUD_SHIFT)
81#define PUD_MASK (~(PUD_SIZE-1))
82#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83#define PGDIR_MASK (~(PGDIR_SIZE-1))
84
85/*
86 * entries per page directory level: the S390 is two-level, so
87 * we don't really have any PMD directory physically.
88 * for S390 segment-table entries are combined to one PGD
89 * that leads to 1024 pte per pgd
90 */
91#define PTRS_PER_PTE 256
92#ifndef CONFIG_64BIT
93#define PTRS_PER_PMD 1
94#define PTRS_PER_PUD 1
95#else /* CONFIG_64BIT */
96#define PTRS_PER_PMD 2048
97#define PTRS_PER_PUD 2048
98#endif /* CONFIG_64BIT */
99#define PTRS_PER_PGD 2048
100
101#define FIRST_USER_ADDRESS 0
102
103#define pte_ERROR(e) \
104 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
105#define pmd_ERROR(e) \
106 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
107#define pud_ERROR(e) \
108 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
109#define pgd_ERROR(e) \
110 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
111
112#ifndef __ASSEMBLY__
113/*
114 * The vmalloc and module area will always be on the topmost area of the kernel
115 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
116 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
117 * modules will reside. That makes sure that inter module branches always
118 * happen without trampolines and in addition the placement within a 2GB frame
119 * is branch prediction unit friendly.
120 */
121extern unsigned long VMALLOC_START;
122extern unsigned long VMALLOC_END;
123extern struct page *vmemmap;
124
125#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
126
127#ifdef CONFIG_64BIT
128extern unsigned long MODULES_VADDR;
129extern unsigned long MODULES_END;
130#define MODULES_VADDR MODULES_VADDR
131#define MODULES_END MODULES_END
132#define MODULES_LEN (1UL << 31)
133#endif
134
135/*
136 * A 31 bit pagetable entry of S390 has following format:
137 * | PFRA | | OS |
138 * 0 0IP0
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
141 *
142 * I Page-Invalid Bit: Page is not available for address-translation
143 * P Page-Protection Bit: Store access not possible for page
144 *
145 * A 31 bit segmenttable entry of S390 has following format:
146 * | P-table origin | |PTL
147 * 0 IC
148 * 00000000001111111111222222222233
149 * 01234567890123456789012345678901
150 *
151 * I Segment-Invalid Bit: Segment is not available for address-translation
152 * C Common-Segment Bit: Segment is not private (PoP 3-30)
153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
154 *
155 * The 31 bit segmenttable origin of S390 has following format:
156 *
157 * |S-table origin | | STL |
158 * X **GPS
159 * 00000000001111111111222222222233
160 * 01234567890123456789012345678901
161 *
162 * X Space-Switch event:
163 * G Segment-Invalid Bit: *
164 * P Private-Space Bit: Segment is not private (PoP 3-30)
165 * S Storage-Alteration:
166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
167 *
168 * A 64 bit pagetable entry of S390 has following format:
169 * | PFRA |0IPC| OS |
170 * 0000000000111111111122222222223333333333444444444455555555556666
171 * 0123456789012345678901234567890123456789012345678901234567890123
172 *
173 * I Page-Invalid Bit: Page is not available for address-translation
174 * P Page-Protection Bit: Store access not possible for page
175 * C Change-bit override: HW is not required to set change bit
176 *
177 * A 64 bit segmenttable entry of S390 has following format:
178 * | P-table origin | TT
179 * 0000000000111111111122222222223333333333444444444455555555556666
180 * 0123456789012345678901234567890123456789012345678901234567890123
181 *
182 * I Segment-Invalid Bit: Segment is not available for address-translation
183 * C Common-Segment Bit: Segment is not private (PoP 3-30)
184 * P Page-Protection Bit: Store access not possible for page
185 * TT Type 00
186 *
187 * A 64 bit region table entry of S390 has following format:
188 * | S-table origin | TF TTTL
189 * 0000000000111111111122222222223333333333444444444455555555556666
190 * 0123456789012345678901234567890123456789012345678901234567890123
191 *
192 * I Segment-Invalid Bit: Segment is not available for address-translation
193 * TT Type 01
194 * TF
195 * TL Table length
196 *
197 * The 64 bit regiontable origin of S390 has following format:
198 * | region table origon | DTTL
199 * 0000000000111111111122222222223333333333444444444455555555556666
200 * 0123456789012345678901234567890123456789012345678901234567890123
201 *
202 * X Space-Switch event:
203 * G Segment-Invalid Bit:
204 * P Private-Space Bit:
205 * S Storage-Alteration:
206 * R Real space
207 * TL Table-Length:
208 *
209 * A storage key has the following format:
210 * | ACC |F|R|C|0|
211 * 0 3 4 5 6 7
212 * ACC: access key
213 * F : fetch protection bit
214 * R : referenced bit
215 * C : changed bit
216 */
217
218/* Hardware bits in the page table entry */
219#define _PAGE_CO 0x100 /* HW Change-bit override */
220#define _PAGE_PROTECT 0x200 /* HW read-only bit */
221#define _PAGE_INVALID 0x400 /* HW invalid bit */
222#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
223
224/* Software bits in the page table entry */
225#define _PAGE_PRESENT 0x001 /* SW pte present bit */
226#define _PAGE_TYPE 0x002 /* SW pte type bit */
227#define _PAGE_YOUNG 0x004 /* SW pte young bit */
228#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
229#define _PAGE_READ 0x010 /* SW pte read bit */
230#define _PAGE_WRITE 0x020 /* SW pte write bit */
231#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
232#define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
233#define __HAVE_ARCH_PTE_SPECIAL
234
235/* Set of bits not changed in pte_modify */
236#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \
237 _PAGE_DIRTY | _PAGE_YOUNG)
238
239/*
240 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the
241 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit
242 * is used to distinguish present from not-present ptes. It is changed only
243 * with the page table lock held.
244 *
245 * The following table gives the different possible bit combinations for
246 * the pte hardware and software bits in the last 12 bits of a pte:
247 *
248 * 842100000000
249 * 000084210000
250 * 000000008421
251 * .IR...wrdytp
252 * empty .10...000000
253 * swap .10...xxxx10
254 * file .11...xxxxx0
255 * prot-none, clean, old .11...000001
256 * prot-none, clean, young .11...000101
257 * prot-none, dirty, old .10...001001
258 * prot-none, dirty, young .10...001101
259 * read-only, clean, old .11...010001
260 * read-only, clean, young .01...010101
261 * read-only, dirty, old .11...011001
262 * read-only, dirty, young .01...011101
263 * read-write, clean, old .11...110001
264 * read-write, clean, young .01...110101
265 * read-write, dirty, old .10...111001
266 * read-write, dirty, young .00...111101
267 *
268 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001
269 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400
270 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600
271 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402
272 */
273
274#ifndef CONFIG_64BIT
275
276/* Bits in the segment table address-space-control-element */
277#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
278#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
279#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
280#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
281#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
282
283/* Bits in the segment table entry */
284#define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */
285#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
286#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
287#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
288#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
289#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
290#define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_PROTECT
291
292#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
293#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
294
295/*
296 * Segment table entry encoding (I = invalid, R = read-only bit):
297 * ..R...I.....
298 * prot-none ..1...1.....
299 * read-only ..1...0.....
300 * read-write ..0...0.....
301 * empty ..0...1.....
302 */
303
304/* Page status table bits for virtualization */
305#define PGSTE_ACC_BITS 0xf0000000UL
306#define PGSTE_FP_BIT 0x08000000UL
307#define PGSTE_PCL_BIT 0x00800000UL
308#define PGSTE_HR_BIT 0x00400000UL
309#define PGSTE_HC_BIT 0x00200000UL
310#define PGSTE_GR_BIT 0x00040000UL
311#define PGSTE_GC_BIT 0x00020000UL
312#define PGSTE_IN_BIT 0x00008000UL /* IPTE notify bit */
313
314#else /* CONFIG_64BIT */
315
316/* Bits in the segment/region table address-space-control-element */
317#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
318#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
319#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
320#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
321#define _ASCE_REAL_SPACE 0x20 /* real space control */
322#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
323#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
324#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
325#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
326#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
327#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
328
329/* Bits in the region table entry */
330#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
331#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
332#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
333#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
334#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
335#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
336#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
337#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
338
339#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
340#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
341#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
342#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
343#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
344#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
345
346#define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
347#define _REGION3_ENTRY_RO 0x200 /* page protection bit */
348#define _REGION3_ENTRY_CO 0x100 /* change-recording override */
349
350/* Bits in the segment table entry */
351#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
352#define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff1ff33UL
353#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
354#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
355#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
356#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
357
358#define _SEGMENT_ENTRY (0)
359#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
360
361#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
362#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
363#define _SEGMENT_ENTRY_SPLIT 0x001 /* THP splitting bit */
364#define _SEGMENT_ENTRY_YOUNG 0x002 /* SW segment young bit */
365#define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_YOUNG
366
367/*
368 * Segment table entry encoding (R = read-only, I = invalid, y = young bit):
369 * ..R...I...y.
370 * prot-none, old ..0...1...1.
371 * prot-none, young ..1...1...1.
372 * read-only, old ..1...1...0.
373 * read-only, young ..1...0...1.
374 * read-write, old ..0...1...0.
375 * read-write, young ..0...0...1.
376 * The segment table origin is used to distinguish empty (origin==0) from
377 * read-write, old segment table entries (origin!=0)
378 */
379
380#define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
381
382/* Set of bits not changed in pmd_modify */
383#define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
384 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
385
386/* Page status table bits for virtualization */
387#define PGSTE_ACC_BITS 0xf000000000000000UL
388#define PGSTE_FP_BIT 0x0800000000000000UL
389#define PGSTE_PCL_BIT 0x0080000000000000UL
390#define PGSTE_HR_BIT 0x0040000000000000UL
391#define PGSTE_HC_BIT 0x0020000000000000UL
392#define PGSTE_GR_BIT 0x0004000000000000UL
393#define PGSTE_GC_BIT 0x0002000000000000UL
394#define PGSTE_IN_BIT 0x0000800000000000UL /* IPTE notify bit */
395
396#endif /* CONFIG_64BIT */
397
398/* Guest Page State used for virtualization */
399#define _PGSTE_GPS_ZERO 0x0000000080000000UL
400#define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
401#define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
402#define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
403
404/*
405 * A user page table pointer has the space-switch-event bit, the
406 * private-space-control bit and the storage-alteration-event-control
407 * bit set. A kernel page table pointer doesn't need them.
408 */
409#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
410 _ASCE_ALT_EVENT)
411
412/*
413 * Page protection definitions.
414 */
415#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
416#define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \
417 _PAGE_INVALID | _PAGE_PROTECT)
418#define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
419 _PAGE_INVALID | _PAGE_PROTECT)
420
421#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
422 _PAGE_YOUNG | _PAGE_DIRTY)
423#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
424 _PAGE_YOUNG | _PAGE_DIRTY)
425#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
426 _PAGE_PROTECT)
427
428/*
429 * On s390 the page table entry has an invalid bit and a read-only bit.
430 * Read permission implies execute permission and write permission
431 * implies read permission.
432 */
433 /*xwr*/
434#define __P000 PAGE_NONE
435#define __P001 PAGE_READ
436#define __P010 PAGE_READ
437#define __P011 PAGE_READ
438#define __P100 PAGE_READ
439#define __P101 PAGE_READ
440#define __P110 PAGE_READ
441#define __P111 PAGE_READ
442
443#define __S000 PAGE_NONE
444#define __S001 PAGE_READ
445#define __S010 PAGE_WRITE
446#define __S011 PAGE_WRITE
447#define __S100 PAGE_READ
448#define __S101 PAGE_READ
449#define __S110 PAGE_WRITE
450#define __S111 PAGE_WRITE
451
452/*
453 * Segment entry (large page) protection definitions.
454 */
455#define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
456 _SEGMENT_ENTRY_NONE)
457#define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_INVALID | \
458 _SEGMENT_ENTRY_PROTECT)
459#define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_INVALID)
460
461static inline int mm_has_pgste(struct mm_struct *mm)
462{
463#ifdef CONFIG_PGSTE
464 if (unlikely(mm->context.has_pgste))
465 return 1;
466#endif
467 return 0;
468}
469/*
470 * pgd/pmd/pte query functions
471 */
472#ifndef CONFIG_64BIT
473
474static inline int pgd_present(pgd_t pgd) { return 1; }
475static inline int pgd_none(pgd_t pgd) { return 0; }
476static inline int pgd_bad(pgd_t pgd) { return 0; }
477
478static inline int pud_present(pud_t pud) { return 1; }
479static inline int pud_none(pud_t pud) { return 0; }
480static inline int pud_large(pud_t pud) { return 0; }
481static inline int pud_bad(pud_t pud) { return 0; }
482
483#else /* CONFIG_64BIT */
484
485static inline int pgd_present(pgd_t pgd)
486{
487 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
488 return 1;
489 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
490}
491
492static inline int pgd_none(pgd_t pgd)
493{
494 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
495 return 0;
496 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
497}
498
499static inline int pgd_bad(pgd_t pgd)
500{
501 /*
502 * With dynamic page table levels the pgd can be a region table
503 * entry or a segment table entry. Check for the bit that are
504 * invalid for either table entry.
505 */
506 unsigned long mask =
507 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
508 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
509 return (pgd_val(pgd) & mask) != 0;
510}
511
512static inline int pud_present(pud_t pud)
513{
514 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
515 return 1;
516 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
517}
518
519static inline int pud_none(pud_t pud)
520{
521 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
522 return 0;
523 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
524}
525
526static inline int pud_large(pud_t pud)
527{
528 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
529 return 0;
530 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
531}
532
533static inline int pud_bad(pud_t pud)
534{
535 /*
536 * With dynamic page table levels the pud can be a region table
537 * entry or a segment table entry. Check for the bit that are
538 * invalid for either table entry.
539 */
540 unsigned long mask =
541 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
542 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
543 return (pud_val(pud) & mask) != 0;
544}
545
546#endif /* CONFIG_64BIT */
547
548static inline int pmd_present(pmd_t pmd)
549{
550 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
551}
552
553static inline int pmd_none(pmd_t pmd)
554{
555 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
556}
557
558static inline int pmd_large(pmd_t pmd)
559{
560#ifdef CONFIG_64BIT
561 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
562#else
563 return 0;
564#endif
565}
566
567static inline int pmd_prot_none(pmd_t pmd)
568{
569 return (pmd_val(pmd) & _SEGMENT_ENTRY_INVALID) &&
570 (pmd_val(pmd) & _SEGMENT_ENTRY_NONE);
571}
572
573static inline int pmd_bad(pmd_t pmd)
574{
575#ifdef CONFIG_64BIT
576 if (pmd_large(pmd))
577 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0;
578#endif
579 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
580}
581
582#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
583extern void pmdp_splitting_flush(struct vm_area_struct *vma,
584 unsigned long addr, pmd_t *pmdp);
585
586#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
587extern int pmdp_set_access_flags(struct vm_area_struct *vma,
588 unsigned long address, pmd_t *pmdp,
589 pmd_t entry, int dirty);
590
591#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
592extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
593 unsigned long address, pmd_t *pmdp);
594
595#define __HAVE_ARCH_PMD_WRITE
596static inline int pmd_write(pmd_t pmd)
597{
598 if (pmd_prot_none(pmd))
599 return 0;
600 return (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) == 0;
601}
602
603static inline int pmd_young(pmd_t pmd)
604{
605 int young = 0;
606#ifdef CONFIG_64BIT
607 if (pmd_prot_none(pmd))
608 young = (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) != 0;
609 else
610 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
611#endif
612 return young;
613}
614
615static inline int pte_present(pte_t pte)
616{
617 /* Bit pattern: (pte & 0x001) == 0x001 */
618 return (pte_val(pte) & _PAGE_PRESENT) != 0;
619}
620
621static inline int pte_none(pte_t pte)
622{
623 /* Bit pattern: pte == 0x400 */
624 return pte_val(pte) == _PAGE_INVALID;
625}
626
627static inline int pte_swap(pte_t pte)
628{
629 /* Bit pattern: (pte & 0x603) == 0x402 */
630 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT |
631 _PAGE_TYPE | _PAGE_PRESENT))
632 == (_PAGE_INVALID | _PAGE_TYPE);
633}
634
635static inline int pte_file(pte_t pte)
636{
637 /* Bit pattern: (pte & 0x601) == 0x600 */
638 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT))
639 == (_PAGE_INVALID | _PAGE_PROTECT);
640}
641
642static inline int pte_special(pte_t pte)
643{
644 return (pte_val(pte) & _PAGE_SPECIAL);
645}
646
647#define __HAVE_ARCH_PTE_SAME
648static inline int pte_same(pte_t a, pte_t b)
649{
650 return pte_val(a) == pte_val(b);
651}
652
653static inline pgste_t pgste_get_lock(pte_t *ptep)
654{
655 unsigned long new = 0;
656#ifdef CONFIG_PGSTE
657 unsigned long old;
658
659 preempt_disable();
660 asm(
661 " lg %0,%2\n"
662 "0: lgr %1,%0\n"
663 " nihh %0,0xff7f\n" /* clear PCL bit in old */
664 " oihh %1,0x0080\n" /* set PCL bit in new */
665 " csg %0,%1,%2\n"
666 " jl 0b\n"
667 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
668 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
669#endif
670 return __pgste(new);
671}
672
673static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
674{
675#ifdef CONFIG_PGSTE
676 asm(
677 " nihh %1,0xff7f\n" /* clear PCL bit */
678 " stg %1,%0\n"
679 : "=Q" (ptep[PTRS_PER_PTE])
680 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
681 : "cc", "memory");
682 preempt_enable();
683#endif
684}
685
686static inline pgste_t pgste_get(pte_t *ptep)
687{
688 unsigned long pgste = 0;
689#ifdef CONFIG_PGSTE
690 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
691#endif
692 return __pgste(pgste);
693}
694
695static inline void pgste_set(pte_t *ptep, pgste_t pgste)
696{
697#ifdef CONFIG_PGSTE
698 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
699#endif
700}
701
702static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
703{
704#ifdef CONFIG_PGSTE
705 unsigned long address, bits, skey;
706
707 if (pte_val(*ptep) & _PAGE_INVALID)
708 return pgste;
709 address = pte_val(*ptep) & PAGE_MASK;
710 skey = (unsigned long) page_get_storage_key(address);
711 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
712 if (!(pgste_val(pgste) & PGSTE_HC_BIT) && (bits & _PAGE_CHANGED)) {
713 /* Transfer dirty + referenced bit to host bits in pgste */
714 pgste_val(pgste) |= bits << 52;
715 page_set_storage_key(address, skey ^ bits, 0);
716 } else if (!(pgste_val(pgste) & PGSTE_HR_BIT) &&
717 (bits & _PAGE_REFERENCED)) {
718 /* Transfer referenced bit to host bit in pgste */
719 pgste_val(pgste) |= PGSTE_HR_BIT;
720 page_reset_referenced(address);
721 }
722 /* Transfer page changed & referenced bit to guest bits in pgste */
723 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
724 /* Copy page access key and fetch protection bit to pgste */
725 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
726 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
727#endif
728 return pgste;
729
730}
731
732static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
733{
734#ifdef CONFIG_PGSTE
735 if (pte_val(*ptep) & _PAGE_INVALID)
736 return pgste;
737 /* Get referenced bit from storage key */
738 if (page_reset_referenced(pte_val(*ptep) & PAGE_MASK))
739 pgste_val(pgste) |= PGSTE_HR_BIT | PGSTE_GR_BIT;
740#endif
741 return pgste;
742}
743
744static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
745{
746#ifdef CONFIG_PGSTE
747 unsigned long address;
748 unsigned long nkey;
749
750 if (pte_val(entry) & _PAGE_INVALID)
751 return;
752 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
753 address = pte_val(entry) & PAGE_MASK;
754 /*
755 * Set page access key and fetch protection bit from pgste.
756 * The guest C/R information is still in the PGSTE, set real
757 * key C/R to 0.
758 */
759 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
760 page_set_storage_key(address, nkey, 0);
761#endif
762}
763
764static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
765{
766 if (!MACHINE_HAS_ESOP &&
767 (pte_val(entry) & _PAGE_PRESENT) &&
768 (pte_val(entry) & _PAGE_WRITE)) {
769 /*
770 * Without enhanced suppression-on-protection force
771 * the dirty bit on for all writable ptes.
772 */
773 pte_val(entry) |= _PAGE_DIRTY;
774 pte_val(entry) &= ~_PAGE_PROTECT;
775 }
776 *ptep = entry;
777}
778
779/**
780 * struct gmap_struct - guest address space
781 * @mm: pointer to the parent mm_struct
782 * @table: pointer to the page directory
783 * @asce: address space control element for gmap page table
784 * @crst_list: list of all crst tables used in the guest address space
785 */
786struct gmap {
787 struct list_head list;
788 struct mm_struct *mm;
789 unsigned long *table;
790 unsigned long asce;
791 void *private;
792 struct list_head crst_list;
793};
794
795/**
796 * struct gmap_rmap - reverse mapping for segment table entries
797 * @gmap: pointer to the gmap_struct
798 * @entry: pointer to a segment table entry
799 * @vmaddr: virtual address in the guest address space
800 */
801struct gmap_rmap {
802 struct list_head list;
803 struct gmap *gmap;
804 unsigned long *entry;
805 unsigned long vmaddr;
806};
807
808/**
809 * struct gmap_pgtable - gmap information attached to a page table
810 * @vmaddr: address of the 1MB segment in the process virtual memory
811 * @mapper: list of segment table entries mapping a page table
812 */
813struct gmap_pgtable {
814 unsigned long vmaddr;
815 struct list_head mapper;
816};
817
818/**
819 * struct gmap_notifier - notify function block for page invalidation
820 * @notifier_call: address of callback function
821 */
822struct gmap_notifier {
823 struct list_head list;
824 void (*notifier_call)(struct gmap *gmap, unsigned long address);
825};
826
827struct gmap *gmap_alloc(struct mm_struct *mm);
828void gmap_free(struct gmap *gmap);
829void gmap_enable(struct gmap *gmap);
830void gmap_disable(struct gmap *gmap);
831int gmap_map_segment(struct gmap *gmap, unsigned long from,
832 unsigned long to, unsigned long len);
833int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
834unsigned long __gmap_translate(unsigned long address, struct gmap *);
835unsigned long gmap_translate(unsigned long address, struct gmap *);
836unsigned long __gmap_fault(unsigned long address, struct gmap *);
837unsigned long gmap_fault(unsigned long address, struct gmap *);
838void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
839void __gmap_zap(unsigned long address, struct gmap *);
840
841void gmap_register_ipte_notifier(struct gmap_notifier *);
842void gmap_unregister_ipte_notifier(struct gmap_notifier *);
843int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
844void gmap_do_ipte_notify(struct mm_struct *, pte_t *);
845
846static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
847 pte_t *ptep, pgste_t pgste)
848{
849#ifdef CONFIG_PGSTE
850 if (pgste_val(pgste) & PGSTE_IN_BIT) {
851 pgste_val(pgste) &= ~PGSTE_IN_BIT;
852 gmap_do_ipte_notify(mm, ptep);
853 }
854#endif
855 return pgste;
856}
857
858/*
859 * Certain architectures need to do special things when PTEs
860 * within a page table are directly modified. Thus, the following
861 * hook is made available.
862 */
863static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
864 pte_t *ptep, pte_t entry)
865{
866 pgste_t pgste;
867
868 if (mm_has_pgste(mm)) {
869 pgste = pgste_get_lock(ptep);
870 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO;
871 pgste_set_key(ptep, pgste, entry);
872 pgste_set_pte(ptep, entry);
873 pgste_set_unlock(ptep, pgste);
874 } else {
875 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1)
876 pte_val(entry) |= _PAGE_CO;
877 *ptep = entry;
878 }
879}
880
881/*
882 * query functions pte_write/pte_dirty/pte_young only work if
883 * pte_present() is true. Undefined behaviour if not..
884 */
885static inline int pte_write(pte_t pte)
886{
887 return (pte_val(pte) & _PAGE_WRITE) != 0;
888}
889
890static inline int pte_dirty(pte_t pte)
891{
892 return (pte_val(pte) & _PAGE_DIRTY) != 0;
893}
894
895static inline int pte_young(pte_t pte)
896{
897 return (pte_val(pte) & _PAGE_YOUNG) != 0;
898}
899
900#define __HAVE_ARCH_PTE_UNUSED
901static inline int pte_unused(pte_t pte)
902{
903 return pte_val(pte) & _PAGE_UNUSED;
904}
905
906/*
907 * pgd/pmd/pte modification functions
908 */
909
910static inline void pgd_clear(pgd_t *pgd)
911{
912#ifdef CONFIG_64BIT
913 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
914 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
915#endif
916}
917
918static inline void pud_clear(pud_t *pud)
919{
920#ifdef CONFIG_64BIT
921 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
922 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
923#endif
924}
925
926static inline void pmd_clear(pmd_t *pmdp)
927{
928 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
929}
930
931static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
932{
933 pte_val(*ptep) = _PAGE_INVALID;
934}
935
936/*
937 * The following pte modification functions only work if
938 * pte_present() is true. Undefined behaviour if not..
939 */
940static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
941{
942 pte_val(pte) &= _PAGE_CHG_MASK;
943 pte_val(pte) |= pgprot_val(newprot);
944 /*
945 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the
946 * invalid bit set, clear it again for readable, young pages
947 */
948 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
949 pte_val(pte) &= ~_PAGE_INVALID;
950 /*
951 * newprot for PAGE_READ and PAGE_WRITE has the page protection
952 * bit set, clear it again for writable, dirty pages
953 */
954 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
955 pte_val(pte) &= ~_PAGE_PROTECT;
956 return pte;
957}
958
959static inline pte_t pte_wrprotect(pte_t pte)
960{
961 pte_val(pte) &= ~_PAGE_WRITE;
962 pte_val(pte) |= _PAGE_PROTECT;
963 return pte;
964}
965
966static inline pte_t pte_mkwrite(pte_t pte)
967{
968 pte_val(pte) |= _PAGE_WRITE;
969 if (pte_val(pte) & _PAGE_DIRTY)
970 pte_val(pte) &= ~_PAGE_PROTECT;
971 return pte;
972}
973
974static inline pte_t pte_mkclean(pte_t pte)
975{
976 pte_val(pte) &= ~_PAGE_DIRTY;
977 pte_val(pte) |= _PAGE_PROTECT;
978 return pte;
979}
980
981static inline pte_t pte_mkdirty(pte_t pte)
982{
983 pte_val(pte) |= _PAGE_DIRTY;
984 if (pte_val(pte) & _PAGE_WRITE)
985 pte_val(pte) &= ~_PAGE_PROTECT;
986 return pte;
987}
988
989static inline pte_t pte_mkold(pte_t pte)
990{
991 pte_val(pte) &= ~_PAGE_YOUNG;
992 pte_val(pte) |= _PAGE_INVALID;
993 return pte;
994}
995
996static inline pte_t pte_mkyoung(pte_t pte)
997{
998 pte_val(pte) |= _PAGE_YOUNG;
999 if (pte_val(pte) & _PAGE_READ)
1000 pte_val(pte) &= ~_PAGE_INVALID;
1001 return pte;
1002}
1003
1004static inline pte_t pte_mkspecial(pte_t pte)
1005{
1006 pte_val(pte) |= _PAGE_SPECIAL;
1007 return pte;
1008}
1009
1010#ifdef CONFIG_HUGETLB_PAGE
1011static inline pte_t pte_mkhuge(pte_t pte)
1012{
1013 pte_val(pte) |= _PAGE_LARGE;
1014 return pte;
1015}
1016#endif
1017
1018/*
1019 * Get (and clear) the user dirty bit for a pte.
1020 */
1021static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
1022 pte_t *ptep)
1023{
1024 pgste_t pgste;
1025 int dirty = 0;
1026
1027 if (mm_has_pgste(mm)) {
1028 pgste = pgste_get_lock(ptep);
1029 pgste = pgste_update_all(ptep, pgste);
1030 dirty = !!(pgste_val(pgste) & PGSTE_HC_BIT);
1031 pgste_val(pgste) &= ~PGSTE_HC_BIT;
1032 pgste_set_unlock(ptep, pgste);
1033 return dirty;
1034 }
1035 return dirty;
1036}
1037
1038/*
1039 * Get (and clear) the user referenced bit for a pte.
1040 */
1041static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
1042 pte_t *ptep)
1043{
1044 pgste_t pgste;
1045 int young = 0;
1046
1047 if (mm_has_pgste(mm)) {
1048 pgste = pgste_get_lock(ptep);
1049 pgste = pgste_update_young(ptep, pgste);
1050 young = !!(pgste_val(pgste) & PGSTE_HR_BIT);
1051 pgste_val(pgste) &= ~PGSTE_HR_BIT;
1052 pgste_set_unlock(ptep, pgste);
1053 }
1054 return young;
1055}
1056
1057static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1058{
1059 unsigned long pto = (unsigned long) ptep;
1060
1061#ifndef CONFIG_64BIT
1062 /* pto in ESA mode must point to the start of the segment table */
1063 pto &= 0x7ffffc00;
1064#endif
1065 /* Invalidation + global TLB flush for the pte */
1066 asm volatile(
1067 " ipte %2,%3"
1068 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1069}
1070
1071static inline void ptep_flush_direct(struct mm_struct *mm,
1072 unsigned long address, pte_t *ptep)
1073{
1074 if (pte_val(*ptep) & _PAGE_INVALID)
1075 return;
1076 __ptep_ipte(address, ptep);
1077}
1078
1079static inline void ptep_flush_lazy(struct mm_struct *mm,
1080 unsigned long address, pte_t *ptep)
1081{
1082 int active, count;
1083
1084 if (pte_val(*ptep) & _PAGE_INVALID)
1085 return;
1086 active = (mm == current->active_mm) ? 1 : 0;
1087 count = atomic_add_return(0x10000, &mm->context.attach_count);
1088 if ((count & 0xffff) <= active) {
1089 pte_val(*ptep) |= _PAGE_INVALID;
1090 mm->context.flush_mm = 1;
1091 } else
1092 __ptep_ipte(address, ptep);
1093 atomic_sub(0x10000, &mm->context.attach_count);
1094}
1095
1096#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1097static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1098 unsigned long addr, pte_t *ptep)
1099{
1100 pgste_t pgste;
1101 pte_t pte;
1102 int young;
1103
1104 if (mm_has_pgste(vma->vm_mm)) {
1105 pgste = pgste_get_lock(ptep);
1106 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
1107 }
1108
1109 pte = *ptep;
1110 ptep_flush_direct(vma->vm_mm, addr, ptep);
1111 young = pte_young(pte);
1112 pte = pte_mkold(pte);
1113
1114 if (mm_has_pgste(vma->vm_mm)) {
1115 pgste_set_pte(ptep, pte);
1116 pgste_set_unlock(ptep, pgste);
1117 } else
1118 *ptep = pte;
1119
1120 return young;
1121}
1122
1123#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1124static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1125 unsigned long address, pte_t *ptep)
1126{
1127 return ptep_test_and_clear_young(vma, address, ptep);
1128}
1129
1130/*
1131 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1132 * both clear the TLB for the unmapped pte. The reason is that
1133 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1134 * to modify an active pte. The sequence is
1135 * 1) ptep_get_and_clear
1136 * 2) set_pte_at
1137 * 3) flush_tlb_range
1138 * On s390 the tlb needs to get flushed with the modification of the pte
1139 * if the pte is active. The only way how this can be implemented is to
1140 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1141 * is a nop.
1142 */
1143#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1144static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1145 unsigned long address, pte_t *ptep)
1146{
1147 pgste_t pgste;
1148 pte_t pte;
1149
1150 if (mm_has_pgste(mm)) {
1151 pgste = pgste_get_lock(ptep);
1152 pgste = pgste_ipte_notify(mm, ptep, pgste);
1153 }
1154
1155 pte = *ptep;
1156 ptep_flush_lazy(mm, address, ptep);
1157 pte_val(*ptep) = _PAGE_INVALID;
1158
1159 if (mm_has_pgste(mm)) {
1160 pgste = pgste_update_all(&pte, pgste);
1161 pgste_set_unlock(ptep, pgste);
1162 }
1163 return pte;
1164}
1165
1166#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1167static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1168 unsigned long address,
1169 pte_t *ptep)
1170{
1171 pgste_t pgste;
1172 pte_t pte;
1173
1174 if (mm_has_pgste(mm)) {
1175 pgste = pgste_get_lock(ptep);
1176 pgste_ipte_notify(mm, ptep, pgste);
1177 }
1178
1179 pte = *ptep;
1180 ptep_flush_lazy(mm, address, ptep);
1181
1182 if (mm_has_pgste(mm)) {
1183 pgste = pgste_update_all(&pte, pgste);
1184 pgste_set(ptep, pgste);
1185 }
1186 return pte;
1187}
1188
1189static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1190 unsigned long address,
1191 pte_t *ptep, pte_t pte)
1192{
1193 pgste_t pgste;
1194
1195 if (mm_has_pgste(mm)) {
1196 pgste = pgste_get(ptep);
1197 pgste_set_key(ptep, pgste, pte);
1198 pgste_set_pte(ptep, pte);
1199 pgste_set_unlock(ptep, pgste);
1200 } else
1201 *ptep = pte;
1202}
1203
1204#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
1205static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1206 unsigned long address, pte_t *ptep)
1207{
1208 pgste_t pgste;
1209 pte_t pte;
1210
1211 if (mm_has_pgste(vma->vm_mm)) {
1212 pgste = pgste_get_lock(ptep);
1213 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
1214 }
1215
1216 pte = *ptep;
1217 ptep_flush_direct(vma->vm_mm, address, ptep);
1218 pte_val(*ptep) = _PAGE_INVALID;
1219
1220 if (mm_has_pgste(vma->vm_mm)) {
1221 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) ==
1222 _PGSTE_GPS_USAGE_UNUSED)
1223 pte_val(pte) |= _PAGE_UNUSED;
1224 pgste = pgste_update_all(&pte, pgste);
1225 pgste_set_unlock(ptep, pgste);
1226 }
1227 return pte;
1228}
1229
1230/*
1231 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1232 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1233 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1234 * cannot be accessed while the batched unmap is running. In this case
1235 * full==1 and a simple pte_clear is enough. See tlb.h.
1236 */
1237#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1238static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1239 unsigned long address,
1240 pte_t *ptep, int full)
1241{
1242 pgste_t pgste;
1243 pte_t pte;
1244
1245 if (!full && mm_has_pgste(mm)) {
1246 pgste = pgste_get_lock(ptep);
1247 pgste = pgste_ipte_notify(mm, ptep, pgste);
1248 }
1249
1250 pte = *ptep;
1251 if (!full)
1252 ptep_flush_lazy(mm, address, ptep);
1253 pte_val(*ptep) = _PAGE_INVALID;
1254
1255 if (!full && mm_has_pgste(mm)) {
1256 pgste = pgste_update_all(&pte, pgste);
1257 pgste_set_unlock(ptep, pgste);
1258 }
1259 return pte;
1260}
1261
1262#define __HAVE_ARCH_PTEP_SET_WRPROTECT
1263static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1264 unsigned long address, pte_t *ptep)
1265{
1266 pgste_t pgste;
1267 pte_t pte = *ptep;
1268
1269 if (pte_write(pte)) {
1270 if (mm_has_pgste(mm)) {
1271 pgste = pgste_get_lock(ptep);
1272 pgste = pgste_ipte_notify(mm, ptep, pgste);
1273 }
1274
1275 ptep_flush_lazy(mm, address, ptep);
1276 pte = pte_wrprotect(pte);
1277
1278 if (mm_has_pgste(mm)) {
1279 pgste_set_pte(ptep, pte);
1280 pgste_set_unlock(ptep, pgste);
1281 } else
1282 *ptep = pte;
1283 }
1284 return pte;
1285}
1286
1287#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1288static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1289 unsigned long address, pte_t *ptep,
1290 pte_t entry, int dirty)
1291{
1292 pgste_t pgste;
1293
1294 if (pte_same(*ptep, entry))
1295 return 0;
1296 if (mm_has_pgste(vma->vm_mm)) {
1297 pgste = pgste_get_lock(ptep);
1298 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
1299 }
1300
1301 ptep_flush_direct(vma->vm_mm, address, ptep);
1302
1303 if (mm_has_pgste(vma->vm_mm)) {
1304 pgste_set_pte(ptep, entry);
1305 pgste_set_unlock(ptep, pgste);
1306 } else
1307 *ptep = entry;
1308 return 1;
1309}
1310
1311/*
1312 * Conversion functions: convert a page and protection to a page entry,
1313 * and a page entry and page directory to the page they refer to.
1314 */
1315static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1316{
1317 pte_t __pte;
1318 pte_val(__pte) = physpage + pgprot_val(pgprot);
1319 return pte_mkyoung(__pte);
1320}
1321
1322static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1323{
1324 unsigned long physpage = page_to_phys(page);
1325 pte_t __pte = mk_pte_phys(physpage, pgprot);
1326
1327 if (pte_write(__pte) && PageDirty(page))
1328 __pte = pte_mkdirty(__pte);
1329 return __pte;
1330}
1331
1332#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1333#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1334#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1335#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1336
1337#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1338#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1339
1340#ifndef CONFIG_64BIT
1341
1342#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1343#define pud_deref(pmd) ({ BUG(); 0UL; })
1344#define pgd_deref(pmd) ({ BUG(); 0UL; })
1345
1346#define pud_offset(pgd, address) ((pud_t *) pgd)
1347#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1348
1349#else /* CONFIG_64BIT */
1350
1351#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1352#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1353#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1354
1355static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1356{
1357 pud_t *pud = (pud_t *) pgd;
1358 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1359 pud = (pud_t *) pgd_deref(*pgd);
1360 return pud + pud_index(address);
1361}
1362
1363static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1364{
1365 pmd_t *pmd = (pmd_t *) pud;
1366 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1367 pmd = (pmd_t *) pud_deref(*pud);
1368 return pmd + pmd_index(address);
1369}
1370
1371#endif /* CONFIG_64BIT */
1372
1373#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1374#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1375#define pte_page(x) pfn_to_page(pte_pfn(x))
1376
1377#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1378
1379/* Find an entry in the lowest level page table.. */
1380#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1381#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1382#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1383#define pte_unmap(pte) do { } while (0)
1384
1385static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1386{
1387 unsigned long sto = (unsigned long) pmdp -
1388 pmd_index(address) * sizeof(pmd_t);
1389
1390 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)) {
1391 asm volatile(
1392 " .insn rrf,0xb98e0000,%2,%3,0,0"
1393 : "=m" (*pmdp)
1394 : "m" (*pmdp), "a" (sto),
1395 "a" ((address & HPAGE_MASK))
1396 : "cc"
1397 );
1398 }
1399}
1400
1401static inline void __pmd_csp(pmd_t *pmdp)
1402{
1403 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1404 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1405 _SEGMENT_ENTRY_INVALID;
1406 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1407
1408 asm volatile(
1409 " csp %1,%3"
1410 : "=m" (*pmdp)
1411 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1412}
1413
1414#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1415static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1416{
1417 /*
1418 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
1419 * Convert to segment table entry format.
1420 */
1421 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1422 return pgprot_val(SEGMENT_NONE);
1423 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1424 return pgprot_val(SEGMENT_READ);
1425 return pgprot_val(SEGMENT_WRITE);
1426}
1427
1428static inline pmd_t pmd_mkyoung(pmd_t pmd)
1429{
1430#ifdef CONFIG_64BIT
1431 if (pmd_prot_none(pmd)) {
1432 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1433 } else {
1434 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1435 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID;
1436 }
1437#endif
1438 return pmd;
1439}
1440
1441static inline pmd_t pmd_mkold(pmd_t pmd)
1442{
1443#ifdef CONFIG_64BIT
1444 if (pmd_prot_none(pmd)) {
1445 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1446 } else {
1447 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG;
1448 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1449 }
1450#endif
1451 return pmd;
1452}
1453
1454static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1455{
1456 int young;
1457
1458 young = pmd_young(pmd);
1459 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1460 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1461 if (young)
1462 pmd = pmd_mkyoung(pmd);
1463 return pmd;
1464}
1465
1466static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1467{
1468 pmd_t __pmd;
1469 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1470 return pmd_mkyoung(__pmd);
1471}
1472
1473static inline pmd_t pmd_mkwrite(pmd_t pmd)
1474{
1475 /* Do not clobber PROT_NONE segments! */
1476 if (!pmd_prot_none(pmd))
1477 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1478 return pmd;
1479}
1480#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1481
1482static inline void pmdp_flush_lazy(struct mm_struct *mm,
1483 unsigned long address, pmd_t *pmdp)
1484{
1485 int active, count;
1486
1487 active = (mm == current->active_mm) ? 1 : 0;
1488 count = atomic_add_return(0x10000, &mm->context.attach_count);
1489 if ((count & 0xffff) <= active) {
1490 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID;
1491 mm->context.flush_mm = 1;
1492 } else
1493 __pmd_idte(address, pmdp);
1494 atomic_sub(0x10000, &mm->context.attach_count);
1495}
1496
1497#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1498
1499#define __HAVE_ARCH_PGTABLE_DEPOSIT
1500extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1501 pgtable_t pgtable);
1502
1503#define __HAVE_ARCH_PGTABLE_WITHDRAW
1504extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1505
1506static inline int pmd_trans_splitting(pmd_t pmd)
1507{
1508 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1509}
1510
1511static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1512 pmd_t *pmdp, pmd_t entry)
1513{
1514 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INVALID) && MACHINE_HAS_EDAT1)
1515 pmd_val(entry) |= _SEGMENT_ENTRY_CO;
1516 *pmdp = entry;
1517}
1518
1519static inline pmd_t pmd_mkhuge(pmd_t pmd)
1520{
1521 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1522 return pmd;
1523}
1524
1525static inline pmd_t pmd_wrprotect(pmd_t pmd)
1526{
1527 /* Do not clobber PROT_NONE segments! */
1528 if (!pmd_prot_none(pmd))
1529 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1530 return pmd;
1531}
1532
1533static inline pmd_t pmd_mkdirty(pmd_t pmd)
1534{
1535 /* No dirty bit in the segment table entry. */
1536 return pmd;
1537}
1538
1539#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1540static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1541 unsigned long address, pmd_t *pmdp)
1542{
1543 pmd_t pmd;
1544
1545 pmd = *pmdp;
1546 __pmd_idte(address, pmdp);
1547 *pmdp = pmd_mkold(pmd);
1548 return pmd_young(pmd);
1549}
1550
1551#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1552static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1553 unsigned long address, pmd_t *pmdp)
1554{
1555 pmd_t pmd = *pmdp;
1556
1557 __pmd_idte(address, pmdp);
1558 pmd_clear(pmdp);
1559 return pmd;
1560}
1561
1562#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1563static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1564 unsigned long address, pmd_t *pmdp)
1565{
1566 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1567}
1568
1569#define __HAVE_ARCH_PMDP_INVALIDATE
1570static inline void pmdp_invalidate(struct vm_area_struct *vma,
1571 unsigned long address, pmd_t *pmdp)
1572{
1573 __pmd_idte(address, pmdp);
1574}
1575
1576#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1577static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1578 unsigned long address, pmd_t *pmdp)
1579{
1580 pmd_t pmd = *pmdp;
1581
1582 if (pmd_write(pmd)) {
1583 __pmd_idte(address, pmdp);
1584 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1585 }
1586}
1587
1588#define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1589#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1590
1591static inline int pmd_trans_huge(pmd_t pmd)
1592{
1593 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1594}
1595
1596static inline int has_transparent_hugepage(void)
1597{
1598 return MACHINE_HAS_HPAGE ? 1 : 0;
1599}
1600
1601static inline unsigned long pmd_pfn(pmd_t pmd)
1602{
1603 return pmd_val(pmd) >> PAGE_SHIFT;
1604}
1605#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1606
1607/*
1608 * 31 bit swap entry format:
1609 * A page-table entry has some bits we have to treat in a special way.
1610 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1611 * exception will occur instead of a page translation exception. The
1612 * specifiation exception has the bad habit not to store necessary
1613 * information in the lowcore.
1614 * Bits 21, 22, 30 and 31 are used to indicate the page type.
1615 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1616 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1617 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1618 * plus 24 for the offset.
1619 * 0| offset |0110|o|type |00|
1620 * 0 0000000001111111111 2222 2 22222 33
1621 * 0 1234567890123456789 0123 4 56789 01
1622 *
1623 * 64 bit swap entry format:
1624 * A page-table entry has some bits we have to treat in a special way.
1625 * Bits 52 and bit 55 have to be zero, otherwise an specification
1626 * exception will occur instead of a page translation exception. The
1627 * specifiation exception has the bad habit not to store necessary
1628 * information in the lowcore.
1629 * Bits 53, 54, 62 and 63 are used to indicate the page type.
1630 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1631 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1632 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1633 * plus 56 for the offset.
1634 * | offset |0110|o|type |00|
1635 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1636 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1637 */
1638#ifndef CONFIG_64BIT
1639#define __SWP_OFFSET_MASK (~0UL >> 12)
1640#else
1641#define __SWP_OFFSET_MASK (~0UL >> 11)
1642#endif
1643static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1644{
1645 pte_t pte;
1646 offset &= __SWP_OFFSET_MASK;
1647 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) |
1648 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1649 return pte;
1650}
1651
1652#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1653#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1654#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1655
1656#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1657#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1658
1659#ifndef CONFIG_64BIT
1660# define PTE_FILE_MAX_BITS 26
1661#else /* CONFIG_64BIT */
1662# define PTE_FILE_MAX_BITS 59
1663#endif /* CONFIG_64BIT */
1664
1665#define pte_to_pgoff(__pte) \
1666 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1667
1668#define pgoff_to_pte(__off) \
1669 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1670 | _PAGE_INVALID | _PAGE_PROTECT })
1671
1672#endif /* !__ASSEMBLY__ */
1673
1674#define kern_addr_valid(addr) (1)
1675
1676extern int vmem_add_mapping(unsigned long start, unsigned long size);
1677extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1678extern int s390_enable_sie(void);
1679
1680/*
1681 * No page table caches to initialise
1682 */
1683static inline void pgtable_cache_init(void) { }
1684static inline void check_pgt_cache(void) { }
1685
1686#include <asm-generic/pgtable.h>
1687
1688#endif /* _S390_PAGE_H */
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