[linux-2.6-block.git] / include / uapi / rdma / mlx5-abi.h

/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_ABI_USER_H
#define MLX5_ABI_USER_H

#include <linux/types.h>
#include <linux/if_ether.h>	/* For ETH_ALEN. */
#include <rdma/ib_user_ioctl_verbs.h>
#include <rdma/mlx5_user_ioctl_verbs.h>

enum {
	MLX5_QP_FLAG_SIGNATURE		= 1 << 0,
	MLX5_QP_FLAG_SCATTER_CQE	= 1 << 1,
	MLX5_QP_FLAG_TUNNEL_OFFLOADS	= 1 << 2,
	MLX5_QP_FLAG_BFREG_INDEX	= 1 << 3,
	MLX5_QP_FLAG_TYPE_DCT		= 1 << 4,
	MLX5_QP_FLAG_TYPE_DCI		= 1 << 5,
	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
	MLX5_QP_FLAG_ALLOW_SCATTER_CQE	= 1 << 8,
	MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE	= 1 << 9,
	MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
	MLX5_QP_FLAG_DCI_STREAM	= 1 << 11,
};

enum {
	MLX5_SRQ_FLAG_SIGNATURE		= 1 << 0,
};

enum {
	MLX5_WQ_FLAG_SIGNATURE		= 1 << 0,
};

/* Increment this value if any changes that break userspace ABI
 * compatibility are made.
 */
#define MLX5_IB_UVERBS_ABI_VERSION	1

/* Make sure that all structs defined in this file remain laid out so
 * that they pack the same way on 32-bit and 64-bit architectures (to
 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
 * In particular do not use pointer types -- pass pointers in __u64
 * instead.
 */

struct mlx5_ib_alloc_ucontext_req {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
};

enum mlx5_lib_caps {
	MLX5_LIB_CAP_4K_UAR	= (__u64)1 << 0,
	MLX5_LIB_CAP_DYN_UAR	= (__u64)1 << 1,
};

enum mlx5_ib_alloc_uctx_v2_flags {
	MLX5_IB_ALLOC_UCTX_DEVX	= 1 << 0,
};
struct mlx5_ib_alloc_ucontext_req_v2 {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
	__u32	flags;
	__u32	comp_mask;
	__u8	max_cqe_version;
	__u8	reserved0;
	__u16	reserved1;
	__u32	reserved2;
	__aligned_u64 lib_caps;
};

enum mlx5_ib_alloc_ucontext_resp_mask {
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY    = 1UL << 1,
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE               = 1UL << 2,
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS           = 1UL << 3,
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS	   = 1UL << 4,
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG   = 1UL << 5,
};

enum mlx5_user_cmds_supp_uhw {
	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH    = 1 << 1,
};

/* The eth_min_inline response value is set to off-by-one vs the FW
 * returned value to allow user-space to deal with older kernels.
 */
enum mlx5_user_inline_mode {
	MLX5_USER_INLINE_MODE_NA,
	MLX5_USER_INLINE_MODE_NONE,
	MLX5_USER_INLINE_MODE_L2,
	MLX5_USER_INLINE_MODE_IP,
	MLX5_USER_INLINE_MODE_TCP_UDP,
};

enum {
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
};

struct mlx5_ib_alloc_ucontext_resp {
	__u32	qp_tab_size;
	__u32	bf_reg_size;
	__u32	tot_bfregs;
	__u32	cache_line_size;
	__u16	max_sq_desc_sz;
	__u16	max_rq_desc_sz;
	__u32	max_send_wqebb;
	__u32	max_recv_wr;
	__u32	max_srq_recv_wr;
	__u16	num_ports;
	__u16	flow_action_flags;
	__u32	comp_mask;
	__u32	response_length;
	__u8	cqe_version;
	__u8	cmds_supp_uhw;
	__u8	eth_min_inline;
	__u8	clock_info_versions;
	__aligned_u64 hca_core_clock_offset;
	__u32	log_uar_size;
	__u32	num_uars_per_page;
	__u32	num_dyn_bfregs;
	__u32	dump_fill_mkey;
};

struct mlx5_ib_alloc_pd_resp {
	__u32	pdn;
};

struct mlx5_ib_tso_caps {
	__u32 max_tso; /* Maximum tso payload size in bytes */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_UD
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_rss_caps {
	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 reserved[7];
};

enum mlx5_ib_cqe_comp_res_format {
	MLX5_IB_CQE_RES_FORMAT_HASH	= 1 << 0,
	MLX5_IB_CQE_RES_FORMAT_CSUM	= 1 << 1,
	MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
};

struct mlx5_ib_cqe_comp_caps {
	__u32 max_num;
	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
};

enum mlx5_ib_packet_pacing_cap_flags {
	MLX5_IB_PP_SUPPORT_BURST	= 1 << 0,
};

struct mlx5_packet_pacing_caps {
	__u32 qp_rate_limit_min;
	__u32 qp_rate_limit_max; /* In kpbs */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u8  cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
	__u8  reserved[3];
};

enum mlx5_ib_mpw_caps {
	MPW_RESERVED		= 1 << 0,
	MLX5_IB_ALLOW_MPW	= 1 << 1,
	MLX5_IB_SUPPORT_EMPW	= 1 << 2,
};

enum mlx5_ib_sw_parsing_offloads {
	MLX5_IB_SW_PARSING = 1 << 0,
	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	MLX5_IB_SW_PARSING_LSO = 1 << 2,
};

struct mlx5_ib_sw_parsing_caps {
	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_striding_rq_caps {
	__u32 min_single_stride_log_num_of_bytes;
	__u32 max_single_stride_log_num_of_bytes;
	__u32 min_single_wqe_log_num_of_strides;
	__u32 max_single_wqe_log_num_of_strides;

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u32 reserved;
};

struct mlx5_ib_dci_streams_caps {
	__u8 max_log_num_concurent;
	__u8 max_log_num_errored;
};

enum mlx5_ib_query_dev_resp_flags {
	/* Support 128B CQE compression */
	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD  = 1 << 1,
	MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
	MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
	MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP = 1 << 4,
};

enum mlx5_ib_tunnel_offloads {
	MLX5_IB_TUNNELED_OFFLOADS_VXLAN  = 1 << 0,
	MLX5_IB_TUNNELED_OFFLOADS_GRE    = 1 << 1,
	MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
	MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
	MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
};

struct mlx5_ib_query_device_resp {
	__u32	comp_mask;
	__u32	response_length;
	struct	mlx5_ib_tso_caps tso_caps;
	struct	mlx5_ib_rss_caps rss_caps;
	struct	mlx5_ib_cqe_comp_caps cqe_comp_caps;
	struct	mlx5_packet_pacing_caps packet_pacing_caps;
	__u32	mlx5_ib_support_multi_pkt_send_wqes;
	__u32	flags; /* Use enum mlx5_ib_query_dev_resp_flags */
	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
	struct mlx5_ib_striding_rq_caps striding_rq_caps;
	__u32	tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
	struct  mlx5_ib_dci_streams_caps dci_streams_caps;
	__u16 reserved;
	struct mlx5_ib_uapi_reg reg_c0;
};

enum mlx5_ib_create_cq_flags {
	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD	= 1 << 0,
	MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX  = 1 << 1,
	MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS	= 1 << 2,
};

struct mlx5_ib_create_cq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32	cqe_size;
	__u8    cqe_comp_en;
	__u8    cqe_comp_res_format;
	__u16	flags;
	__u16	uar_page_index;
	__u16	reserved0;
	__u32	reserved1;
};

struct mlx5_ib_create_cq_resp {
	__u32	cqn;
	__u32	reserved;
};

struct mlx5_ib_resize_cq {
	__aligned_u64 buf_addr;
	__u16	cqe_size;
	__u16	reserved0;
	__u32	reserved1;
};

struct mlx5_ib_create_srq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32	flags;
	__u32	reserved0; /* explicit padding (optional on i386) */
	__u32	uidx;
	__u32	reserved1;
};

struct mlx5_ib_create_srq_resp {
	__u32	srqn;
	__u32	reserved;
};

struct mlx5_ib_create_qp_dci_streams {
	__u8 log_num_concurent;
	__u8 log_num_errored;
};

struct mlx5_ib_create_qp {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32	sq_wqe_count;
	__u32	rq_wqe_count;
	__u32	rq_wqe_shift;
	__u32	flags;
	__u32	uidx;
	__u32	bfreg_index;
	union {
		__aligned_u64 sq_buf_addr;
		__aligned_u64 access_key;
	};
	__u32  ece_options;
	struct  mlx5_ib_create_qp_dci_streams dci_streams;
	__u16 reserved;
};

/* RX Hash function flags */
enum mlx5_rx_hash_function_flags {
	MLX5_RX_HASH_FUNC_TOEPLITZ	= 1 << 0,
};

/*
 * RX Hash flags, these flags allows to set which incoming packet's field should
 * participates in RX Hash. Each flag represent certain packet's field,
 * when the flag is set the field that is represented by the flag will
 * participate in RX Hash calculation.
 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
 * and *TCP and *UDP flags can't be enabled together on the same QP.
*/
enum mlx5_rx_hash_fields {
	MLX5_RX_HASH_SRC_IPV4	= 1 << 0,
	MLX5_RX_HASH_DST_IPV4	= 1 << 1,
	MLX5_RX_HASH_SRC_IPV6	= 1 << 2,
	MLX5_RX_HASH_DST_IPV6	= 1 << 3,
	MLX5_RX_HASH_SRC_PORT_TCP	= 1 << 4,
	MLX5_RX_HASH_DST_PORT_TCP	= 1 << 5,
	MLX5_RX_HASH_SRC_PORT_UDP	= 1 << 6,
	MLX5_RX_HASH_DST_PORT_UDP	= 1 << 7,
	MLX5_RX_HASH_IPSEC_SPI		= 1 << 8,
	/* Save bits for future fields */
	MLX5_RX_HASH_INNER		= (1UL << 31),
};

struct mlx5_ib_create_qp_rss {
	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 rx_key_len; /* valid only for Toeplitz */
	__u8 reserved[6];
	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	__u32   comp_mask;
	__u32	flags;
};

enum mlx5_ib_create_qp_resp_mask {
	MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
	MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
	MLX5_IB_CREATE_QP_RESP_MASK_RQN  = 1UL << 2,
	MLX5_IB_CREATE_QP_RESP_MASK_SQN  = 1UL << 3,
	MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR  = 1UL << 4,
};

struct mlx5_ib_create_qp_resp {
	__u32	bfreg_index;
	__u32   ece_options;
	__u32	comp_mask;
	__u32	tirn;
	__u32	tisn;
	__u32	rqn;
	__u32	sqn;
	__u32   reserved1;
	__u64	tir_icm_addr;
};

struct mlx5_ib_alloc_mw {
	__u32	comp_mask;
	__u8	num_klms;
	__u8	reserved1;
	__u16	reserved2;
};

enum mlx5_ib_create_wq_mask {
	MLX5_IB_CREATE_WQ_STRIDING_RQ	= (1 << 0),
};

struct mlx5_ib_create_wq {
	__aligned_u64 buf_addr;
	__aligned_u64 db_addr;
	__u32   rq_wqe_count;
	__u32   rq_wqe_shift;
	__u32   user_index;
	__u32   flags;
	__u32   comp_mask;
	__u32	single_stride_log_num_of_bytes;
	__u32	single_wqe_log_num_of_strides;
	__u32	two_byte_shift_en;
};

struct mlx5_ib_create_ah_resp {
	__u32	response_length;
	__u8	dmac[ETH_ALEN];
	__u8	reserved[6];
};

struct mlx5_ib_burst_info {
	__u32       max_burst_sz;
	__u16       typical_pkt_sz;
	__u16       reserved;
};

enum mlx5_ib_modify_qp_mask {
	MLX5_IB_MODIFY_QP_OOO_DP = 1 << 0,
};

struct mlx5_ib_modify_qp {
	__u32			   comp_mask;
	struct mlx5_ib_burst_info  burst_info;
	__u32			   ece_options;
};

struct mlx5_ib_modify_qp_resp {
	__u32	response_length;
	__u32	dctn;
	__u32   ece_options;
	__u32   reserved;
};

struct mlx5_ib_create_wq_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_create_rwq_ind_tbl_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_modify_wq {
	__u32	comp_mask;
	__u32	reserved;
};

struct mlx5_ib_clock_info {
	__u32 sign;
	__u32 resv;
	__aligned_u64 nsec;
	__aligned_u64 cycles;
	__aligned_u64 frac;
	__u32 mult;
	__u32 shift;
	__aligned_u64 mask;
	__aligned_u64 overflow_period;
};

enum mlx5_ib_mmap_cmd {
	MLX5_IB_MMAP_REGULAR_PAGE               = 0,
	MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES       = 1,
	MLX5_IB_MMAP_WC_PAGE                    = 2,
	MLX5_IB_MMAP_NC_PAGE                    = 3,
	/* 5 is chosen in order to be compatible with old versions of libmlx5 */
	MLX5_IB_MMAP_CORE_CLOCK                 = 5,
	MLX5_IB_MMAP_ALLOC_WC                   = 6,
	MLX5_IB_MMAP_CLOCK_INFO                 = 7,
	MLX5_IB_MMAP_DEVICE_MEM                 = 8,
};

enum {
	MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
};

/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
enum {
	MLX5_IB_CLOCK_INFO_V1              = 0,
};

struct mlx5_ib_flow_counters_desc {
	__u32	description;
	__u32	index;
};

struct mlx5_ib_flow_counters_data {
	RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
	__u32   ncounters;
	__u32   reserved;
};

struct mlx5_ib_create_flow {
	__u32   ncounters_data;
	__u32   reserved;
	/*
	 * Following are counters data based on ncounters_data, each
	 * entry in the data[] should match a corresponding counter object
	 * that was pointed by a counters spec upon the flow creation
	 */
	struct mlx5_ib_flow_counters_data data[];
};

#endif /* MLX5_ABI_USER_H */
Commit	Line	Data
	1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
	2	/*
	3	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
	34	#ifndef MLX5_ABI_USER_H
	35	#define MLX5_ABI_USER_H
	36
	37	#include <linux/types.h>
	38	#include <linux/if_ether.h> /* For ETH_ALEN. */
	39	#include <rdma/ib_user_ioctl_verbs.h>
	40	#include <rdma/mlx5_user_ioctl_verbs.h>
	41
	42	enum {
	43	MLX5_QP_FLAG_SIGNATURE = 1 << 0,
	44	MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
	45	MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
	46	MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
	47	MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
	48	MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
	49	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
	50	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
	51	MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
	52	MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
	53	MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
	54	MLX5_QP_FLAG_DCI_STREAM = 1 << 11,
	55	};
	56
	57	enum {
	58	MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
	59	};
	60
	61	enum {
	62	MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
	63	};
	64
	65	/* Increment this value if any changes that break userspace ABI
	66	* compatibility are made.
	67	*/
	68	#define MLX5_IB_UVERBS_ABI_VERSION 1
	69
	70	/* Make sure that all structs defined in this file remain laid out so
	71	* that they pack the same way on 32-bit and 64-bit architectures (to
	72	* avoid incompatibility between 32-bit userspace and 64-bit kernels).
	73	* In particular do not use pointer types -- pass pointers in __u64
	74	* instead.
	75	*/
	76
	77	struct mlx5_ib_alloc_ucontext_req {
	78	__u32 total_num_bfregs;
	79	__u32 num_low_latency_bfregs;
	80	};
	81
	82	enum mlx5_lib_caps {
	83	MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
	84	MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
	85	};
	86
	87	enum mlx5_ib_alloc_uctx_v2_flags {
	88	MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
	89	};
	90	struct mlx5_ib_alloc_ucontext_req_v2 {
	91	__u32 total_num_bfregs;
	92	__u32 num_low_latency_bfregs;
	93	__u32 flags;
	94	__u32 comp_mask;
	95	__u8 max_cqe_version;
	96	__u8 reserved0;
	97	__u16 reserved1;
	98	__u32 reserved2;
	99	__aligned_u64 lib_caps;
	100	};
	101
	102	enum mlx5_ib_alloc_ucontext_resp_mask {
	103	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
	104	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
	105	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
	106	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
	107	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4,
	108	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5,
	109	};
	110
	111	enum mlx5_user_cmds_supp_uhw {
	112	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
	113	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
	114	};
	115
	116	/* The eth_min_inline response value is set to off-by-one vs the FW
	117	* returned value to allow user-space to deal with older kernels.
	118	*/
	119	enum mlx5_user_inline_mode {
	120	MLX5_USER_INLINE_MODE_NA,
	121	MLX5_USER_INLINE_MODE_NONE,
	122	MLX5_USER_INLINE_MODE_L2,
	123	MLX5_USER_INLINE_MODE_IP,
	124	MLX5_USER_INLINE_MODE_TCP_UDP,
	125	};
	126
	127	enum {
	128	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
	129	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
	130	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
	131	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
	132	MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
	133	};
	134
	135	struct mlx5_ib_alloc_ucontext_resp {
	136	__u32 qp_tab_size;
	137	__u32 bf_reg_size;
	138	__u32 tot_bfregs;
	139	__u32 cache_line_size;
	140	__u16 max_sq_desc_sz;
	141	__u16 max_rq_desc_sz;
	142	__u32 max_send_wqebb;
	143	__u32 max_recv_wr;
	144	__u32 max_srq_recv_wr;
	145	__u16 num_ports;
	146	__u16 flow_action_flags;
	147	__u32 comp_mask;
	148	__u32 response_length;
	149	__u8 cqe_version;
	150	__u8 cmds_supp_uhw;
	151	__u8 eth_min_inline;
	152	__u8 clock_info_versions;
	153	__aligned_u64 hca_core_clock_offset;
	154	__u32 log_uar_size;
	155	__u32 num_uars_per_page;
	156	__u32 num_dyn_bfregs;
	157	__u32 dump_fill_mkey;
	158	};
	159
	160	struct mlx5_ib_alloc_pd_resp {
	161	__u32 pdn;
	162	};
	163
	164	struct mlx5_ib_tso_caps {
	165	__u32 max_tso; /* Maximum tso payload size in bytes */
	166
	167	/* Corresponding bit will be set if qp type from
	168	* 'enum ib_qp_type' is supported, e.g.
	169	* supported_qpts \|= 1 << IB_QPT_UD
	170	*/
	171	__u32 supported_qpts;
	172	};
	173
	174	struct mlx5_ib_rss_caps {
	175	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	176	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	177	__u8 reserved[7];
	178	};
	179
	180	enum mlx5_ib_cqe_comp_res_format {
	181	MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
	182	MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
	183	MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
	184	};
	185
	186	struct mlx5_ib_cqe_comp_caps {
	187	__u32 max_num;
	188	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
	189	};
	190
	191	enum mlx5_ib_packet_pacing_cap_flags {
	192	MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
	193	};
	194
	195	struct mlx5_packet_pacing_caps {
	196	__u32 qp_rate_limit_min;
	197	__u32 qp_rate_limit_max; /* In kpbs */
	198
	199	/* Corresponding bit will be set if qp type from
	200	* 'enum ib_qp_type' is supported, e.g.
	201	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	202	*/
	203	__u32 supported_qpts;
	204	__u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
	205	__u8 reserved[3];
	206	};
	207
	208	enum mlx5_ib_mpw_caps {
	209	MPW_RESERVED = 1 << 0,
	210	MLX5_IB_ALLOW_MPW = 1 << 1,
	211	MLX5_IB_SUPPORT_EMPW = 1 << 2,
	212	};
	213
	214	enum mlx5_ib_sw_parsing_offloads {
	215	MLX5_IB_SW_PARSING = 1 << 0,
	216	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	217	MLX5_IB_SW_PARSING_LSO = 1 << 2,
	218	};
	219
	220	struct mlx5_ib_sw_parsing_caps {
	221	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
	222
	223	/* Corresponding bit will be set if qp type from
	224	* 'enum ib_qp_type' is supported, e.g.
	225	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	226	*/
	227	__u32 supported_qpts;
	228	};
	229
	230	struct mlx5_ib_striding_rq_caps {
	231	__u32 min_single_stride_log_num_of_bytes;
	232	__u32 max_single_stride_log_num_of_bytes;
	233	__u32 min_single_wqe_log_num_of_strides;
	234	__u32 max_single_wqe_log_num_of_strides;
	235
	236	/* Corresponding bit will be set if qp type from
	237	* 'enum ib_qp_type' is supported, e.g.
	238	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	239	*/
	240	__u32 supported_qpts;
	241	__u32 reserved;
	242	};
	243
	244	struct mlx5_ib_dci_streams_caps {
	245	__u8 max_log_num_concurent;
	246	__u8 max_log_num_errored;
	247	};
	248
	249	enum mlx5_ib_query_dev_resp_flags {
	250	/* Support 128B CQE compression */
	251	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
	252	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
	253	MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
	254	MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
	255	MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP = 1 << 4,
	256	};
	257
	258	enum mlx5_ib_tunnel_offloads {
	259	MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
	260	MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
	261	MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
	262	MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
	263	MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
	264	};
	265
	266	struct mlx5_ib_query_device_resp {
	267	__u32 comp_mask;
	268	__u32 response_length;
	269	struct mlx5_ib_tso_caps tso_caps;
	270	struct mlx5_ib_rss_caps rss_caps;
	271	struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
	272	struct mlx5_packet_pacing_caps packet_pacing_caps;
	273	__u32 mlx5_ib_support_multi_pkt_send_wqes;
	274	__u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
	275	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
	276	struct mlx5_ib_striding_rq_caps striding_rq_caps;
	277	__u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
	278	struct mlx5_ib_dci_streams_caps dci_streams_caps;
	279	__u16 reserved;
	280	struct mlx5_ib_uapi_reg reg_c0;
	281	};
	282
	283	enum mlx5_ib_create_cq_flags {
	284	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
	285	MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
	286	MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2,
	287	};
	288
	289	struct mlx5_ib_create_cq {
	290	__aligned_u64 buf_addr;
	291	__aligned_u64 db_addr;
	292	__u32 cqe_size;
	293	__u8 cqe_comp_en;
	294	__u8 cqe_comp_res_format;
	295	__u16 flags;
	296	__u16 uar_page_index;
	297	__u16 reserved0;
	298	__u32 reserved1;
	299	};
	300
	301	struct mlx5_ib_create_cq_resp {
	302	__u32 cqn;
	303	__u32 reserved;
	304	};
	305
	306	struct mlx5_ib_resize_cq {
	307	__aligned_u64 buf_addr;
	308	__u16 cqe_size;
	309	__u16 reserved0;
	310	__u32 reserved1;
	311	};
	312
	313	struct mlx5_ib_create_srq {
	314	__aligned_u64 buf_addr;
	315	__aligned_u64 db_addr;
	316	__u32 flags;
	317	__u32 reserved0; /* explicit padding (optional on i386) */
	318	__u32 uidx;
	319	__u32 reserved1;
	320	};
	321
	322	struct mlx5_ib_create_srq_resp {
	323	__u32 srqn;
	324	__u32 reserved;
	325	};
	326
	327	struct mlx5_ib_create_qp_dci_streams {
	328	__u8 log_num_concurent;
	329	__u8 log_num_errored;
	330	};
	331
	332	struct mlx5_ib_create_qp {
	333	__aligned_u64 buf_addr;
	334	__aligned_u64 db_addr;
	335	__u32 sq_wqe_count;
	336	__u32 rq_wqe_count;
	337	__u32 rq_wqe_shift;
	338	__u32 flags;
	339	__u32 uidx;
	340	__u32 bfreg_index;
	341	union {
	342	__aligned_u64 sq_buf_addr;
	343	__aligned_u64 access_key;
	344	};
	345	__u32 ece_options;
	346	struct mlx5_ib_create_qp_dci_streams dci_streams;
	347	__u16 reserved;
	348	};
	349
	350	/* RX Hash function flags */
	351	enum mlx5_rx_hash_function_flags {
	352	MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
	353	};
	354
	355	/*
	356	* RX Hash flags, these flags allows to set which incoming packet's field should
	357	* participates in RX Hash. Each flag represent certain packet's field,
	358	* when the flag is set the field that is represented by the flag will
	359	* participate in RX Hash calculation.
	360	* Note: IPV4 and IPV6 flags can't be enabled together on the same QP
	361	* and TCP and UDP flags can't be enabled together on the same QP.
	362	*/
	363	enum mlx5_rx_hash_fields {
	364	MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
	365	MLX5_RX_HASH_DST_IPV4 = 1 << 1,
	366	MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
	367	MLX5_RX_HASH_DST_IPV6 = 1 << 3,
	368	MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
	369	MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
	370	MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
	371	MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
	372	MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
	373	/* Save bits for future fields */
	374	MLX5_RX_HASH_INNER = (1UL << 31),
	375	};
	376
	377	struct mlx5_ib_create_qp_rss {
	378	__aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	379	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	380	__u8 rx_key_len; /* valid only for Toeplitz */
	381	__u8 reserved[6];
	382	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	383	__u32 comp_mask;
	384	__u32 flags;
	385	};
	386
	387	enum mlx5_ib_create_qp_resp_mask {
	388	MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
	389	MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
	390	MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
	391	MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
	392	MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4,
	393	};
	394
	395	struct mlx5_ib_create_qp_resp {
	396	__u32 bfreg_index;
	397	__u32 ece_options;
	398	__u32 comp_mask;
	399	__u32 tirn;
	400	__u32 tisn;
	401	__u32 rqn;
	402	__u32 sqn;
	403	__u32 reserved1;
	404	__u64 tir_icm_addr;
	405	};
	406
	407	struct mlx5_ib_alloc_mw {
	408	__u32 comp_mask;
	409	__u8 num_klms;
	410	__u8 reserved1;
	411	__u16 reserved2;
	412	};
	413
	414	enum mlx5_ib_create_wq_mask {
	415	MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
	416	};
	417
	418	struct mlx5_ib_create_wq {
	419	__aligned_u64 buf_addr;
	420	__aligned_u64 db_addr;
	421	__u32 rq_wqe_count;
	422	__u32 rq_wqe_shift;
	423	__u32 user_index;
	424	__u32 flags;
	425	__u32 comp_mask;
	426	__u32 single_stride_log_num_of_bytes;
	427	__u32 single_wqe_log_num_of_strides;
	428	__u32 two_byte_shift_en;
	429	};
	430
	431	struct mlx5_ib_create_ah_resp {
	432	__u32 response_length;
	433	__u8 dmac[ETH_ALEN];
	434	__u8 reserved[6];
	435	};
	436
	437	struct mlx5_ib_burst_info {
	438	__u32 max_burst_sz;
	439	__u16 typical_pkt_sz;
	440	__u16 reserved;
	441	};
	442
	443	enum mlx5_ib_modify_qp_mask {
	444	MLX5_IB_MODIFY_QP_OOO_DP = 1 << 0,
	445	};
	446
	447	struct mlx5_ib_modify_qp {
	448	__u32 comp_mask;
	449	struct mlx5_ib_burst_info burst_info;
	450	__u32 ece_options;
	451	};
	452
	453	struct mlx5_ib_modify_qp_resp {
	454	__u32 response_length;
	455	__u32 dctn;
	456	__u32 ece_options;
	457	__u32 reserved;
	458	};
	459
	460	struct mlx5_ib_create_wq_resp {
	461	__u32 response_length;
	462	__u32 reserved;
	463	};
	464
	465	struct mlx5_ib_create_rwq_ind_tbl_resp {
	466	__u32 response_length;
	467	__u32 reserved;
	468	};
	469
	470	struct mlx5_ib_modify_wq {
	471	__u32 comp_mask;
	472	__u32 reserved;
	473	};
	474
	475	struct mlx5_ib_clock_info {
	476	__u32 sign;
	477	__u32 resv;
	478	__aligned_u64 nsec;
	479	__aligned_u64 cycles;
	480	__aligned_u64 frac;
	481	__u32 mult;
	482	__u32 shift;
	483	__aligned_u64 mask;
	484	__aligned_u64 overflow_period;
	485	};
	486
	487	enum mlx5_ib_mmap_cmd {
	488	MLX5_IB_MMAP_REGULAR_PAGE = 0,
	489	MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
	490	MLX5_IB_MMAP_WC_PAGE = 2,
	491	MLX5_IB_MMAP_NC_PAGE = 3,
	492	/* 5 is chosen in order to be compatible with old versions of libmlx5 */
	493	MLX5_IB_MMAP_CORE_CLOCK = 5,
	494	MLX5_IB_MMAP_ALLOC_WC = 6,
	495	MLX5_IB_MMAP_CLOCK_INFO = 7,
	496	MLX5_IB_MMAP_DEVICE_MEM = 8,
	497	};
	498
	499	enum {
	500	MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
	501	};
	502
	503	/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
	504	enum {
	505	MLX5_IB_CLOCK_INFO_V1 = 0,
	506	};
	507
	508	struct mlx5_ib_flow_counters_desc {
	509	__u32 description;
	510	__u32 index;
	511	};
	512
	513	struct mlx5_ib_flow_counters_data {
	514	RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
	515	__u32 ncounters;
	516	__u32 reserved;
	517	};
	518
	519	struct mlx5_ib_create_flow {
	520	__u32 ncounters_data;
	521	__u32 reserved;
	522	/*
	523	* Following are counters data based on ncounters_data, each
	524	* entry in the data[] should match a corresponding counter object
	525	* that was pointed by a counters spec upon the flow creation
	526	*/
	527	struct mlx5_ib_flow_counters_data data[];
	528	};
	529
	530	#endif /* MLX5_ABI_USER_H */