[linux-2.6-block.git] / include / linux / soundwire / sdw_intel.h

/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/* Copyright(c) 2015-17 Intel Corporation. */

#ifndef __SDW_INTEL_H
#define __SDW_INTEL_H

#include <linux/acpi.h>
#include <linux/irqreturn.h>
#include <linux/soundwire/sdw.h>

/*********************************************************************
 * cAVS and ACE1.x definitions
 *********************************************************************/

#define SDW_SHIM_BASE			0x2C000
#define SDW_ALH_BASE			0x2C800
#define SDW_SHIM_BASE_ACE		0x38000
#define SDW_ALH_BASE_ACE		0x24000
#define SDW_LINK_BASE			0x30000
#define SDW_LINK_SIZE			0x10000

/* Intel SHIM Registers Definition */
/* LCAP */
#define SDW_SHIM_LCAP			0x0
#define SDW_SHIM_LCAP_LCOUNT_MASK	GENMASK(2, 0)
#define SDW_SHIM_LCAP_MLCS_MASK		BIT(8)

/* LCTL */
#define SDW_SHIM_LCTL			0x4

#define SDW_SHIM_LCTL_SPA		BIT(0)
#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
#define SDW_SHIM_LCTL_CPA		BIT(8)
#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
#define SDW_SHIM_LCTL_MLCS_MASK		GENMASK(29, 27)
#define SDW_SHIM_MLCS_XTAL_CLK		0x0
#define SDW_SHIM_MLCS_CARDINAL_CLK	0x1
#define SDW_SHIM_MLCS_AUDIO_PLL_CLK	0x2

/* SYNC */
#define SDW_SHIM_SYNC			0xC

#define SDW_SHIM_SYNC_SYNCPRD_VAL_24		(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576	(24576 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4		(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD_VAL_96		(96000 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
#define SDW_SHIM_SYNC_SYNCGO		BIT(24)

/* Control stream capabililities and channel mask */
#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))

/* PCM Stream capabilities */
#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))

#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)

/* PCM Stream Channel Map */
#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))

/* PCM Stream Channel Count */
#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))

#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
#define SDW_SHIM_PCMSYCM_DIR		BIT(15)

/* IO control */
#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))

#define SDW_SHIM_IOCTL_MIF		BIT(0)
#define SDW_SHIM_IOCTL_CO		BIT(1)
#define SDW_SHIM_IOCTL_COE		BIT(2)
#define SDW_SHIM_IOCTL_DO		BIT(3)
#define SDW_SHIM_IOCTL_DOE		BIT(4)
#define SDW_SHIM_IOCTL_BKE		BIT(5)
#define SDW_SHIM_IOCTL_WPDD		BIT(6)
#define SDW_SHIM_IOCTL_CIBD		BIT(8)
#define SDW_SHIM_IOCTL_DIBD		BIT(9)

/* Wake Enable*/
#define SDW_SHIM_WAKEEN			0x190

#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)

/* Wake Status */
#define SDW_SHIM_WAKESTS		0x192

#define SDW_SHIM_WAKESTS_STATUS		BIT(0)

/* AC Timing control */
#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))

#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
#define SDW_SHIM_CTMCTL_DODS		BIT(1)
#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)

/* Intel ALH Register definitions */
#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
#define SDW_ALH_NUM_STREAMS		64

#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)

/*********************************************************************
 * ACE2.x definitions for SHIM registers - only accessible when the
 * HDAudio extended link LCTL.SPA/CPA = 1.
 *********************************************************************/
/* x variable is link index */
#define SDW_SHIM2_GENERIC_BASE(x)	(0x00030000 + 0x8000 * (x))
#define SDW_IP_BASE(x)			(0x00030100 + 0x8000 * (x))
#define SDW_SHIM2_VS_BASE(x)		(0x00036000 + 0x8000 * (x))

/* SHIM2 Generic Registers */
/* Read-only capabilities */
#define SDW_SHIM2_LECAP			0x00
#define SDW_SHIM2_LECAP_HDS		BIT(0)		/* unset -> Host mode */
#define SDW_SHIM2_LECAP_MLC		GENMASK(3, 1)	/* Number of Lanes */

/* PCM Stream capabilities */
#define SDW_SHIM2_PCMSCAP		0x10
#define SDW_SHIM2_PCMSCAP_ISS		GENMASK(3, 0)	/* Input-only streams */
#define SDW_SHIM2_PCMSCAP_OSS		GENMASK(7, 4)	/* Output-only streams */
#define SDW_SHIM2_PCMSCAP_BSS		GENMASK(12, 8)	/* Bidirectional streams */

/* Read-only PCM Stream Channel Count, y variable is stream */
#define SDW_SHIM2_PCMSYCHC(y)		(0x14 + (0x4 * (y)))
#define SDW_SHIM2_PCMSYCHC_CS		GENMASK(3, 0)	/* Channels Supported */

/* PCM Stream Channel Map */
#define SDW_SHIM2_PCMSYCHM(y)		(0x16 + (0x4 * (y)))
#define SDW_SHIM2_PCMSYCHM_LCHAN	GENMASK(3, 0)	/* Lowest channel used by the FIFO port */
#define SDW_SHIM2_PCMSYCHM_HCHAN	GENMASK(7, 4)	/* Lowest channel used by the FIFO port */
#define SDW_SHIM2_PCMSYCHM_STRM		GENMASK(13, 8)	/* HDaudio stream tag */
#define SDW_SHIM2_PCMSYCHM_DIR		BIT(15)		/* HDaudio stream direction */

/* SHIM2 vendor-specific registers */
#define SDW_SHIM2_INTEL_VS_LVSCTL	0x04
#define SDW_SHIM2_INTEL_VS_LVSCTL_FCG	BIT(26)
#define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS	GENMASK(29, 27)
#define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD	BIT(30)
#define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD	BIT(31)

#define SDW_SHIM2_MLCS_XTAL_CLK		0x0
#define SDW_SHIM2_MLCS_CARDINAL_CLK	0x1
#define SDW_SHIM2_MLCS_AUDIO_PLL_CLK	0x2
#define SDW_SHIM2_MLCS_MCLK_INPUT_CLK	0x3
#define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4

#define SDW_SHIM2_INTEL_VS_WAKEEN	0x08
#define SDW_SHIM2_INTEL_VS_WAKEEN_PWE	BIT(0)

#define SDW_SHIM2_INTEL_VS_WAKESTS	0x0A
#define SDW_SHIM2_INTEL_VS_WAKEEN_PWS	BIT(0)

#define SDW_SHIM2_INTEL_VS_IOCTL	0x0C
#define SDW_SHIM2_INTEL_VS_IOCTL_MIF	BIT(0)
#define SDW_SHIM2_INTEL_VS_IOCTL_CO	BIT(1)
#define SDW_SHIM2_INTEL_VS_IOCTL_COE	BIT(2)
#define SDW_SHIM2_INTEL_VS_IOCTL_DO	BIT(3)
#define SDW_SHIM2_INTEL_VS_IOCTL_DOE	BIT(4)
#define SDW_SHIM2_INTEL_VS_IOCTL_BKE	BIT(5)
#define SDW_SHIM2_INTEL_VS_IOCTL_WPDD	BIT(6)
#define SDW_SHIM2_INTEL_VS_IOCTL_ODC	BIT(7)
#define SDW_SHIM2_INTEL_VS_IOCTL_CIBD	BIT(8)
#define SDW_SHIM2_INTEL_VS_IOCTL_DIBD	BIT(9)
#define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD	BIT(10)

#define SDW_SHIM2_INTEL_VS_ACTMCTL	0x0E
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE	BIT(0)
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS		BIT(1)
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE	BIT(2)
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS	GENMASK(4, 3)
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE	BIT(5)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS		BIT(6)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS		GENMASK(11, 7)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2	GENMASK(13, 12)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2	BIT(14)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE		BIT(15)

/* ACE3+ Mic privacy control and status register */
#define SDW_SHIM2_INTEL_VS_PVCCS		0x10

/**
 * struct sdw_intel_stream_params_data: configuration passed during
 * the @params_stream callback, e.g. for interaction with DSP
 * firmware.
 */
struct sdw_intel_stream_params_data {
	struct snd_pcm_substream *substream;
	struct snd_soc_dai *dai;
	struct snd_pcm_hw_params *hw_params;
	int link_id;
	int alh_stream_id;
};

/**
 * struct sdw_intel_stream_free_data: configuration passed during
 * the @free_stream callback, e.g. for interaction with DSP
 * firmware.
 */
struct sdw_intel_stream_free_data {
	struct snd_pcm_substream *substream;
	struct snd_soc_dai *dai;
	int link_id;
};

/**
 * struct sdw_intel_ops: Intel audio driver callback ops
 *
 */
struct sdw_intel_ops {
	int (*params_stream)(struct device *dev,
			     struct sdw_intel_stream_params_data *params_data);
	int (*free_stream)(struct device *dev,
			   struct sdw_intel_stream_free_data *free_data);
	int (*trigger)(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai);
};

/**
 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
 * @handle: ACPI controller handle
 * @count: link count found with "sdw-master-count" or "sdw-manager-list" property
 * @link_mask: bit-wise mask listing links enabled by BIOS menu
 *
 * this structure could be expanded to e.g. provide all the _ADR
 * information in case the link_mask is not sufficient to identify
 * platform capabilities.
 */
struct sdw_intel_acpi_info {
	acpi_handle handle;
	int count;
	u32 link_mask;
};

struct sdw_intel_link_dev;

/* Intel clock-stop/pm_runtime quirk definitions */

/*
 * Force the clock to remain on during pm_runtime suspend. This might
 * be needed if Slave devices do not have an alternate clock source or
 * if the latency requirements are very strict.
 */
#define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)

/*
 * Stop the bus during pm_runtime suspend. If set, a complete bus
 * reset and re-enumeration will be performed when the bus
 * restarts. This mode shall not be used if Slave devices can generate
 * in-band wakes.
 */
#define SDW_INTEL_CLK_STOP_TEARDOWN		BIT(1)

/*
 * Stop the bus during pm_suspend if Slaves are not wake capable
 * (e.g. speaker amplifiers). The clock-stop mode is typically
 * slightly higher power than when the IP is completely powered-off.
 */
#define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY	BIT(2)

/*
 * Require a bus reset (and complete re-enumeration) when exiting
 * clock stop modes. This may be needed if the controller power was
 * turned off and all context lost. This quirk shall not be used if a
 * Slave device needs to remain enumerated and keep its context,
 * e.g. to provide the reasons for the wake, report acoustic events or
 * pass a history buffer.
 */
#define SDW_INTEL_CLK_STOP_BUS_RESET		BIT(3)

struct hdac_bus;

/**
 * struct sdw_intel_ctx - context allocated by the controller
 * driver probe
 * @count: link count
 * @mmio_base: mmio base of SoundWire registers, only used to check
 * hardware capabilities after all power dependencies are settled.
 * @link_mask: bit-wise mask listing SoundWire links reported by the
 * Controller
 * @handle: ACPI parent handle
 * @ldev: information for each link (controller-specific and kept
 * opaque here)
 * @link_list: list to handle interrupts across all links
 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
 * @shim_mask: flags to track initialization of SHIM shared registers
 * @shim_base: sdw shim base.
 * @alh_base: sdw alh base.
 * @peripherals: array representing Peripherals exposed across all enabled links
 */
struct sdw_intel_ctx {
	int count;
	void __iomem *mmio_base;
	u32 link_mask;
	acpi_handle handle;
	struct sdw_intel_link_dev **ldev;
	struct list_head link_list;
	struct mutex shim_lock; /* lock for access to shared SHIM registers */
	u32 shim_mask;
	u32 shim_base;
	u32 alh_base;
	struct sdw_peripherals *peripherals;
};

/**
 * struct sdw_intel_res - Soundwire Intel global resource structure,
 * typically populated by the DSP driver
 *
 * @hw_ops: abstraction for platform ops
 * @count: link count
 * @mmio_base: mmio base of SoundWire registers
 * @irq: interrupt number
 * @handle: ACPI parent handle
 * @parent: parent device
 * @ops: callback ops
 * @dev: device implementing hwparams and free callbacks
 * @link_mask: bit-wise mask listing links selected by the DSP driver
 * This mask may be a subset of the one reported by the controller since
 * machine-specific quirks are handled in the DSP driver.
 * @clock_stop_quirks: mask array of possible behaviors requested by the
 * DSP driver. The quirks are common for all links for now.
 * @shim_base: sdw shim base.
 * @alh_base: sdw alh base.
 * @ext: extended HDaudio link support
 * @mic_privacy: ACE version supports microphone privacy
 * @hbus: hdac_bus pointer, needed for power management
 * @eml_lock: mutex protecting shared registers in the HDaudio multi-link
 * space
 */
struct sdw_intel_res {
	const struct sdw_intel_hw_ops *hw_ops;
	int count;
	void __iomem *mmio_base;
	int irq;
	acpi_handle handle;
	struct device *parent;
	const struct sdw_intel_ops *ops;
	struct device *dev;
	u32 link_mask;
	u32 clock_stop_quirks;
	u32 shim_base;
	u32 alh_base;
	bool ext;
	bool mic_privacy;
	struct hdac_bus *hbus;
	struct mutex *eml_lock;
};

/*
 * On Intel platforms, the SoundWire IP has dependencies on power
 * rails shared with the DSP, and the initialization steps are split
 * in three. First an ACPI scan to check what the firmware describes
 * in DSDT tables, then an allocation step (with no hardware
 * configuration but with all the relevant devices created) and last
 * the actual hardware configuration. The final stage is a global
 * interrupt enable which is controlled by the DSP driver. Splitting
 * these phases helps simplify the boot flow and make early decisions
 * on e.g. which machine driver to select (I2S mode, HDaudio or
 * SoundWire).
 */
int sdw_intel_acpi_scan(acpi_handle parent_handle,
			struct sdw_intel_acpi_info *info);

void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);

struct sdw_intel_ctx *
sdw_intel_probe(struct sdw_intel_res *res);

int sdw_intel_startup(struct sdw_intel_ctx *ctx);

void sdw_intel_exit(struct sdw_intel_ctx *ctx);

irqreturn_t sdw_intel_thread(int irq, void *dev_id);

#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE      BIT(1)

struct sdw_intel;

/* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
 * @debugfs_init: initialize all debugfs capabilities
 * @debugfs_exit: close and cleanup debugfs capabilities
 * @get_link_count: fetch link count from hardware registers
 * @register_dai: read all PDI information and register DAIs
 * @check_clock_stop: throw error message if clock is not stopped.
 * @start_bus: normal start
 * @start_bus_after_reset: start after reset
 * @start_bus_after_clock_stop: start after mode0 clock stop
 * @stop_bus: stop all bus
 * @link_power_up: power-up using chip-specific helpers
 * @link_power_down: power-down with chip-specific helpers
 * @shim_check_wake: check if a wake was received
 * @shim_wake: enable/disable in-band wake management
 * @pre_bank_switch: helper for bus management
 * @post_bank_switch: helper for bus management
 * @sync_arm: helper for multi-link synchronization
 * @sync_go_unlocked: helper for multi-link synchronization -
 * shim_lock is assumed to be locked at higher level
 * @sync_go: helper for multi-link synchronization
 * @sync_check_cmdsync_unlocked: helper for multi-link synchronization
 * and bank switch - shim_lock is assumed to be locked at higher level
 * @program_sdi: helper for codec command/control based on dev_num
 */
struct sdw_intel_hw_ops {
	void (*debugfs_init)(struct sdw_intel *sdw);
	void (*debugfs_exit)(struct sdw_intel *sdw);

	int (*get_link_count)(struct sdw_intel *sdw);

	int (*register_dai)(struct sdw_intel *sdw);

	void (*check_clock_stop)(struct sdw_intel *sdw);
	int (*start_bus)(struct sdw_intel *sdw);
	int (*start_bus_after_reset)(struct sdw_intel *sdw);
	int (*start_bus_after_clock_stop)(struct sdw_intel *sdw);
	int (*stop_bus)(struct sdw_intel *sdw, bool clock_stop);

	int (*link_power_up)(struct sdw_intel *sdw);
	int (*link_power_down)(struct sdw_intel *sdw);

	int  (*shim_check_wake)(struct sdw_intel *sdw);
	void (*shim_wake)(struct sdw_intel *sdw, bool wake_enable);

	int (*pre_bank_switch)(struct sdw_intel *sdw);
	int (*post_bank_switch)(struct sdw_intel *sdw);

	void (*sync_arm)(struct sdw_intel *sdw);
	int (*sync_go_unlocked)(struct sdw_intel *sdw);
	int (*sync_go)(struct sdw_intel *sdw);
	bool (*sync_check_cmdsync_unlocked)(struct sdw_intel *sdw);

	void (*program_sdi)(struct sdw_intel *sdw, int dev_num);

	int (*bpt_send_async)(struct sdw_intel *sdw, struct sdw_slave *slave,
			      struct sdw_bpt_msg *msg);
	int (*bpt_wait)(struct sdw_intel *sdw, struct sdw_slave *slave, struct sdw_bpt_msg *msg);
};

extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops;
extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops;

/*
 * IDA min selected to allow for 5 unconstrained devices per link,
 * and 6 system-unique Device Numbers for wake-capable devices.
 */

#define SDW_INTEL_DEV_NUM_IDA_MIN           6

/*
 * Max number of links supported in hardware
 */
#define SDW_INTEL_MAX_LINKS                5

#endif
Commit	Line	Data
	1	/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
	2	/* Copyright(c) 2015-17 Intel Corporation. */
	3
	4	#ifndef __SDW_INTEL_H
	5	#define __SDW_INTEL_H
	6
	7	#include <linux/acpi.h>
	8	#include <linux/irqreturn.h>
	9	#include <linux/soundwire/sdw.h>
	10
	11	/*********************************************************************
	12	* cAVS and ACE1.x definitions
	13	*********************************************************************/
	14
	15	#define SDW_SHIM_BASE 0x2C000
	16	#define SDW_ALH_BASE 0x2C800
	17	#define SDW_SHIM_BASE_ACE 0x38000
	18	#define SDW_ALH_BASE_ACE 0x24000
	19	#define SDW_LINK_BASE 0x30000
	20	#define SDW_LINK_SIZE 0x10000
	21
	22	/* Intel SHIM Registers Definition */
	23	/* LCAP */
	24	#define SDW_SHIM_LCAP 0x0
	25	#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
	26	#define SDW_SHIM_LCAP_MLCS_MASK BIT(8)
	27
	28	/* LCTL */
	29	#define SDW_SHIM_LCTL 0x4
	30
	31	#define SDW_SHIM_LCTL_SPA BIT(0)
	32	#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
	33	#define SDW_SHIM_LCTL_CPA BIT(8)
	34	#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
	35	#define SDW_SHIM_LCTL_MLCS_MASK GENMASK(29, 27)
	36	#define SDW_SHIM_MLCS_XTAL_CLK 0x0
	37	#define SDW_SHIM_MLCS_CARDINAL_CLK 0x1
	38	#define SDW_SHIM_MLCS_AUDIO_PLL_CLK 0x2
	39
	40	/* SYNC */
	41	#define SDW_SHIM_SYNC 0xC
	42
	43	#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
	44	#define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 (24576 / SDW_CADENCE_GSYNC_KHZ - 1)
	45	#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
	46	#define SDW_SHIM_SYNC_SYNCPRD_VAL_96 (96000 / SDW_CADENCE_GSYNC_KHZ - 1)
	47	#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
	48	#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
	49	#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
	50	#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
	51	#define SDW_SHIM_SYNC_SYNCGO BIT(24)
	52
	53	/* Control stream capabililities and channel mask */
	54	#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
	55	#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
	56	#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
	57	#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
	58	#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
	59
	60	/* PCM Stream capabilities */
	61	#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
	62
	63	#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
	64	#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
	65	#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
	66
	67	/* PCM Stream Channel Map */
	68	#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
	69
	70	/* PCM Stream Channel Count */
	71	#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
	72
	73	#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
	74	#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
	75	#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
	76	#define SDW_SHIM_PCMSYCM_DIR BIT(15)
	77
	78	/* IO control */
	79	#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
	80
	81	#define SDW_SHIM_IOCTL_MIF BIT(0)
	82	#define SDW_SHIM_IOCTL_CO BIT(1)
	83	#define SDW_SHIM_IOCTL_COE BIT(2)
	84	#define SDW_SHIM_IOCTL_DO BIT(3)
	85	#define SDW_SHIM_IOCTL_DOE BIT(4)
	86	#define SDW_SHIM_IOCTL_BKE BIT(5)
	87	#define SDW_SHIM_IOCTL_WPDD BIT(6)
	88	#define SDW_SHIM_IOCTL_CIBD BIT(8)
	89	#define SDW_SHIM_IOCTL_DIBD BIT(9)
	90
	91	/* Wake Enable*/
	92	#define SDW_SHIM_WAKEEN 0x190
	93
	94	#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
	95
	96	/* Wake Status */
	97	#define SDW_SHIM_WAKESTS 0x192
	98
	99	#define SDW_SHIM_WAKESTS_STATUS BIT(0)
	100
	101	/* AC Timing control */
	102	#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
	103
	104	#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
	105	#define SDW_SHIM_CTMCTL_DODS BIT(1)
	106	#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
	107
	108	/* Intel ALH Register definitions */
	109	#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
	110	#define SDW_ALH_NUM_STREAMS 64
	111
	112	#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
	113	#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
	114	#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
	115
	116	/*********************************************************************
	117	* ACE2.x definitions for SHIM registers - only accessible when the
	118	* HDAudio extended link LCTL.SPA/CPA = 1.
	119	*********************************************************************/
	120	/* x variable is link index */
	121	#define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x))
	122	#define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x))
	123	#define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x))
	124
	125	/* SHIM2 Generic Registers */
	126	/* Read-only capabilities */
	127	#define SDW_SHIM2_LECAP 0x00
	128	#define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */
	129	#define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */
	130
	131	/* PCM Stream capabilities */
	132	#define SDW_SHIM2_PCMSCAP 0x10
	133	#define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */
	134	#define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */
	135	#define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */
	136
	137	/* Read-only PCM Stream Channel Count, y variable is stream */
	138	#define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y)))
	139	#define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */
	140
	141	/* PCM Stream Channel Map */
	142	#define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y)))
	143	#define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */
	144	#define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */
	145	#define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */
	146	#define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */
	147
	148	/* SHIM2 vendor-specific registers */
	149	#define SDW_SHIM2_INTEL_VS_LVSCTL 0x04
	150	#define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26)
	151	#define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27)
	152	#define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30)
	153	#define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31)
	154
	155	#define SDW_SHIM2_MLCS_XTAL_CLK 0x0
	156	#define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1
	157	#define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2
	158	#define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3
	159	#define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4
	160
	161	#define SDW_SHIM2_INTEL_VS_WAKEEN 0x08
	162	#define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0)
	163
	164	#define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A
	165	#define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0)
	166
	167	#define SDW_SHIM2_INTEL_VS_IOCTL 0x0C
	168	#define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0)
	169	#define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1)
	170	#define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2)
	171	#define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3)
	172	#define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4)
	173	#define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5)
	174	#define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6)
	175	#define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7)
	176	#define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8)
	177	#define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9)
	178	#define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10)
	179
	180	#define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E
	181	#define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0)
	182	#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1)
	183	#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
	184	#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
	185	#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
	186	#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS BIT(6)
	187	#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS GENMASK(11, 7)
	188	#define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 GENMASK(13, 12)
	189	#define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14)
	190	#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15)
	191
	192	/* ACE3+ Mic privacy control and status register */
	193	#define SDW_SHIM2_INTEL_VS_PVCCS 0x10
	194
	195	/**
	196	* struct sdw_intel_stream_params_data: configuration passed during
	197	* the @params_stream callback, e.g. for interaction with DSP
	198	* firmware.
	199	*/
	200	struct sdw_intel_stream_params_data {
	201	struct snd_pcm_substream *substream;
	202	struct snd_soc_dai *dai;
	203	struct snd_pcm_hw_params *hw_params;
	204	int link_id;
	205	int alh_stream_id;
	206	};
	207
	208	/**
	209	* struct sdw_intel_stream_free_data: configuration passed during
	210	* the @free_stream callback, e.g. for interaction with DSP
	211	* firmware.
	212	*/
	213	struct sdw_intel_stream_free_data {
	214	struct snd_pcm_substream *substream;
	215	struct snd_soc_dai *dai;
	216	int link_id;
	217	};
	218
	219	/**
	220	* struct sdw_intel_ops: Intel audio driver callback ops
	221	*
	222	*/
	223	struct sdw_intel_ops {
	224	int (params_stream)(struct device dev,
	225	struct sdw_intel_stream_params_data *params_data);
	226	int (free_stream)(struct device dev,
	227	struct sdw_intel_stream_free_data *free_data);
	228	int (trigger)(struct snd_pcm_substream substream, int cmd, struct snd_soc_dai *dai);
	229	};
	230
	231	/**
	232	* struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
	233	* @handle: ACPI controller handle
	234	* @count: link count found with "sdw-master-count" or "sdw-manager-list" property
	235	* @link_mask: bit-wise mask listing links enabled by BIOS menu
	236	*
	237	* this structure could be expanded to e.g. provide all the _ADR
	238	* information in case the link_mask is not sufficient to identify
	239	* platform capabilities.
	240	*/
	241	struct sdw_intel_acpi_info {
	242	acpi_handle handle;
	243	int count;
	244	u32 link_mask;
	245	};
	246
	247	struct sdw_intel_link_dev;
	248
	249	/* Intel clock-stop/pm_runtime quirk definitions */
	250
	251	/*
	252	* Force the clock to remain on during pm_runtime suspend. This might
	253	* be needed if Slave devices do not have an alternate clock source or
	254	* if the latency requirements are very strict.
	255	*/
	256	#define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
	257
	258	/*
	259	* Stop the bus during pm_runtime suspend. If set, a complete bus
	260	* reset and re-enumeration will be performed when the bus
	261	* restarts. This mode shall not be used if Slave devices can generate
	262	* in-band wakes.
	263	*/
	264	#define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
	265
	266	/*
	267	* Stop the bus during pm_suspend if Slaves are not wake capable
	268	* (e.g. speaker amplifiers). The clock-stop mode is typically
	269	* slightly higher power than when the IP is completely powered-off.
	270	*/
	271	#define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
	272
	273	/*
	274	* Require a bus reset (and complete re-enumeration) when exiting
	275	* clock stop modes. This may be needed if the controller power was
	276	* turned off and all context lost. This quirk shall not be used if a
	277	* Slave device needs to remain enumerated and keep its context,
	278	* e.g. to provide the reasons for the wake, report acoustic events or
	279	* pass a history buffer.
	280	*/
	281	#define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
	282
	283	struct hdac_bus;
	284
	285	/**
	286	* struct sdw_intel_ctx - context allocated by the controller
	287	* driver probe
	288	* @count: link count
	289	* @mmio_base: mmio base of SoundWire registers, only used to check
	290	* hardware capabilities after all power dependencies are settled.
	291	* @link_mask: bit-wise mask listing SoundWire links reported by the
	292	* Controller
	293	* @handle: ACPI parent handle
	294	* @ldev: information for each link (controller-specific and kept
	295	* opaque here)
	296	* @link_list: list to handle interrupts across all links
	297	* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
	298	* @shim_mask: flags to track initialization of SHIM shared registers
	299	* @shim_base: sdw shim base.
	300	* @alh_base: sdw alh base.
	301	* @peripherals: array representing Peripherals exposed across all enabled links
	302	*/
	303	struct sdw_intel_ctx {
	304	int count;
	305	void __iomem *mmio_base;
	306	u32 link_mask;
	307	acpi_handle handle;
	308	struct sdw_intel_link_dev **ldev;
	309	struct list_head link_list;
	310	struct mutex shim_lock; /* lock for access to shared SHIM registers */
	311	u32 shim_mask;
	312	u32 shim_base;
	313	u32 alh_base;
	314	struct sdw_peripherals *peripherals;
	315	};
	316
	317	/**
	318	* struct sdw_intel_res - Soundwire Intel global resource structure,
	319	* typically populated by the DSP driver
	320	*
	321	* @hw_ops: abstraction for platform ops
	322	* @count: link count
	323	* @mmio_base: mmio base of SoundWire registers
	324	* @irq: interrupt number
	325	* @handle: ACPI parent handle
	326	* @parent: parent device
	327	* @ops: callback ops
	328	* @dev: device implementing hwparams and free callbacks
	329	* @link_mask: bit-wise mask listing links selected by the DSP driver
	330	* This mask may be a subset of the one reported by the controller since
	331	* machine-specific quirks are handled in the DSP driver.
	332	* @clock_stop_quirks: mask array of possible behaviors requested by the
	333	* DSP driver. The quirks are common for all links for now.
	334	* @shim_base: sdw shim base.
	335	* @alh_base: sdw alh base.
	336	* @ext: extended HDaudio link support
	337	* @mic_privacy: ACE version supports microphone privacy
	338	* @hbus: hdac_bus pointer, needed for power management
	339	* @eml_lock: mutex protecting shared registers in the HDaudio multi-link
	340	* space
	341	*/
	342	struct sdw_intel_res {
	343	const struct sdw_intel_hw_ops *hw_ops;
	344	int count;
	345	void __iomem *mmio_base;
	346	int irq;
	347	acpi_handle handle;
	348	struct device *parent;
	349	const struct sdw_intel_ops *ops;
	350	struct device *dev;
	351	u32 link_mask;
	352	u32 clock_stop_quirks;
	353	u32 shim_base;
	354	u32 alh_base;
	355	bool ext;
	356	bool mic_privacy;
	357	struct hdac_bus *hbus;
	358	struct mutex *eml_lock;
	359	};
	360
	361	/*
	362	* On Intel platforms, the SoundWire IP has dependencies on power
	363	* rails shared with the DSP, and the initialization steps are split
	364	* in three. First an ACPI scan to check what the firmware describes
	365	* in DSDT tables, then an allocation step (with no hardware
	366	* configuration but with all the relevant devices created) and last
	367	* the actual hardware configuration. The final stage is a global
	368	* interrupt enable which is controlled by the DSP driver. Splitting
	369	* these phases helps simplify the boot flow and make early decisions
	370	* on e.g. which machine driver to select (I2S mode, HDaudio or
	371	* SoundWire).
	372	*/
	373	int sdw_intel_acpi_scan(acpi_handle parent_handle,
	374	struct sdw_intel_acpi_info *info);
	375
	376	void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
	377
	378	struct sdw_intel_ctx *
	379	sdw_intel_probe(struct sdw_intel_res *res);
	380
	381	int sdw_intel_startup(struct sdw_intel_ctx *ctx);
	382
	383	void sdw_intel_exit(struct sdw_intel_ctx *ctx);
	384
	385	irqreturn_t sdw_intel_thread(int irq, void *dev_id);
	386
	387	#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
	388
	389	struct sdw_intel;
	390
	391	/* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
	392	* @debugfs_init: initialize all debugfs capabilities
	393	* @debugfs_exit: close and cleanup debugfs capabilities
	394	* @get_link_count: fetch link count from hardware registers
	395	* @register_dai: read all PDI information and register DAIs
	396	* @check_clock_stop: throw error message if clock is not stopped.
	397	* @start_bus: normal start
	398	* @start_bus_after_reset: start after reset
	399	* @start_bus_after_clock_stop: start after mode0 clock stop
	400	* @stop_bus: stop all bus
	401	* @link_power_up: power-up using chip-specific helpers
	402	* @link_power_down: power-down with chip-specific helpers
	403	* @shim_check_wake: check if a wake was received
	404	* @shim_wake: enable/disable in-band wake management
	405	* @pre_bank_switch: helper for bus management
	406	* @post_bank_switch: helper for bus management
	407	* @sync_arm: helper for multi-link synchronization
	408	* @sync_go_unlocked: helper for multi-link synchronization -
	409	* shim_lock is assumed to be locked at higher level
	410	* @sync_go: helper for multi-link synchronization
	411	* @sync_check_cmdsync_unlocked: helper for multi-link synchronization
	412	* and bank switch - shim_lock is assumed to be locked at higher level
	413	* @program_sdi: helper for codec command/control based on dev_num
	414	*/
	415	struct sdw_intel_hw_ops {
	416	void (debugfs_init)(struct sdw_intel sdw);
	417	void (debugfs_exit)(struct sdw_intel sdw);
	418
	419	int (get_link_count)(struct sdw_intel sdw);
	420
	421	int (register_dai)(struct sdw_intel sdw);
	422
	423	void (check_clock_stop)(struct sdw_intel sdw);
	424	int (start_bus)(struct sdw_intel sdw);
	425	int (start_bus_after_reset)(struct sdw_intel sdw);
	426	int (start_bus_after_clock_stop)(struct sdw_intel sdw);
	427	int (stop_bus)(struct sdw_intel sdw, bool clock_stop);
	428
	429	int (link_power_up)(struct sdw_intel sdw);
	430	int (link_power_down)(struct sdw_intel sdw);
	431
	432	int (shim_check_wake)(struct sdw_intel sdw);
	433	void (shim_wake)(struct sdw_intel sdw, bool wake_enable);
	434
	435	int (pre_bank_switch)(struct sdw_intel sdw);
	436	int (post_bank_switch)(struct sdw_intel sdw);
	437
	438	void (sync_arm)(struct sdw_intel sdw);
	439	int (sync_go_unlocked)(struct sdw_intel sdw);
	440	int (sync_go)(struct sdw_intel sdw);
	441	bool (sync_check_cmdsync_unlocked)(struct sdw_intel sdw);
	442
	443	void (program_sdi)(struct sdw_intel sdw, int dev_num);
	444
	445	int (bpt_send_async)(struct sdw_intel sdw, struct sdw_slave *slave,
	446	struct sdw_bpt_msg *msg);
	447	int (bpt_wait)(struct sdw_intel sdw, struct sdw_slave slave, struct sdw_bpt_msg msg);
	448	};
	449
	450	extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops;
	451	extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops;
	452
	453	/*
	454	* IDA min selected to allow for 5 unconstrained devices per link,
	455	* and 6 system-unique Device Numbers for wake-capable devices.
	456	*/
	457
	458	#define SDW_INTEL_DEV_NUM_IDA_MIN 6
	459
	460	/*
	461	* Max number of links supported in hardware
	462	*/
	463	#define SDW_INTEL_MAX_LINKS 5
	464
	465	#endif