[linux-block.git] / include / linux / platform_data / ti-sysc.h

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __TI_SYSC_DATA_H__
#define __TI_SYSC_DATA_H__

enum ti_sysc_module_type {
	TI_SYSC_OMAP2,
	TI_SYSC_OMAP2_TIMER,
	TI_SYSC_OMAP3_SHAM,
	TI_SYSC_OMAP3_AES,
	TI_SYSC_OMAP4,
	TI_SYSC_OMAP4_TIMER,
	TI_SYSC_OMAP4_SIMPLE,
	TI_SYSC_OMAP34XX_SR,
	TI_SYSC_OMAP36XX_SR,
	TI_SYSC_OMAP4_SR,
	TI_SYSC_OMAP4_MCASP,
	TI_SYSC_OMAP4_USB_HOST_FS,
	TI_SYSC_DRA7_MCAN,
	TI_SYSC_PRUSS,
};

struct ti_sysc_cookie {
	void *data;
	void *clkdm;
};

/**
 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
 * @midle_shift: Offset of the midle bit
 * @clkact_shift: Offset of the clockactivity bit
 * @sidle_shift: Offset of the sidle bit
 * @enwkup_shift: Offset of the enawakeup bit
 * @srst_shift: Offset of the softreset bit
 * @autoidle_shift: Offset of the autoidle bit
 * @dmadisable_shift: Offset of the dmadisable bit
 * @emufree_shift; Offset of the emufree bit
 *
 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
 * feature is not available.
 */
struct sysc_regbits {
	s8 midle_shift;
	s8 clkact_shift;
	s8 sidle_shift;
	s8 enwkup_shift;
	s8 srst_shift;
	s8 autoidle_shift;
	s8 dmadisable_shift;
	s8 emufree_shift;
};

#define SYSC_MODULE_QUIRK_OTG		BIT(30)
#define SYSC_QUIRK_RESET_ON_CTX_LOST	BIT(29)
#define SYSC_QUIRK_REINIT_ON_CTX_LOST	BIT(28)
#define SYSC_QUIRK_REINIT_ON_RESUME	BIT(27)
#define SYSC_QUIRK_GPMC_DEBUG		BIT(26)
#define SYSC_MODULE_QUIRK_ENA_RESETDONE	BIT(25)
#define SYSC_MODULE_QUIRK_PRUSS		BIT(24)
#define SYSC_MODULE_QUIRK_DSS_RESET	BIT(23)
#define SYSC_MODULE_QUIRK_RTC_UNLOCK	BIT(22)
#define SYSC_QUIRK_CLKDM_NOAUTO		BIT(21)
#define SYSC_QUIRK_FORCE_MSTANDBY	BIT(20)
#define SYSC_MODULE_QUIRK_AESS		BIT(19)
#define SYSC_MODULE_QUIRK_SGX		BIT(18)
#define SYSC_MODULE_QUIRK_HDQ1W		BIT(17)
#define SYSC_MODULE_QUIRK_I2C		BIT(16)
#define SYSC_MODULE_QUIRK_WDT		BIT(15)
#define SYSS_QUIRK_RESETDONE_INVERTED	BIT(14)
#define SYSC_QUIRK_SWSUP_MSTANDBY	BIT(13)
#define SYSC_QUIRK_SWSUP_SIDLE_ACT	BIT(12)
#define SYSC_QUIRK_SWSUP_SIDLE		BIT(11)
#define SYSC_QUIRK_EXT_OPT_CLOCK	BIT(10)
#define SYSC_QUIRK_RESET_STATUS		BIT(8)
#define SYSC_QUIRK_NO_IDLE		BIT(7)
#define SYSC_QUIRK_NO_IDLE_ON_INIT	BIT(6)
#define SYSC_QUIRK_NO_RESET_ON_INIT	BIT(5)
#define SYSC_QUIRK_OPT_CLKS_NEEDED	BIT(4)
#define SYSC_QUIRK_OPT_CLKS_IN_RESET	BIT(3)
#define SYSC_QUIRK_16BIT		BIT(2)
#define SYSC_QUIRK_UNCACHED		BIT(1)
#define SYSC_QUIRK_USE_CLOCKACT		BIT(0)

#define SYSC_NR_IDLEMODES		4

/**
 * struct sysc_capabilities - capabilities for an interconnect target module
 * @type: sysc type identifier for the module
 * @sysc_mask: bitmask of supported SYSCONFIG register bits
 * @regbits: bitmask of SYSCONFIG register bits
 * @mod_quirks: bitmask of module specific quirks
 */
struct sysc_capabilities {
	const enum ti_sysc_module_type type;
	const u32 sysc_mask;
	const struct sysc_regbits *regbits;
	const u32 mod_quirks;
};

/**
 * struct sysc_config - configuration for an interconnect target module
 * @sysc_val: configured value for sysc register
 * @syss_mask: configured mask value for SYSSTATUS register
 * @midlemodes: bitmask of supported master idle modes
 * @sidlemodes: bitmask of supported slave idle modes
 * @srst_udelay: optional delay needed after OCP soft reset
 * @quirks: bitmask of enabled quirks
 */
struct sysc_config {
	u32 sysc_val;
	u32 syss_mask;
	u8 midlemodes;
	u8 sidlemodes;
	u8 srst_udelay;
	u32 quirks;
};

enum sysc_registers {
	SYSC_REVISION,
	SYSC_SYSCONFIG,
	SYSC_SYSSTATUS,
	SYSC_MAX_REGS,
};

/**
 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
 * @name: legacy "ti,hwmods" module name
 * @module_pa: physical address of the interconnect target module
 * @module_size: size of the interconnect target module
 * @offsets: array of register offsets as listed in enum sysc_registers
 * @nr_offsets: number of registers
 * @cap: interconnect target module capabilities
 * @cfg: interconnect target module configuration
 *
 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
 * based on device tree data parsed by ti-sysc driver.
 */
struct ti_sysc_module_data {
	const char *name;
	u64 module_pa;
	u32 module_size;
	int *offsets;
	int nr_offsets;
	const struct sysc_capabilities *cap;
	struct sysc_config *cfg;
};

struct device;
struct clk;

struct ti_sysc_platform_data {
	struct of_dev_auxdata *auxdata;
	bool (*soc_type_gp)(void);
	int (*init_clockdomain)(struct device *dev, struct clk *fck,
				struct clk *ick, struct ti_sysc_cookie *cookie);
	void (*clkdm_deny_idle)(struct device *dev,
				const struct ti_sysc_cookie *cookie);
	void (*clkdm_allow_idle)(struct device *dev,
				 const struct ti_sysc_cookie *cookie);
	int (*init_module)(struct device *dev,
			   const struct ti_sysc_module_data *data,
			   struct ti_sysc_cookie *cookie);
	int (*enable_module)(struct device *dev,
			     const struct ti_sysc_cookie *cookie);
	int (*idle_module)(struct device *dev,
			   const struct ti_sysc_cookie *cookie);
	int (*shutdown_module)(struct device *dev,
			       const struct ti_sysc_cookie *cookie);
};

#endif	/* __TI_SYSC_DATA_H__ */
Commit	Line	Data
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2
	3	#ifndef __TI_SYSC_DATA_H__
	4	#define __TI_SYSC_DATA_H__
	5
	6	enum ti_sysc_module_type {
	7	TI_SYSC_OMAP2,
	8	TI_SYSC_OMAP2_TIMER,
	9	TI_SYSC_OMAP3_SHAM,
	10	TI_SYSC_OMAP3_AES,
	11	TI_SYSC_OMAP4,
	12	TI_SYSC_OMAP4_TIMER,
	13	TI_SYSC_OMAP4_SIMPLE,
	14	TI_SYSC_OMAP34XX_SR,
	15	TI_SYSC_OMAP36XX_SR,
	16	TI_SYSC_OMAP4_SR,
	17	TI_SYSC_OMAP4_MCASP,
	18	TI_SYSC_OMAP4_USB_HOST_FS,
	19	TI_SYSC_DRA7_MCAN,
	20	TI_SYSC_PRUSS,
	21	};
	22
	23	struct ti_sysc_cookie {
	24	void *data;
	25	void *clkdm;
	26	};
	27
	28	/**
	29	* struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
	30	* @midle_shift: Offset of the midle bit
	31	* @clkact_shift: Offset of the clockactivity bit
	32	* @sidle_shift: Offset of the sidle bit
	33	* @enwkup_shift: Offset of the enawakeup bit
	34	* @srst_shift: Offset of the softreset bit
	35	* @autoidle_shift: Offset of the autoidle bit
	36	* @dmadisable_shift: Offset of the dmadisable bit
	37	* @emufree_shift; Offset of the emufree bit
	38	*
	39	* Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
	40	* feature is not available.
	41	*/
	42	struct sysc_regbits {
	43	s8 midle_shift;
	44	s8 clkact_shift;
	45	s8 sidle_shift;
	46	s8 enwkup_shift;
	47	s8 srst_shift;
	48	s8 autoidle_shift;
	49	s8 dmadisable_shift;
	50	s8 emufree_shift;
	51	};
	52
	53	#define SYSC_MODULE_QUIRK_OTG BIT(30)
	54	#define SYSC_QUIRK_RESET_ON_CTX_LOST BIT(29)
	55	#define SYSC_QUIRK_REINIT_ON_CTX_LOST BIT(28)
	56	#define SYSC_QUIRK_REINIT_ON_RESUME BIT(27)
	57	#define SYSC_QUIRK_GPMC_DEBUG BIT(26)
	58	#define SYSC_MODULE_QUIRK_ENA_RESETDONE BIT(25)
	59	#define SYSC_MODULE_QUIRK_PRUSS BIT(24)
	60	#define SYSC_MODULE_QUIRK_DSS_RESET BIT(23)
	61	#define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22)
	62	#define SYSC_QUIRK_CLKDM_NOAUTO BIT(21)
	63	#define SYSC_QUIRK_FORCE_MSTANDBY BIT(20)
	64	#define SYSC_MODULE_QUIRK_AESS BIT(19)
	65	#define SYSC_MODULE_QUIRK_SGX BIT(18)
	66	#define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
	67	#define SYSC_MODULE_QUIRK_I2C BIT(16)
	68	#define SYSC_MODULE_QUIRK_WDT BIT(15)
	69	#define SYSS_QUIRK_RESETDONE_INVERTED BIT(14)
	70	#define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13)
	71	#define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12)
	72	#define SYSC_QUIRK_SWSUP_SIDLE BIT(11)
	73	#define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10)
	74	#define SYSC_QUIRK_RESET_STATUS BIT(8)
	75	#define SYSC_QUIRK_NO_IDLE BIT(7)
	76	#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
	77	#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
	78	#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
	79	#define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3)
	80	#define SYSC_QUIRK_16BIT BIT(2)
	81	#define SYSC_QUIRK_UNCACHED BIT(1)
	82	#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
	83
	84	#define SYSC_NR_IDLEMODES 4
	85
	86	/**
	87	* struct sysc_capabilities - capabilities for an interconnect target module
	88	* @type: sysc type identifier for the module
	89	* @sysc_mask: bitmask of supported SYSCONFIG register bits
	90	* @regbits: bitmask of SYSCONFIG register bits
	91	* @mod_quirks: bitmask of module specific quirks
	92	*/
	93	struct sysc_capabilities {
	94	const enum ti_sysc_module_type type;
	95	const u32 sysc_mask;
	96	const struct sysc_regbits *regbits;
	97	const u32 mod_quirks;
	98	};
	99
	100	/**
	101	* struct sysc_config - configuration for an interconnect target module
	102	* @sysc_val: configured value for sysc register
	103	* @syss_mask: configured mask value for SYSSTATUS register
	104	* @midlemodes: bitmask of supported master idle modes
	105	* @sidlemodes: bitmask of supported slave idle modes
	106	* @srst_udelay: optional delay needed after OCP soft reset
	107	* @quirks: bitmask of enabled quirks
	108	*/
	109	struct sysc_config {
	110	u32 sysc_val;
	111	u32 syss_mask;
	112	u8 midlemodes;
	113	u8 sidlemodes;
	114	u8 srst_udelay;
	115	u32 quirks;
	116	};
	117
	118	enum sysc_registers {
	119	SYSC_REVISION,
	120	SYSC_SYSCONFIG,
	121	SYSC_SYSSTATUS,
	122	SYSC_MAX_REGS,
	123	};
	124
	125	/**
	126	* struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
	127	* @name: legacy "ti,hwmods" module name
	128	* @module_pa: physical address of the interconnect target module
	129	* @module_size: size of the interconnect target module
	130	* @offsets: array of register offsets as listed in enum sysc_registers
	131	* @nr_offsets: number of registers
	132	* @cap: interconnect target module capabilities
	133	* @cfg: interconnect target module configuration
	134	*
	135	* This data is enough to allocate a new struct omap_hwmod_class_sysconfig
	136	* based on device tree data parsed by ti-sysc driver.
	137	*/
	138	struct ti_sysc_module_data {
	139	const char *name;
	140	u64 module_pa;
	141	u32 module_size;
	142	int *offsets;
	143	int nr_offsets;
	144	const struct sysc_capabilities *cap;
	145	struct sysc_config *cfg;
	146	};
	147
	148	struct device;
	149	struct clk;
	150
	151	struct ti_sysc_platform_data {
	152	struct of_dev_auxdata *auxdata;
	153	bool (*soc_type_gp)(void);
	154	int (init_clockdomain)(struct device dev, struct clk *fck,
	155	struct clk ick, struct ti_sysc_cookie cookie);
	156	void (clkdm_deny_idle)(struct device dev,
	157	const struct ti_sysc_cookie *cookie);
	158	void (clkdm_allow_idle)(struct device dev,
	159	const struct ti_sysc_cookie *cookie);
	160	int (init_module)(struct device dev,
	161	const struct ti_sysc_module_data *data,
	162	struct ti_sysc_cookie *cookie);
	163	int (enable_module)(struct device dev,
	164	const struct ti_sysc_cookie *cookie);
	165	int (idle_module)(struct device dev,
	166	const struct ti_sysc_cookie *cookie);
	167	int (shutdown_module)(struct device dev,
	168	const struct ti_sysc_cookie *cookie);
	169	};
	170
	171	#endif /* __TI_SYSC_DATA_H__ */