| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * pci.h |
| 4 | * |
| 5 | * PCI defines and function prototypes |
| 6 | * Copyright 1994, Drew Eckhardt |
| 7 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> |
| 8 | * |
| 9 | * For more information, please consult the following manuals (look at |
| 10 | * http://www.pcisig.com/ for how to get them): |
| 11 | * |
| 12 | * PCI BIOS Specification |
| 13 | * PCI Local Bus Specification |
| 14 | * PCI to PCI Bridge Specification |
| 15 | * PCI System Design Guide |
| 16 | */ |
| 17 | #ifndef LINUX_PCI_H |
| 18 | #define LINUX_PCI_H |
| 19 | |
| 20 | |
| 21 | #include <linux/mod_devicetable.h> |
| 22 | |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/ioport.h> |
| 26 | #include <linux/list.h> |
| 27 | #include <linux/compiler.h> |
| 28 | #include <linux/errno.h> |
| 29 | #include <linux/kobject.h> |
| 30 | #include <linux/atomic.h> |
| 31 | #include <linux/device.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/io.h> |
| 34 | #include <linux/resource_ext.h> |
| 35 | #include <uapi/linux/pci.h> |
| 36 | |
| 37 | #include <linux/pci_ids.h> |
| 38 | |
| 39 | /* |
| 40 | * The PCI interface treats multi-function devices as independent |
| 41 | * devices. The slot/function address of each device is encoded |
| 42 | * in a single byte as follows: |
| 43 | * |
| 44 | * 7:3 = slot |
| 45 | * 2:0 = function |
| 46 | * |
| 47 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. |
| 48 | * In the interest of not exposing interfaces to user-space unnecessarily, |
| 49 | * the following kernel-only defines are being added here. |
| 50 | */ |
| 51 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
| 52 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
| 53 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
| 54 | |
| 55 | /* pci_slot represents a physical slot */ |
| 56 | struct pci_slot { |
| 57 | struct pci_bus *bus; /* Bus this slot is on */ |
| 58 | struct list_head list; /* Node in list of slots */ |
| 59 | struct hotplug_slot *hotplug; /* Hotplug info (move here) */ |
| 60 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
| 61 | struct kobject kobj; |
| 62 | }; |
| 63 | |
| 64 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
| 65 | { |
| 66 | return kobject_name(&slot->kobj); |
| 67 | } |
| 68 | |
| 69 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
| 70 | enum pci_mmap_state { |
| 71 | pci_mmap_io, |
| 72 | pci_mmap_mem |
| 73 | }; |
| 74 | |
| 75 | /* For PCI devices, the region numbers are assigned this way: */ |
| 76 | enum { |
| 77 | /* #0-5: standard PCI resources */ |
| 78 | PCI_STD_RESOURCES, |
| 79 | PCI_STD_RESOURCE_END = 5, |
| 80 | |
| 81 | /* #6: expansion ROM resource */ |
| 82 | PCI_ROM_RESOURCE, |
| 83 | |
| 84 | /* Device-specific resources */ |
| 85 | #ifdef CONFIG_PCI_IOV |
| 86 | PCI_IOV_RESOURCES, |
| 87 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
| 88 | #endif |
| 89 | |
| 90 | /* Resources assigned to buses behind the bridge */ |
| 91 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
| 92 | |
| 93 | PCI_BRIDGE_RESOURCES, |
| 94 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
| 95 | PCI_BRIDGE_RESOURCE_NUM - 1, |
| 96 | |
| 97 | /* Total resources associated with a PCI device */ |
| 98 | PCI_NUM_RESOURCES, |
| 99 | |
| 100 | /* Preserve this for compatibility */ |
| 101 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
| 102 | }; |
| 103 | |
| 104 | /** |
| 105 | * enum pci_interrupt_pin - PCI INTx interrupt values |
| 106 | * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt |
| 107 | * @PCI_INTERRUPT_INTA: PCI INTA pin |
| 108 | * @PCI_INTERRUPT_INTB: PCI INTB pin |
| 109 | * @PCI_INTERRUPT_INTC: PCI INTC pin |
| 110 | * @PCI_INTERRUPT_INTD: PCI INTD pin |
| 111 | * |
| 112 | * Corresponds to values for legacy PCI INTx interrupts, as can be found in the |
| 113 | * PCI_INTERRUPT_PIN register. |
| 114 | */ |
| 115 | enum pci_interrupt_pin { |
| 116 | PCI_INTERRUPT_UNKNOWN, |
| 117 | PCI_INTERRUPT_INTA, |
| 118 | PCI_INTERRUPT_INTB, |
| 119 | PCI_INTERRUPT_INTC, |
| 120 | PCI_INTERRUPT_INTD, |
| 121 | }; |
| 122 | |
| 123 | /* The number of legacy PCI INTx interrupts */ |
| 124 | #define PCI_NUM_INTX 4 |
| 125 | |
| 126 | /* |
| 127 | * pci_power_t values must match the bits in the Capabilities PME_Support |
| 128 | * and Control/Status PowerState fields in the Power Management capability. |
| 129 | */ |
| 130 | typedef int __bitwise pci_power_t; |
| 131 | |
| 132 | #define PCI_D0 ((pci_power_t __force) 0) |
| 133 | #define PCI_D1 ((pci_power_t __force) 1) |
| 134 | #define PCI_D2 ((pci_power_t __force) 2) |
| 135 | #define PCI_D3hot ((pci_power_t __force) 3) |
| 136 | #define PCI_D3cold ((pci_power_t __force) 4) |
| 137 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
| 138 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
| 139 | |
| 140 | /* Remember to update this when the list above changes! */ |
| 141 | extern const char *pci_power_names[]; |
| 142 | |
| 143 | static inline const char *pci_power_name(pci_power_t state) |
| 144 | { |
| 145 | return pci_power_names[1 + (__force int) state]; |
| 146 | } |
| 147 | |
| 148 | #define PCI_PM_D2_DELAY 200 |
| 149 | #define PCI_PM_D3_WAIT 10 |
| 150 | #define PCI_PM_D3COLD_WAIT 100 |
| 151 | #define PCI_PM_BUS_WAIT 50 |
| 152 | |
| 153 | /** |
| 154 | * The pci_channel state describes connectivity between the CPU and |
| 155 | * the PCI device. If some PCI bus between here and the PCI device |
| 156 | * has crashed or locked up, this info is reflected here. |
| 157 | */ |
| 158 | typedef unsigned int __bitwise pci_channel_state_t; |
| 159 | |
| 160 | enum pci_channel_state { |
| 161 | /* I/O channel is in normal state */ |
| 162 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
| 163 | |
| 164 | /* I/O to channel is blocked */ |
| 165 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
| 166 | |
| 167 | /* PCI card is dead */ |
| 168 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
| 169 | }; |
| 170 | |
| 171 | typedef unsigned int __bitwise pcie_reset_state_t; |
| 172 | |
| 173 | enum pcie_reset_state { |
| 174 | /* Reset is NOT asserted (Use to deassert reset) */ |
| 175 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, |
| 176 | |
| 177 | /* Use #PERST to reset PCIe device */ |
| 178 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
| 179 | |
| 180 | /* Use PCIe Hot Reset to reset device */ |
| 181 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
| 182 | }; |
| 183 | |
| 184 | typedef unsigned short __bitwise pci_dev_flags_t; |
| 185 | enum pci_dev_flags { |
| 186 | /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ |
| 187 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
| 188 | /* Device configuration is irrevocably lost if disabled into D3 */ |
| 189 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
| 190 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
| 191 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
| 192 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
| 193 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
| 194 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
| 195 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), |
| 196 | /* Do not use bus resets for device */ |
| 197 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), |
| 198 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
| 199 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), |
| 200 | /* Get VPD from function 0 VPD */ |
| 201 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), |
| 202 | /* A non-root bridge where translation occurs, stop alias search here */ |
| 203 | PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), |
| 204 | /* Do not use FLR even if device advertises PCI_AF_CAP */ |
| 205 | PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), |
| 206 | /* Don't use Relaxed Ordering for TLPs directed at this device */ |
| 207 | PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), |
| 208 | }; |
| 209 | |
| 210 | enum pci_irq_reroute_variant { |
| 211 | INTEL_IRQ_REROUTE_VARIANT = 1, |
| 212 | MAX_IRQ_REROUTE_VARIANTS = 3 |
| 213 | }; |
| 214 | |
| 215 | typedef unsigned short __bitwise pci_bus_flags_t; |
| 216 | enum pci_bus_flags { |
| 217 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
| 218 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
| 219 | PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, |
| 220 | }; |
| 221 | |
| 222 | /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ |
| 223 | enum pcie_link_width { |
| 224 | PCIE_LNK_WIDTH_RESRV = 0x00, |
| 225 | PCIE_LNK_X1 = 0x01, |
| 226 | PCIE_LNK_X2 = 0x02, |
| 227 | PCIE_LNK_X4 = 0x04, |
| 228 | PCIE_LNK_X8 = 0x08, |
| 229 | PCIE_LNK_X12 = 0x0c, |
| 230 | PCIE_LNK_X16 = 0x10, |
| 231 | PCIE_LNK_X32 = 0x20, |
| 232 | PCIE_LNK_WIDTH_UNKNOWN = 0xff, |
| 233 | }; |
| 234 | |
| 235 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
| 236 | enum pci_bus_speed { |
| 237 | PCI_SPEED_33MHz = 0x00, |
| 238 | PCI_SPEED_66MHz = 0x01, |
| 239 | PCI_SPEED_66MHz_PCIX = 0x02, |
| 240 | PCI_SPEED_100MHz_PCIX = 0x03, |
| 241 | PCI_SPEED_133MHz_PCIX = 0x04, |
| 242 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
| 243 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
| 244 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
| 245 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
| 246 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
| 247 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
| 248 | AGP_UNKNOWN = 0x0c, |
| 249 | AGP_1X = 0x0d, |
| 250 | AGP_2X = 0x0e, |
| 251 | AGP_4X = 0x0f, |
| 252 | AGP_8X = 0x10, |
| 253 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
| 254 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
| 255 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
| 256 | PCIE_SPEED_2_5GT = 0x14, |
| 257 | PCIE_SPEED_5_0GT = 0x15, |
| 258 | PCIE_SPEED_8_0GT = 0x16, |
| 259 | PCI_SPEED_UNKNOWN = 0xff, |
| 260 | }; |
| 261 | |
| 262 | struct pci_cap_saved_data { |
| 263 | u16 cap_nr; |
| 264 | bool cap_extended; |
| 265 | unsigned int size; |
| 266 | u32 data[0]; |
| 267 | }; |
| 268 | |
| 269 | struct pci_cap_saved_state { |
| 270 | struct hlist_node next; |
| 271 | struct pci_cap_saved_data cap; |
| 272 | }; |
| 273 | |
| 274 | struct irq_affinity; |
| 275 | struct pcie_link_state; |
| 276 | struct pci_vpd; |
| 277 | struct pci_sriov; |
| 278 | struct pci_ats; |
| 279 | |
| 280 | /* The pci_dev structure describes PCI devices */ |
| 281 | struct pci_dev { |
| 282 | struct list_head bus_list; /* Node in per-bus list */ |
| 283 | struct pci_bus *bus; /* Bus this device is on */ |
| 284 | struct pci_bus *subordinate; /* Bus this device bridges to */ |
| 285 | |
| 286 | void *sysdata; /* Hook for sys-specific extension */ |
| 287 | struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ |
| 288 | struct pci_slot *slot; /* Physical slot this device is in */ |
| 289 | |
| 290 | unsigned int devfn; /* Encoded device & function index */ |
| 291 | unsigned short vendor; |
| 292 | unsigned short device; |
| 293 | unsigned short subsystem_vendor; |
| 294 | unsigned short subsystem_device; |
| 295 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
| 296 | u8 revision; /* PCI revision, low byte of class word */ |
| 297 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
| 298 | #ifdef CONFIG_PCIEAER |
| 299 | u16 aer_cap; /* AER capability offset */ |
| 300 | #endif |
| 301 | u8 pcie_cap; /* PCIe capability offset */ |
| 302 | u8 msi_cap; /* MSI capability offset */ |
| 303 | u8 msix_cap; /* MSI-X capability offset */ |
| 304 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
| 305 | u8 rom_base_reg; /* Config register controlling ROM */ |
| 306 | u8 pin; /* Interrupt pin this device uses */ |
| 307 | u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ |
| 308 | unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ |
| 309 | |
| 310 | struct pci_driver *driver; /* Driver bound to this device */ |
| 311 | u64 dma_mask; /* Mask of the bits of bus address this |
| 312 | device implements. Normally this is |
| 313 | 0xffffffff. You only need to change |
| 314 | this if your device has broken DMA |
| 315 | or supports 64-bit transfers. */ |
| 316 | |
| 317 | struct device_dma_parameters dma_parms; |
| 318 | |
| 319 | pci_power_t current_state; /* Current operating state. In ACPI, |
| 320 | this is D0-D3, D0 being fully |
| 321 | functional, and D3 being off. */ |
| 322 | u8 pm_cap; /* PM capability offset */ |
| 323 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
| 324 | can be generated */ |
| 325 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
| 326 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
| 327 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
| 328 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
| 329 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
| 330 | unsigned int bridge_d3:1; /* Allow D3 for bridge */ |
| 331 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
| 332 | unsigned int mmio_always_on:1; /* Disallow turning off io/mem |
| 333 | decoding during BAR sizing */ |
| 334 | unsigned int wakeup_prepared:1; |
| 335 | unsigned int runtime_d3cold:1; /* Whether go through runtime |
| 336 | D3cold, not set for devices |
| 337 | powered on/off by the |
| 338 | corresponding bridge */ |
| 339 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
| 340 | unsigned int hotplug_user_indicators:1; /* SlotCtl indicators |
| 341 | controlled exclusively by |
| 342 | user sysfs */ |
| 343 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
| 344 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
| 345 | |
| 346 | #ifdef CONFIG_PCIEASPM |
| 347 | struct pcie_link_state *link_state; /* ASPM link state */ |
| 348 | unsigned int ltr_path:1; /* Latency Tolerance Reporting |
| 349 | supported from root to here */ |
| 350 | #endif |
| 351 | |
| 352 | pci_channel_state_t error_state; /* Current connectivity state */ |
| 353 | struct device dev; /* Generic device interface */ |
| 354 | |
| 355 | int cfg_size; /* Size of config space */ |
| 356 | |
| 357 | /* |
| 358 | * Instead of touching interrupt line and base address registers |
| 359 | * directly, use the values stored here. They might be different! |
| 360 | */ |
| 361 | unsigned int irq; |
| 362 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
| 363 | |
| 364 | bool match_driver; /* Skip attaching driver */ |
| 365 | |
| 366 | unsigned int transparent:1; /* Subtractive decode bridge */ |
| 367 | unsigned int multifunction:1; /* Multi-function device */ |
| 368 | |
| 369 | unsigned int is_added:1; |
| 370 | unsigned int is_busmaster:1; /* Is busmaster */ |
| 371 | unsigned int no_msi:1; /* May not use MSI */ |
| 372 | unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ |
| 373 | unsigned int block_cfg_access:1; /* Config space access blocked */ |
| 374 | unsigned int broken_parity_status:1; /* Generates false positive parity */ |
| 375 | unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ |
| 376 | unsigned int msi_enabled:1; |
| 377 | unsigned int msix_enabled:1; |
| 378 | unsigned int ari_enabled:1; /* ARI forwarding */ |
| 379 | unsigned int ats_enabled:1; /* Address Translation Svc */ |
| 380 | unsigned int pasid_enabled:1; /* Process Address Space ID */ |
| 381 | unsigned int pri_enabled:1; /* Page Request Interface */ |
| 382 | unsigned int is_managed:1; |
| 383 | unsigned int needs_freset:1; /* Requires fundamental reset */ |
| 384 | unsigned int state_saved:1; |
| 385 | unsigned int is_physfn:1; |
| 386 | unsigned int is_virtfn:1; |
| 387 | unsigned int reset_fn:1; |
| 388 | unsigned int is_hotplug_bridge:1; |
| 389 | unsigned int is_thunderbolt:1; /* Thunderbolt controller */ |
| 390 | unsigned int __aer_firmware_first_valid:1; |
| 391 | unsigned int __aer_firmware_first:1; |
| 392 | unsigned int broken_intx_masking:1; /* INTx masking can't be used */ |
| 393 | unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ |
| 394 | unsigned int irq_managed:1; |
| 395 | unsigned int has_secondary_link:1; |
| 396 | unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ |
| 397 | unsigned int is_probed:1; /* Device probing in progress */ |
| 398 | pci_dev_flags_t dev_flags; |
| 399 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
| 400 | |
| 401 | u32 saved_config_space[16]; /* Config space saved at suspend time */ |
| 402 | struct hlist_head saved_cap_space; |
| 403 | struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ |
| 404 | int rom_attr_enabled; /* Display of ROM attribute enabled? */ |
| 405 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
| 406 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
| 407 | |
| 408 | #ifdef CONFIG_PCIE_PTM |
| 409 | unsigned int ptm_root:1; |
| 410 | unsigned int ptm_enabled:1; |
| 411 | u8 ptm_granularity; |
| 412 | #endif |
| 413 | #ifdef CONFIG_PCI_MSI |
| 414 | const struct attribute_group **msi_irq_groups; |
| 415 | #endif |
| 416 | struct pci_vpd *vpd; |
| 417 | #ifdef CONFIG_PCI_ATS |
| 418 | union { |
| 419 | struct pci_sriov *sriov; /* PF: SR-IOV info */ |
| 420 | struct pci_dev *physfn; /* VF: related PF */ |
| 421 | }; |
| 422 | u16 ats_cap; /* ATS Capability offset */ |
| 423 | u8 ats_stu; /* ATS Smallest Translation Unit */ |
| 424 | atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ |
| 425 | #endif |
| 426 | #ifdef CONFIG_PCI_PRI |
| 427 | u32 pri_reqs_alloc; /* Number of PRI requests allocated */ |
| 428 | #endif |
| 429 | #ifdef CONFIG_PCI_PASID |
| 430 | u16 pasid_features; |
| 431 | #endif |
| 432 | phys_addr_t rom; /* Physical address if not from BAR */ |
| 433 | size_t romlen; /* Length if not from BAR */ |
| 434 | char *driver_override; /* Driver name to force a match */ |
| 435 | |
| 436 | unsigned long priv_flags; /* Private flags for the PCI driver */ |
| 437 | }; |
| 438 | |
| 439 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
| 440 | { |
| 441 | #ifdef CONFIG_PCI_IOV |
| 442 | if (dev->is_virtfn) |
| 443 | dev = dev->physfn; |
| 444 | #endif |
| 445 | return dev; |
| 446 | } |
| 447 | |
| 448 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
| 449 | |
| 450 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
| 451 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
| 452 | |
| 453 | static inline int pci_channel_offline(struct pci_dev *pdev) |
| 454 | { |
| 455 | return (pdev->error_state != pci_channel_io_normal); |
| 456 | } |
| 457 | |
| 458 | struct pci_host_bridge { |
| 459 | struct device dev; |
| 460 | struct pci_bus *bus; /* Root bus */ |
| 461 | struct pci_ops *ops; |
| 462 | void *sysdata; |
| 463 | int busnr; |
| 464 | struct list_head windows; /* resource_entry */ |
| 465 | u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ |
| 466 | int (*map_irq)(const struct pci_dev *, u8, u8); |
| 467 | void (*release_fn)(struct pci_host_bridge *); |
| 468 | void *release_data; |
| 469 | struct msi_controller *msi; |
| 470 | unsigned int ignore_reset_delay:1; /* For entire hierarchy */ |
| 471 | unsigned int no_ext_tags:1; /* No Extended Tags */ |
| 472 | /* Resource alignment requirements */ |
| 473 | resource_size_t (*align_resource)(struct pci_dev *dev, |
| 474 | const struct resource *res, |
| 475 | resource_size_t start, |
| 476 | resource_size_t size, |
| 477 | resource_size_t align); |
| 478 | unsigned long private[0] ____cacheline_aligned; |
| 479 | }; |
| 480 | |
| 481 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
| 482 | |
| 483 | static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) |
| 484 | { |
| 485 | return (void *)bridge->private; |
| 486 | } |
| 487 | |
| 488 | static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) |
| 489 | { |
| 490 | return container_of(priv, struct pci_host_bridge, private); |
| 491 | } |
| 492 | |
| 493 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); |
| 494 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
| 495 | size_t priv); |
| 496 | void pci_free_host_bridge(struct pci_host_bridge *bridge); |
| 497 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
| 498 | |
| 499 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
| 500 | void (*release_fn)(struct pci_host_bridge *), |
| 501 | void *release_data); |
| 502 | |
| 503 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
| 504 | |
| 505 | /* |
| 506 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
| 507 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
| 508 | * buses below host bridges or subtractive decode bridges) go in the list. |
| 509 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
| 510 | */ |
| 511 | |
| 512 | /* |
| 513 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
| 514 | * and there's no way to program the bridge with the details of the window. |
| 515 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
| 516 | * decode bit set, because they are explicit and can be programmed with _SRS. |
| 517 | */ |
| 518 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
| 519 | |
| 520 | struct pci_bus_resource { |
| 521 | struct list_head list; |
| 522 | struct resource *res; |
| 523 | unsigned int flags; |
| 524 | }; |
| 525 | |
| 526 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
| 527 | |
| 528 | struct pci_bus { |
| 529 | struct list_head node; /* Node in list of buses */ |
| 530 | struct pci_bus *parent; /* Parent bus this bridge is on */ |
| 531 | struct list_head children; /* List of child buses */ |
| 532 | struct list_head devices; /* List of devices on this bus */ |
| 533 | struct pci_dev *self; /* Bridge device as seen by parent */ |
| 534 | struct list_head slots; /* List of slots on this bus; |
| 535 | protected by pci_slot_mutex */ |
| 536 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
| 537 | struct list_head resources; /* Address space routed to this bus */ |
| 538 | struct resource busn_res; /* Bus numbers routed to this bus */ |
| 539 | |
| 540 | struct pci_ops *ops; /* Configuration access functions */ |
| 541 | struct msi_controller *msi; /* MSI controller */ |
| 542 | void *sysdata; /* Hook for sys-specific extension */ |
| 543 | struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ |
| 544 | |
| 545 | unsigned char number; /* Bus number */ |
| 546 | unsigned char primary; /* Number of primary bridge */ |
| 547 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
| 548 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
| 549 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
| 550 | int domain_nr; |
| 551 | #endif |
| 552 | |
| 553 | char name[48]; |
| 554 | |
| 555 | unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ |
| 556 | pci_bus_flags_t bus_flags; /* Inherited by child buses */ |
| 557 | struct device *bridge; |
| 558 | struct device dev; |
| 559 | struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ |
| 560 | struct bin_attribute *legacy_mem; /* Legacy mem */ |
| 561 | unsigned int is_added:1; |
| 562 | }; |
| 563 | |
| 564 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
| 565 | |
| 566 | /* |
| 567 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
| 568 | * false otherwise |
| 569 | * |
| 570 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. |
| 571 | * This is incorrect because "virtual" buses added for SR-IOV (via |
| 572 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. |
| 573 | */ |
| 574 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
| 575 | { |
| 576 | return !(pbus->parent); |
| 577 | } |
| 578 | |
| 579 | /** |
| 580 | * pci_is_bridge - check if the PCI device is a bridge |
| 581 | * @dev: PCI device |
| 582 | * |
| 583 | * Return true if the PCI device is bridge whether it has subordinate |
| 584 | * or not. |
| 585 | */ |
| 586 | static inline bool pci_is_bridge(struct pci_dev *dev) |
| 587 | { |
| 588 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
| 589 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; |
| 590 | } |
| 591 | |
| 592 | #define for_each_pci_bridge(dev, bus) \ |
| 593 | list_for_each_entry(dev, &bus->devices, bus_list) \ |
| 594 | if (!pci_is_bridge(dev)) {} else |
| 595 | |
| 596 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
| 597 | { |
| 598 | dev = pci_physfn(dev); |
| 599 | if (pci_is_root_bus(dev->bus)) |
| 600 | return NULL; |
| 601 | |
| 602 | return dev->bus->self; |
| 603 | } |
| 604 | |
| 605 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
| 606 | void pci_put_host_bridge_device(struct device *dev); |
| 607 | |
| 608 | #ifdef CONFIG_PCI_MSI |
| 609 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) |
| 610 | { |
| 611 | return pci_dev->msi_enabled || pci_dev->msix_enabled; |
| 612 | } |
| 613 | #else |
| 614 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
| 615 | #endif |
| 616 | |
| 617 | /* Error values that may be returned by PCI functions */ |
| 618 | #define PCIBIOS_SUCCESSFUL 0x00 |
| 619 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
| 620 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
| 621 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
| 622 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
| 623 | #define PCIBIOS_SET_FAILED 0x88 |
| 624 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
| 625 | |
| 626 | /* Translate above to generic errno for passing back through non-PCI code */ |
| 627 | static inline int pcibios_err_to_errno(int err) |
| 628 | { |
| 629 | if (err <= PCIBIOS_SUCCESSFUL) |
| 630 | return err; /* Assume already errno */ |
| 631 | |
| 632 | switch (err) { |
| 633 | case PCIBIOS_FUNC_NOT_SUPPORTED: |
| 634 | return -ENOENT; |
| 635 | case PCIBIOS_BAD_VENDOR_ID: |
| 636 | return -ENOTTY; |
| 637 | case PCIBIOS_DEVICE_NOT_FOUND: |
| 638 | return -ENODEV; |
| 639 | case PCIBIOS_BAD_REGISTER_NUMBER: |
| 640 | return -EFAULT; |
| 641 | case PCIBIOS_SET_FAILED: |
| 642 | return -EIO; |
| 643 | case PCIBIOS_BUFFER_TOO_SMALL: |
| 644 | return -ENOSPC; |
| 645 | } |
| 646 | |
| 647 | return -ERANGE; |
| 648 | } |
| 649 | |
| 650 | /* Low-level architecture-dependent routines */ |
| 651 | |
| 652 | struct pci_ops { |
| 653 | int (*add_bus)(struct pci_bus *bus); |
| 654 | void (*remove_bus)(struct pci_bus *bus); |
| 655 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
| 656 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
| 657 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
| 658 | }; |
| 659 | |
| 660 | /* |
| 661 | * ACPI needs to be able to access PCI config space before we've done a |
| 662 | * PCI bus scan and created pci_bus structures. |
| 663 | */ |
| 664 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
| 665 | int reg, int len, u32 *val); |
| 666 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, |
| 667 | int reg, int len, u32 val); |
| 668 | |
| 669 | #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT |
| 670 | typedef u64 pci_bus_addr_t; |
| 671 | #else |
| 672 | typedef u32 pci_bus_addr_t; |
| 673 | #endif |
| 674 | |
| 675 | struct pci_bus_region { |
| 676 | pci_bus_addr_t start; |
| 677 | pci_bus_addr_t end; |
| 678 | }; |
| 679 | |
| 680 | struct pci_dynids { |
| 681 | spinlock_t lock; /* Protects list, index */ |
| 682 | struct list_head list; /* For IDs added at runtime */ |
| 683 | }; |
| 684 | |
| 685 | |
| 686 | /* |
| 687 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides |
| 688 | * a set of callbacks in struct pci_error_handlers, that device driver |
| 689 | * will be notified of PCI bus errors, and will be driven to recovery |
| 690 | * when an error occurs. |
| 691 | */ |
| 692 | |
| 693 | typedef unsigned int __bitwise pci_ers_result_t; |
| 694 | |
| 695 | enum pci_ers_result { |
| 696 | /* No result/none/not supported in device driver */ |
| 697 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
| 698 | |
| 699 | /* Device driver can recover without slot reset */ |
| 700 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, |
| 701 | |
| 702 | /* Device driver wants slot to be reset */ |
| 703 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
| 704 | |
| 705 | /* Device has completely failed, is unrecoverable */ |
| 706 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, |
| 707 | |
| 708 | /* Device driver is fully recovered and operational */ |
| 709 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, |
| 710 | |
| 711 | /* No AER capabilities registered for the driver */ |
| 712 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, |
| 713 | }; |
| 714 | |
| 715 | /* PCI bus error event callbacks */ |
| 716 | struct pci_error_handlers { |
| 717 | /* PCI bus error detected on this device */ |
| 718 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, |
| 719 | enum pci_channel_state error); |
| 720 | |
| 721 | /* MMIO has been re-enabled, but not DMA */ |
| 722 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); |
| 723 | |
| 724 | /* PCI slot has been reset */ |
| 725 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); |
| 726 | |
| 727 | /* PCI function reset prepare or completed */ |
| 728 | void (*reset_prepare)(struct pci_dev *dev); |
| 729 | void (*reset_done)(struct pci_dev *dev); |
| 730 | |
| 731 | /* Device driver may resume normal operations */ |
| 732 | void (*resume)(struct pci_dev *dev); |
| 733 | }; |
| 734 | |
| 735 | |
| 736 | struct module; |
| 737 | struct pci_driver { |
| 738 | struct list_head node; |
| 739 | const char *name; |
| 740 | const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ |
| 741 | int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ |
| 742 | void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ |
| 743 | int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ |
| 744 | int (*suspend_late)(struct pci_dev *dev, pm_message_t state); |
| 745 | int (*resume_early)(struct pci_dev *dev); |
| 746 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
| 747 | void (*shutdown) (struct pci_dev *dev); |
| 748 | int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */ |
| 749 | const struct pci_error_handlers *err_handler; |
| 750 | const struct attribute_group **groups; |
| 751 | struct device_driver driver; |
| 752 | struct pci_dynids dynids; |
| 753 | }; |
| 754 | |
| 755 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
| 756 | |
| 757 | /** |
| 758 | * PCI_DEVICE - macro used to describe a specific PCI device |
| 759 | * @vend: the 16 bit PCI Vendor ID |
| 760 | * @dev: the 16 bit PCI Device ID |
| 761 | * |
| 762 | * This macro is used to create a struct pci_device_id that matches a |
| 763 | * specific device. The subvendor and subdevice fields will be set to |
| 764 | * PCI_ANY_ID. |
| 765 | */ |
| 766 | #define PCI_DEVICE(vend,dev) \ |
| 767 | .vendor = (vend), .device = (dev), \ |
| 768 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
| 769 | |
| 770 | /** |
| 771 | * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem |
| 772 | * @vend: the 16 bit PCI Vendor ID |
| 773 | * @dev: the 16 bit PCI Device ID |
| 774 | * @subvend: the 16 bit PCI Subvendor ID |
| 775 | * @subdev: the 16 bit PCI Subdevice ID |
| 776 | * |
| 777 | * This macro is used to create a struct pci_device_id that matches a |
| 778 | * specific device with subsystem information. |
| 779 | */ |
| 780 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ |
| 781 | .vendor = (vend), .device = (dev), \ |
| 782 | .subvendor = (subvend), .subdevice = (subdev) |
| 783 | |
| 784 | /** |
| 785 | * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class |
| 786 | * @dev_class: the class, subclass, prog-if triple for this device |
| 787 | * @dev_class_mask: the class mask for this device |
| 788 | * |
| 789 | * This macro is used to create a struct pci_device_id that matches a |
| 790 | * specific PCI class. The vendor, device, subvendor, and subdevice |
| 791 | * fields will be set to PCI_ANY_ID. |
| 792 | */ |
| 793 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ |
| 794 | .class = (dev_class), .class_mask = (dev_class_mask), \ |
| 795 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ |
| 796 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
| 797 | |
| 798 | /** |
| 799 | * PCI_VDEVICE - macro used to describe a specific PCI device in short form |
| 800 | * @vend: the vendor name |
| 801 | * @dev: the 16 bit PCI Device ID |
| 802 | * |
| 803 | * This macro is used to create a struct pci_device_id that matches a |
| 804 | * specific PCI device. The subvendor, and subdevice fields will be set |
| 805 | * to PCI_ANY_ID. The macro allows the next field to follow as the device |
| 806 | * private data. |
| 807 | */ |
| 808 | #define PCI_VDEVICE(vend, dev) \ |
| 809 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ |
| 810 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 |
| 811 | |
| 812 | enum { |
| 813 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ |
| 814 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ |
| 815 | PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ |
| 816 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ |
| 817 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ |
| 818 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ |
| 819 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ |
| 820 | }; |
| 821 | |
| 822 | /* These external functions are only available when PCI support is enabled */ |
| 823 | #ifdef CONFIG_PCI |
| 824 | |
| 825 | extern unsigned int pci_flags; |
| 826 | |
| 827 | static inline void pci_set_flags(int flags) { pci_flags = flags; } |
| 828 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } |
| 829 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } |
| 830 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } |
| 831 | |
| 832 | void pcie_bus_configure_settings(struct pci_bus *bus); |
| 833 | |
| 834 | enum pcie_bus_config_types { |
| 835 | PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ |
| 836 | PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ |
| 837 | PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ |
| 838 | PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ |
| 839 | PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ |
| 840 | }; |
| 841 | |
| 842 | extern enum pcie_bus_config_types pcie_bus_config; |
| 843 | |
| 844 | extern struct bus_type pci_bus_type; |
| 845 | |
| 846 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
| 847 | * code, or PCI core code. */ |
| 848 | extern struct list_head pci_root_buses; /* List of all known PCI buses */ |
| 849 | /* Some device drivers need know if PCI is initiated */ |
| 850 | int no_pci_devices(void); |
| 851 | |
| 852 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
| 853 | void pcibios_bus_add_device(struct pci_dev *pdev); |
| 854 | void pcibios_add_bus(struct pci_bus *bus); |
| 855 | void pcibios_remove_bus(struct pci_bus *bus); |
| 856 | void pcibios_fixup_bus(struct pci_bus *); |
| 857 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
| 858 | /* Architecture-specific versions may override this (weak) */ |
| 859 | char *pcibios_setup(char *str); |
| 860 | |
| 861 | /* Used only when drivers/pci/setup.c is used */ |
| 862 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
| 863 | resource_size_t, |
| 864 | resource_size_t); |
| 865 | |
| 866 | /* Weak but can be overriden by arch */ |
| 867 | void pci_fixup_cardbus(struct pci_bus *); |
| 868 | |
| 869 | /* Generic PCI functions used internally */ |
| 870 | |
| 871 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
| 872 | struct resource *res); |
| 873 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
| 874 | struct pci_bus_region *region); |
| 875 | void pcibios_scan_specific_bus(int busn); |
| 876 | struct pci_bus *pci_find_bus(int domain, int busnr); |
| 877 | void pci_bus_add_devices(const struct pci_bus *bus); |
| 878 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
| 879 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
| 880 | struct pci_ops *ops, void *sysdata, |
| 881 | struct list_head *resources); |
| 882 | int pci_host_probe(struct pci_host_bridge *bridge); |
| 883 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
| 884 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); |
| 885 | void pci_bus_release_busn_res(struct pci_bus *b); |
| 886 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
| 887 | struct pci_ops *ops, void *sysdata, |
| 888 | struct list_head *resources); |
| 889 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); |
| 890 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
| 891 | int busnr); |
| 892 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
| 893 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
| 894 | const char *name, |
| 895 | struct hotplug_slot *hotplug); |
| 896 | void pci_destroy_slot(struct pci_slot *slot); |
| 897 | #ifdef CONFIG_SYSFS |
| 898 | void pci_dev_assign_slot(struct pci_dev *dev); |
| 899 | #else |
| 900 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } |
| 901 | #endif |
| 902 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
| 903 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
| 904 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
| 905 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
| 906 | void pci_bus_add_device(struct pci_dev *dev); |
| 907 | void pci_read_bridge_bases(struct pci_bus *child); |
| 908 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
| 909 | struct resource *res); |
| 910 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
| 911 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
| 912 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
| 913 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
| 914 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
| 915 | void pci_dev_put(struct pci_dev *dev); |
| 916 | void pci_remove_bus(struct pci_bus *b); |
| 917 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); |
| 918 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
| 919 | void pci_stop_root_bus(struct pci_bus *bus); |
| 920 | void pci_remove_root_bus(struct pci_bus *bus); |
| 921 | void pci_setup_cardbus(struct pci_bus *bus); |
| 922 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); |
| 923 | void pci_sort_breadthfirst(void); |
| 924 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
| 925 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) |
| 926 | |
| 927 | /* Generic PCI functions exported to card drivers */ |
| 928 | |
| 929 | enum pci_lost_interrupt_reason { |
| 930 | PCI_LOST_IRQ_NO_INFORMATION = 0, |
| 931 | PCI_LOST_IRQ_DISABLE_MSI, |
| 932 | PCI_LOST_IRQ_DISABLE_MSIX, |
| 933 | PCI_LOST_IRQ_DISABLE_ACPI, |
| 934 | }; |
| 935 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); |
| 936 | int pci_find_capability(struct pci_dev *dev, int cap); |
| 937 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
| 938 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
| 939 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
| 940 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
| 941 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
| 942 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
| 943 | |
| 944 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
| 945 | struct pci_dev *from); |
| 946 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
| 947 | unsigned int ss_vendor, unsigned int ss_device, |
| 948 | struct pci_dev *from); |
| 949 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
| 950 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
| 951 | unsigned int devfn); |
| 952 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
| 953 | unsigned int devfn) |
| 954 | { |
| 955 | return pci_get_domain_bus_and_slot(0, bus, devfn); |
| 956 | } |
| 957 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
| 958 | int pci_dev_present(const struct pci_device_id *ids); |
| 959 | |
| 960 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
| 961 | int where, u8 *val); |
| 962 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, |
| 963 | int where, u16 *val); |
| 964 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, |
| 965 | int where, u32 *val); |
| 966 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, |
| 967 | int where, u8 val); |
| 968 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, |
| 969 | int where, u16 val); |
| 970 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, |
| 971 | int where, u32 val); |
| 972 | |
| 973 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
| 974 | int where, int size, u32 *val); |
| 975 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, |
| 976 | int where, int size, u32 val); |
| 977 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, |
| 978 | int where, int size, u32 *val); |
| 979 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, |
| 980 | int where, int size, u32 val); |
| 981 | |
| 982 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
| 983 | |
| 984 | int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); |
| 985 | int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); |
| 986 | int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); |
| 987 | int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); |
| 988 | int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); |
| 989 | int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); |
| 990 | |
| 991 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
| 992 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); |
| 993 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); |
| 994 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); |
| 995 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
| 996 | u16 clear, u16 set); |
| 997 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, |
| 998 | u32 clear, u32 set); |
| 999 | |
| 1000 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, |
| 1001 | u16 set) |
| 1002 | { |
| 1003 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); |
| 1004 | } |
| 1005 | |
| 1006 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, |
| 1007 | u32 set) |
| 1008 | { |
| 1009 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); |
| 1010 | } |
| 1011 | |
| 1012 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, |
| 1013 | u16 clear) |
| 1014 | { |
| 1015 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); |
| 1016 | } |
| 1017 | |
| 1018 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, |
| 1019 | u32 clear) |
| 1020 | { |
| 1021 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); |
| 1022 | } |
| 1023 | |
| 1024 | /* User-space driven config access */ |
| 1025 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
| 1026 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); |
| 1027 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
| 1028 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); |
| 1029 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); |
| 1030 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); |
| 1031 | |
| 1032 | int __must_check pci_enable_device(struct pci_dev *dev); |
| 1033 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
| 1034 | int __must_check pci_enable_device_mem(struct pci_dev *dev); |
| 1035 | int __must_check pci_reenable_device(struct pci_dev *); |
| 1036 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
| 1037 | void pcim_pin_device(struct pci_dev *pdev); |
| 1038 | |
| 1039 | static inline bool pci_intx_mask_supported(struct pci_dev *pdev) |
| 1040 | { |
| 1041 | /* |
| 1042 | * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is |
| 1043 | * writable and no quirk has marked the feature broken. |
| 1044 | */ |
| 1045 | return !pdev->broken_intx_masking; |
| 1046 | } |
| 1047 | |
| 1048 | static inline int pci_is_enabled(struct pci_dev *pdev) |
| 1049 | { |
| 1050 | return (atomic_read(&pdev->enable_cnt) > 0); |
| 1051 | } |
| 1052 | |
| 1053 | static inline int pci_is_managed(struct pci_dev *pdev) |
| 1054 | { |
| 1055 | return pdev->is_managed; |
| 1056 | } |
| 1057 | |
| 1058 | void pci_disable_device(struct pci_dev *dev); |
| 1059 | |
| 1060 | extern unsigned int pcibios_max_latency; |
| 1061 | void pci_set_master(struct pci_dev *dev); |
| 1062 | void pci_clear_master(struct pci_dev *dev); |
| 1063 | |
| 1064 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
| 1065 | int pci_set_cacheline_size(struct pci_dev *dev); |
| 1066 | #define HAVE_PCI_SET_MWI |
| 1067 | int __must_check pci_set_mwi(struct pci_dev *dev); |
| 1068 | int __must_check pcim_set_mwi(struct pci_dev *dev); |
| 1069 | int pci_try_set_mwi(struct pci_dev *dev); |
| 1070 | void pci_clear_mwi(struct pci_dev *dev); |
| 1071 | void pci_intx(struct pci_dev *dev, int enable); |
| 1072 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
| 1073 | bool pci_check_and_unmask_intx(struct pci_dev *dev); |
| 1074 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
| 1075 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
| 1076 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
| 1077 | int pcix_get_mmrbc(struct pci_dev *dev); |
| 1078 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); |
| 1079 | int pcie_get_readrq(struct pci_dev *dev); |
| 1080 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
| 1081 | int pcie_get_mps(struct pci_dev *dev); |
| 1082 | int pcie_set_mps(struct pci_dev *dev, int mps); |
| 1083 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, |
| 1084 | enum pcie_link_width *width); |
| 1085 | void pcie_flr(struct pci_dev *dev); |
| 1086 | int __pci_reset_function_locked(struct pci_dev *dev); |
| 1087 | int pci_reset_function(struct pci_dev *dev); |
| 1088 | int pci_reset_function_locked(struct pci_dev *dev); |
| 1089 | int pci_try_reset_function(struct pci_dev *dev); |
| 1090 | int pci_probe_reset_slot(struct pci_slot *slot); |
| 1091 | int pci_reset_slot(struct pci_slot *slot); |
| 1092 | int pci_try_reset_slot(struct pci_slot *slot); |
| 1093 | int pci_probe_reset_bus(struct pci_bus *bus); |
| 1094 | int pci_reset_bus(struct pci_bus *bus); |
| 1095 | int pci_try_reset_bus(struct pci_bus *bus); |
| 1096 | void pci_reset_secondary_bus(struct pci_dev *dev); |
| 1097 | void pcibios_reset_secondary_bus(struct pci_dev *dev); |
| 1098 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev); |
| 1099 | void pci_update_resource(struct pci_dev *dev, int resno); |
| 1100 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
| 1101 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
| 1102 | void pci_release_resource(struct pci_dev *dev, int resno); |
| 1103 | int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); |
| 1104 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
| 1105 | bool pci_device_is_present(struct pci_dev *pdev); |
| 1106 | void pci_ignore_hotplug(struct pci_dev *dev); |
| 1107 | |
| 1108 | int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, |
| 1109 | irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, |
| 1110 | const char *fmt, ...); |
| 1111 | void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); |
| 1112 | |
| 1113 | /* ROM control related routines */ |
| 1114 | int pci_enable_rom(struct pci_dev *pdev); |
| 1115 | void pci_disable_rom(struct pci_dev *pdev); |
| 1116 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
| 1117 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
| 1118 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
| 1119 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
| 1120 | |
| 1121 | /* Power management related routines */ |
| 1122 | int pci_save_state(struct pci_dev *dev); |
| 1123 | void pci_restore_state(struct pci_dev *dev); |
| 1124 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
| 1125 | int pci_load_saved_state(struct pci_dev *dev, |
| 1126 | struct pci_saved_state *state); |
| 1127 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
| 1128 | struct pci_saved_state **state); |
| 1129 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
| 1130 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, |
| 1131 | u16 cap); |
| 1132 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); |
| 1133 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, |
| 1134 | u16 cap, unsigned int size); |
| 1135 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
| 1136 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
| 1137 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); |
| 1138 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
| 1139 | void pci_pme_active(struct pci_dev *dev, bool enable); |
| 1140 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
| 1141 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
| 1142 | int pci_prepare_to_sleep(struct pci_dev *dev); |
| 1143 | int pci_back_from_sleep(struct pci_dev *dev); |
| 1144 | bool pci_dev_run_wake(struct pci_dev *dev); |
| 1145 | bool pci_check_pme_status(struct pci_dev *dev); |
| 1146 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
| 1147 | void pci_d3cold_enable(struct pci_dev *dev); |
| 1148 | void pci_d3cold_disable(struct pci_dev *dev); |
| 1149 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); |
| 1150 | |
| 1151 | /* PCI Virtual Channel */ |
| 1152 | int pci_save_vc_state(struct pci_dev *dev); |
| 1153 | void pci_restore_vc_state(struct pci_dev *dev); |
| 1154 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); |
| 1155 | |
| 1156 | /* For use by arch with custom probe code */ |
| 1157 | void set_pcie_port_type(struct pci_dev *pdev); |
| 1158 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); |
| 1159 | |
| 1160 | /* Functions for PCI Hotplug drivers to use */ |
| 1161 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
| 1162 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
| 1163 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
| 1164 | void pci_lock_rescan_remove(void); |
| 1165 | void pci_unlock_rescan_remove(void); |
| 1166 | |
| 1167 | /* Vital Product Data routines */ |
| 1168 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
| 1169 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); |
| 1170 | int pci_set_vpd_size(struct pci_dev *dev, size_t len); |
| 1171 | |
| 1172 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
| 1173 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
| 1174 | void pci_bus_assign_resources(const struct pci_bus *bus); |
| 1175 | void pci_bus_claim_resources(struct pci_bus *bus); |
| 1176 | void pci_bus_size_bridges(struct pci_bus *bus); |
| 1177 | int pci_claim_resource(struct pci_dev *, int); |
| 1178 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
| 1179 | void pci_assign_unassigned_resources(void); |
| 1180 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
| 1181 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
| 1182 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
| 1183 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); |
| 1184 | void pdev_enable_device(struct pci_dev *); |
| 1185 | int pci_enable_resources(struct pci_dev *, int mask); |
| 1186 | void pci_assign_irq(struct pci_dev *dev); |
| 1187 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); |
| 1188 | #define HAVE_PCI_REQ_REGIONS 2 |
| 1189 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
| 1190 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
| 1191 | void pci_release_regions(struct pci_dev *); |
| 1192 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
| 1193 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
| 1194 | void pci_release_region(struct pci_dev *, int); |
| 1195 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
| 1196 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
| 1197 | void pci_release_selected_regions(struct pci_dev *, int); |
| 1198 | |
| 1199 | /* drivers/pci/bus.c */ |
| 1200 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
| 1201 | void pci_bus_put(struct pci_bus *bus); |
| 1202 | void pci_add_resource(struct list_head *resources, struct resource *res); |
| 1203 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
| 1204 | resource_size_t offset); |
| 1205 | void pci_free_resource_list(struct list_head *resources); |
| 1206 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, |
| 1207 | unsigned int flags); |
| 1208 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
| 1209 | void pci_bus_remove_resources(struct pci_bus *bus); |
| 1210 | int devm_request_pci_bus_resources(struct device *dev, |
| 1211 | struct list_head *resources); |
| 1212 | |
| 1213 | #define pci_bus_for_each_resource(bus, res, i) \ |
| 1214 | for (i = 0; \ |
| 1215 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ |
| 1216 | i++) |
| 1217 | |
| 1218 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
| 1219 | struct resource *res, resource_size_t size, |
| 1220 | resource_size_t align, resource_size_t min, |
| 1221 | unsigned long type_mask, |
| 1222 | resource_size_t (*alignf)(void *, |
| 1223 | const struct resource *, |
| 1224 | resource_size_t, |
| 1225 | resource_size_t), |
| 1226 | void *alignf_data); |
| 1227 | |
| 1228 | |
| 1229 | int pci_register_io_range(phys_addr_t addr, resource_size_t size); |
| 1230 | unsigned long pci_address_to_pio(phys_addr_t addr); |
| 1231 | phys_addr_t pci_pio_to_address(unsigned long pio); |
| 1232 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
| 1233 | void pci_unmap_iospace(struct resource *res); |
| 1234 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, |
| 1235 | resource_size_t offset, |
| 1236 | resource_size_t size); |
| 1237 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, |
| 1238 | struct resource *res); |
| 1239 | |
| 1240 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
| 1241 | { |
| 1242 | struct pci_bus_region region; |
| 1243 | |
| 1244 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); |
| 1245 | return region.start; |
| 1246 | } |
| 1247 | |
| 1248 | /* Proper probing supporting hot-pluggable devices */ |
| 1249 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
| 1250 | const char *mod_name); |
| 1251 | |
| 1252 | /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ |
| 1253 | #define pci_register_driver(driver) \ |
| 1254 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) |
| 1255 | |
| 1256 | void pci_unregister_driver(struct pci_driver *dev); |
| 1257 | |
| 1258 | /** |
| 1259 | * module_pci_driver() - Helper macro for registering a PCI driver |
| 1260 | * @__pci_driver: pci_driver struct |
| 1261 | * |
| 1262 | * Helper macro for PCI drivers which do not do anything special in module |
| 1263 | * init/exit. This eliminates a lot of boilerplate. Each module may only |
| 1264 | * use this macro once, and calling it replaces module_init() and module_exit() |
| 1265 | */ |
| 1266 | #define module_pci_driver(__pci_driver) \ |
| 1267 | module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) |
| 1268 | |
| 1269 | /** |
| 1270 | * builtin_pci_driver() - Helper macro for registering a PCI driver |
| 1271 | * @__pci_driver: pci_driver struct |
| 1272 | * |
| 1273 | * Helper macro for PCI drivers which do not do anything special in their |
| 1274 | * init code. This eliminates a lot of boilerplate. Each driver may only |
| 1275 | * use this macro once, and calling it replaces device_initcall(...) |
| 1276 | */ |
| 1277 | #define builtin_pci_driver(__pci_driver) \ |
| 1278 | builtin_driver(__pci_driver, pci_register_driver) |
| 1279 | |
| 1280 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
| 1281 | int pci_add_dynid(struct pci_driver *drv, |
| 1282 | unsigned int vendor, unsigned int device, |
| 1283 | unsigned int subvendor, unsigned int subdevice, |
| 1284 | unsigned int class, unsigned int class_mask, |
| 1285 | unsigned long driver_data); |
| 1286 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
| 1287 | struct pci_dev *dev); |
| 1288 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, |
| 1289 | int pass); |
| 1290 | |
| 1291 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
| 1292 | void *userdata); |
| 1293 | int pci_cfg_space_size(struct pci_dev *dev); |
| 1294 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
| 1295 | void pci_setup_bridge(struct pci_bus *bus); |
| 1296 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
| 1297 | unsigned long type); |
| 1298 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); |
| 1299 | |
| 1300 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
| 1301 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) |
| 1302 | |
| 1303 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
| 1304 | unsigned int command_bits, u32 flags); |
| 1305 | |
| 1306 | #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ |
| 1307 | #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ |
| 1308 | #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ |
| 1309 | #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ |
| 1310 | #define PCI_IRQ_ALL_TYPES \ |
| 1311 | (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) |
| 1312 | |
| 1313 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
| 1314 | |
| 1315 | #include <linux/pci-dma.h> |
| 1316 | #include <linux/dmapool.h> |
| 1317 | |
| 1318 | #define pci_pool dma_pool |
| 1319 | #define pci_pool_create(name, pdev, size, align, allocation) \ |
| 1320 | dma_pool_create(name, &pdev->dev, size, align, allocation) |
| 1321 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) |
| 1322 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) |
| 1323 | #define pci_pool_zalloc(pool, flags, handle) \ |
| 1324 | dma_pool_zalloc(pool, flags, handle) |
| 1325 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
| 1326 | |
| 1327 | struct msix_entry { |
| 1328 | u32 vector; /* Kernel uses to write allocated vector */ |
| 1329 | u16 entry; /* Driver uses to specify entry, OS writes */ |
| 1330 | }; |
| 1331 | |
| 1332 | #ifdef CONFIG_PCI_MSI |
| 1333 | int pci_msi_vec_count(struct pci_dev *dev); |
| 1334 | void pci_disable_msi(struct pci_dev *dev); |
| 1335 | int pci_msix_vec_count(struct pci_dev *dev); |
| 1336 | void pci_disable_msix(struct pci_dev *dev); |
| 1337 | void pci_restore_msi_state(struct pci_dev *dev); |
| 1338 | int pci_msi_enabled(void); |
| 1339 | int pci_enable_msi(struct pci_dev *dev); |
| 1340 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
| 1341 | int minvec, int maxvec); |
| 1342 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
| 1343 | struct msix_entry *entries, int nvec) |
| 1344 | { |
| 1345 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); |
| 1346 | if (rc < 0) |
| 1347 | return rc; |
| 1348 | return 0; |
| 1349 | } |
| 1350 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
| 1351 | unsigned int max_vecs, unsigned int flags, |
| 1352 | const struct irq_affinity *affd); |
| 1353 | |
| 1354 | void pci_free_irq_vectors(struct pci_dev *dev); |
| 1355 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); |
| 1356 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); |
| 1357 | int pci_irq_get_node(struct pci_dev *pdev, int vec); |
| 1358 | |
| 1359 | #else |
| 1360 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
| 1361 | static inline void pci_disable_msi(struct pci_dev *dev) { } |
| 1362 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
| 1363 | static inline void pci_disable_msix(struct pci_dev *dev) { } |
| 1364 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
| 1365 | static inline int pci_msi_enabled(void) { return 0; } |
| 1366 | static inline int pci_enable_msi(struct pci_dev *dev) |
| 1367 | { return -ENOSYS; } |
| 1368 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
| 1369 | struct msix_entry *entries, int minvec, int maxvec) |
| 1370 | { return -ENOSYS; } |
| 1371 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
| 1372 | struct msix_entry *entries, int nvec) |
| 1373 | { return -ENOSYS; } |
| 1374 | |
| 1375 | static inline int |
| 1376 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
| 1377 | unsigned int max_vecs, unsigned int flags, |
| 1378 | const struct irq_affinity *aff_desc) |
| 1379 | { |
| 1380 | if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) |
| 1381 | return 1; |
| 1382 | return -ENOSPC; |
| 1383 | } |
| 1384 | |
| 1385 | static inline void pci_free_irq_vectors(struct pci_dev *dev) |
| 1386 | { |
| 1387 | } |
| 1388 | |
| 1389 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) |
| 1390 | { |
| 1391 | if (WARN_ON_ONCE(nr > 0)) |
| 1392 | return -EINVAL; |
| 1393 | return dev->irq; |
| 1394 | } |
| 1395 | static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, |
| 1396 | int vec) |
| 1397 | { |
| 1398 | return cpu_possible_mask; |
| 1399 | } |
| 1400 | |
| 1401 | static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) |
| 1402 | { |
| 1403 | return first_online_node; |
| 1404 | } |
| 1405 | #endif |
| 1406 | |
| 1407 | static inline int |
| 1408 | pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, |
| 1409 | unsigned int max_vecs, unsigned int flags) |
| 1410 | { |
| 1411 | return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, |
| 1412 | NULL); |
| 1413 | } |
| 1414 | |
| 1415 | /** |
| 1416 | * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq |
| 1417 | * @d: the INTx IRQ domain |
| 1418 | * @node: the DT node for the device whose interrupt we're translating |
| 1419 | * @intspec: the interrupt specifier data from the DT |
| 1420 | * @intsize: the number of entries in @intspec |
| 1421 | * @out_hwirq: pointer at which to write the hwirq number |
| 1422 | * @out_type: pointer at which to write the interrupt type |
| 1423 | * |
| 1424 | * Translate a PCI INTx interrupt number from device tree in the range 1-4, as |
| 1425 | * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range |
| 1426 | * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the |
| 1427 | * INTx value to obtain the hwirq number. |
| 1428 | * |
| 1429 | * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. |
| 1430 | */ |
| 1431 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, |
| 1432 | struct device_node *node, |
| 1433 | const u32 *intspec, |
| 1434 | unsigned int intsize, |
| 1435 | unsigned long *out_hwirq, |
| 1436 | unsigned int *out_type) |
| 1437 | { |
| 1438 | const u32 intx = intspec[0]; |
| 1439 | |
| 1440 | if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) |
| 1441 | return -EINVAL; |
| 1442 | |
| 1443 | *out_hwirq = intx - PCI_INTERRUPT_INTA; |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | #ifdef CONFIG_PCIEPORTBUS |
| 1448 | extern bool pcie_ports_disabled; |
| 1449 | extern bool pcie_ports_auto; |
| 1450 | #else |
| 1451 | #define pcie_ports_disabled true |
| 1452 | #define pcie_ports_auto false |
| 1453 | #endif |
| 1454 | |
| 1455 | #ifdef CONFIG_PCIEASPM |
| 1456 | bool pcie_aspm_support_enabled(void); |
| 1457 | #else |
| 1458 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
| 1459 | #endif |
| 1460 | |
| 1461 | #ifdef CONFIG_PCIEAER |
| 1462 | void pci_no_aer(void); |
| 1463 | bool pci_aer_available(void); |
| 1464 | int pci_aer_init(struct pci_dev *dev); |
| 1465 | #else |
| 1466 | static inline void pci_no_aer(void) { } |
| 1467 | static inline bool pci_aer_available(void) { return false; } |
| 1468 | static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } |
| 1469 | #endif |
| 1470 | |
| 1471 | #ifdef CONFIG_PCIE_ECRC |
| 1472 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
| 1473 | void pcie_ecrc_get_policy(char *str); |
| 1474 | #else |
| 1475 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
| 1476 | static inline void pcie_ecrc_get_policy(char *str) { } |
| 1477 | #endif |
| 1478 | |
| 1479 | #ifdef CONFIG_PCI_ATS |
| 1480 | /* Address Translation Service */ |
| 1481 | void pci_ats_init(struct pci_dev *dev); |
| 1482 | int pci_enable_ats(struct pci_dev *dev, int ps); |
| 1483 | void pci_disable_ats(struct pci_dev *dev); |
| 1484 | int pci_ats_queue_depth(struct pci_dev *dev); |
| 1485 | #else |
| 1486 | static inline void pci_ats_init(struct pci_dev *d) { } |
| 1487 | static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } |
| 1488 | static inline void pci_disable_ats(struct pci_dev *d) { } |
| 1489 | static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } |
| 1490 | #endif |
| 1491 | |
| 1492 | #ifdef CONFIG_PCIE_PTM |
| 1493 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); |
| 1494 | #else |
| 1495 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) |
| 1496 | { return -EINVAL; } |
| 1497 | #endif |
| 1498 | |
| 1499 | void pci_cfg_access_lock(struct pci_dev *dev); |
| 1500 | bool pci_cfg_access_trylock(struct pci_dev *dev); |
| 1501 | void pci_cfg_access_unlock(struct pci_dev *dev); |
| 1502 | |
| 1503 | /* |
| 1504 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
| 1505 | * a PCI domain is defined to be a set of PCI buses which share |
| 1506 | * configuration space. |
| 1507 | */ |
| 1508 | #ifdef CONFIG_PCI_DOMAINS |
| 1509 | extern int pci_domains_supported; |
| 1510 | int pci_get_new_domain_nr(void); |
| 1511 | #else |
| 1512 | enum { pci_domains_supported = 0 }; |
| 1513 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
| 1514 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } |
| 1515 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
| 1516 | #endif /* CONFIG_PCI_DOMAINS */ |
| 1517 | |
| 1518 | /* |
| 1519 | * Generic implementation for PCI domain support. If your |
| 1520 | * architecture does not need custom management of PCI |
| 1521 | * domains then this implementation will be used |
| 1522 | */ |
| 1523 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
| 1524 | static inline int pci_domain_nr(struct pci_bus *bus) |
| 1525 | { |
| 1526 | return bus->domain_nr; |
| 1527 | } |
| 1528 | #ifdef CONFIG_ACPI |
| 1529 | int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); |
| 1530 | #else |
| 1531 | static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) |
| 1532 | { return 0; } |
| 1533 | #endif |
| 1534 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); |
| 1535 | #endif |
| 1536 | |
| 1537 | /* Some architectures require additional setup to direct VGA traffic */ |
| 1538 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
| 1539 | unsigned int command_bits, u32 flags); |
| 1540 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
| 1541 | |
| 1542 | static inline int |
| 1543 | pci_request_io_regions(struct pci_dev *pdev, const char *name) |
| 1544 | { |
| 1545 | return pci_request_selected_regions(pdev, |
| 1546 | pci_select_bars(pdev, IORESOURCE_IO), name); |
| 1547 | } |
| 1548 | |
| 1549 | static inline void |
| 1550 | pci_release_io_regions(struct pci_dev *pdev) |
| 1551 | { |
| 1552 | return pci_release_selected_regions(pdev, |
| 1553 | pci_select_bars(pdev, IORESOURCE_IO)); |
| 1554 | } |
| 1555 | |
| 1556 | static inline int |
| 1557 | pci_request_mem_regions(struct pci_dev *pdev, const char *name) |
| 1558 | { |
| 1559 | return pci_request_selected_regions(pdev, |
| 1560 | pci_select_bars(pdev, IORESOURCE_MEM), name); |
| 1561 | } |
| 1562 | |
| 1563 | static inline void |
| 1564 | pci_release_mem_regions(struct pci_dev *pdev) |
| 1565 | { |
| 1566 | return pci_release_selected_regions(pdev, |
| 1567 | pci_select_bars(pdev, IORESOURCE_MEM)); |
| 1568 | } |
| 1569 | |
| 1570 | #else /* CONFIG_PCI is not enabled */ |
| 1571 | |
| 1572 | static inline void pci_set_flags(int flags) { } |
| 1573 | static inline void pci_add_flags(int flags) { } |
| 1574 | static inline void pci_clear_flags(int flags) { } |
| 1575 | static inline int pci_has_flag(int flag) { return 0; } |
| 1576 | |
| 1577 | /* |
| 1578 | * If the system does not have PCI, clearly these return errors. Define |
| 1579 | * these as simple inline functions to avoid hair in drivers. |
| 1580 | */ |
| 1581 | #define _PCI_NOP(o, s, t) \ |
| 1582 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ |
| 1583 | int where, t val) \ |
| 1584 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
| 1585 | |
| 1586 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ |
| 1587 | _PCI_NOP(o, word, u16 x) \ |
| 1588 | _PCI_NOP(o, dword, u32 x) |
| 1589 | _PCI_NOP_ALL(read, *) |
| 1590 | _PCI_NOP_ALL(write,) |
| 1591 | |
| 1592 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
| 1593 | unsigned int device, |
| 1594 | struct pci_dev *from) |
| 1595 | { return NULL; } |
| 1596 | |
| 1597 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
| 1598 | unsigned int device, |
| 1599 | unsigned int ss_vendor, |
| 1600 | unsigned int ss_device, |
| 1601 | struct pci_dev *from) |
| 1602 | { return NULL; } |
| 1603 | |
| 1604 | static inline struct pci_dev *pci_get_class(unsigned int class, |
| 1605 | struct pci_dev *from) |
| 1606 | { return NULL; } |
| 1607 | |
| 1608 | #define pci_dev_present(ids) (0) |
| 1609 | #define no_pci_devices() (1) |
| 1610 | #define pci_dev_put(dev) do { } while (0) |
| 1611 | |
| 1612 | static inline void pci_set_master(struct pci_dev *dev) { } |
| 1613 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } |
| 1614 | static inline void pci_disable_device(struct pci_dev *dev) { } |
| 1615 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
| 1616 | { return -EBUSY; } |
| 1617 | static inline int __pci_register_driver(struct pci_driver *drv, |
| 1618 | struct module *owner) |
| 1619 | { return 0; } |
| 1620 | static inline int pci_register_driver(struct pci_driver *drv) |
| 1621 | { return 0; } |
| 1622 | static inline void pci_unregister_driver(struct pci_driver *drv) { } |
| 1623 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
| 1624 | { return 0; } |
| 1625 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
| 1626 | int cap) |
| 1627 | { return 0; } |
| 1628 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
| 1629 | { return 0; } |
| 1630 | |
| 1631 | /* Power management related routines */ |
| 1632 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
| 1633 | static inline void pci_restore_state(struct pci_dev *dev) { } |
| 1634 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
| 1635 | { return 0; } |
| 1636 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
| 1637 | { return 0; } |
| 1638 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
| 1639 | pm_message_t state) |
| 1640 | { return PCI_D0; } |
| 1641 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
| 1642 | int enable) |
| 1643 | { return 0; } |
| 1644 | |
| 1645 | static inline struct resource *pci_find_resource(struct pci_dev *dev, |
| 1646 | struct resource *res) |
| 1647 | { return NULL; } |
| 1648 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
| 1649 | { return -EIO; } |
| 1650 | static inline void pci_release_regions(struct pci_dev *dev) { } |
| 1651 | |
| 1652 | static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } |
| 1653 | |
| 1654 | static inline void pci_block_cfg_access(struct pci_dev *dev) { } |
| 1655 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
| 1656 | { return 0; } |
| 1657 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } |
| 1658 | |
| 1659 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
| 1660 | { return NULL; } |
| 1661 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
| 1662 | unsigned int devfn) |
| 1663 | { return NULL; } |
| 1664 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
| 1665 | unsigned int devfn) |
| 1666 | { return NULL; } |
| 1667 | static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, |
| 1668 | unsigned int bus, unsigned int devfn) |
| 1669 | { return NULL; } |
| 1670 | |
| 1671 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
| 1672 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } |
| 1673 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
| 1674 | |
| 1675 | #define dev_is_pci(d) (false) |
| 1676 | #define dev_is_pf(d) (false) |
| 1677 | static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) |
| 1678 | { return false; } |
| 1679 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, |
| 1680 | struct device_node *node, |
| 1681 | const u32 *intspec, |
| 1682 | unsigned int intsize, |
| 1683 | unsigned long *out_hwirq, |
| 1684 | unsigned int *out_type) |
| 1685 | { return -EINVAL; } |
| 1686 | #endif /* CONFIG_PCI */ |
| 1687 | |
| 1688 | /* Include architecture-dependent settings and functions */ |
| 1689 | |
| 1690 | #include <asm/pci.h> |
| 1691 | |
| 1692 | /* These two functions provide almost identical functionality. Depennding |
| 1693 | * on the architecture, one will be implemented as a wrapper around the |
| 1694 | * other (in drivers/pci/mmap.c). |
| 1695 | * |
| 1696 | * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff |
| 1697 | * is expected to be an offset within that region. |
| 1698 | * |
| 1699 | * pci_mmap_page_range() is the legacy architecture-specific interface, |
| 1700 | * which accepts a "user visible" resource address converted by |
| 1701 | * pci_resource_to_user(), as used in the legacy mmap() interface in |
| 1702 | * /proc/bus/pci/. |
| 1703 | */ |
| 1704 | int pci_mmap_resource_range(struct pci_dev *dev, int bar, |
| 1705 | struct vm_area_struct *vma, |
| 1706 | enum pci_mmap_state mmap_state, int write_combine); |
| 1707 | int pci_mmap_page_range(struct pci_dev *pdev, int bar, |
| 1708 | struct vm_area_struct *vma, |
| 1709 | enum pci_mmap_state mmap_state, int write_combine); |
| 1710 | |
| 1711 | #ifndef arch_can_pci_mmap_wc |
| 1712 | #define arch_can_pci_mmap_wc() 0 |
| 1713 | #endif |
| 1714 | |
| 1715 | #ifndef arch_can_pci_mmap_io |
| 1716 | #define arch_can_pci_mmap_io() 0 |
| 1717 | #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) |
| 1718 | #else |
| 1719 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); |
| 1720 | #endif |
| 1721 | |
| 1722 | #ifndef pci_root_bus_fwnode |
| 1723 | #define pci_root_bus_fwnode(bus) NULL |
| 1724 | #endif |
| 1725 | |
| 1726 | /* |
| 1727 | * These helpers provide future and backwards compatibility |
| 1728 | * for accessing popular PCI BAR info |
| 1729 | */ |
| 1730 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
| 1731 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
| 1732 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
| 1733 | #define pci_resource_len(dev,bar) \ |
| 1734 | ((pci_resource_start((dev), (bar)) == 0 && \ |
| 1735 | pci_resource_end((dev), (bar)) == \ |
| 1736 | pci_resource_start((dev), (bar))) ? 0 : \ |
| 1737 | \ |
| 1738 | (pci_resource_end((dev), (bar)) - \ |
| 1739 | pci_resource_start((dev), (bar)) + 1)) |
| 1740 | |
| 1741 | /* |
| 1742 | * Similar to the helpers above, these manipulate per-pci_dev |
| 1743 | * driver-specific data. They are really just a wrapper around |
| 1744 | * the generic device structure functions of these calls. |
| 1745 | */ |
| 1746 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
| 1747 | { |
| 1748 | return dev_get_drvdata(&pdev->dev); |
| 1749 | } |
| 1750 | |
| 1751 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
| 1752 | { |
| 1753 | dev_set_drvdata(&pdev->dev, data); |
| 1754 | } |
| 1755 | |
| 1756 | static inline const char *pci_name(const struct pci_dev *pdev) |
| 1757 | { |
| 1758 | return dev_name(&pdev->dev); |
| 1759 | } |
| 1760 | |
| 1761 | |
| 1762 | /* |
| 1763 | * Some archs don't want to expose struct resource to userland as-is |
| 1764 | * in sysfs and /proc |
| 1765 | */ |
| 1766 | #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER |
| 1767 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
| 1768 | const struct resource *rsrc, |
| 1769 | resource_size_t *start, resource_size_t *end); |
| 1770 | #else |
| 1771 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
| 1772 | const struct resource *rsrc, resource_size_t *start, |
| 1773 | resource_size_t *end) |
| 1774 | { |
| 1775 | *start = rsrc->start; |
| 1776 | *end = rsrc->end; |
| 1777 | } |
| 1778 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ |
| 1779 | |
| 1780 | |
| 1781 | /* |
| 1782 | * The world is not perfect and supplies us with broken PCI devices. |
| 1783 | * For at least a part of these bugs we need a work-around, so both |
| 1784 | * generic (drivers/pci/quirks.c) and per-architecture code can define |
| 1785 | * fixup hooks to be called for particular buggy devices. |
| 1786 | */ |
| 1787 | |
| 1788 | struct pci_fixup { |
| 1789 | u16 vendor; /* Or PCI_ANY_ID */ |
| 1790 | u16 device; /* Or PCI_ANY_ID */ |
| 1791 | u32 class; /* Or PCI_ANY_ID */ |
| 1792 | unsigned int class_shift; /* should be 0, 8, 16 */ |
| 1793 | void (*hook)(struct pci_dev *dev); |
| 1794 | }; |
| 1795 | |
| 1796 | enum pci_fixup_pass { |
| 1797 | pci_fixup_early, /* Before probing BARs */ |
| 1798 | pci_fixup_header, /* After reading configuration header */ |
| 1799 | pci_fixup_final, /* Final phase of device fixups */ |
| 1800 | pci_fixup_enable, /* pci_enable_device() time */ |
| 1801 | pci_fixup_resume, /* pci_device_resume() */ |
| 1802 | pci_fixup_suspend, /* pci_device_suspend() */ |
| 1803 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
| 1804 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
| 1805 | }; |
| 1806 | |
| 1807 | /* Anonymous variables would be nice... */ |
| 1808 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
| 1809 | class_shift, hook) \ |
| 1810 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
| 1811 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
| 1812 | = { vendor, device, class, class_shift, hook }; |
| 1813 | |
| 1814 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ |
| 1815 | class_shift, hook) \ |
| 1816 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
| 1817 | hook, vendor, device, class, class_shift, hook) |
| 1818 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
| 1819 | class_shift, hook) \ |
| 1820 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
| 1821 | hook, vendor, device, class, class_shift, hook) |
| 1822 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
| 1823 | class_shift, hook) \ |
| 1824 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
| 1825 | hook, vendor, device, class, class_shift, hook) |
| 1826 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
| 1827 | class_shift, hook) \ |
| 1828 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
| 1829 | hook, vendor, device, class, class_shift, hook) |
| 1830 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
| 1831 | class_shift, hook) \ |
| 1832 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
| 1833 | resume##hook, vendor, device, class, class_shift, hook) |
| 1834 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
| 1835 | class_shift, hook) \ |
| 1836 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
| 1837 | resume_early##hook, vendor, device, class, class_shift, hook) |
| 1838 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
| 1839 | class_shift, hook) \ |
| 1840 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
| 1841 | suspend##hook, vendor, device, class, class_shift, hook) |
| 1842 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
| 1843 | class_shift, hook) \ |
| 1844 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ |
| 1845 | suspend_late##hook, vendor, device, class, class_shift, hook) |
| 1846 | |
| 1847 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
| 1848 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
| 1849 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1850 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
| 1851 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
| 1852 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1853 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
| 1854 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
| 1855 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1856 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
| 1857 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
| 1858 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1859 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
| 1860 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
| 1861 | resume##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1862 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
| 1863 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
| 1864 | resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1865 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
| 1866 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
| 1867 | suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1868 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
| 1869 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ |
| 1870 | suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1871 | |
| 1872 | #ifdef CONFIG_PCI_QUIRKS |
| 1873 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
| 1874 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
| 1875 | int pci_dev_specific_enable_acs(struct pci_dev *dev); |
| 1876 | #else |
| 1877 | static inline void pci_fixup_device(enum pci_fixup_pass pass, |
| 1878 | struct pci_dev *dev) { } |
| 1879 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
| 1880 | u16 acs_flags) |
| 1881 | { |
| 1882 | return -ENOTTY; |
| 1883 | } |
| 1884 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) |
| 1885 | { |
| 1886 | return -ENOTTY; |
| 1887 | } |
| 1888 | #endif |
| 1889 | |
| 1890 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
| 1891 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
| 1892 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
| 1893 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
| 1894 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, |
| 1895 | const char *name); |
| 1896 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
| 1897 | |
| 1898 | extern int pci_pci_problems; |
| 1899 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
| 1900 | #define PCIPCI_TRITON 2 |
| 1901 | #define PCIPCI_NATOMA 4 |
| 1902 | #define PCIPCI_VIAETBF 8 |
| 1903 | #define PCIPCI_VSFX 16 |
| 1904 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
| 1905 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ |
| 1906 | |
| 1907 | extern unsigned long pci_cardbus_io_size; |
| 1908 | extern unsigned long pci_cardbus_mem_size; |
| 1909 | extern u8 pci_dfl_cache_line_size; |
| 1910 | extern u8 pci_cache_line_size; |
| 1911 | |
| 1912 | extern unsigned long pci_hotplug_io_size; |
| 1913 | extern unsigned long pci_hotplug_mem_size; |
| 1914 | extern unsigned long pci_hotplug_bus_size; |
| 1915 | |
| 1916 | /* Architecture-specific versions may override these (weak) */ |
| 1917 | void pcibios_disable_device(struct pci_dev *dev); |
| 1918 | void pcibios_set_master(struct pci_dev *dev); |
| 1919 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
| 1920 | enum pcie_reset_state state); |
| 1921 | int pcibios_add_device(struct pci_dev *dev); |
| 1922 | void pcibios_release_device(struct pci_dev *dev); |
| 1923 | void pcibios_penalize_isa_irq(int irq, int active); |
| 1924 | int pcibios_alloc_irq(struct pci_dev *dev); |
| 1925 | void pcibios_free_irq(struct pci_dev *dev); |
| 1926 | |
| 1927 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
| 1928 | extern struct dev_pm_ops pcibios_pm_ops; |
| 1929 | #endif |
| 1930 | |
| 1931 | #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) |
| 1932 | void __init pci_mmcfg_early_init(void); |
| 1933 | void __init pci_mmcfg_late_init(void); |
| 1934 | #else |
| 1935 | static inline void pci_mmcfg_early_init(void) { } |
| 1936 | static inline void pci_mmcfg_late_init(void) { } |
| 1937 | #endif |
| 1938 | |
| 1939 | int pci_ext_cfg_avail(void); |
| 1940 | |
| 1941 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
| 1942 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
| 1943 | |
| 1944 | #ifdef CONFIG_PCI_IOV |
| 1945 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
| 1946 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); |
| 1947 | |
| 1948 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
| 1949 | void pci_disable_sriov(struct pci_dev *dev); |
| 1950 | int pci_iov_add_virtfn(struct pci_dev *dev, int id); |
| 1951 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id); |
| 1952 | int pci_num_vf(struct pci_dev *dev); |
| 1953 | int pci_vfs_assigned(struct pci_dev *dev); |
| 1954 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
| 1955 | int pci_sriov_get_totalvfs(struct pci_dev *dev); |
| 1956 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
| 1957 | void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); |
| 1958 | #else |
| 1959 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
| 1960 | { |
| 1961 | return -ENOSYS; |
| 1962 | } |
| 1963 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) |
| 1964 | { |
| 1965 | return -ENOSYS; |
| 1966 | } |
| 1967 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
| 1968 | { return -ENODEV; } |
| 1969 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) |
| 1970 | { |
| 1971 | return -ENOSYS; |
| 1972 | } |
| 1973 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, |
| 1974 | int id) { } |
| 1975 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
| 1976 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
| 1977 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
| 1978 | { return 0; } |
| 1979 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
| 1980 | { return 0; } |
| 1981 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
| 1982 | { return 0; } |
| 1983 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
| 1984 | { return 0; } |
| 1985 | static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } |
| 1986 | #endif |
| 1987 | |
| 1988 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
| 1989 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
| 1990 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); |
| 1991 | #endif |
| 1992 | |
| 1993 | /** |
| 1994 | * pci_pcie_cap - get the saved PCIe capability offset |
| 1995 | * @dev: PCI device |
| 1996 | * |
| 1997 | * PCIe capability offset is calculated at PCI device initialization |
| 1998 | * time and saved in the data structure. This function returns saved |
| 1999 | * PCIe capability offset. Using this instead of pci_find_capability() |
| 2000 | * reduces unnecessary search in the PCI configuration space. If you |
| 2001 | * need to calculate PCIe capability offset from raw device for some |
| 2002 | * reasons, please use pci_find_capability() instead. |
| 2003 | */ |
| 2004 | static inline int pci_pcie_cap(struct pci_dev *dev) |
| 2005 | { |
| 2006 | return dev->pcie_cap; |
| 2007 | } |
| 2008 | |
| 2009 | /** |
| 2010 | * pci_is_pcie - check if the PCI device is PCI Express capable |
| 2011 | * @dev: PCI device |
| 2012 | * |
| 2013 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
| 2014 | */ |
| 2015 | static inline bool pci_is_pcie(struct pci_dev *dev) |
| 2016 | { |
| 2017 | return pci_pcie_cap(dev); |
| 2018 | } |
| 2019 | |
| 2020 | /** |
| 2021 | * pcie_caps_reg - get the PCIe Capabilities Register |
| 2022 | * @dev: PCI device |
| 2023 | */ |
| 2024 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) |
| 2025 | { |
| 2026 | return dev->pcie_flags_reg; |
| 2027 | } |
| 2028 | |
| 2029 | /** |
| 2030 | * pci_pcie_type - get the PCIe device/port type |
| 2031 | * @dev: PCI device |
| 2032 | */ |
| 2033 | static inline int pci_pcie_type(const struct pci_dev *dev) |
| 2034 | { |
| 2035 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
| 2036 | } |
| 2037 | |
| 2038 | static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) |
| 2039 | { |
| 2040 | while (1) { |
| 2041 | if (!pci_is_pcie(dev)) |
| 2042 | break; |
| 2043 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) |
| 2044 | return dev; |
| 2045 | if (!dev->bus->self) |
| 2046 | break; |
| 2047 | dev = dev->bus->self; |
| 2048 | } |
| 2049 | return NULL; |
| 2050 | } |
| 2051 | |
| 2052 | void pci_request_acs(void); |
| 2053 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
| 2054 | bool pci_acs_path_enabled(struct pci_dev *start, |
| 2055 | struct pci_dev *end, u16 acs_flags); |
| 2056 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); |
| 2057 | |
| 2058 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
| 2059 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
| 2060 | |
| 2061 | /* Large Resource Data Type Tag Item Names */ |
| 2062 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ |
| 2063 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ |
| 2064 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ |
| 2065 | |
| 2066 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) |
| 2067 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) |
| 2068 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) |
| 2069 | |
| 2070 | /* Small Resource Data Type Tag Item Names */ |
| 2071 | #define PCI_VPD_STIN_END 0x0f /* End */ |
| 2072 | |
| 2073 | #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) |
| 2074 | |
| 2075 | #define PCI_VPD_SRDT_TIN_MASK 0x78 |
| 2076 | #define PCI_VPD_SRDT_LEN_MASK 0x07 |
| 2077 | #define PCI_VPD_LRDT_TIN_MASK 0x7f |
| 2078 | |
| 2079 | #define PCI_VPD_LRDT_TAG_SIZE 3 |
| 2080 | #define PCI_VPD_SRDT_TAG_SIZE 1 |
| 2081 | |
| 2082 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
| 2083 | |
| 2084 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
| 2085 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
| 2086 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" |
| 2087 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
| 2088 | |
| 2089 | /** |
| 2090 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length |
| 2091 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
| 2092 | * |
| 2093 | * Returns the extracted Large Resource Data Type length. |
| 2094 | */ |
| 2095 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) |
| 2096 | { |
| 2097 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); |
| 2098 | } |
| 2099 | |
| 2100 | /** |
| 2101 | * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item |
| 2102 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
| 2103 | * |
| 2104 | * Returns the extracted Large Resource Data Type Tag item. |
| 2105 | */ |
| 2106 | static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) |
| 2107 | { |
| 2108 | return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); |
| 2109 | } |
| 2110 | |
| 2111 | /** |
| 2112 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length |
| 2113 | * @srdt: Pointer to the beginning of the Small Resource Data Type tag |
| 2114 | * |
| 2115 | * Returns the extracted Small Resource Data Type length. |
| 2116 | */ |
| 2117 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) |
| 2118 | { |
| 2119 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; |
| 2120 | } |
| 2121 | |
| 2122 | /** |
| 2123 | * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item |
| 2124 | * @srdt: Pointer to the beginning of the Small Resource Data Type tag |
| 2125 | * |
| 2126 | * Returns the extracted Small Resource Data Type Tag Item. |
| 2127 | */ |
| 2128 | static inline u8 pci_vpd_srdt_tag(const u8 *srdt) |
| 2129 | { |
| 2130 | return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; |
| 2131 | } |
| 2132 | |
| 2133 | /** |
| 2134 | * pci_vpd_info_field_size - Extracts the information field length |
| 2135 | * @lrdt: Pointer to the beginning of an information field header |
| 2136 | * |
| 2137 | * Returns the extracted information field length. |
| 2138 | */ |
| 2139 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) |
| 2140 | { |
| 2141 | return info_field[2]; |
| 2142 | } |
| 2143 | |
| 2144 | /** |
| 2145 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided |
| 2146 | * @buf: Pointer to buffered vpd data |
| 2147 | * @off: The offset into the buffer at which to begin the search |
| 2148 | * @len: The length of the vpd buffer |
| 2149 | * @rdt: The Resource Data Type to search for |
| 2150 | * |
| 2151 | * Returns the index where the Resource Data Type was found or |
| 2152 | * -ENOENT otherwise. |
| 2153 | */ |
| 2154 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); |
| 2155 | |
| 2156 | /** |
| 2157 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD |
| 2158 | * @buf: Pointer to buffered vpd data |
| 2159 | * @off: The offset into the buffer at which to begin the search |
| 2160 | * @len: The length of the buffer area, relative to off, in which to search |
| 2161 | * @kw: The keyword to search for |
| 2162 | * |
| 2163 | * Returns the index where the information field keyword was found or |
| 2164 | * -ENOENT otherwise. |
| 2165 | */ |
| 2166 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, |
| 2167 | unsigned int len, const char *kw); |
| 2168 | |
| 2169 | /* PCI <-> OF binding helpers */ |
| 2170 | #ifdef CONFIG_OF |
| 2171 | struct device_node; |
| 2172 | struct irq_domain; |
| 2173 | void pci_set_of_node(struct pci_dev *dev); |
| 2174 | void pci_release_of_node(struct pci_dev *dev); |
| 2175 | void pci_set_bus_of_node(struct pci_bus *bus); |
| 2176 | void pci_release_bus_of_node(struct pci_bus *bus); |
| 2177 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
| 2178 | int pci_parse_request_of_pci_ranges(struct device *dev, |
| 2179 | struct list_head *resources, |
| 2180 | struct resource **bus_range); |
| 2181 | |
| 2182 | /* Arch may override this (weak) */ |
| 2183 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
| 2184 | |
| 2185 | static inline struct device_node * |
| 2186 | pci_device_to_OF_node(const struct pci_dev *pdev) |
| 2187 | { |
| 2188 | return pdev ? pdev->dev.of_node : NULL; |
| 2189 | } |
| 2190 | |
| 2191 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
| 2192 | { |
| 2193 | return bus ? bus->dev.of_node : NULL; |
| 2194 | } |
| 2195 | |
| 2196 | #else /* CONFIG_OF */ |
| 2197 | static inline void pci_set_of_node(struct pci_dev *dev) { } |
| 2198 | static inline void pci_release_of_node(struct pci_dev *dev) { } |
| 2199 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
| 2200 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
| 2201 | static inline struct device_node * |
| 2202 | pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } |
| 2203 | static inline struct irq_domain * |
| 2204 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } |
| 2205 | static inline int pci_parse_request_of_pci_ranges(struct device *dev, |
| 2206 | struct list_head *resources, |
| 2207 | struct resource **bus_range) |
| 2208 | { |
| 2209 | return -EINVAL; |
| 2210 | } |
| 2211 | #endif /* CONFIG_OF */ |
| 2212 | |
| 2213 | #ifdef CONFIG_ACPI |
| 2214 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); |
| 2215 | |
| 2216 | void |
| 2217 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); |
| 2218 | #else |
| 2219 | static inline struct irq_domain * |
| 2220 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } |
| 2221 | #endif |
| 2222 | |
| 2223 | #ifdef CONFIG_EEH |
| 2224 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) |
| 2225 | { |
| 2226 | return pdev->dev.archdata.edev; |
| 2227 | } |
| 2228 | #endif |
| 2229 | |
| 2230 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); |
| 2231 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); |
| 2232 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
| 2233 | int (*fn)(struct pci_dev *pdev, |
| 2234 | u16 alias, void *data), void *data); |
| 2235 | |
| 2236 | /* Helper functions for operation of device flag */ |
| 2237 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
| 2238 | { |
| 2239 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; |
| 2240 | } |
| 2241 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) |
| 2242 | { |
| 2243 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; |
| 2244 | } |
| 2245 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) |
| 2246 | { |
| 2247 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; |
| 2248 | } |
| 2249 | |
| 2250 | /** |
| 2251 | * pci_ari_enabled - query ARI forwarding status |
| 2252 | * @bus: the PCI bus |
| 2253 | * |
| 2254 | * Returns true if ARI forwarding is enabled. |
| 2255 | */ |
| 2256 | static inline bool pci_ari_enabled(struct pci_bus *bus) |
| 2257 | { |
| 2258 | return bus->self && bus->self->ari_enabled; |
| 2259 | } |
| 2260 | |
| 2261 | /** |
| 2262 | * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain |
| 2263 | * @pdev: PCI device to check |
| 2264 | * |
| 2265 | * Walk upwards from @pdev and check for each encountered bridge if it's part |
| 2266 | * of a Thunderbolt controller. Reaching the host bridge means @pdev is not |
| 2267 | * Thunderbolt-attached. (But rather soldered to the mainboard usually.) |
| 2268 | */ |
| 2269 | static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) |
| 2270 | { |
| 2271 | struct pci_dev *parent = pdev; |
| 2272 | |
| 2273 | if (pdev->is_thunderbolt) |
| 2274 | return true; |
| 2275 | |
| 2276 | while ((parent = pci_upstream_bridge(parent))) |
| 2277 | if (parent->is_thunderbolt) |
| 2278 | return true; |
| 2279 | |
| 2280 | return false; |
| 2281 | } |
| 2282 | |
| 2283 | /** |
| 2284 | * pci_uevent_ers - emit a uevent during recovery path of pci device |
| 2285 | * @pdev: pci device to check |
| 2286 | * @err_type: type of error event |
| 2287 | * |
| 2288 | */ |
| 2289 | static inline void pci_uevent_ers(struct pci_dev *pdev, |
| 2290 | enum pci_ers_result err_type) |
| 2291 | { |
| 2292 | int idx = 0; |
| 2293 | char *envp[3]; |
| 2294 | |
| 2295 | switch (err_type) { |
| 2296 | case PCI_ERS_RESULT_NONE: |
| 2297 | case PCI_ERS_RESULT_CAN_RECOVER: |
| 2298 | envp[idx++] = "ERROR_EVENT=BEGIN_RECOVERY"; |
| 2299 | envp[idx++] = "DEVICE_ONLINE=0"; |
| 2300 | break; |
| 2301 | case PCI_ERS_RESULT_RECOVERED: |
| 2302 | envp[idx++] = "ERROR_EVENT=SUCCESSFUL_RECOVERY"; |
| 2303 | envp[idx++] = "DEVICE_ONLINE=1"; |
| 2304 | break; |
| 2305 | case PCI_ERS_RESULT_DISCONNECT: |
| 2306 | envp[idx++] = "ERROR_EVENT=FAILED_RECOVERY"; |
| 2307 | envp[idx++] = "DEVICE_ONLINE=0"; |
| 2308 | break; |
| 2309 | default: |
| 2310 | break; |
| 2311 | } |
| 2312 | |
| 2313 | if (idx > 0) { |
| 2314 | envp[idx++] = NULL; |
| 2315 | kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp); |
| 2316 | } |
| 2317 | } |
| 2318 | |
| 2319 | /* Provide the legacy pci_dma_* API */ |
| 2320 | #include <linux/pci-dma-compat.h> |
| 2321 | |
| 2322 | #define pci_printk(level, pdev, fmt, arg...) \ |
| 2323 | dev_printk(level, &(pdev)->dev, fmt, ##arg) |
| 2324 | |
| 2325 | #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) |
| 2326 | #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) |
| 2327 | #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) |
| 2328 | #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) |
| 2329 | #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) |
| 2330 | #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) |
| 2331 | #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) |
| 2332 | #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) |
| 2333 | |
| 2334 | #endif /* LINUX_PCI_H */ |