| 1 | /* |
| 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #ifndef MLX5_DRIVER_H |
| 34 | #define MLX5_DRIVER_H |
| 35 | |
| 36 | #include <linux/kernel.h> |
| 37 | #include <linux/completion.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/irq.h> |
| 40 | #include <linux/spinlock_types.h> |
| 41 | #include <linux/semaphore.h> |
| 42 | #include <linux/slab.h> |
| 43 | #include <linux/vmalloc.h> |
| 44 | #include <linux/xarray.h> |
| 45 | #include <linux/workqueue.h> |
| 46 | #include <linux/mempool.h> |
| 47 | #include <linux/interrupt.h> |
| 48 | #include <linux/idr.h> |
| 49 | #include <linux/notifier.h> |
| 50 | #include <linux/refcount.h> |
| 51 | #include <linux/auxiliary_bus.h> |
| 52 | #include <linux/mutex.h> |
| 53 | |
| 54 | #include <linux/mlx5/device.h> |
| 55 | #include <linux/mlx5/doorbell.h> |
| 56 | #include <linux/mlx5/eq.h> |
| 57 | #include <linux/timecounter.h> |
| 58 | #include <linux/ptp_clock_kernel.h> |
| 59 | #include <net/devlink.h> |
| 60 | |
| 61 | #define MLX5_ADEV_NAME "mlx5_core" |
| 62 | |
| 63 | #define MLX5_IRQ_EQ_CTRL (U8_MAX) |
| 64 | |
| 65 | enum { |
| 66 | MLX5_BOARD_ID_LEN = 64, |
| 67 | }; |
| 68 | |
| 69 | enum { |
| 70 | MLX5_CMD_WQ_MAX_NAME = 32, |
| 71 | }; |
| 72 | |
| 73 | enum { |
| 74 | CMD_OWNER_SW = 0x0, |
| 75 | CMD_OWNER_HW = 0x1, |
| 76 | CMD_STATUS_SUCCESS = 0, |
| 77 | }; |
| 78 | |
| 79 | enum mlx5_sqp_t { |
| 80 | MLX5_SQP_SMI = 0, |
| 81 | MLX5_SQP_GSI = 1, |
| 82 | MLX5_SQP_IEEE_1588 = 2, |
| 83 | MLX5_SQP_SNIFFER = 3, |
| 84 | MLX5_SQP_SYNC_UMR = 4, |
| 85 | }; |
| 86 | |
| 87 | enum { |
| 88 | MLX5_MAX_PORTS = 8, |
| 89 | }; |
| 90 | |
| 91 | enum { |
| 92 | MLX5_ATOMIC_MODE_OFFSET = 16, |
| 93 | MLX5_ATOMIC_MODE_IB_COMP = 1, |
| 94 | MLX5_ATOMIC_MODE_CX = 2, |
| 95 | MLX5_ATOMIC_MODE_8B = 3, |
| 96 | MLX5_ATOMIC_MODE_16B = 4, |
| 97 | MLX5_ATOMIC_MODE_32B = 5, |
| 98 | MLX5_ATOMIC_MODE_64B = 6, |
| 99 | MLX5_ATOMIC_MODE_128B = 7, |
| 100 | MLX5_ATOMIC_MODE_256B = 8, |
| 101 | }; |
| 102 | |
| 103 | enum { |
| 104 | MLX5_REG_SBPR = 0xb001, |
| 105 | MLX5_REG_SBCM = 0xb002, |
| 106 | MLX5_REG_QPTS = 0x4002, |
| 107 | MLX5_REG_QETCR = 0x4005, |
| 108 | MLX5_REG_QTCT = 0x400a, |
| 109 | MLX5_REG_QPDPM = 0x4013, |
| 110 | MLX5_REG_QCAM = 0x4019, |
| 111 | MLX5_REG_DCBX_PARAM = 0x4020, |
| 112 | MLX5_REG_DCBX_APP = 0x4021, |
| 113 | MLX5_REG_FPGA_CAP = 0x4022, |
| 114 | MLX5_REG_FPGA_CTRL = 0x4023, |
| 115 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
| 116 | MLX5_REG_CORE_DUMP = 0x402e, |
| 117 | MLX5_REG_PCAP = 0x5001, |
| 118 | MLX5_REG_PMTU = 0x5003, |
| 119 | MLX5_REG_PTYS = 0x5004, |
| 120 | MLX5_REG_PAOS = 0x5006, |
| 121 | MLX5_REG_PFCC = 0x5007, |
| 122 | MLX5_REG_PPCNT = 0x5008, |
| 123 | MLX5_REG_PPTB = 0x500b, |
| 124 | MLX5_REG_PBMC = 0x500c, |
| 125 | MLX5_REG_PMAOS = 0x5012, |
| 126 | MLX5_REG_PUDE = 0x5009, |
| 127 | MLX5_REG_PMPE = 0x5010, |
| 128 | MLX5_REG_PELC = 0x500e, |
| 129 | MLX5_REG_PVLC = 0x500f, |
| 130 | MLX5_REG_PCMR = 0x5041, |
| 131 | MLX5_REG_PDDR = 0x5031, |
| 132 | MLX5_REG_PMLP = 0x5002, |
| 133 | MLX5_REG_PPLM = 0x5023, |
| 134 | MLX5_REG_PCAM = 0x507f, |
| 135 | MLX5_REG_NODE_DESC = 0x6001, |
| 136 | MLX5_REG_HOST_ENDIANNESS = 0x7004, |
| 137 | MLX5_REG_MTCAP = 0x9009, |
| 138 | MLX5_REG_MTMP = 0x900A, |
| 139 | MLX5_REG_MCIA = 0x9014, |
| 140 | MLX5_REG_MFRL = 0x9028, |
| 141 | MLX5_REG_MLCR = 0x902b, |
| 142 | MLX5_REG_MRTC = 0x902d, |
| 143 | MLX5_REG_MTRC_CAP = 0x9040, |
| 144 | MLX5_REG_MTRC_CONF = 0x9041, |
| 145 | MLX5_REG_MTRC_STDB = 0x9042, |
| 146 | MLX5_REG_MTRC_CTRL = 0x9043, |
| 147 | MLX5_REG_MPEIN = 0x9050, |
| 148 | MLX5_REG_MPCNT = 0x9051, |
| 149 | MLX5_REG_MTPPS = 0x9053, |
| 150 | MLX5_REG_MTPPSE = 0x9054, |
| 151 | MLX5_REG_MTUTC = 0x9055, |
| 152 | MLX5_REG_MPEGC = 0x9056, |
| 153 | MLX5_REG_MPIR = 0x9059, |
| 154 | MLX5_REG_MCQS = 0x9060, |
| 155 | MLX5_REG_MCQI = 0x9061, |
| 156 | MLX5_REG_MCC = 0x9062, |
| 157 | MLX5_REG_MCDA = 0x9063, |
| 158 | MLX5_REG_MCAM = 0x907f, |
| 159 | MLX5_REG_MSECQ = 0x9155, |
| 160 | MLX5_REG_MSEES = 0x9156, |
| 161 | MLX5_REG_MIRC = 0x9162, |
| 162 | MLX5_REG_MTPTM = 0x9180, |
| 163 | MLX5_REG_MTCTR = 0x9181, |
| 164 | MLX5_REG_SBCAM = 0xB01F, |
| 165 | MLX5_REG_RESOURCE_DUMP = 0xC000, |
| 166 | MLX5_REG_DTOR = 0xC00E, |
| 167 | }; |
| 168 | |
| 169 | enum mlx5_qpts_trust_state { |
| 170 | MLX5_QPTS_TRUST_PCP = 1, |
| 171 | MLX5_QPTS_TRUST_DSCP = 2, |
| 172 | }; |
| 173 | |
| 174 | enum mlx5_dcbx_oper_mode { |
| 175 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, |
| 176 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, |
| 177 | }; |
| 178 | |
| 179 | enum { |
| 180 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, |
| 181 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, |
| 182 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
| 183 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, |
| 184 | }; |
| 185 | |
| 186 | enum mlx5_page_fault_resume_flags { |
| 187 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, |
| 188 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, |
| 189 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, |
| 190 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, |
| 191 | }; |
| 192 | |
| 193 | enum dbg_rsc_type { |
| 194 | MLX5_DBG_RSC_QP, |
| 195 | MLX5_DBG_RSC_EQ, |
| 196 | MLX5_DBG_RSC_CQ, |
| 197 | }; |
| 198 | |
| 199 | enum port_state_policy { |
| 200 | MLX5_POLICY_DOWN = 0, |
| 201 | MLX5_POLICY_UP = 1, |
| 202 | MLX5_POLICY_FOLLOW = 2, |
| 203 | MLX5_POLICY_INVALID = 0xffffffff |
| 204 | }; |
| 205 | |
| 206 | enum mlx5_coredev_type { |
| 207 | MLX5_COREDEV_PF, |
| 208 | MLX5_COREDEV_VF, |
| 209 | MLX5_COREDEV_SF, |
| 210 | }; |
| 211 | |
| 212 | struct mlx5_field_desc { |
| 213 | int i; |
| 214 | }; |
| 215 | |
| 216 | struct mlx5_rsc_debug { |
| 217 | struct mlx5_core_dev *dev; |
| 218 | void *object; |
| 219 | enum dbg_rsc_type type; |
| 220 | struct dentry *root; |
| 221 | struct mlx5_field_desc fields[]; |
| 222 | }; |
| 223 | |
| 224 | enum mlx5_dev_event { |
| 225 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
| 226 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
| 227 | MLX5_DEV_EVENT_MULTIPORT_ESW = 130, |
| 228 | }; |
| 229 | |
| 230 | enum mlx5_port_status { |
| 231 | MLX5_PORT_UP = 1, |
| 232 | MLX5_PORT_DOWN = 2, |
| 233 | }; |
| 234 | |
| 235 | enum mlx5_cmdif_state { |
| 236 | MLX5_CMDIF_STATE_UNINITIALIZED, |
| 237 | MLX5_CMDIF_STATE_UP, |
| 238 | MLX5_CMDIF_STATE_DOWN, |
| 239 | }; |
| 240 | |
| 241 | struct mlx5_cmd_first { |
| 242 | __be32 data[4]; |
| 243 | }; |
| 244 | |
| 245 | struct mlx5_cmd_msg { |
| 246 | struct list_head list; |
| 247 | struct cmd_msg_cache *parent; |
| 248 | u32 len; |
| 249 | struct mlx5_cmd_first first; |
| 250 | struct mlx5_cmd_mailbox *next; |
| 251 | }; |
| 252 | |
| 253 | struct mlx5_cmd_debug { |
| 254 | struct dentry *dbg_root; |
| 255 | void *in_msg; |
| 256 | void *out_msg; |
| 257 | u8 status; |
| 258 | u16 inlen; |
| 259 | u16 outlen; |
| 260 | }; |
| 261 | |
| 262 | struct cmd_msg_cache { |
| 263 | /* protect block chain allocations |
| 264 | */ |
| 265 | spinlock_t lock; |
| 266 | struct list_head head; |
| 267 | unsigned int max_inbox_size; |
| 268 | unsigned int num_ent; |
| 269 | }; |
| 270 | |
| 271 | enum { |
| 272 | MLX5_NUM_COMMAND_CACHES = 5, |
| 273 | }; |
| 274 | |
| 275 | struct mlx5_cmd_stats { |
| 276 | u64 sum; |
| 277 | u64 n; |
| 278 | /* number of times command failed */ |
| 279 | u64 failed; |
| 280 | /* number of times command failed on bad status returned by FW */ |
| 281 | u64 failed_mbox_status; |
| 282 | /* last command failed returned errno */ |
| 283 | u32 last_failed_errno; |
| 284 | /* last bad status returned by FW */ |
| 285 | u8 last_failed_mbox_status; |
| 286 | /* last command failed syndrome returned by FW */ |
| 287 | u32 last_failed_syndrome; |
| 288 | struct dentry *root; |
| 289 | /* protect command average calculations */ |
| 290 | spinlock_t lock; |
| 291 | }; |
| 292 | |
| 293 | struct mlx5_cmd { |
| 294 | struct mlx5_nb nb; |
| 295 | |
| 296 | /* members which needs to be queried or reinitialized each reload */ |
| 297 | struct { |
| 298 | u16 cmdif_rev; |
| 299 | u8 log_sz; |
| 300 | u8 log_stride; |
| 301 | int max_reg_cmds; |
| 302 | unsigned long bitmask; |
| 303 | struct semaphore sem; |
| 304 | struct semaphore pages_sem; |
| 305 | struct semaphore throttle_sem; |
| 306 | } vars; |
| 307 | enum mlx5_cmdif_state state; |
| 308 | void *cmd_alloc_buf; |
| 309 | dma_addr_t alloc_dma; |
| 310 | int alloc_size; |
| 311 | void *cmd_buf; |
| 312 | dma_addr_t dma; |
| 313 | |
| 314 | /* protect command queue allocations |
| 315 | */ |
| 316 | spinlock_t alloc_lock; |
| 317 | |
| 318 | /* protect token allocations |
| 319 | */ |
| 320 | spinlock_t token_lock; |
| 321 | u8 token; |
| 322 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; |
| 323 | struct workqueue_struct *wq; |
| 324 | int mode; |
| 325 | u16 allowed_opcode; |
| 326 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
| 327 | struct dma_pool *pool; |
| 328 | struct mlx5_cmd_debug dbg; |
| 329 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
| 330 | int checksum_disabled; |
| 331 | struct xarray stats; |
| 332 | }; |
| 333 | |
| 334 | struct mlx5_cmd_mailbox { |
| 335 | void *buf; |
| 336 | dma_addr_t dma; |
| 337 | struct mlx5_cmd_mailbox *next; |
| 338 | }; |
| 339 | |
| 340 | struct mlx5_buf_list { |
| 341 | void *buf; |
| 342 | dma_addr_t map; |
| 343 | }; |
| 344 | |
| 345 | struct mlx5_frag_buf { |
| 346 | struct mlx5_buf_list *frags; |
| 347 | int npages; |
| 348 | int size; |
| 349 | u8 page_shift; |
| 350 | }; |
| 351 | |
| 352 | struct mlx5_frag_buf_ctrl { |
| 353 | struct mlx5_buf_list *frags; |
| 354 | u32 sz_m1; |
| 355 | u16 frag_sz_m1; |
| 356 | u16 strides_offset; |
| 357 | u8 log_sz; |
| 358 | u8 log_stride; |
| 359 | u8 log_frag_strides; |
| 360 | }; |
| 361 | |
| 362 | struct mlx5_core_psv { |
| 363 | u32 psv_idx; |
| 364 | struct psv_layout { |
| 365 | u32 pd; |
| 366 | u16 syndrome; |
| 367 | u16 reserved; |
| 368 | u16 bg; |
| 369 | u16 app_tag; |
| 370 | u32 ref_tag; |
| 371 | } psv; |
| 372 | }; |
| 373 | |
| 374 | struct mlx5_core_sig_ctx { |
| 375 | struct mlx5_core_psv psv_memory; |
| 376 | struct mlx5_core_psv psv_wire; |
| 377 | struct ib_sig_err err_item; |
| 378 | bool sig_status_checked; |
| 379 | bool sig_err_exists; |
| 380 | u32 sigerr_count; |
| 381 | }; |
| 382 | |
| 383 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
| 384 | |
| 385 | enum mlx5_res_type { |
| 386 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
| 387 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, |
| 388 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, |
| 389 | MLX5_RES_SRQ = 3, |
| 390 | MLX5_RES_XSRQ = 4, |
| 391 | MLX5_RES_XRQ = 5, |
| 392 | }; |
| 393 | |
| 394 | struct mlx5_core_rsc_common { |
| 395 | enum mlx5_res_type res; |
| 396 | refcount_t refcount; |
| 397 | struct completion free; |
| 398 | }; |
| 399 | |
| 400 | struct mlx5_uars_page { |
| 401 | void __iomem *map; |
| 402 | bool wc; |
| 403 | u32 index; |
| 404 | struct list_head list; |
| 405 | unsigned int bfregs; |
| 406 | unsigned long *reg_bitmap; /* for non fast path bf regs */ |
| 407 | unsigned long *fp_bitmap; |
| 408 | unsigned int reg_avail; |
| 409 | unsigned int fp_avail; |
| 410 | struct kref ref_count; |
| 411 | struct mlx5_core_dev *mdev; |
| 412 | }; |
| 413 | |
| 414 | struct mlx5_bfreg_head { |
| 415 | /* protect blue flame registers allocations */ |
| 416 | struct mutex lock; |
| 417 | struct list_head list; |
| 418 | }; |
| 419 | |
| 420 | struct mlx5_bfreg_data { |
| 421 | struct mlx5_bfreg_head reg_head; |
| 422 | struct mlx5_bfreg_head wc_head; |
| 423 | }; |
| 424 | |
| 425 | struct mlx5_sq_bfreg { |
| 426 | void __iomem *map; |
| 427 | struct mlx5_uars_page *up; |
| 428 | bool wc; |
| 429 | u32 index; |
| 430 | unsigned int offset; |
| 431 | }; |
| 432 | |
| 433 | struct mlx5_core_health { |
| 434 | struct health_buffer __iomem *health; |
| 435 | __be32 __iomem *health_counter; |
| 436 | struct timer_list timer; |
| 437 | u32 prev; |
| 438 | int miss_counter; |
| 439 | u8 synd; |
| 440 | u32 fatal_error; |
| 441 | u32 crdump_size; |
| 442 | struct workqueue_struct *wq; |
| 443 | unsigned long flags; |
| 444 | struct work_struct fatal_report_work; |
| 445 | struct work_struct report_work; |
| 446 | struct devlink_health_reporter *fw_reporter; |
| 447 | struct devlink_health_reporter *fw_fatal_reporter; |
| 448 | struct devlink_health_reporter *vnic_reporter; |
| 449 | struct delayed_work update_fw_log_ts_work; |
| 450 | }; |
| 451 | |
| 452 | enum { |
| 453 | MLX5_PF_NOTIFY_DISABLE_VF, |
| 454 | MLX5_PF_NOTIFY_ENABLE_VF, |
| 455 | }; |
| 456 | |
| 457 | struct mlx5_vf_context { |
| 458 | int enabled; |
| 459 | u64 port_guid; |
| 460 | u64 node_guid; |
| 461 | /* Valid bits are used to validate administrative guid only. |
| 462 | * Enabled after ndo_set_vf_guid |
| 463 | */ |
| 464 | u8 port_guid_valid:1; |
| 465 | u8 node_guid_valid:1; |
| 466 | enum port_state_policy policy; |
| 467 | struct blocking_notifier_head notifier; |
| 468 | }; |
| 469 | |
| 470 | struct mlx5_core_sriov { |
| 471 | struct mlx5_vf_context *vfs_ctx; |
| 472 | int num_vfs; |
| 473 | u16 max_vfs; |
| 474 | u16 max_ec_vfs; |
| 475 | }; |
| 476 | |
| 477 | struct mlx5_fc_pool { |
| 478 | struct mlx5_core_dev *dev; |
| 479 | struct mutex pool_lock; /* protects pool lists */ |
| 480 | struct list_head fully_used; |
| 481 | struct list_head partially_used; |
| 482 | struct list_head unused; |
| 483 | int available_fcs; |
| 484 | int used_fcs; |
| 485 | int threshold; |
| 486 | }; |
| 487 | |
| 488 | struct mlx5_fc_stats { |
| 489 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
| 490 | struct idr counters_idr; |
| 491 | struct list_head counters; |
| 492 | struct llist_head addlist; |
| 493 | struct llist_head dellist; |
| 494 | |
| 495 | struct workqueue_struct *wq; |
| 496 | struct delayed_work work; |
| 497 | unsigned long next_query; |
| 498 | unsigned long sampling_interval; /* jiffies */ |
| 499 | u32 *bulk_query_out; |
| 500 | int bulk_query_len; |
| 501 | size_t num_counters; |
| 502 | bool bulk_query_alloc_failed; |
| 503 | unsigned long next_bulk_query_alloc; |
| 504 | struct mlx5_fc_pool fc_pool; |
| 505 | }; |
| 506 | |
| 507 | struct mlx5_events; |
| 508 | struct mlx5_mpfs; |
| 509 | struct mlx5_eswitch; |
| 510 | struct mlx5_lag; |
| 511 | struct mlx5_devcom_dev; |
| 512 | struct mlx5_fw_reset; |
| 513 | struct mlx5_eq_table; |
| 514 | struct mlx5_irq_table; |
| 515 | struct mlx5_vhca_state_notifier; |
| 516 | struct mlx5_sf_dev_table; |
| 517 | struct mlx5_sf_hw_table; |
| 518 | struct mlx5_sf_table; |
| 519 | struct mlx5_crypto_dek_priv; |
| 520 | |
| 521 | struct mlx5_rate_limit { |
| 522 | u32 rate; |
| 523 | u32 max_burst_sz; |
| 524 | u16 typical_pkt_sz; |
| 525 | }; |
| 526 | |
| 527 | struct mlx5_rl_entry { |
| 528 | u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; |
| 529 | u64 refcount; |
| 530 | u16 index; |
| 531 | u16 uid; |
| 532 | u8 dedicated : 1; |
| 533 | }; |
| 534 | |
| 535 | struct mlx5_rl_table { |
| 536 | /* protect rate limit table */ |
| 537 | struct mutex rl_lock; |
| 538 | u16 max_size; |
| 539 | u32 max_rate; |
| 540 | u32 min_rate; |
| 541 | struct mlx5_rl_entry *rl_entry; |
| 542 | u64 refcount; |
| 543 | }; |
| 544 | |
| 545 | struct mlx5_core_roce { |
| 546 | struct mlx5_flow_table *ft; |
| 547 | struct mlx5_flow_group *fg; |
| 548 | struct mlx5_flow_handle *allow_rule; |
| 549 | }; |
| 550 | |
| 551 | enum { |
| 552 | MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0, |
| 553 | MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1, |
| 554 | /* Set during device detach to block any further devices |
| 555 | * creation/deletion on drivers rescan. Unset during device attach. |
| 556 | */ |
| 557 | MLX5_PRIV_FLAGS_DETACH = 1 << 2, |
| 558 | }; |
| 559 | |
| 560 | struct mlx5_adev { |
| 561 | struct auxiliary_device adev; |
| 562 | struct mlx5_core_dev *mdev; |
| 563 | int idx; |
| 564 | }; |
| 565 | |
| 566 | struct mlx5_debugfs_entries { |
| 567 | struct dentry *dbg_root; |
| 568 | struct dentry *qp_debugfs; |
| 569 | struct dentry *eq_debugfs; |
| 570 | struct dentry *cq_debugfs; |
| 571 | struct dentry *cmdif_debugfs; |
| 572 | struct dentry *pages_debugfs; |
| 573 | struct dentry *lag_debugfs; |
| 574 | }; |
| 575 | |
| 576 | enum mlx5_func_type { |
| 577 | MLX5_PF, |
| 578 | MLX5_VF, |
| 579 | MLX5_SF, |
| 580 | MLX5_HOST_PF, |
| 581 | MLX5_EC_VF, |
| 582 | MLX5_FUNC_TYPE_NUM, |
| 583 | }; |
| 584 | |
| 585 | struct mlx5_ft_pool; |
| 586 | struct mlx5_priv { |
| 587 | /* IRQ table valid only for real pci devices PF or VF */ |
| 588 | struct mlx5_irq_table *irq_table; |
| 589 | struct mlx5_eq_table *eq_table; |
| 590 | |
| 591 | /* pages stuff */ |
| 592 | struct mlx5_nb pg_nb; |
| 593 | struct workqueue_struct *pg_wq; |
| 594 | struct xarray page_root_xa; |
| 595 | atomic_t reg_pages; |
| 596 | struct list_head free_list; |
| 597 | u32 fw_pages; |
| 598 | u32 page_counters[MLX5_FUNC_TYPE_NUM]; |
| 599 | u32 fw_pages_alloc_failed; |
| 600 | u32 give_pages_dropped; |
| 601 | u32 reclaim_pages_discard; |
| 602 | |
| 603 | struct mlx5_core_health health; |
| 604 | struct list_head traps; |
| 605 | |
| 606 | struct mlx5_debugfs_entries dbg; |
| 607 | |
| 608 | /* start: alloc staff */ |
| 609 | /* protect buffer allocation according to numa node */ |
| 610 | struct mutex alloc_mutex; |
| 611 | int numa_node; |
| 612 | |
| 613 | struct mutex pgdir_mutex; |
| 614 | struct list_head pgdir_list; |
| 615 | /* end: alloc staff */ |
| 616 | |
| 617 | struct mlx5_adev **adev; |
| 618 | int adev_idx; |
| 619 | int sw_vhca_id; |
| 620 | struct mlx5_events *events; |
| 621 | struct mlx5_vhca_events *vhca_events; |
| 622 | |
| 623 | struct mlx5_flow_steering *steering; |
| 624 | struct mlx5_mpfs *mpfs; |
| 625 | struct mlx5_eswitch *eswitch; |
| 626 | struct mlx5_core_sriov sriov; |
| 627 | struct mlx5_lag *lag; |
| 628 | u32 flags; |
| 629 | struct mlx5_devcom_dev *devc; |
| 630 | struct mlx5_devcom_comp_dev *hca_devcom_comp; |
| 631 | struct mlx5_fw_reset *fw_reset; |
| 632 | struct mlx5_core_roce roce; |
| 633 | struct mlx5_fc_stats fc_stats; |
| 634 | struct mlx5_rl_table rl_table; |
| 635 | struct mlx5_ft_pool *ft_pool; |
| 636 | |
| 637 | struct mlx5_bfreg_data bfregs; |
| 638 | struct mlx5_uars_page *uar; |
| 639 | #ifdef CONFIG_MLX5_SF |
| 640 | struct mlx5_vhca_state_notifier *vhca_state_notifier; |
| 641 | struct mlx5_sf_dev_table *sf_dev_table; |
| 642 | struct mlx5_core_dev *parent_mdev; |
| 643 | #endif |
| 644 | #ifdef CONFIG_MLX5_SF_MANAGER |
| 645 | struct mlx5_sf_hw_table *sf_hw_table; |
| 646 | struct mlx5_sf_table *sf_table; |
| 647 | #endif |
| 648 | struct blocking_notifier_head lag_nh; |
| 649 | }; |
| 650 | |
| 651 | enum mlx5_device_state { |
| 652 | MLX5_DEVICE_STATE_UP = 1, |
| 653 | MLX5_DEVICE_STATE_INTERNAL_ERROR, |
| 654 | }; |
| 655 | |
| 656 | enum mlx5_interface_state { |
| 657 | MLX5_INTERFACE_STATE_UP = BIT(0), |
| 658 | MLX5_BREAK_FW_WAIT = BIT(1), |
| 659 | }; |
| 660 | |
| 661 | enum mlx5_pci_status { |
| 662 | MLX5_PCI_STATUS_DISABLED, |
| 663 | MLX5_PCI_STATUS_ENABLED, |
| 664 | }; |
| 665 | |
| 666 | enum mlx5_pagefault_type_flags { |
| 667 | MLX5_PFAULT_REQUESTOR = 1 << 0, |
| 668 | MLX5_PFAULT_WRITE = 1 << 1, |
| 669 | MLX5_PFAULT_RDMA = 1 << 2, |
| 670 | }; |
| 671 | |
| 672 | struct mlx5_td { |
| 673 | /* protects tirs list changes while tirs refresh */ |
| 674 | struct mutex list_lock; |
| 675 | struct list_head tirs_list; |
| 676 | u32 tdn; |
| 677 | }; |
| 678 | |
| 679 | struct mlx5e_resources { |
| 680 | struct mlx5e_hw_objs { |
| 681 | u32 pdn; |
| 682 | struct mlx5_td td; |
| 683 | u32 mkey; |
| 684 | struct mlx5_sq_bfreg bfreg; |
| 685 | #define MLX5_MAX_NUM_TC 8 |
| 686 | u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC]; |
| 687 | bool tisn_valid; |
| 688 | } hw_objs; |
| 689 | struct net_device *uplink_netdev; |
| 690 | struct mutex uplink_netdev_lock; |
| 691 | struct mlx5_crypto_dek_priv *dek_priv; |
| 692 | }; |
| 693 | |
| 694 | enum mlx5_sw_icm_type { |
| 695 | MLX5_SW_ICM_TYPE_STEERING, |
| 696 | MLX5_SW_ICM_TYPE_HEADER_MODIFY, |
| 697 | MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN, |
| 698 | MLX5_SW_ICM_TYPE_SW_ENCAP, |
| 699 | }; |
| 700 | |
| 701 | #define MLX5_MAX_RESERVED_GIDS 8 |
| 702 | |
| 703 | struct mlx5_rsvd_gids { |
| 704 | unsigned int start; |
| 705 | unsigned int count; |
| 706 | struct ida ida; |
| 707 | }; |
| 708 | |
| 709 | #define MAX_PIN_NUM 8 |
| 710 | struct mlx5_pps { |
| 711 | u8 pin_caps[MAX_PIN_NUM]; |
| 712 | struct work_struct out_work; |
| 713 | u64 start[MAX_PIN_NUM]; |
| 714 | u8 enabled; |
| 715 | u64 min_npps_period; |
| 716 | u64 min_out_pulse_duration_ns; |
| 717 | }; |
| 718 | |
| 719 | struct mlx5_timer { |
| 720 | struct cyclecounter cycles; |
| 721 | struct timecounter tc; |
| 722 | u32 nominal_c_mult; |
| 723 | unsigned long overflow_period; |
| 724 | struct delayed_work overflow_work; |
| 725 | }; |
| 726 | |
| 727 | struct mlx5_clock { |
| 728 | struct mlx5_nb pps_nb; |
| 729 | seqlock_t lock; |
| 730 | struct hwtstamp_config hwtstamp_config; |
| 731 | struct ptp_clock *ptp; |
| 732 | struct ptp_clock_info ptp_info; |
| 733 | struct mlx5_pps pps_info; |
| 734 | struct mlx5_timer timer; |
| 735 | }; |
| 736 | |
| 737 | struct mlx5_dm; |
| 738 | struct mlx5_fw_tracer; |
| 739 | struct mlx5_vxlan; |
| 740 | struct mlx5_geneve; |
| 741 | struct mlx5_hv_vhca; |
| 742 | |
| 743 | #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) |
| 744 | #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) |
| 745 | |
| 746 | enum { |
| 747 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, |
| 748 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
| 749 | }; |
| 750 | |
| 751 | enum { |
| 752 | MKEY_CACHE_LAST_STD_ENTRY = 20, |
| 753 | MLX5_IMR_KSM_CACHE_ENTRY, |
| 754 | MAX_MKEY_CACHE_ENTRIES |
| 755 | }; |
| 756 | |
| 757 | struct mlx5_profile { |
| 758 | u64 mask; |
| 759 | u8 log_max_qp; |
| 760 | u8 num_cmd_caches; |
| 761 | struct { |
| 762 | int size; |
| 763 | int limit; |
| 764 | } mr_cache[MAX_MKEY_CACHE_ENTRIES]; |
| 765 | }; |
| 766 | |
| 767 | struct mlx5_hca_cap { |
| 768 | u32 cur[MLX5_UN_SZ_DW(hca_cap_union)]; |
| 769 | u32 max[MLX5_UN_SZ_DW(hca_cap_union)]; |
| 770 | }; |
| 771 | |
| 772 | enum mlx5_wc_state { |
| 773 | MLX5_WC_STATE_UNINITIALIZED, |
| 774 | MLX5_WC_STATE_UNSUPPORTED, |
| 775 | MLX5_WC_STATE_SUPPORTED, |
| 776 | }; |
| 777 | |
| 778 | struct mlx5_core_dev { |
| 779 | struct device *device; |
| 780 | enum mlx5_coredev_type coredev_type; |
| 781 | struct pci_dev *pdev; |
| 782 | /* sync pci state */ |
| 783 | struct mutex pci_status_mutex; |
| 784 | enum mlx5_pci_status pci_status; |
| 785 | u8 rev_id; |
| 786 | char board_id[MLX5_BOARD_ID_LEN]; |
| 787 | struct mlx5_cmd cmd; |
| 788 | struct { |
| 789 | struct mlx5_hca_cap *hca[MLX5_CAP_NUM]; |
| 790 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
| 791 | u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; |
| 792 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
| 793 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
| 794 | u8 embedded_cpu; |
| 795 | } caps; |
| 796 | struct mlx5_timeouts *timeouts; |
| 797 | u64 sys_image_guid; |
| 798 | phys_addr_t iseg_base; |
| 799 | struct mlx5_init_seg __iomem *iseg; |
| 800 | phys_addr_t bar_addr; |
| 801 | enum mlx5_device_state state; |
| 802 | /* sync interface state */ |
| 803 | struct mutex intf_state_mutex; |
| 804 | struct lock_class_key lock_key; |
| 805 | unsigned long intf_state; |
| 806 | struct mlx5_priv priv; |
| 807 | struct mlx5_profile profile; |
| 808 | u32 issi; |
| 809 | struct mlx5e_resources mlx5e_res; |
| 810 | struct mlx5_dm *dm; |
| 811 | struct mlx5_vxlan *vxlan; |
| 812 | struct mlx5_geneve *geneve; |
| 813 | struct { |
| 814 | struct mlx5_rsvd_gids reserved_gids; |
| 815 | u32 roce_en; |
| 816 | } roce; |
| 817 | #ifdef CONFIG_MLX5_FPGA |
| 818 | struct mlx5_fpga_device *fpga; |
| 819 | #endif |
| 820 | struct mlx5_clock clock; |
| 821 | struct mlx5_ib_clock_info *clock_info; |
| 822 | struct mlx5_fw_tracer *tracer; |
| 823 | struct mlx5_rsc_dump *rsc_dump; |
| 824 | u32 vsc_addr; |
| 825 | struct mlx5_hv_vhca *hv_vhca; |
| 826 | struct mlx5_hwmon *hwmon; |
| 827 | u64 num_block_tc; |
| 828 | u64 num_block_ipsec; |
| 829 | #ifdef CONFIG_MLX5_MACSEC |
| 830 | struct mlx5_macsec_fs *macsec_fs; |
| 831 | /* MACsec notifier chain to sync MACsec core and IB database */ |
| 832 | struct blocking_notifier_head macsec_nh; |
| 833 | #endif |
| 834 | u64 num_ipsec_offloads; |
| 835 | struct mlx5_sd *sd; |
| 836 | enum mlx5_wc_state wc_state; |
| 837 | /* sync write combining state */ |
| 838 | struct mutex wc_state_lock; |
| 839 | }; |
| 840 | |
| 841 | struct mlx5_db { |
| 842 | __be32 *db; |
| 843 | union { |
| 844 | struct mlx5_db_pgdir *pgdir; |
| 845 | struct mlx5_ib_user_db_page *user_page; |
| 846 | } u; |
| 847 | dma_addr_t dma; |
| 848 | int index; |
| 849 | }; |
| 850 | |
| 851 | enum { |
| 852 | MLX5_COMP_EQ_SIZE = 1024, |
| 853 | }; |
| 854 | |
| 855 | enum { |
| 856 | MLX5_PTYS_IB = 1 << 0, |
| 857 | MLX5_PTYS_EN = 1 << 2, |
| 858 | }; |
| 859 | |
| 860 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
| 861 | |
| 862 | enum { |
| 863 | MLX5_CMD_ENT_STATE_PENDING_COMP, |
| 864 | }; |
| 865 | |
| 866 | struct mlx5_cmd_work_ent { |
| 867 | unsigned long state; |
| 868 | struct mlx5_cmd_msg *in; |
| 869 | struct mlx5_cmd_msg *out; |
| 870 | void *uout; |
| 871 | int uout_size; |
| 872 | mlx5_cmd_cbk_t callback; |
| 873 | struct delayed_work cb_timeout_work; |
| 874 | void *context; |
| 875 | int idx; |
| 876 | struct completion handling; |
| 877 | struct completion slotted; |
| 878 | struct completion done; |
| 879 | struct mlx5_cmd *cmd; |
| 880 | struct work_struct work; |
| 881 | struct mlx5_cmd_layout *lay; |
| 882 | int ret; |
| 883 | int page_queue; |
| 884 | u8 status; |
| 885 | u8 token; |
| 886 | u64 ts1; |
| 887 | u64 ts2; |
| 888 | u16 op; |
| 889 | bool polling; |
| 890 | /* Track the max comp handlers */ |
| 891 | refcount_t refcnt; |
| 892 | }; |
| 893 | |
| 894 | enum phy_port_state { |
| 895 | MLX5_AAA_111 |
| 896 | }; |
| 897 | |
| 898 | struct mlx5_hca_vport_context { |
| 899 | u32 field_select; |
| 900 | bool sm_virt_aware; |
| 901 | bool has_smi; |
| 902 | bool has_raw; |
| 903 | enum port_state_policy policy; |
| 904 | enum phy_port_state phys_state; |
| 905 | enum ib_port_state vport_state; |
| 906 | u8 port_physical_state; |
| 907 | u64 sys_image_guid; |
| 908 | u64 port_guid; |
| 909 | u64 node_guid; |
| 910 | u32 cap_mask1; |
| 911 | u32 cap_mask1_perm; |
| 912 | u16 cap_mask2; |
| 913 | u16 cap_mask2_perm; |
| 914 | u16 lid; |
| 915 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ |
| 916 | u8 lmc; |
| 917 | u8 subnet_timeout; |
| 918 | u16 sm_lid; |
| 919 | u8 sm_sl; |
| 920 | u16 qkey_violation_counter; |
| 921 | u16 pkey_violation_counter; |
| 922 | bool grh_required; |
| 923 | u8 num_plane; |
| 924 | }; |
| 925 | |
| 926 | #define STRUCT_FIELD(header, field) \ |
| 927 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ |
| 928 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field |
| 929 | |
| 930 | extern struct dentry *mlx5_debugfs_root; |
| 931 | |
| 932 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) |
| 933 | { |
| 934 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; |
| 935 | } |
| 936 | |
| 937 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) |
| 938 | { |
| 939 | return ioread32be(&dev->iseg->fw_rev) >> 16; |
| 940 | } |
| 941 | |
| 942 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) |
| 943 | { |
| 944 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; |
| 945 | } |
| 946 | |
| 947 | static inline u32 mlx5_base_mkey(const u32 key) |
| 948 | { |
| 949 | return key & 0xffffff00u; |
| 950 | } |
| 951 | |
| 952 | static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride) |
| 953 | { |
| 954 | return ((u32)1 << log_sz) << log_stride; |
| 955 | } |
| 956 | |
| 957 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
| 958 | u8 log_stride, u8 log_sz, |
| 959 | u16 strides_offset, |
| 960 | struct mlx5_frag_buf_ctrl *fbc) |
| 961 | { |
| 962 | fbc->frags = frags; |
| 963 | fbc->log_stride = log_stride; |
| 964 | fbc->log_sz = log_sz; |
| 965 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
| 966 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; |
| 967 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; |
| 968 | fbc->strides_offset = strides_offset; |
| 969 | } |
| 970 | |
| 971 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
| 972 | u8 log_stride, u8 log_sz, |
| 973 | struct mlx5_frag_buf_ctrl *fbc) |
| 974 | { |
| 975 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
| 976 | } |
| 977 | |
| 978 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
| 979 | u32 ix) |
| 980 | { |
| 981 | unsigned int frag; |
| 982 | |
| 983 | ix += fbc->strides_offset; |
| 984 | frag = ix >> fbc->log_frag_strides; |
| 985 | |
| 986 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
| 987 | } |
| 988 | |
| 989 | static inline u32 |
| 990 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) |
| 991 | { |
| 992 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; |
| 993 | |
| 994 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); |
| 995 | } |
| 996 | |
| 997 | enum { |
| 998 | CMD_ALLOWED_OPCODE_ALL, |
| 999 | }; |
| 1000 | |
| 1001 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); |
| 1002 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); |
| 1003 | void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode); |
| 1004 | |
| 1005 | struct mlx5_async_ctx { |
| 1006 | struct mlx5_core_dev *dev; |
| 1007 | atomic_t num_inflight; |
| 1008 | struct completion inflight_done; |
| 1009 | }; |
| 1010 | |
| 1011 | struct mlx5_async_work; |
| 1012 | |
| 1013 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); |
| 1014 | |
| 1015 | struct mlx5_async_work { |
| 1016 | struct mlx5_async_ctx *ctx; |
| 1017 | mlx5_async_cbk_t user_callback; |
| 1018 | u16 opcode; /* cmd opcode */ |
| 1019 | u16 op_mod; /* cmd op_mod */ |
| 1020 | void *out; /* pointer to the cmd output buffer */ |
| 1021 | }; |
| 1022 | |
| 1023 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, |
| 1024 | struct mlx5_async_ctx *ctx); |
| 1025 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); |
| 1026 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, |
| 1027 | void *out, int out_size, mlx5_async_cbk_t callback, |
| 1028 | struct mlx5_async_work *work); |
| 1029 | void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out); |
| 1030 | int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size); |
| 1031 | int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out); |
| 1032 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
| 1033 | int out_size); |
| 1034 | |
| 1035 | #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \ |
| 1036 | ({ \ |
| 1037 | mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \ |
| 1038 | MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \ |
| 1039 | }) |
| 1040 | |
| 1041 | #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \ |
| 1042 | ({ \ |
| 1043 | u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \ |
| 1044 | mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \ |
| 1045 | }) |
| 1046 | |
| 1047 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
| 1048 | void *out, int out_size); |
| 1049 | bool mlx5_cmd_is_down(struct mlx5_core_dev *dev); |
| 1050 | |
| 1051 | void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev); |
| 1052 | void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev); |
| 1053 | |
| 1054 | void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data); |
| 1055 | |
| 1056 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
| 1057 | int mlx5_health_init(struct mlx5_core_dev *dev); |
| 1058 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
| 1059 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
| 1060 | void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev); |
| 1061 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
| 1062 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
| 1063 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
| 1064 | struct mlx5_frag_buf *buf, int node); |
| 1065 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); |
| 1066 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in, |
| 1067 | int inlen); |
| 1068 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey); |
| 1069 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out, |
| 1070 | int outlen); |
| 1071 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
| 1072 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); |
| 1073 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
| 1074 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
| 1075 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
| 1076 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
| 1077 | void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev); |
| 1078 | void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 1079 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
| 1080 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
| 1081 | void mlx5_register_debugfs(void); |
| 1082 | void mlx5_unregister_debugfs(void); |
| 1083 | |
| 1084 | void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm); |
| 1085 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
| 1086 | int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn); |
| 1087 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
| 1088 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
| 1089 | |
| 1090 | struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev); |
| 1091 | void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
| 1092 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 1093 | int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in, |
| 1094 | void *data_out, int size_out, u16 reg_id, int arg, |
| 1095 | int write, bool verbose); |
| 1096 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, |
| 1097 | int size_in, void *data_out, int size_out, |
| 1098 | u16 reg_num, int arg, int write); |
| 1099 | |
| 1100 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
| 1101 | int node); |
| 1102 | |
| 1103 | static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db) |
| 1104 | { |
| 1105 | return mlx5_db_alloc_node(dev, db, dev->priv.numa_node); |
| 1106 | } |
| 1107 | |
| 1108 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
| 1109 | |
| 1110 | const char *mlx5_command_str(int command); |
| 1111 | void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
| 1112 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 1113 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
| 1114 | int npsvs, u32 *sig_index); |
| 1115 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); |
| 1116 | __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev); |
| 1117 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
| 1118 | |
| 1119 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
| 1120 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); |
| 1121 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
| 1122 | struct mlx5_rate_limit *rl); |
| 1123 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); |
| 1124 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
| 1125 | int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, |
| 1126 | bool dedicated_entry, u16 *index); |
| 1127 | void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); |
| 1128 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
| 1129 | struct mlx5_rate_limit *rl_1); |
| 1130 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
| 1131 | bool map_wc, bool fast_path); |
| 1132 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); |
| 1133 | |
| 1134 | unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev); |
| 1135 | int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector); |
| 1136 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
| 1137 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, |
| 1138 | u8 roce_version, u8 roce_l3_type, const u8 *gid, |
| 1139 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
| 1140 | |
| 1141 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
| 1142 | { |
| 1143 | return mkey >> 8; |
| 1144 | } |
| 1145 | |
| 1146 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) |
| 1147 | { |
| 1148 | return mkey_idx << 8; |
| 1149 | } |
| 1150 | |
| 1151 | static inline u8 mlx5_mkey_variant(u32 mkey) |
| 1152 | { |
| 1153 | return mkey & 0xff; |
| 1154 | } |
| 1155 | |
| 1156 | /* Async-atomic event notifier used by mlx5 core to forward FW |
| 1157 | * evetns received from event queue to mlx5 consumers. |
| 1158 | * Optimise event queue dipatching. |
| 1159 | */ |
| 1160 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
| 1161 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); |
| 1162 | |
| 1163 | /* Async-atomic event notifier used for forwarding |
| 1164 | * evetns from the event queue into the to mlx5 events dispatcher, |
| 1165 | * eswitch, clock and others. |
| 1166 | */ |
| 1167 | int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
| 1168 | int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
| 1169 | |
| 1170 | /* Blocking event notifier used to forward SW events, used for slow path */ |
| 1171 | int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
| 1172 | int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); |
| 1173 | int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event, |
| 1174 | void *data); |
| 1175 | |
| 1176 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
| 1177 | |
| 1178 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
| 1179 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); |
| 1180 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
| 1181 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); |
| 1182 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
| 1183 | bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev); |
| 1184 | bool mlx5_lag_is_master(struct mlx5_core_dev *dev); |
| 1185 | bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev); |
| 1186 | bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev); |
| 1187 | u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev, |
| 1188 | struct net_device *slave); |
| 1189 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
| 1190 | u64 *values, |
| 1191 | int num_counters, |
| 1192 | size_t *offsets); |
| 1193 | struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i); |
| 1194 | |
| 1195 | #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \ |
| 1196 | for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \ |
| 1197 | peer; \ |
| 1198 | peer = mlx5_lag_get_next_peer_mdev(dev, &i)) |
| 1199 | |
| 1200 | u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev); |
| 1201 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
| 1202 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); |
| 1203 | int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
| 1204 | u64 length, u32 log_alignment, u16 uid, |
| 1205 | phys_addr_t *addr, u32 *obj_id); |
| 1206 | int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
| 1207 | u64 length, u16 uid, phys_addr_t addr, u32 obj_id); |
| 1208 | |
| 1209 | struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev); |
| 1210 | void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev); |
| 1211 | |
| 1212 | int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev, |
| 1213 | int vf_id, |
| 1214 | struct notifier_block *nb); |
| 1215 | void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev, |
| 1216 | int vf_id, |
| 1217 | struct notifier_block *nb); |
| 1218 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
| 1219 | struct ib_device *device, |
| 1220 | struct rdma_netdev_alloc_params *params); |
| 1221 | |
| 1222 | enum { |
| 1223 | MLX5_PCI_DEV_IS_VF = 1 << 0, |
| 1224 | }; |
| 1225 | |
| 1226 | static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) |
| 1227 | { |
| 1228 | return dev->coredev_type == MLX5_COREDEV_PF; |
| 1229 | } |
| 1230 | |
| 1231 | static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) |
| 1232 | { |
| 1233 | return dev->coredev_type == MLX5_COREDEV_VF; |
| 1234 | } |
| 1235 | |
| 1236 | static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev) |
| 1237 | { |
| 1238 | return dev->caps.embedded_cpu; |
| 1239 | } |
| 1240 | |
| 1241 | static inline bool |
| 1242 | mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) |
| 1243 | { |
| 1244 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); |
| 1245 | } |
| 1246 | |
| 1247 | static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) |
| 1248 | { |
| 1249 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); |
| 1250 | } |
| 1251 | |
| 1252 | static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) |
| 1253 | { |
| 1254 | return dev->priv.sriov.max_vfs; |
| 1255 | } |
| 1256 | |
| 1257 | static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev) |
| 1258 | { |
| 1259 | /* LACP owner conditions: |
| 1260 | * 1) Function is physical. |
| 1261 | * 2) LAG is supported by FW. |
| 1262 | * 3) LAG is managed by driver (currently the only option). |
| 1263 | */ |
| 1264 | return MLX5_CAP_GEN(dev, vport_group_manager) && |
| 1265 | (MLX5_CAP_GEN(dev, num_lag_ports) > 1) && |
| 1266 | MLX5_CAP_GEN(dev, lag_master); |
| 1267 | } |
| 1268 | |
| 1269 | static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev) |
| 1270 | { |
| 1271 | return dev->priv.sriov.max_ec_vfs; |
| 1272 | } |
| 1273 | |
| 1274 | static inline int mlx5_get_gid_table_len(u16 param) |
| 1275 | { |
| 1276 | if (param > 4) { |
| 1277 | pr_warn("gid table length is zero\n"); |
| 1278 | return 0; |
| 1279 | } |
| 1280 | |
| 1281 | return 8 * (1 << param); |
| 1282 | } |
| 1283 | |
| 1284 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
| 1285 | { |
| 1286 | return !!(dev->priv.rl_table.max_size); |
| 1287 | } |
| 1288 | |
| 1289 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
| 1290 | { |
| 1291 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && |
| 1292 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; |
| 1293 | } |
| 1294 | |
| 1295 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) |
| 1296 | { |
| 1297 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; |
| 1298 | } |
| 1299 | |
| 1300 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) |
| 1301 | { |
| 1302 | return mlx5_core_is_mp_slave(dev) || |
| 1303 | mlx5_core_is_mp_master(dev); |
| 1304 | } |
| 1305 | |
| 1306 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
| 1307 | { |
| 1308 | if (!mlx5_core_mp_enabled(dev)) |
| 1309 | return 1; |
| 1310 | |
| 1311 | return MLX5_CAP_GEN(dev, native_port_num); |
| 1312 | } |
| 1313 | |
| 1314 | static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev) |
| 1315 | { |
| 1316 | int idx = MLX5_CAP_GEN(dev, native_port_num); |
| 1317 | |
| 1318 | if (idx >= 1 && idx <= MLX5_MAX_PORTS) |
| 1319 | return idx - 1; |
| 1320 | else |
| 1321 | return PCI_FUNC(dev->pdev->devfn); |
| 1322 | } |
| 1323 | |
| 1324 | enum { |
| 1325 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, |
| 1326 | }; |
| 1327 | |
| 1328 | bool mlx5_is_roce_on(struct mlx5_core_dev *dev); |
| 1329 | |
| 1330 | static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev) |
| 1331 | { |
| 1332 | if (MLX5_CAP_GEN(dev, roce_rw_supported)) |
| 1333 | return MLX5_CAP_GEN(dev, roce); |
| 1334 | |
| 1335 | /* If RoCE cap is read-only in FW, get RoCE state from devlink |
| 1336 | * in order to support RoCE enable/disable feature |
| 1337 | */ |
| 1338 | return mlx5_is_roce_on(dev); |
| 1339 | } |
| 1340 | |
| 1341 | #ifdef CONFIG_MLX5_MACSEC |
| 1342 | static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev) |
| 1343 | { |
| 1344 | if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) & |
| 1345 | MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD)) |
| 1346 | return false; |
| 1347 | |
| 1348 | if (!MLX5_CAP_GEN(mdev, log_max_dek)) |
| 1349 | return false; |
| 1350 | |
| 1351 | if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload)) |
| 1352 | return false; |
| 1353 | |
| 1354 | if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) || |
| 1355 | !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec)) |
| 1356 | return false; |
| 1357 | |
| 1358 | if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) || |
| 1359 | !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec)) |
| 1360 | return false; |
| 1361 | |
| 1362 | if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) && |
| 1363 | !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt)) |
| 1364 | return false; |
| 1365 | |
| 1366 | if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) && |
| 1367 | !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt)) |
| 1368 | return false; |
| 1369 | |
| 1370 | return true; |
| 1371 | } |
| 1372 | |
| 1373 | #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX) |
| 1374 | |
| 1375 | static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev) |
| 1376 | { |
| 1377 | if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) & |
| 1378 | NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) || |
| 1379 | !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) || |
| 1380 | !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs) |
| 1381 | return false; |
| 1382 | |
| 1383 | return true; |
| 1384 | } |
| 1385 | #endif |
| 1386 | |
| 1387 | enum { |
| 1388 | MLX5_OCTWORD = 16, |
| 1389 | }; |
| 1390 | |
| 1391 | bool mlx5_wc_support_get(struct mlx5_core_dev *mdev); |
| 1392 | #endif /* MLX5_DRIVER_H */ |