| 1 | /* |
| 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #ifndef MLX5_DRIVER_H |
| 34 | #define MLX5_DRIVER_H |
| 35 | |
| 36 | #include <linux/kernel.h> |
| 37 | #include <linux/completion.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/irq.h> |
| 40 | #include <linux/spinlock_types.h> |
| 41 | #include <linux/semaphore.h> |
| 42 | #include <linux/slab.h> |
| 43 | #include <linux/vmalloc.h> |
| 44 | #include <linux/radix-tree.h> |
| 45 | #include <linux/workqueue.h> |
| 46 | #include <linux/mempool.h> |
| 47 | #include <linux/interrupt.h> |
| 48 | #include <linux/idr.h> |
| 49 | |
| 50 | #include <linux/mlx5/device.h> |
| 51 | #include <linux/mlx5/doorbell.h> |
| 52 | #include <linux/mlx5/srq.h> |
| 53 | #include <linux/timecounter.h> |
| 54 | #include <linux/ptp_clock_kernel.h> |
| 55 | |
| 56 | enum { |
| 57 | MLX5_BOARD_ID_LEN = 64, |
| 58 | MLX5_MAX_NAME_LEN = 16, |
| 59 | }; |
| 60 | |
| 61 | enum { |
| 62 | /* one minute for the sake of bringup. Generally, commands must always |
| 63 | * complete and we may need to increase this timeout value |
| 64 | */ |
| 65 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
| 66 | MLX5_CMD_WQ_MAX_NAME = 32, |
| 67 | }; |
| 68 | |
| 69 | enum { |
| 70 | CMD_OWNER_SW = 0x0, |
| 71 | CMD_OWNER_HW = 0x1, |
| 72 | CMD_STATUS_SUCCESS = 0, |
| 73 | }; |
| 74 | |
| 75 | enum mlx5_sqp_t { |
| 76 | MLX5_SQP_SMI = 0, |
| 77 | MLX5_SQP_GSI = 1, |
| 78 | MLX5_SQP_IEEE_1588 = 2, |
| 79 | MLX5_SQP_SNIFFER = 3, |
| 80 | MLX5_SQP_SYNC_UMR = 4, |
| 81 | }; |
| 82 | |
| 83 | enum { |
| 84 | MLX5_MAX_PORTS = 2, |
| 85 | }; |
| 86 | |
| 87 | enum { |
| 88 | MLX5_EQ_VEC_PAGES = 0, |
| 89 | MLX5_EQ_VEC_CMD = 1, |
| 90 | MLX5_EQ_VEC_ASYNC = 2, |
| 91 | MLX5_EQ_VEC_PFAULT = 3, |
| 92 | MLX5_EQ_VEC_COMP_BASE, |
| 93 | }; |
| 94 | |
| 95 | enum { |
| 96 | MLX5_MAX_IRQ_NAME = 32 |
| 97 | }; |
| 98 | |
| 99 | enum { |
| 100 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, |
| 101 | MLX5_ATOMIC_MODE_CX = 2 << 16, |
| 102 | MLX5_ATOMIC_MODE_8B = 3 << 16, |
| 103 | MLX5_ATOMIC_MODE_16B = 4 << 16, |
| 104 | MLX5_ATOMIC_MODE_32B = 5 << 16, |
| 105 | MLX5_ATOMIC_MODE_64B = 6 << 16, |
| 106 | MLX5_ATOMIC_MODE_128B = 7 << 16, |
| 107 | MLX5_ATOMIC_MODE_256B = 8 << 16, |
| 108 | }; |
| 109 | |
| 110 | enum { |
| 111 | MLX5_REG_QPTS = 0x4002, |
| 112 | MLX5_REG_QETCR = 0x4005, |
| 113 | MLX5_REG_QTCT = 0x400a, |
| 114 | MLX5_REG_QPDPM = 0x4013, |
| 115 | MLX5_REG_QCAM = 0x4019, |
| 116 | MLX5_REG_DCBX_PARAM = 0x4020, |
| 117 | MLX5_REG_DCBX_APP = 0x4021, |
| 118 | MLX5_REG_FPGA_CAP = 0x4022, |
| 119 | MLX5_REG_FPGA_CTRL = 0x4023, |
| 120 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
| 121 | MLX5_REG_PCAP = 0x5001, |
| 122 | MLX5_REG_PMTU = 0x5003, |
| 123 | MLX5_REG_PTYS = 0x5004, |
| 124 | MLX5_REG_PAOS = 0x5006, |
| 125 | MLX5_REG_PFCC = 0x5007, |
| 126 | MLX5_REG_PPCNT = 0x5008, |
| 127 | MLX5_REG_PPTB = 0x500b, |
| 128 | MLX5_REG_PBMC = 0x500c, |
| 129 | MLX5_REG_PMAOS = 0x5012, |
| 130 | MLX5_REG_PUDE = 0x5009, |
| 131 | MLX5_REG_PMPE = 0x5010, |
| 132 | MLX5_REG_PELC = 0x500e, |
| 133 | MLX5_REG_PVLC = 0x500f, |
| 134 | MLX5_REG_PCMR = 0x5041, |
| 135 | MLX5_REG_PMLP = 0x5002, |
| 136 | MLX5_REG_PCAM = 0x507f, |
| 137 | MLX5_REG_NODE_DESC = 0x6001, |
| 138 | MLX5_REG_HOST_ENDIANNESS = 0x7004, |
| 139 | MLX5_REG_MCIA = 0x9014, |
| 140 | MLX5_REG_MLCR = 0x902b, |
| 141 | MLX5_REG_MTRC_CAP = 0x9040, |
| 142 | MLX5_REG_MTRC_CONF = 0x9041, |
| 143 | MLX5_REG_MTRC_STDB = 0x9042, |
| 144 | MLX5_REG_MTRC_CTRL = 0x9043, |
| 145 | MLX5_REG_MPCNT = 0x9051, |
| 146 | MLX5_REG_MTPPS = 0x9053, |
| 147 | MLX5_REG_MTPPSE = 0x9054, |
| 148 | MLX5_REG_MPEGC = 0x9056, |
| 149 | MLX5_REG_MCQI = 0x9061, |
| 150 | MLX5_REG_MCC = 0x9062, |
| 151 | MLX5_REG_MCDA = 0x9063, |
| 152 | MLX5_REG_MCAM = 0x907f, |
| 153 | }; |
| 154 | |
| 155 | enum mlx5_qpts_trust_state { |
| 156 | MLX5_QPTS_TRUST_PCP = 1, |
| 157 | MLX5_QPTS_TRUST_DSCP = 2, |
| 158 | }; |
| 159 | |
| 160 | enum mlx5_dcbx_oper_mode { |
| 161 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, |
| 162 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, |
| 163 | }; |
| 164 | |
| 165 | enum mlx5_dct_atomic_mode { |
| 166 | MLX5_ATOMIC_MODE_DCT_OFF = 20, |
| 167 | MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, |
| 168 | MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, |
| 169 | MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, |
| 170 | }; |
| 171 | |
| 172 | enum { |
| 173 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, |
| 174 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, |
| 175 | }; |
| 176 | |
| 177 | enum mlx5_page_fault_resume_flags { |
| 178 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, |
| 179 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, |
| 180 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, |
| 181 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, |
| 182 | }; |
| 183 | |
| 184 | enum dbg_rsc_type { |
| 185 | MLX5_DBG_RSC_QP, |
| 186 | MLX5_DBG_RSC_EQ, |
| 187 | MLX5_DBG_RSC_CQ, |
| 188 | }; |
| 189 | |
| 190 | enum port_state_policy { |
| 191 | MLX5_POLICY_DOWN = 0, |
| 192 | MLX5_POLICY_UP = 1, |
| 193 | MLX5_POLICY_FOLLOW = 2, |
| 194 | MLX5_POLICY_INVALID = 0xffffffff |
| 195 | }; |
| 196 | |
| 197 | struct mlx5_field_desc { |
| 198 | struct dentry *dent; |
| 199 | int i; |
| 200 | }; |
| 201 | |
| 202 | struct mlx5_rsc_debug { |
| 203 | struct mlx5_core_dev *dev; |
| 204 | void *object; |
| 205 | enum dbg_rsc_type type; |
| 206 | struct dentry *root; |
| 207 | struct mlx5_field_desc fields[0]; |
| 208 | }; |
| 209 | |
| 210 | enum mlx5_dev_event { |
| 211 | MLX5_DEV_EVENT_SYS_ERROR, |
| 212 | MLX5_DEV_EVENT_PORT_UP, |
| 213 | MLX5_DEV_EVENT_PORT_DOWN, |
| 214 | MLX5_DEV_EVENT_PORT_INITIALIZED, |
| 215 | MLX5_DEV_EVENT_LID_CHANGE, |
| 216 | MLX5_DEV_EVENT_PKEY_CHANGE, |
| 217 | MLX5_DEV_EVENT_GUID_CHANGE, |
| 218 | MLX5_DEV_EVENT_CLIENT_REREG, |
| 219 | MLX5_DEV_EVENT_PPS, |
| 220 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
| 221 | }; |
| 222 | |
| 223 | enum mlx5_port_status { |
| 224 | MLX5_PORT_UP = 1, |
| 225 | MLX5_PORT_DOWN = 2, |
| 226 | }; |
| 227 | |
| 228 | enum mlx5_eq_type { |
| 229 | MLX5_EQ_TYPE_COMP, |
| 230 | MLX5_EQ_TYPE_ASYNC, |
| 231 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
| 232 | MLX5_EQ_TYPE_PF, |
| 233 | #endif |
| 234 | }; |
| 235 | |
| 236 | struct mlx5_bfreg_info { |
| 237 | u32 *sys_pages; |
| 238 | int num_low_latency_bfregs; |
| 239 | unsigned int *count; |
| 240 | |
| 241 | /* |
| 242 | * protect bfreg allocation data structs |
| 243 | */ |
| 244 | struct mutex lock; |
| 245 | u32 ver; |
| 246 | bool lib_uar_4k; |
| 247 | u32 num_sys_pages; |
| 248 | u32 num_static_sys_pages; |
| 249 | u32 total_num_bfregs; |
| 250 | u32 num_dyn_bfregs; |
| 251 | }; |
| 252 | |
| 253 | struct mlx5_cmd_first { |
| 254 | __be32 data[4]; |
| 255 | }; |
| 256 | |
| 257 | struct mlx5_cmd_msg { |
| 258 | struct list_head list; |
| 259 | struct cmd_msg_cache *parent; |
| 260 | u32 len; |
| 261 | struct mlx5_cmd_first first; |
| 262 | struct mlx5_cmd_mailbox *next; |
| 263 | }; |
| 264 | |
| 265 | struct mlx5_cmd_debug { |
| 266 | struct dentry *dbg_root; |
| 267 | struct dentry *dbg_in; |
| 268 | struct dentry *dbg_out; |
| 269 | struct dentry *dbg_outlen; |
| 270 | struct dentry *dbg_status; |
| 271 | struct dentry *dbg_run; |
| 272 | void *in_msg; |
| 273 | void *out_msg; |
| 274 | u8 status; |
| 275 | u16 inlen; |
| 276 | u16 outlen; |
| 277 | }; |
| 278 | |
| 279 | struct cmd_msg_cache { |
| 280 | /* protect block chain allocations |
| 281 | */ |
| 282 | spinlock_t lock; |
| 283 | struct list_head head; |
| 284 | unsigned int max_inbox_size; |
| 285 | unsigned int num_ent; |
| 286 | }; |
| 287 | |
| 288 | enum { |
| 289 | MLX5_NUM_COMMAND_CACHES = 5, |
| 290 | }; |
| 291 | |
| 292 | struct mlx5_cmd_stats { |
| 293 | u64 sum; |
| 294 | u64 n; |
| 295 | struct dentry *root; |
| 296 | struct dentry *avg; |
| 297 | struct dentry *count; |
| 298 | /* protect command average calculations */ |
| 299 | spinlock_t lock; |
| 300 | }; |
| 301 | |
| 302 | struct mlx5_cmd { |
| 303 | void *cmd_alloc_buf; |
| 304 | dma_addr_t alloc_dma; |
| 305 | int alloc_size; |
| 306 | void *cmd_buf; |
| 307 | dma_addr_t dma; |
| 308 | u16 cmdif_rev; |
| 309 | u8 log_sz; |
| 310 | u8 log_stride; |
| 311 | int max_reg_cmds; |
| 312 | int events; |
| 313 | u32 __iomem *vector; |
| 314 | |
| 315 | /* protect command queue allocations |
| 316 | */ |
| 317 | spinlock_t alloc_lock; |
| 318 | |
| 319 | /* protect token allocations |
| 320 | */ |
| 321 | spinlock_t token_lock; |
| 322 | u8 token; |
| 323 | unsigned long bitmask; |
| 324 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; |
| 325 | struct workqueue_struct *wq; |
| 326 | struct semaphore sem; |
| 327 | struct semaphore pages_sem; |
| 328 | int mode; |
| 329 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
| 330 | struct dma_pool *pool; |
| 331 | struct mlx5_cmd_debug dbg; |
| 332 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
| 333 | int checksum_disabled; |
| 334 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; |
| 335 | }; |
| 336 | |
| 337 | struct mlx5_port_caps { |
| 338 | int gid_table_len; |
| 339 | int pkey_table_len; |
| 340 | u8 ext_port_cap; |
| 341 | bool has_smi; |
| 342 | }; |
| 343 | |
| 344 | struct mlx5_cmd_mailbox { |
| 345 | void *buf; |
| 346 | dma_addr_t dma; |
| 347 | struct mlx5_cmd_mailbox *next; |
| 348 | }; |
| 349 | |
| 350 | struct mlx5_buf_list { |
| 351 | void *buf; |
| 352 | dma_addr_t map; |
| 353 | }; |
| 354 | |
| 355 | struct mlx5_frag_buf { |
| 356 | struct mlx5_buf_list *frags; |
| 357 | int npages; |
| 358 | int size; |
| 359 | u8 page_shift; |
| 360 | }; |
| 361 | |
| 362 | struct mlx5_frag_buf_ctrl { |
| 363 | struct mlx5_frag_buf frag_buf; |
| 364 | u32 sz_m1; |
| 365 | u32 frag_sz_m1; |
| 366 | u8 log_sz; |
| 367 | u8 log_stride; |
| 368 | u8 log_frag_strides; |
| 369 | }; |
| 370 | |
| 371 | struct mlx5_eq_tasklet { |
| 372 | struct list_head list; |
| 373 | struct list_head process_list; |
| 374 | struct tasklet_struct task; |
| 375 | /* lock on completion tasklet list */ |
| 376 | spinlock_t lock; |
| 377 | }; |
| 378 | |
| 379 | struct mlx5_eq_pagefault { |
| 380 | struct work_struct work; |
| 381 | /* Pagefaults lock */ |
| 382 | spinlock_t lock; |
| 383 | struct workqueue_struct *wq; |
| 384 | mempool_t *pool; |
| 385 | }; |
| 386 | |
| 387 | struct mlx5_cq_table { |
| 388 | /* protect radix tree */ |
| 389 | spinlock_t lock; |
| 390 | struct radix_tree_root tree; |
| 391 | }; |
| 392 | |
| 393 | struct mlx5_eq { |
| 394 | struct mlx5_core_dev *dev; |
| 395 | struct mlx5_cq_table cq_table; |
| 396 | __be32 __iomem *doorbell; |
| 397 | u32 cons_index; |
| 398 | struct mlx5_frag_buf buf; |
| 399 | int size; |
| 400 | unsigned int irqn; |
| 401 | u8 eqn; |
| 402 | int nent; |
| 403 | u64 mask; |
| 404 | struct list_head list; |
| 405 | int index; |
| 406 | struct mlx5_rsc_debug *dbg; |
| 407 | enum mlx5_eq_type type; |
| 408 | union { |
| 409 | struct mlx5_eq_tasklet tasklet_ctx; |
| 410 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
| 411 | struct mlx5_eq_pagefault pf_ctx; |
| 412 | #endif |
| 413 | }; |
| 414 | }; |
| 415 | |
| 416 | struct mlx5_core_psv { |
| 417 | u32 psv_idx; |
| 418 | struct psv_layout { |
| 419 | u32 pd; |
| 420 | u16 syndrome; |
| 421 | u16 reserved; |
| 422 | u16 bg; |
| 423 | u16 app_tag; |
| 424 | u32 ref_tag; |
| 425 | } psv; |
| 426 | }; |
| 427 | |
| 428 | struct mlx5_core_sig_ctx { |
| 429 | struct mlx5_core_psv psv_memory; |
| 430 | struct mlx5_core_psv psv_wire; |
| 431 | struct ib_sig_err err_item; |
| 432 | bool sig_status_checked; |
| 433 | bool sig_err_exists; |
| 434 | u32 sigerr_count; |
| 435 | }; |
| 436 | |
| 437 | enum { |
| 438 | MLX5_MKEY_MR = 1, |
| 439 | MLX5_MKEY_MW, |
| 440 | }; |
| 441 | |
| 442 | struct mlx5_core_mkey { |
| 443 | u64 iova; |
| 444 | u64 size; |
| 445 | u32 key; |
| 446 | u32 pd; |
| 447 | u32 type; |
| 448 | }; |
| 449 | |
| 450 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
| 451 | |
| 452 | enum mlx5_res_type { |
| 453 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
| 454 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, |
| 455 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, |
| 456 | MLX5_RES_SRQ = 3, |
| 457 | MLX5_RES_XSRQ = 4, |
| 458 | MLX5_RES_XRQ = 5, |
| 459 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
| 460 | }; |
| 461 | |
| 462 | struct mlx5_core_rsc_common { |
| 463 | enum mlx5_res_type res; |
| 464 | atomic_t refcount; |
| 465 | struct completion free; |
| 466 | }; |
| 467 | |
| 468 | struct mlx5_core_srq { |
| 469 | struct mlx5_core_rsc_common common; /* must be first */ |
| 470 | u32 srqn; |
| 471 | int max; |
| 472 | size_t max_gs; |
| 473 | size_t max_avail_gather; |
| 474 | int wqe_shift; |
| 475 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); |
| 476 | |
| 477 | atomic_t refcount; |
| 478 | struct completion free; |
| 479 | }; |
| 480 | |
| 481 | struct mlx5_eq_table { |
| 482 | void __iomem *update_ci; |
| 483 | void __iomem *update_arm_ci; |
| 484 | struct list_head comp_eqs_list; |
| 485 | struct mlx5_eq pages_eq; |
| 486 | struct mlx5_eq async_eq; |
| 487 | struct mlx5_eq cmd_eq; |
| 488 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
| 489 | struct mlx5_eq pfault_eq; |
| 490 | #endif |
| 491 | int num_comp_vectors; |
| 492 | /* protect EQs list |
| 493 | */ |
| 494 | spinlock_t lock; |
| 495 | }; |
| 496 | |
| 497 | struct mlx5_uars_page { |
| 498 | void __iomem *map; |
| 499 | bool wc; |
| 500 | u32 index; |
| 501 | struct list_head list; |
| 502 | unsigned int bfregs; |
| 503 | unsigned long *reg_bitmap; /* for non fast path bf regs */ |
| 504 | unsigned long *fp_bitmap; |
| 505 | unsigned int reg_avail; |
| 506 | unsigned int fp_avail; |
| 507 | struct kref ref_count; |
| 508 | struct mlx5_core_dev *mdev; |
| 509 | }; |
| 510 | |
| 511 | struct mlx5_bfreg_head { |
| 512 | /* protect blue flame registers allocations */ |
| 513 | struct mutex lock; |
| 514 | struct list_head list; |
| 515 | }; |
| 516 | |
| 517 | struct mlx5_bfreg_data { |
| 518 | struct mlx5_bfreg_head reg_head; |
| 519 | struct mlx5_bfreg_head wc_head; |
| 520 | }; |
| 521 | |
| 522 | struct mlx5_sq_bfreg { |
| 523 | void __iomem *map; |
| 524 | struct mlx5_uars_page *up; |
| 525 | bool wc; |
| 526 | u32 index; |
| 527 | unsigned int offset; |
| 528 | }; |
| 529 | |
| 530 | struct mlx5_core_health { |
| 531 | struct health_buffer __iomem *health; |
| 532 | __be32 __iomem *health_counter; |
| 533 | struct timer_list timer; |
| 534 | u32 prev; |
| 535 | int miss_counter; |
| 536 | bool sick; |
| 537 | /* wq spinlock to synchronize draining */ |
| 538 | spinlock_t wq_lock; |
| 539 | struct workqueue_struct *wq; |
| 540 | unsigned long flags; |
| 541 | struct work_struct work; |
| 542 | struct delayed_work recover_work; |
| 543 | }; |
| 544 | |
| 545 | struct mlx5_qp_table { |
| 546 | /* protect radix tree |
| 547 | */ |
| 548 | spinlock_t lock; |
| 549 | struct radix_tree_root tree; |
| 550 | }; |
| 551 | |
| 552 | struct mlx5_srq_table { |
| 553 | /* protect radix tree |
| 554 | */ |
| 555 | spinlock_t lock; |
| 556 | struct radix_tree_root tree; |
| 557 | }; |
| 558 | |
| 559 | struct mlx5_mkey_table { |
| 560 | /* protect radix tree |
| 561 | */ |
| 562 | rwlock_t lock; |
| 563 | struct radix_tree_root tree; |
| 564 | }; |
| 565 | |
| 566 | struct mlx5_vf_context { |
| 567 | int enabled; |
| 568 | u64 port_guid; |
| 569 | u64 node_guid; |
| 570 | enum port_state_policy policy; |
| 571 | }; |
| 572 | |
| 573 | struct mlx5_core_sriov { |
| 574 | struct mlx5_vf_context *vfs_ctx; |
| 575 | int num_vfs; |
| 576 | int enabled_vfs; |
| 577 | }; |
| 578 | |
| 579 | struct mlx5_irq_info { |
| 580 | cpumask_var_t mask; |
| 581 | char name[MLX5_MAX_IRQ_NAME]; |
| 582 | }; |
| 583 | |
| 584 | struct mlx5_fc_stats { |
| 585 | struct rb_root counters; |
| 586 | struct list_head addlist; |
| 587 | /* protect addlist add/splice operations */ |
| 588 | spinlock_t addlist_lock; |
| 589 | |
| 590 | struct workqueue_struct *wq; |
| 591 | struct delayed_work work; |
| 592 | unsigned long next_query; |
| 593 | unsigned long sampling_interval; /* jiffies */ |
| 594 | }; |
| 595 | |
| 596 | struct mlx5_mpfs; |
| 597 | struct mlx5_eswitch; |
| 598 | struct mlx5_lag; |
| 599 | struct mlx5_pagefault; |
| 600 | |
| 601 | struct mlx5_rate_limit { |
| 602 | u32 rate; |
| 603 | u32 max_burst_sz; |
| 604 | u16 typical_pkt_sz; |
| 605 | }; |
| 606 | |
| 607 | struct mlx5_rl_entry { |
| 608 | struct mlx5_rate_limit rl; |
| 609 | u16 index; |
| 610 | u16 refcount; |
| 611 | }; |
| 612 | |
| 613 | struct mlx5_rl_table { |
| 614 | /* protect rate limit table */ |
| 615 | struct mutex rl_lock; |
| 616 | u16 max_size; |
| 617 | u32 max_rate; |
| 618 | u32 min_rate; |
| 619 | struct mlx5_rl_entry *rl_entry; |
| 620 | }; |
| 621 | |
| 622 | enum port_module_event_status_type { |
| 623 | MLX5_MODULE_STATUS_PLUGGED = 0x1, |
| 624 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, |
| 625 | MLX5_MODULE_STATUS_ERROR = 0x3, |
| 626 | MLX5_MODULE_STATUS_NUM = 0x3, |
| 627 | }; |
| 628 | |
| 629 | enum port_module_event_error_type { |
| 630 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, |
| 631 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, |
| 632 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, |
| 633 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, |
| 634 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, |
| 635 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, |
| 636 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, |
| 637 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, |
| 638 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, |
| 639 | MLX5_MODULE_EVENT_ERROR_NUM, |
| 640 | }; |
| 641 | |
| 642 | struct mlx5_port_module_event_stats { |
| 643 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; |
| 644 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; |
| 645 | }; |
| 646 | |
| 647 | struct mlx5_priv { |
| 648 | char name[MLX5_MAX_NAME_LEN]; |
| 649 | struct mlx5_eq_table eq_table; |
| 650 | struct mlx5_irq_info *irq_info; |
| 651 | |
| 652 | /* pages stuff */ |
| 653 | struct workqueue_struct *pg_wq; |
| 654 | struct rb_root page_root; |
| 655 | int fw_pages; |
| 656 | atomic_t reg_pages; |
| 657 | struct list_head free_list; |
| 658 | int vfs_pages; |
| 659 | |
| 660 | struct mlx5_core_health health; |
| 661 | |
| 662 | struct mlx5_srq_table srq_table; |
| 663 | |
| 664 | /* start: qp staff */ |
| 665 | struct mlx5_qp_table qp_table; |
| 666 | struct dentry *qp_debugfs; |
| 667 | struct dentry *eq_debugfs; |
| 668 | struct dentry *cq_debugfs; |
| 669 | struct dentry *cmdif_debugfs; |
| 670 | /* end: qp staff */ |
| 671 | |
| 672 | /* start: mkey staff */ |
| 673 | struct mlx5_mkey_table mkey_table; |
| 674 | /* end: mkey staff */ |
| 675 | |
| 676 | /* start: alloc staff */ |
| 677 | /* protect buffer alocation according to numa node */ |
| 678 | struct mutex alloc_mutex; |
| 679 | int numa_node; |
| 680 | |
| 681 | struct mutex pgdir_mutex; |
| 682 | struct list_head pgdir_list; |
| 683 | /* end: alloc staff */ |
| 684 | struct dentry *dbg_root; |
| 685 | |
| 686 | /* protect mkey key part */ |
| 687 | spinlock_t mkey_lock; |
| 688 | u8 mkey_key; |
| 689 | |
| 690 | struct list_head dev_list; |
| 691 | struct list_head ctx_list; |
| 692 | spinlock_t ctx_lock; |
| 693 | |
| 694 | struct list_head waiting_events_list; |
| 695 | bool is_accum_events; |
| 696 | |
| 697 | struct mlx5_flow_steering *steering; |
| 698 | struct mlx5_mpfs *mpfs; |
| 699 | struct mlx5_eswitch *eswitch; |
| 700 | struct mlx5_core_sriov sriov; |
| 701 | struct mlx5_lag *lag; |
| 702 | unsigned long pci_dev_data; |
| 703 | struct mlx5_fc_stats fc_stats; |
| 704 | struct mlx5_rl_table rl_table; |
| 705 | |
| 706 | struct mlx5_port_module_event_stats pme_stats; |
| 707 | |
| 708 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
| 709 | void (*pfault)(struct mlx5_core_dev *dev, |
| 710 | void *context, |
| 711 | struct mlx5_pagefault *pfault); |
| 712 | void *pfault_ctx; |
| 713 | struct srcu_struct pfault_srcu; |
| 714 | #endif |
| 715 | struct mlx5_bfreg_data bfregs; |
| 716 | struct mlx5_uars_page *uar; |
| 717 | }; |
| 718 | |
| 719 | enum mlx5_device_state { |
| 720 | MLX5_DEVICE_STATE_UP, |
| 721 | MLX5_DEVICE_STATE_INTERNAL_ERROR, |
| 722 | }; |
| 723 | |
| 724 | enum mlx5_interface_state { |
| 725 | MLX5_INTERFACE_STATE_UP = BIT(0), |
| 726 | }; |
| 727 | |
| 728 | enum mlx5_pci_status { |
| 729 | MLX5_PCI_STATUS_DISABLED, |
| 730 | MLX5_PCI_STATUS_ENABLED, |
| 731 | }; |
| 732 | |
| 733 | enum mlx5_pagefault_type_flags { |
| 734 | MLX5_PFAULT_REQUESTOR = 1 << 0, |
| 735 | MLX5_PFAULT_WRITE = 1 << 1, |
| 736 | MLX5_PFAULT_RDMA = 1 << 2, |
| 737 | }; |
| 738 | |
| 739 | /* Contains the details of a pagefault. */ |
| 740 | struct mlx5_pagefault { |
| 741 | u32 bytes_committed; |
| 742 | u32 token; |
| 743 | u8 event_subtype; |
| 744 | u8 type; |
| 745 | union { |
| 746 | /* Initiator or send message responder pagefault details. */ |
| 747 | struct { |
| 748 | /* Received packet size, only valid for responders. */ |
| 749 | u32 packet_size; |
| 750 | /* |
| 751 | * Number of resource holding WQE, depends on type. |
| 752 | */ |
| 753 | u32 wq_num; |
| 754 | /* |
| 755 | * WQE index. Refers to either the send queue or |
| 756 | * receive queue, according to event_subtype. |
| 757 | */ |
| 758 | u16 wqe_index; |
| 759 | } wqe; |
| 760 | /* RDMA responder pagefault details */ |
| 761 | struct { |
| 762 | u32 r_key; |
| 763 | /* |
| 764 | * Received packet size, minimal size page fault |
| 765 | * resolution required for forward progress. |
| 766 | */ |
| 767 | u32 packet_size; |
| 768 | u32 rdma_op_len; |
| 769 | u64 rdma_va; |
| 770 | } rdma; |
| 771 | }; |
| 772 | |
| 773 | struct mlx5_eq *eq; |
| 774 | struct work_struct work; |
| 775 | }; |
| 776 | |
| 777 | struct mlx5_td { |
| 778 | struct list_head tirs_list; |
| 779 | u32 tdn; |
| 780 | }; |
| 781 | |
| 782 | struct mlx5e_resources { |
| 783 | u32 pdn; |
| 784 | struct mlx5_td td; |
| 785 | struct mlx5_core_mkey mkey; |
| 786 | struct mlx5_sq_bfreg bfreg; |
| 787 | }; |
| 788 | |
| 789 | #define MLX5_MAX_RESERVED_GIDS 8 |
| 790 | |
| 791 | struct mlx5_rsvd_gids { |
| 792 | unsigned int start; |
| 793 | unsigned int count; |
| 794 | struct ida ida; |
| 795 | }; |
| 796 | |
| 797 | #define MAX_PIN_NUM 8 |
| 798 | struct mlx5_pps { |
| 799 | u8 pin_caps[MAX_PIN_NUM]; |
| 800 | struct work_struct out_work; |
| 801 | u64 start[MAX_PIN_NUM]; |
| 802 | u8 enabled; |
| 803 | }; |
| 804 | |
| 805 | struct mlx5_clock { |
| 806 | rwlock_t lock; |
| 807 | struct cyclecounter cycles; |
| 808 | struct timecounter tc; |
| 809 | struct hwtstamp_config hwtstamp_config; |
| 810 | u32 nominal_c_mult; |
| 811 | unsigned long overflow_period; |
| 812 | struct delayed_work overflow_work; |
| 813 | struct mlx5_core_dev *mdev; |
| 814 | struct ptp_clock *ptp; |
| 815 | struct ptp_clock_info ptp_info; |
| 816 | struct mlx5_pps pps_info; |
| 817 | }; |
| 818 | |
| 819 | struct mlx5_core_dev { |
| 820 | struct pci_dev *pdev; |
| 821 | /* sync pci state */ |
| 822 | struct mutex pci_status_mutex; |
| 823 | enum mlx5_pci_status pci_status; |
| 824 | u8 rev_id; |
| 825 | char board_id[MLX5_BOARD_ID_LEN]; |
| 826 | struct mlx5_cmd cmd; |
| 827 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
| 828 | struct { |
| 829 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
| 830 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
| 831 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
| 832 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; |
| 833 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
| 834 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
| 835 | } caps; |
| 836 | phys_addr_t iseg_base; |
| 837 | struct mlx5_init_seg __iomem *iseg; |
| 838 | enum mlx5_device_state state; |
| 839 | /* sync interface state */ |
| 840 | struct mutex intf_state_mutex; |
| 841 | unsigned long intf_state; |
| 842 | void (*event) (struct mlx5_core_dev *dev, |
| 843 | enum mlx5_dev_event event, |
| 844 | unsigned long param); |
| 845 | struct mlx5_priv priv; |
| 846 | struct mlx5_profile *profile; |
| 847 | atomic_t num_qps; |
| 848 | u32 issi; |
| 849 | struct mlx5e_resources mlx5e_res; |
| 850 | struct { |
| 851 | struct mlx5_rsvd_gids reserved_gids; |
| 852 | u32 roce_en; |
| 853 | } roce; |
| 854 | #ifdef CONFIG_MLX5_FPGA |
| 855 | struct mlx5_fpga_device *fpga; |
| 856 | #endif |
| 857 | #ifdef CONFIG_RFS_ACCEL |
| 858 | struct cpu_rmap *rmap; |
| 859 | #endif |
| 860 | struct mlx5_clock clock; |
| 861 | struct mlx5_ib_clock_info *clock_info; |
| 862 | struct page *clock_info_page; |
| 863 | }; |
| 864 | |
| 865 | struct mlx5_db { |
| 866 | __be32 *db; |
| 867 | union { |
| 868 | struct mlx5_db_pgdir *pgdir; |
| 869 | struct mlx5_ib_user_db_page *user_page; |
| 870 | } u; |
| 871 | dma_addr_t dma; |
| 872 | int index; |
| 873 | }; |
| 874 | |
| 875 | enum { |
| 876 | MLX5_COMP_EQ_SIZE = 1024, |
| 877 | }; |
| 878 | |
| 879 | enum { |
| 880 | MLX5_PTYS_IB = 1 << 0, |
| 881 | MLX5_PTYS_EN = 1 << 2, |
| 882 | }; |
| 883 | |
| 884 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
| 885 | |
| 886 | enum { |
| 887 | MLX5_CMD_ENT_STATE_PENDING_COMP, |
| 888 | }; |
| 889 | |
| 890 | struct mlx5_cmd_work_ent { |
| 891 | unsigned long state; |
| 892 | struct mlx5_cmd_msg *in; |
| 893 | struct mlx5_cmd_msg *out; |
| 894 | void *uout; |
| 895 | int uout_size; |
| 896 | mlx5_cmd_cbk_t callback; |
| 897 | struct delayed_work cb_timeout_work; |
| 898 | void *context; |
| 899 | int idx; |
| 900 | struct completion done; |
| 901 | struct mlx5_cmd *cmd; |
| 902 | struct work_struct work; |
| 903 | struct mlx5_cmd_layout *lay; |
| 904 | int ret; |
| 905 | int page_queue; |
| 906 | u8 status; |
| 907 | u8 token; |
| 908 | u64 ts1; |
| 909 | u64 ts2; |
| 910 | u16 op; |
| 911 | bool polling; |
| 912 | }; |
| 913 | |
| 914 | struct mlx5_pas { |
| 915 | u64 pa; |
| 916 | u8 log_sz; |
| 917 | }; |
| 918 | |
| 919 | enum phy_port_state { |
| 920 | MLX5_AAA_111 |
| 921 | }; |
| 922 | |
| 923 | struct mlx5_hca_vport_context { |
| 924 | u32 field_select; |
| 925 | bool sm_virt_aware; |
| 926 | bool has_smi; |
| 927 | bool has_raw; |
| 928 | enum port_state_policy policy; |
| 929 | enum phy_port_state phys_state; |
| 930 | enum ib_port_state vport_state; |
| 931 | u8 port_physical_state; |
| 932 | u64 sys_image_guid; |
| 933 | u64 port_guid; |
| 934 | u64 node_guid; |
| 935 | u32 cap_mask1; |
| 936 | u32 cap_mask1_perm; |
| 937 | u32 cap_mask2; |
| 938 | u32 cap_mask2_perm; |
| 939 | u16 lid; |
| 940 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ |
| 941 | u8 lmc; |
| 942 | u8 subnet_timeout; |
| 943 | u16 sm_lid; |
| 944 | u8 sm_sl; |
| 945 | u16 qkey_violation_counter; |
| 946 | u16 pkey_violation_counter; |
| 947 | bool grh_required; |
| 948 | }; |
| 949 | |
| 950 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
| 951 | { |
| 952 | return buf->frags->buf + offset; |
| 953 | } |
| 954 | |
| 955 | #define STRUCT_FIELD(header, field) \ |
| 956 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ |
| 957 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field |
| 958 | |
| 959 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
| 960 | { |
| 961 | return pci_get_drvdata(pdev); |
| 962 | } |
| 963 | |
| 964 | extern struct dentry *mlx5_debugfs_root; |
| 965 | |
| 966 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) |
| 967 | { |
| 968 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; |
| 969 | } |
| 970 | |
| 971 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) |
| 972 | { |
| 973 | return ioread32be(&dev->iseg->fw_rev) >> 16; |
| 974 | } |
| 975 | |
| 976 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) |
| 977 | { |
| 978 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; |
| 979 | } |
| 980 | |
| 981 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) |
| 982 | { |
| 983 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; |
| 984 | } |
| 985 | |
| 986 | static inline u32 mlx5_base_mkey(const u32 key) |
| 987 | { |
| 988 | return key & 0xffffff00u; |
| 989 | } |
| 990 | |
| 991 | static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz, |
| 992 | struct mlx5_frag_buf_ctrl *fbc) |
| 993 | { |
| 994 | fbc->log_stride = log_stride; |
| 995 | fbc->log_sz = log_sz; |
| 996 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
| 997 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; |
| 998 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; |
| 999 | } |
| 1000 | |
| 1001 | static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc, |
| 1002 | void *cqc) |
| 1003 | { |
| 1004 | mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz), |
| 1005 | MLX5_GET(cqc, cqc, log_cq_size), |
| 1006 | fbc); |
| 1007 | } |
| 1008 | |
| 1009 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
| 1010 | u32 ix) |
| 1011 | { |
| 1012 | unsigned int frag = (ix >> fbc->log_frag_strides); |
| 1013 | |
| 1014 | return fbc->frag_buf.frags[frag].buf + |
| 1015 | ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
| 1016 | } |
| 1017 | |
| 1018 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
| 1019 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); |
| 1020 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); |
| 1021 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); |
| 1022 | |
| 1023 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
| 1024 | int out_size); |
| 1025 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
| 1026 | void *out, int out_size, mlx5_cmd_cbk_t callback, |
| 1027 | void *context); |
| 1028 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
| 1029 | void *out, int out_size); |
| 1030 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
| 1031 | |
| 1032 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); |
| 1033 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
| 1034 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); |
| 1035 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
| 1036 | int mlx5_health_init(struct mlx5_core_dev *dev); |
| 1037 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
| 1038 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); |
| 1039 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
| 1040 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
| 1041 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
| 1042 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
| 1043 | struct mlx5_frag_buf *buf, int node); |
| 1044 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, |
| 1045 | int size, struct mlx5_frag_buf *buf); |
| 1046 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); |
| 1047 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
| 1048 | struct mlx5_frag_buf *buf, int node); |
| 1049 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); |
| 1050 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
| 1051 | gfp_t flags, int npages); |
| 1052 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
| 1053 | struct mlx5_cmd_mailbox *head); |
| 1054 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
| 1055 | struct mlx5_srq_attr *in); |
| 1056 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
| 1057 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
| 1058 | struct mlx5_srq_attr *out); |
| 1059 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
| 1060 | u16 lwm, int is_srq); |
| 1061 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
| 1062 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); |
| 1063 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
| 1064 | struct mlx5_core_mkey *mkey, |
| 1065 | u32 *in, int inlen, |
| 1066 | u32 *out, int outlen, |
| 1067 | mlx5_cmd_cbk_t callback, void *context); |
| 1068 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
| 1069 | struct mlx5_core_mkey *mkey, |
| 1070 | u32 *in, int inlen); |
| 1071 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
| 1072 | struct mlx5_core_mkey *mkey); |
| 1073 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, |
| 1074 | u32 *out, int outlen); |
| 1075 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
| 1076 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); |
| 1077 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
| 1078 | u16 opmod, u8 port); |
| 1079 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
| 1080 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
| 1081 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
| 1082 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
| 1083 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, |
| 1084 | s32 npages); |
| 1085 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
| 1086 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
| 1087 | void mlx5_register_debugfs(void); |
| 1088 | void mlx5_unregister_debugfs(void); |
| 1089 | |
| 1090 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); |
| 1091 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
| 1092 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
| 1093 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
| 1094 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); |
| 1095 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
| 1096 | unsigned int *irqn); |
| 1097 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
| 1098 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
| 1099 | |
| 1100 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
| 1101 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 1102 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, |
| 1103 | int size_in, void *data_out, int size_out, |
| 1104 | u16 reg_num, int arg, int write); |
| 1105 | |
| 1106 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
| 1107 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
| 1108 | int node); |
| 1109 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
| 1110 | |
| 1111 | const char *mlx5_command_str(int command); |
| 1112 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
| 1113 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 1114 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
| 1115 | int npsvs, u32 *sig_index); |
| 1116 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); |
| 1117 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
| 1118 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
| 1119 | struct mlx5_odp_caps *odp_caps); |
| 1120 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
| 1121 | u8 port_num, void *out, size_t sz); |
| 1122 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
| 1123 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, |
| 1124 | u32 wq_num, u8 type, int error); |
| 1125 | #endif |
| 1126 | |
| 1127 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
| 1128 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); |
| 1129 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
| 1130 | struct mlx5_rate_limit *rl); |
| 1131 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); |
| 1132 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
| 1133 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
| 1134 | struct mlx5_rate_limit *rl_1); |
| 1135 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
| 1136 | bool map_wc, bool fast_path); |
| 1137 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); |
| 1138 | |
| 1139 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
| 1140 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, |
| 1141 | u8 roce_version, u8 roce_l3_type, const u8 *gid, |
| 1142 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
| 1143 | |
| 1144 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
| 1145 | { |
| 1146 | return ioread32be(&dev->iseg->initializing) >> 31; |
| 1147 | } |
| 1148 | |
| 1149 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
| 1150 | { |
| 1151 | return mkey >> 8; |
| 1152 | } |
| 1153 | |
| 1154 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) |
| 1155 | { |
| 1156 | return mkey_idx << 8; |
| 1157 | } |
| 1158 | |
| 1159 | static inline u8 mlx5_mkey_variant(u32 mkey) |
| 1160 | { |
| 1161 | return mkey & 0xff; |
| 1162 | } |
| 1163 | |
| 1164 | enum { |
| 1165 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, |
| 1166 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
| 1167 | }; |
| 1168 | |
| 1169 | enum { |
| 1170 | MR_CACHE_LAST_STD_ENTRY = 20, |
| 1171 | MLX5_IMR_MTT_CACHE_ENTRY, |
| 1172 | MLX5_IMR_KSM_CACHE_ENTRY, |
| 1173 | MAX_MR_CACHE_ENTRIES |
| 1174 | }; |
| 1175 | |
| 1176 | enum { |
| 1177 | MLX5_INTERFACE_PROTOCOL_IB = 0, |
| 1178 | MLX5_INTERFACE_PROTOCOL_ETH = 1, |
| 1179 | }; |
| 1180 | |
| 1181 | struct mlx5_interface { |
| 1182 | void * (*add)(struct mlx5_core_dev *dev); |
| 1183 | void (*remove)(struct mlx5_core_dev *dev, void *context); |
| 1184 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
| 1185 | void (*detach)(struct mlx5_core_dev *dev, void *context); |
| 1186 | void (*event)(struct mlx5_core_dev *dev, void *context, |
| 1187 | enum mlx5_dev_event event, unsigned long param); |
| 1188 | void (*pfault)(struct mlx5_core_dev *dev, |
| 1189 | void *context, |
| 1190 | struct mlx5_pagefault *pfault); |
| 1191 | void * (*get_dev)(void *context); |
| 1192 | int protocol; |
| 1193 | struct list_head list; |
| 1194 | }; |
| 1195 | |
| 1196 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
| 1197 | int mlx5_register_interface(struct mlx5_interface *intf); |
| 1198 | void mlx5_unregister_interface(struct mlx5_interface *intf); |
| 1199 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
| 1200 | |
| 1201 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
| 1202 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); |
| 1203 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
| 1204 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
| 1205 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
| 1206 | u64 *values, |
| 1207 | int num_counters, |
| 1208 | size_t *offsets); |
| 1209 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
| 1210 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); |
| 1211 | |
| 1212 | #ifndef CONFIG_MLX5_CORE_IPOIB |
| 1213 | static inline |
| 1214 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
| 1215 | struct ib_device *ibdev, |
| 1216 | const char *name, |
| 1217 | void (*setup)(struct net_device *)) |
| 1218 | { |
| 1219 | return ERR_PTR(-EOPNOTSUPP); |
| 1220 | } |
| 1221 | |
| 1222 | static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {} |
| 1223 | #else |
| 1224 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
| 1225 | struct ib_device *ibdev, |
| 1226 | const char *name, |
| 1227 | void (*setup)(struct net_device *)); |
| 1228 | void mlx5_rdma_netdev_free(struct net_device *netdev); |
| 1229 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
| 1230 | |
| 1231 | struct mlx5_profile { |
| 1232 | u64 mask; |
| 1233 | u8 log_max_qp; |
| 1234 | struct { |
| 1235 | int size; |
| 1236 | int limit; |
| 1237 | } mr_cache[MAX_MR_CACHE_ENTRIES]; |
| 1238 | }; |
| 1239 | |
| 1240 | enum { |
| 1241 | MLX5_PCI_DEV_IS_VF = 1 << 0, |
| 1242 | }; |
| 1243 | |
| 1244 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) |
| 1245 | { |
| 1246 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); |
| 1247 | } |
| 1248 | |
| 1249 | #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) |
| 1250 | #define MLX5_VPORT_MANAGER(mdev) \ |
| 1251 | (MLX5_CAP_GEN(mdev, vport_group_manager) && \ |
| 1252 | (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ |
| 1253 | mlx5_core_is_pf(mdev)) |
| 1254 | |
| 1255 | static inline int mlx5_get_gid_table_len(u16 param) |
| 1256 | { |
| 1257 | if (param > 4) { |
| 1258 | pr_warn("gid table length is zero\n"); |
| 1259 | return 0; |
| 1260 | } |
| 1261 | |
| 1262 | return 8 * (1 << param); |
| 1263 | } |
| 1264 | |
| 1265 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
| 1266 | { |
| 1267 | return !!(dev->priv.rl_table.max_size); |
| 1268 | } |
| 1269 | |
| 1270 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
| 1271 | { |
| 1272 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && |
| 1273 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; |
| 1274 | } |
| 1275 | |
| 1276 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) |
| 1277 | { |
| 1278 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; |
| 1279 | } |
| 1280 | |
| 1281 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) |
| 1282 | { |
| 1283 | return mlx5_core_is_mp_slave(dev) || |
| 1284 | mlx5_core_is_mp_master(dev); |
| 1285 | } |
| 1286 | |
| 1287 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
| 1288 | { |
| 1289 | if (!mlx5_core_mp_enabled(dev)) |
| 1290 | return 1; |
| 1291 | |
| 1292 | return MLX5_CAP_GEN(dev, native_port_num); |
| 1293 | } |
| 1294 | |
| 1295 | enum { |
| 1296 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, |
| 1297 | }; |
| 1298 | |
| 1299 | static inline const struct cpumask * |
| 1300 | mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector) |
| 1301 | { |
| 1302 | return dev->priv.irq_info[vector].mask; |
| 1303 | } |
| 1304 | |
| 1305 | #endif /* MLX5_DRIVER_H */ |