| | 1 | /* |
| | 2 | * include/linux/irqchip/arm-gic.h |
| | 3 | * |
| | 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| | 5 | * |
| | 6 | * This program is free software; you can redistribute it and/or modify |
| | 7 | * it under the terms of the GNU General Public License version 2 as |
| | 8 | * published by the Free Software Foundation. |
| | 9 | */ |
| | 10 | #ifndef __LINUX_IRQCHIP_ARM_GIC_H |
| | 11 | #define __LINUX_IRQCHIP_ARM_GIC_H |
| | 12 | |
| | 13 | #define GIC_CPU_CTRL 0x00 |
| | 14 | #define GIC_CPU_PRIMASK 0x04 |
| | 15 | #define GIC_CPU_BINPOINT 0x08 |
| | 16 | #define GIC_CPU_INTACK 0x0c |
| | 17 | #define GIC_CPU_EOI 0x10 |
| | 18 | #define GIC_CPU_RUNNINGPRI 0x14 |
| | 19 | #define GIC_CPU_HIGHPRI 0x18 |
| | 20 | #define GIC_CPU_ALIAS_BINPOINT 0x1c |
| | 21 | #define GIC_CPU_ACTIVEPRIO 0xd0 |
| | 22 | #define GIC_CPU_IDENT 0xfc |
| | 23 | #define GIC_CPU_DEACTIVATE 0x1000 |
| | 24 | |
| | 25 | #define GICC_ENABLE 0x1 |
| | 26 | #define GICC_INT_PRI_THRESHOLD 0xf0 |
| | 27 | |
| | 28 | #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 |
| | 29 | #define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) |
| | 30 | #define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 |
| | 31 | #define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) |
| | 32 | #define GIC_CPU_CTRL_AckCtl_SHIFT 2 |
| | 33 | #define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) |
| | 34 | #define GIC_CPU_CTRL_FIQEn_SHIFT 3 |
| | 35 | #define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) |
| | 36 | #define GIC_CPU_CTRL_CBPR_SHIFT 4 |
| | 37 | #define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) |
| | 38 | #define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 |
| | 39 | #define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) |
| | 40 | |
| | 41 | #define GICC_IAR_INT_ID_MASK 0x3ff |
| | 42 | #define GICC_INT_SPURIOUS 1023 |
| | 43 | #define GICC_DIS_BYPASS_MASK 0x1e0 |
| | 44 | |
| | 45 | #define GIC_DIST_CTRL 0x000 |
| | 46 | #define GIC_DIST_CTR 0x004 |
| | 47 | #define GIC_DIST_IIDR 0x008 |
| | 48 | #define GIC_DIST_IGROUP 0x080 |
| | 49 | #define GIC_DIST_ENABLE_SET 0x100 |
| | 50 | #define GIC_DIST_ENABLE_CLEAR 0x180 |
| | 51 | #define GIC_DIST_PENDING_SET 0x200 |
| | 52 | #define GIC_DIST_PENDING_CLEAR 0x280 |
| | 53 | #define GIC_DIST_ACTIVE_SET 0x300 |
| | 54 | #define GIC_DIST_ACTIVE_CLEAR 0x380 |
| | 55 | #define GIC_DIST_PRI 0x400 |
| | 56 | #define GIC_DIST_TARGET 0x800 |
| | 57 | #define GIC_DIST_CONFIG 0xc00 |
| | 58 | #define GIC_DIST_SOFTINT 0xf00 |
| | 59 | #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 |
| | 60 | #define GIC_DIST_SGI_PENDING_SET 0xf20 |
| | 61 | |
| | 62 | #define GICD_ENABLE 0x1 |
| | 63 | #define GICD_DISABLE 0x0 |
| | 64 | #define GICD_INT_ACTLOW_LVLTRIG 0x0 |
| | 65 | #define GICD_INT_EN_CLR_X32 0xffffffff |
| | 66 | #define GICD_INT_EN_SET_SGI 0x0000ffff |
| | 67 | #define GICD_INT_EN_CLR_PPI 0xffff0000 |
| | 68 | |
| | 69 | #define GICD_IIDR_IMPLEMENTER_SHIFT 0 |
| | 70 | #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) |
| | 71 | #define GICD_IIDR_REVISION_SHIFT 12 |
| | 72 | #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) |
| | 73 | #define GICD_IIDR_VARIANT_SHIFT 16 |
| | 74 | #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) |
| | 75 | #define GICD_IIDR_PRODUCT_ID_SHIFT 24 |
| | 76 | #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) |
| | 77 | |
| | 78 | |
| | 79 | #define GICH_HCR 0x0 |
| | 80 | #define GICH_VTR 0x4 |
| | 81 | #define GICH_VMCR 0x8 |
| | 82 | #define GICH_MISR 0x10 |
| | 83 | #define GICH_EISR0 0x20 |
| | 84 | #define GICH_EISR1 0x24 |
| | 85 | #define GICH_ELRSR0 0x30 |
| | 86 | #define GICH_ELRSR1 0x34 |
| | 87 | #define GICH_APR 0xf0 |
| | 88 | #define GICH_LR0 0x100 |
| | 89 | |
| | 90 | #define GICH_HCR_EN (1 << 0) |
| | 91 | #define GICH_HCR_UIE (1 << 1) |
| | 92 | #define GICH_HCR_NPIE (1 << 3) |
| | 93 | |
| | 94 | #define GICH_LR_VIRTUALID (0x3ff << 0) |
| | 95 | #define GICH_LR_PHYSID_CPUID_SHIFT (10) |
| | 96 | #define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) |
| | 97 | #define GICH_LR_PRIORITY_SHIFT 23 |
| | 98 | #define GICH_LR_STATE (3 << 28) |
| | 99 | #define GICH_LR_PENDING_BIT (1 << 28) |
| | 100 | #define GICH_LR_ACTIVE_BIT (1 << 29) |
| | 101 | #define GICH_LR_EOI (1 << 19) |
| | 102 | #define GICH_LR_GROUP1 (1 << 30) |
| | 103 | #define GICH_LR_HW (1 << 31) |
| | 104 | |
| | 105 | #define GICH_VMCR_ENABLE_GRP0_SHIFT 0 |
| | 106 | #define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) |
| | 107 | #define GICH_VMCR_ENABLE_GRP1_SHIFT 1 |
| | 108 | #define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) |
| | 109 | #define GICH_VMCR_ACK_CTL_SHIFT 2 |
| | 110 | #define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) |
| | 111 | #define GICH_VMCR_FIQ_EN_SHIFT 3 |
| | 112 | #define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) |
| | 113 | #define GICH_VMCR_CBPR_SHIFT 4 |
| | 114 | #define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) |
| | 115 | #define GICH_VMCR_EOI_MODE_SHIFT 9 |
| | 116 | #define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) |
| | 117 | |
| | 118 | #define GICH_VMCR_PRIMASK_SHIFT 27 |
| | 119 | #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) |
| | 120 | #define GICH_VMCR_BINPOINT_SHIFT 21 |
| | 121 | #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) |
| | 122 | #define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 |
| | 123 | #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) |
| | 124 | |
| | 125 | #define GICH_MISR_EOI (1 << 0) |
| | 126 | #define GICH_MISR_U (1 << 1) |
| | 127 | |
| | 128 | #define GICV_PMR_PRIORITY_SHIFT 3 |
| | 129 | #define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) |
| | 130 | |
| | 131 | #ifndef __ASSEMBLY__ |
| | 132 | |
| | 133 | #include <linux/irqdomain.h> |
| | 134 | |
| | 135 | struct device_node; |
| | 136 | struct gic_chip_data; |
| | 137 | |
| | 138 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
| | 139 | int gic_cpu_if_down(unsigned int gic_nr); |
| | 140 | void gic_cpu_save(struct gic_chip_data *gic); |
| | 141 | void gic_cpu_restore(struct gic_chip_data *gic); |
| | 142 | void gic_dist_save(struct gic_chip_data *gic); |
| | 143 | void gic_dist_restore(struct gic_chip_data *gic); |
| | 144 | |
| | 145 | /* |
| | 146 | * Subdrivers that need some preparatory work can initialize their |
| | 147 | * chips and call this to register their GICs. |
| | 148 | */ |
| | 149 | int gic_of_init(struct device_node *node, struct device_node *parent); |
| | 150 | |
| | 151 | /* |
| | 152 | * Initialises and registers a non-root or child GIC chip. Memory for |
| | 153 | * the gic_chip_data structure is dynamically allocated. |
| | 154 | */ |
| | 155 | int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq); |
| | 156 | |
| | 157 | /* |
| | 158 | * Legacy platforms not converted to DT yet must use this to init |
| | 159 | * their GIC |
| | 160 | */ |
| | 161 | void gic_init(unsigned int nr, int start, |
| | 162 | void __iomem *dist , void __iomem *cpu); |
| | 163 | |
| | 164 | int gicv2m_init(struct fwnode_handle *parent_handle, |
| | 165 | struct irq_domain *parent); |
| | 166 | |
| | 167 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq); |
| | 168 | int gic_get_cpu_id(unsigned int cpu); |
| | 169 | void gic_migrate_target(unsigned int new_cpu_id); |
| | 170 | unsigned long gic_get_sgir_physaddr(void); |
| | 171 | |
| | 172 | #endif /* __ASSEMBLY */ |
| | 173 | #endif |
projects / linux-2.6-block.git / blame_incremental