| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * MUSB OTG driver core code |
| 4 | * |
| 5 | * Copyright 2005 Mentor Graphics Corporation |
| 6 | * Copyright (C) 2005-2006 by Texas Instruments |
| 7 | * Copyright (C) 2006-2007 Nokia Corporation |
| 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. |
| 12 | * |
| 13 | * This consists of a Host Controller Driver (HCD) and a peripheral |
| 14 | * controller driver implementing the "Gadget" API; OTG support is |
| 15 | * in the works. These are normal Linux-USB controller drivers which |
| 16 | * use IRQs and have no dedicated thread. |
| 17 | * |
| 18 | * This version of the driver has only been used with products from |
| 19 | * Texas Instruments. Those products integrate the Inventra logic |
| 20 | * with other DMA, IRQ, and bus modules, as well as other logic that |
| 21 | * needs to be reflected in this driver. |
| 22 | * |
| 23 | * |
| 24 | * NOTE: the original Mentor code here was pretty much a collection |
| 25 | * of mechanisms that don't seem to have been fully integrated/working |
| 26 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, |
| 27 | * Key open issues include: |
| 28 | * |
| 29 | * - Lack of host-side transaction scheduling, for all transfer types. |
| 30 | * The hardware doesn't do it; instead, software must. |
| 31 | * |
| 32 | * This is not an issue for OTG devices that don't support external |
| 33 | * hubs, but for more "normal" USB hosts it's a user issue that the |
| 34 | * "multipoint" support doesn't scale in the expected ways. That |
| 35 | * includes DaVinci EVM in a common non-OTG mode. |
| 36 | * |
| 37 | * * Control and bulk use dedicated endpoints, and there's as |
| 38 | * yet no mechanism to either (a) reclaim the hardware when |
| 39 | * peripherals are NAKing, which gets complicated with bulk |
| 40 | * endpoints, or (b) use more than a single bulk endpoint in |
| 41 | * each direction. |
| 42 | * |
| 43 | * RESULT: one device may be perceived as blocking another one. |
| 44 | * |
| 45 | * * Interrupt and isochronous will dynamically allocate endpoint |
| 46 | * hardware, but (a) there's no record keeping for bandwidth; |
| 47 | * (b) in the common case that few endpoints are available, there |
| 48 | * is no mechanism to reuse endpoints to talk to multiple devices. |
| 49 | * |
| 50 | * RESULT: At one extreme, bandwidth can be overcommitted in |
| 51 | * some hardware configurations, no faults will be reported. |
| 52 | * At the other extreme, the bandwidth capabilities which do |
| 53 | * exist tend to be severely undercommitted. You can't yet hook |
| 54 | * up both a keyboard and a mouse to an external USB hub. |
| 55 | */ |
| 56 | |
| 57 | /* |
| 58 | * This gets many kinds of configuration information: |
| 59 | * - Kconfig for everything user-configurable |
| 60 | * - platform_device for addressing, irq, and platform_data |
| 61 | * - platform_data is mostly for board-specific information |
| 62 | * (plus recentrly, SOC or family details) |
| 63 | * |
| 64 | * Most of the conditional compilation will (someday) vanish. |
| 65 | */ |
| 66 | |
| 67 | #include <linux/module.h> |
| 68 | #include <linux/kernel.h> |
| 69 | #include <linux/sched.h> |
| 70 | #include <linux/slab.h> |
| 71 | #include <linux/list.h> |
| 72 | #include <linux/kobject.h> |
| 73 | #include <linux/prefetch.h> |
| 74 | #include <linux/platform_device.h> |
| 75 | #include <linux/io.h> |
| 76 | #include <linux/iopoll.h> |
| 77 | #include <linux/dma-mapping.h> |
| 78 | #include <linux/usb.h> |
| 79 | #include <linux/usb/of.h> |
| 80 | |
| 81 | #include "musb_core.h" |
| 82 | #include "musb_trace.h" |
| 83 | |
| 84 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
| 85 | |
| 86 | |
| 87 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
| 88 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" |
| 89 | |
| 90 | #define MUSB_VERSION "6.0" |
| 91 | |
| 92 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION |
| 93 | |
| 94 | #define MUSB_DRIVER_NAME "musb-hdrc" |
| 95 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
| 96 | |
| 97 | MODULE_DESCRIPTION(DRIVER_INFO); |
| 98 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 99 | MODULE_LICENSE("GPL"); |
| 100 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); |
| 101 | |
| 102 | |
| 103 | /*-------------------------------------------------------------------------*/ |
| 104 | |
| 105 | static inline struct musb *dev_to_musb(struct device *dev) |
| 106 | { |
| 107 | return dev_get_drvdata(dev); |
| 108 | } |
| 109 | |
| 110 | enum musb_mode musb_get_mode(struct device *dev) |
| 111 | { |
| 112 | enum usb_dr_mode mode; |
| 113 | |
| 114 | mode = usb_get_dr_mode(dev); |
| 115 | switch (mode) { |
| 116 | case USB_DR_MODE_HOST: |
| 117 | return MUSB_HOST; |
| 118 | case USB_DR_MODE_PERIPHERAL: |
| 119 | return MUSB_PERIPHERAL; |
| 120 | case USB_DR_MODE_OTG: |
| 121 | case USB_DR_MODE_UNKNOWN: |
| 122 | default: |
| 123 | return MUSB_OTG; |
| 124 | } |
| 125 | } |
| 126 | EXPORT_SYMBOL_GPL(musb_get_mode); |
| 127 | |
| 128 | /*-------------------------------------------------------------------------*/ |
| 129 | |
| 130 | static int musb_ulpi_read(struct usb_phy *phy, u32 reg) |
| 131 | { |
| 132 | void __iomem *addr = phy->io_priv; |
| 133 | int i = 0; |
| 134 | u8 r; |
| 135 | u8 power; |
| 136 | int ret; |
| 137 | |
| 138 | pm_runtime_get_sync(phy->io_dev); |
| 139 | |
| 140 | /* Make sure the transceiver is not in low power mode */ |
| 141 | power = musb_readb(addr, MUSB_POWER); |
| 142 | power &= ~MUSB_POWER_SUSPENDM; |
| 143 | musb_writeb(addr, MUSB_POWER, power); |
| 144 | |
| 145 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the |
| 146 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. |
| 147 | */ |
| 148 | |
| 149 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); |
| 150 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, |
| 151 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); |
| 152 | |
| 153 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) |
| 154 | & MUSB_ULPI_REG_CMPLT)) { |
| 155 | i++; |
| 156 | if (i == 10000) { |
| 157 | ret = -ETIMEDOUT; |
| 158 | goto out; |
| 159 | } |
| 160 | |
| 161 | } |
| 162 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); |
| 163 | r &= ~MUSB_ULPI_REG_CMPLT; |
| 164 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); |
| 165 | |
| 166 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
| 167 | |
| 168 | out: |
| 169 | pm_runtime_put(phy->io_dev); |
| 170 | |
| 171 | return ret; |
| 172 | } |
| 173 | |
| 174 | static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
| 175 | { |
| 176 | void __iomem *addr = phy->io_priv; |
| 177 | int i = 0; |
| 178 | u8 r = 0; |
| 179 | u8 power; |
| 180 | int ret = 0; |
| 181 | |
| 182 | pm_runtime_get_sync(phy->io_dev); |
| 183 | |
| 184 | /* Make sure the transceiver is not in low power mode */ |
| 185 | power = musb_readb(addr, MUSB_POWER); |
| 186 | power &= ~MUSB_POWER_SUSPENDM; |
| 187 | musb_writeb(addr, MUSB_POWER, power); |
| 188 | |
| 189 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); |
| 190 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val); |
| 191 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); |
| 192 | |
| 193 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) |
| 194 | & MUSB_ULPI_REG_CMPLT)) { |
| 195 | i++; |
| 196 | if (i == 10000) { |
| 197 | ret = -ETIMEDOUT; |
| 198 | goto out; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); |
| 203 | r &= ~MUSB_ULPI_REG_CMPLT; |
| 204 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); |
| 205 | |
| 206 | out: |
| 207 | pm_runtime_put(phy->io_dev); |
| 208 | |
| 209 | return ret; |
| 210 | } |
| 211 | |
| 212 | static struct usb_phy_io_ops musb_ulpi_access = { |
| 213 | .read = musb_ulpi_read, |
| 214 | .write = musb_ulpi_write, |
| 215 | }; |
| 216 | |
| 217 | /*-------------------------------------------------------------------------*/ |
| 218 | |
| 219 | static u32 musb_default_fifo_offset(u8 epnum) |
| 220 | { |
| 221 | return 0x20 + (epnum * 4); |
| 222 | } |
| 223 | |
| 224 | /* "flat" mapping: each endpoint has its own i/o address */ |
| 225 | static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) |
| 226 | { |
| 227 | } |
| 228 | |
| 229 | static u32 musb_flat_ep_offset(u8 epnum, u16 offset) |
| 230 | { |
| 231 | return 0x100 + (0x10 * epnum) + offset; |
| 232 | } |
| 233 | |
| 234 | /* "indexed" mapping: INDEX register controls register bank select */ |
| 235 | static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) |
| 236 | { |
| 237 | musb_writeb(mbase, MUSB_INDEX, epnum); |
| 238 | } |
| 239 | |
| 240 | static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) |
| 241 | { |
| 242 | return 0x10 + offset; |
| 243 | } |
| 244 | |
| 245 | static u32 musb_default_busctl_offset(u8 epnum, u16 offset) |
| 246 | { |
| 247 | return 0x80 + (0x08 * epnum) + offset; |
| 248 | } |
| 249 | |
| 250 | static u8 musb_default_readb(void __iomem *addr, u32 offset) |
| 251 | { |
| 252 | u8 data = __raw_readb(addr + offset); |
| 253 | |
| 254 | trace_musb_readb(__builtin_return_address(0), addr, offset, data); |
| 255 | return data; |
| 256 | } |
| 257 | |
| 258 | static void musb_default_writeb(void __iomem *addr, u32 offset, u8 data) |
| 259 | { |
| 260 | trace_musb_writeb(__builtin_return_address(0), addr, offset, data); |
| 261 | __raw_writeb(data, addr + offset); |
| 262 | } |
| 263 | |
| 264 | static u16 musb_default_readw(void __iomem *addr, u32 offset) |
| 265 | { |
| 266 | u16 data = __raw_readw(addr + offset); |
| 267 | |
| 268 | trace_musb_readw(__builtin_return_address(0), addr, offset, data); |
| 269 | return data; |
| 270 | } |
| 271 | |
| 272 | static void musb_default_writew(void __iomem *addr, u32 offset, u16 data) |
| 273 | { |
| 274 | trace_musb_writew(__builtin_return_address(0), addr, offset, data); |
| 275 | __raw_writew(data, addr + offset); |
| 276 | } |
| 277 | |
| 278 | static u16 musb_default_get_toggle(struct musb_qh *qh, int is_out) |
| 279 | { |
| 280 | void __iomem *epio = qh->hw_ep->regs; |
| 281 | u16 csr; |
| 282 | |
| 283 | if (is_out) |
| 284 | csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; |
| 285 | else |
| 286 | csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; |
| 287 | |
| 288 | return csr; |
| 289 | } |
| 290 | |
| 291 | static u16 musb_default_set_toggle(struct musb_qh *qh, int is_out, |
| 292 | struct urb *urb) |
| 293 | { |
| 294 | u16 csr; |
| 295 | u16 toggle; |
| 296 | |
| 297 | toggle = usb_gettoggle(urb->dev, qh->epnum, is_out); |
| 298 | |
| 299 | if (is_out) |
| 300 | csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE |
| 301 | | MUSB_TXCSR_H_DATATOGGLE) |
| 302 | : MUSB_TXCSR_CLRDATATOG; |
| 303 | else |
| 304 | csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE |
| 305 | | MUSB_RXCSR_H_DATATOGGLE) : 0; |
| 306 | |
| 307 | return csr; |
| 308 | } |
| 309 | |
| 310 | /* |
| 311 | * Load an endpoint's FIFO |
| 312 | */ |
| 313 | static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, |
| 314 | const u8 *src) |
| 315 | { |
| 316 | struct musb *musb = hw_ep->musb; |
| 317 | void __iomem *fifo = hw_ep->fifo; |
| 318 | |
| 319 | if (unlikely(len == 0)) |
| 320 | return; |
| 321 | |
| 322 | prefetch((u8 *)src); |
| 323 | |
| 324 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
| 325 | 'T', hw_ep->epnum, fifo, len, src); |
| 326 | |
| 327 | /* we can't assume unaligned reads work */ |
| 328 | if (likely((0x01 & (unsigned long) src) == 0)) { |
| 329 | u16 index = 0; |
| 330 | |
| 331 | /* best case is 32bit-aligned source address */ |
| 332 | if ((0x02 & (unsigned long) src) == 0) { |
| 333 | if (len >= 4) { |
| 334 | iowrite32_rep(fifo, src + index, len >> 2); |
| 335 | index += len & ~0x03; |
| 336 | } |
| 337 | if (len & 0x02) { |
| 338 | __raw_writew(*(u16 *)&src[index], fifo); |
| 339 | index += 2; |
| 340 | } |
| 341 | } else { |
| 342 | if (len >= 2) { |
| 343 | iowrite16_rep(fifo, src + index, len >> 1); |
| 344 | index += len & ~0x01; |
| 345 | } |
| 346 | } |
| 347 | if (len & 0x01) |
| 348 | __raw_writeb(src[index], fifo); |
| 349 | } else { |
| 350 | /* byte aligned */ |
| 351 | iowrite8_rep(fifo, src, len); |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | /* |
| 356 | * Unload an endpoint's FIFO |
| 357 | */ |
| 358 | static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) |
| 359 | { |
| 360 | struct musb *musb = hw_ep->musb; |
| 361 | void __iomem *fifo = hw_ep->fifo; |
| 362 | |
| 363 | if (unlikely(len == 0)) |
| 364 | return; |
| 365 | |
| 366 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
| 367 | 'R', hw_ep->epnum, fifo, len, dst); |
| 368 | |
| 369 | /* we can't assume unaligned writes work */ |
| 370 | if (likely((0x01 & (unsigned long) dst) == 0)) { |
| 371 | u16 index = 0; |
| 372 | |
| 373 | /* best case is 32bit-aligned destination address */ |
| 374 | if ((0x02 & (unsigned long) dst) == 0) { |
| 375 | if (len >= 4) { |
| 376 | ioread32_rep(fifo, dst, len >> 2); |
| 377 | index = len & ~0x03; |
| 378 | } |
| 379 | if (len & 0x02) { |
| 380 | *(u16 *)&dst[index] = __raw_readw(fifo); |
| 381 | index += 2; |
| 382 | } |
| 383 | } else { |
| 384 | if (len >= 2) { |
| 385 | ioread16_rep(fifo, dst, len >> 1); |
| 386 | index = len & ~0x01; |
| 387 | } |
| 388 | } |
| 389 | if (len & 0x01) |
| 390 | dst[index] = __raw_readb(fifo); |
| 391 | } else { |
| 392 | /* byte aligned */ |
| 393 | ioread8_rep(fifo, dst, len); |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | /* |
| 398 | * Old style IO functions |
| 399 | */ |
| 400 | u8 (*musb_readb)(void __iomem *addr, u32 offset); |
| 401 | EXPORT_SYMBOL_GPL(musb_readb); |
| 402 | |
| 403 | void (*musb_writeb)(void __iomem *addr, u32 offset, u8 data); |
| 404 | EXPORT_SYMBOL_GPL(musb_writeb); |
| 405 | |
| 406 | u8 (*musb_clearb)(void __iomem *addr, u32 offset); |
| 407 | EXPORT_SYMBOL_GPL(musb_clearb); |
| 408 | |
| 409 | u16 (*musb_readw)(void __iomem *addr, u32 offset); |
| 410 | EXPORT_SYMBOL_GPL(musb_readw); |
| 411 | |
| 412 | void (*musb_writew)(void __iomem *addr, u32 offset, u16 data); |
| 413 | EXPORT_SYMBOL_GPL(musb_writew); |
| 414 | |
| 415 | u16 (*musb_clearw)(void __iomem *addr, u32 offset); |
| 416 | EXPORT_SYMBOL_GPL(musb_clearw); |
| 417 | |
| 418 | u32 musb_readl(void __iomem *addr, u32 offset) |
| 419 | { |
| 420 | u32 data = __raw_readl(addr + offset); |
| 421 | |
| 422 | trace_musb_readl(__builtin_return_address(0), addr, offset, data); |
| 423 | return data; |
| 424 | } |
| 425 | EXPORT_SYMBOL_GPL(musb_readl); |
| 426 | |
| 427 | void musb_writel(void __iomem *addr, u32 offset, u32 data) |
| 428 | { |
| 429 | trace_musb_writel(__builtin_return_address(0), addr, offset, data); |
| 430 | __raw_writel(data, addr + offset); |
| 431 | } |
| 432 | EXPORT_SYMBOL_GPL(musb_writel); |
| 433 | |
| 434 | #ifndef CONFIG_MUSB_PIO_ONLY |
| 435 | struct dma_controller * |
| 436 | (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); |
| 437 | EXPORT_SYMBOL(musb_dma_controller_create); |
| 438 | |
| 439 | void (*musb_dma_controller_destroy)(struct dma_controller *c); |
| 440 | EXPORT_SYMBOL(musb_dma_controller_destroy); |
| 441 | #endif |
| 442 | |
| 443 | /* |
| 444 | * New style IO functions |
| 445 | */ |
| 446 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) |
| 447 | { |
| 448 | return hw_ep->musb->io.read_fifo(hw_ep, len, dst); |
| 449 | } |
| 450 | |
| 451 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) |
| 452 | { |
| 453 | return hw_ep->musb->io.write_fifo(hw_ep, len, src); |
| 454 | } |
| 455 | |
| 456 | static u8 musb_read_devctl(struct musb *musb) |
| 457 | { |
| 458 | return musb_readb(musb->mregs, MUSB_DEVCTL); |
| 459 | } |
| 460 | |
| 461 | /** |
| 462 | * musb_set_host - set and initialize host mode |
| 463 | * @musb: musb controller driver data |
| 464 | * |
| 465 | * At least some musb revisions need to enable devctl session bit in |
| 466 | * peripheral mode to switch to host mode. Initializes things to host |
| 467 | * mode and sets A_IDLE. SoC glue needs to advance state further |
| 468 | * based on phy provided VBUS state. |
| 469 | * |
| 470 | * Note that the SoC glue code may need to wait for musb to settle |
| 471 | * on enable before calling this to avoid babble. |
| 472 | */ |
| 473 | int musb_set_host(struct musb *musb) |
| 474 | { |
| 475 | int error = 0; |
| 476 | u8 devctl; |
| 477 | |
| 478 | if (!musb) |
| 479 | return -EINVAL; |
| 480 | |
| 481 | devctl = musb_read_devctl(musb); |
| 482 | if (!(devctl & MUSB_DEVCTL_BDEVICE)) { |
| 483 | dev_info(musb->controller, |
| 484 | "%s: already in host mode: %02x\n", |
| 485 | __func__, devctl); |
| 486 | goto init_data; |
| 487 | } |
| 488 | |
| 489 | devctl |= MUSB_DEVCTL_SESSION; |
| 490 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); |
| 491 | |
| 492 | error = readx_poll_timeout(musb_read_devctl, musb, devctl, |
| 493 | !(devctl & MUSB_DEVCTL_BDEVICE), 5000, |
| 494 | 1000000); |
| 495 | if (error) { |
| 496 | dev_err(musb->controller, "%s: could not set host: %02x\n", |
| 497 | __func__, devctl); |
| 498 | |
| 499 | return error; |
| 500 | } |
| 501 | |
| 502 | init_data: |
| 503 | musb->is_active = 1; |
| 504 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
| 505 | MUSB_HST_MODE(musb); |
| 506 | |
| 507 | return error; |
| 508 | } |
| 509 | EXPORT_SYMBOL_GPL(musb_set_host); |
| 510 | |
| 511 | /** |
| 512 | * musb_set_peripheral - set and initialize peripheral mode |
| 513 | * @musb: musb controller driver data |
| 514 | * |
| 515 | * Clears devctl session bit and initializes things for peripheral |
| 516 | * mode and sets B_IDLE. SoC glue needs to advance state further |
| 517 | * based on phy provided VBUS state. |
| 518 | */ |
| 519 | int musb_set_peripheral(struct musb *musb) |
| 520 | { |
| 521 | int error = 0; |
| 522 | u8 devctl; |
| 523 | |
| 524 | if (!musb) |
| 525 | return -EINVAL; |
| 526 | |
| 527 | devctl = musb_read_devctl(musb); |
| 528 | if (devctl & MUSB_DEVCTL_BDEVICE) { |
| 529 | dev_info(musb->controller, |
| 530 | "%s: already in peripheral mode: %02x\n", |
| 531 | __func__, devctl); |
| 532 | |
| 533 | goto init_data; |
| 534 | } |
| 535 | |
| 536 | devctl &= ~MUSB_DEVCTL_SESSION; |
| 537 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); |
| 538 | |
| 539 | error = readx_poll_timeout(musb_read_devctl, musb, devctl, |
| 540 | devctl & MUSB_DEVCTL_BDEVICE, 5000, |
| 541 | 1000000); |
| 542 | if (error) { |
| 543 | dev_err(musb->controller, "%s: could not set peripheral: %02x\n", |
| 544 | __func__, devctl); |
| 545 | |
| 546 | return error; |
| 547 | } |
| 548 | |
| 549 | init_data: |
| 550 | musb->is_active = 0; |
| 551 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
| 552 | MUSB_DEV_MODE(musb); |
| 553 | |
| 554 | return error; |
| 555 | } |
| 556 | EXPORT_SYMBOL_GPL(musb_set_peripheral); |
| 557 | |
| 558 | /*-------------------------------------------------------------------------*/ |
| 559 | |
| 560 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ |
| 561 | static const u8 musb_test_packet[53] = { |
| 562 | /* implicit SYNC then DATA0 to start */ |
| 563 | |
| 564 | /* JKJKJKJK x9 */ |
| 565 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 566 | /* JJKKJJKK x8 */ |
| 567 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, |
| 568 | /* JJJJKKKK x8 */ |
| 569 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, |
| 570 | /* JJJJJJJKKKKKKK x8 */ |
| 571 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
| 572 | /* JJJJJJJK x8 */ |
| 573 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, |
| 574 | /* JKKKKKKK x10, JK */ |
| 575 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e |
| 576 | |
| 577 | /* implicit CRC16 then EOP to end */ |
| 578 | }; |
| 579 | |
| 580 | void musb_load_testpacket(struct musb *musb) |
| 581 | { |
| 582 | void __iomem *regs = musb->endpoints[0].regs; |
| 583 | |
| 584 | musb_ep_select(musb->mregs, 0); |
| 585 | musb_write_fifo(musb->control_ep, |
| 586 | sizeof(musb_test_packet), musb_test_packet); |
| 587 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); |
| 588 | } |
| 589 | |
| 590 | /*-------------------------------------------------------------------------*/ |
| 591 | |
| 592 | /* |
| 593 | * Handles OTG hnp timeouts, such as b_ase0_brst |
| 594 | */ |
| 595 | static void musb_otg_timer_func(struct timer_list *t) |
| 596 | { |
| 597 | struct musb *musb = from_timer(musb, t, otg_timer); |
| 598 | unsigned long flags; |
| 599 | |
| 600 | spin_lock_irqsave(&musb->lock, flags); |
| 601 | switch (musb->xceiv->otg->state) { |
| 602 | case OTG_STATE_B_WAIT_ACON: |
| 603 | musb_dbg(musb, |
| 604 | "HNP: b_wait_acon timeout; back to b_peripheral"); |
| 605 | musb_g_disconnect(musb); |
| 606 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
| 607 | musb->is_active = 0; |
| 608 | break; |
| 609 | case OTG_STATE_A_SUSPEND: |
| 610 | case OTG_STATE_A_WAIT_BCON: |
| 611 | musb_dbg(musb, "HNP: %s timeout", |
| 612 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 613 | musb_platform_set_vbus(musb, 0); |
| 614 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
| 615 | break; |
| 616 | default: |
| 617 | musb_dbg(musb, "HNP: Unhandled mode %s", |
| 618 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 619 | } |
| 620 | spin_unlock_irqrestore(&musb->lock, flags); |
| 621 | } |
| 622 | |
| 623 | /* |
| 624 | * Stops the HNP transition. Caller must take care of locking. |
| 625 | */ |
| 626 | void musb_hnp_stop(struct musb *musb) |
| 627 | { |
| 628 | struct usb_hcd *hcd = musb->hcd; |
| 629 | void __iomem *mbase = musb->mregs; |
| 630 | u8 reg; |
| 631 | |
| 632 | musb_dbg(musb, "HNP: stop from %s", |
| 633 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 634 | |
| 635 | switch (musb->xceiv->otg->state) { |
| 636 | case OTG_STATE_A_PERIPHERAL: |
| 637 | musb_g_disconnect(musb); |
| 638 | musb_dbg(musb, "HNP: back to %s", |
| 639 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 640 | break; |
| 641 | case OTG_STATE_B_HOST: |
| 642 | musb_dbg(musb, "HNP: Disabling HR"); |
| 643 | if (hcd) |
| 644 | hcd->self.is_b_host = 0; |
| 645 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
| 646 | MUSB_DEV_MODE(musb); |
| 647 | reg = musb_readb(mbase, MUSB_POWER); |
| 648 | reg |= MUSB_POWER_SUSPENDM; |
| 649 | musb_writeb(mbase, MUSB_POWER, reg); |
| 650 | /* REVISIT: Start SESSION_REQUEST here? */ |
| 651 | break; |
| 652 | default: |
| 653 | musb_dbg(musb, "HNP: Stopping in unknown state %s", |
| 654 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 655 | } |
| 656 | |
| 657 | /* |
| 658 | * When returning to A state after HNP, avoid hub_port_rebounce(), |
| 659 | * which cause occasional OPT A "Did not receive reset after connect" |
| 660 | * errors. |
| 661 | */ |
| 662 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
| 663 | } |
| 664 | |
| 665 | static void musb_recover_from_babble(struct musb *musb); |
| 666 | |
| 667 | static void musb_handle_intr_resume(struct musb *musb, u8 devctl) |
| 668 | { |
| 669 | musb_dbg(musb, "RESUME (%s)", |
| 670 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 671 | |
| 672 | if (devctl & MUSB_DEVCTL_HM) { |
| 673 | switch (musb->xceiv->otg->state) { |
| 674 | case OTG_STATE_A_SUSPEND: |
| 675 | /* remote wakeup? */ |
| 676 | musb->port1_status |= |
| 677 | (USB_PORT_STAT_C_SUSPEND << 16) |
| 678 | | MUSB_PORT_STAT_RESUME; |
| 679 | musb->rh_timer = jiffies |
| 680 | + msecs_to_jiffies(USB_RESUME_TIMEOUT); |
| 681 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
| 682 | musb->is_active = 1; |
| 683 | musb_host_resume_root_hub(musb); |
| 684 | schedule_delayed_work(&musb->finish_resume_work, |
| 685 | msecs_to_jiffies(USB_RESUME_TIMEOUT)); |
| 686 | break; |
| 687 | case OTG_STATE_B_WAIT_ACON: |
| 688 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
| 689 | musb->is_active = 1; |
| 690 | MUSB_DEV_MODE(musb); |
| 691 | break; |
| 692 | default: |
| 693 | WARNING("bogus %s RESUME (%s)\n", |
| 694 | "host", |
| 695 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 696 | } |
| 697 | } else { |
| 698 | switch (musb->xceiv->otg->state) { |
| 699 | case OTG_STATE_A_SUSPEND: |
| 700 | /* possibly DISCONNECT is upcoming */ |
| 701 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
| 702 | musb_host_resume_root_hub(musb); |
| 703 | break; |
| 704 | case OTG_STATE_B_WAIT_ACON: |
| 705 | case OTG_STATE_B_PERIPHERAL: |
| 706 | /* disconnect while suspended? we may |
| 707 | * not get a disconnect irq... |
| 708 | */ |
| 709 | if ((devctl & MUSB_DEVCTL_VBUS) |
| 710 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) |
| 711 | ) { |
| 712 | musb->int_usb |= MUSB_INTR_DISCONNECT; |
| 713 | musb->int_usb &= ~MUSB_INTR_SUSPEND; |
| 714 | break; |
| 715 | } |
| 716 | musb_g_resume(musb); |
| 717 | break; |
| 718 | case OTG_STATE_B_IDLE: |
| 719 | musb->int_usb &= ~MUSB_INTR_SUSPEND; |
| 720 | break; |
| 721 | default: |
| 722 | WARNING("bogus %s RESUME (%s)\n", |
| 723 | "peripheral", |
| 724 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 725 | } |
| 726 | } |
| 727 | } |
| 728 | |
| 729 | /* return IRQ_HANDLED to tell the caller to return immediately */ |
| 730 | static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl) |
| 731 | { |
| 732 | void __iomem *mbase = musb->mregs; |
| 733 | |
| 734 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
| 735 | && (devctl & MUSB_DEVCTL_BDEVICE)) { |
| 736 | musb_dbg(musb, "SessReq while on B state"); |
| 737 | return IRQ_HANDLED; |
| 738 | } |
| 739 | |
| 740 | musb_dbg(musb, "SESSION_REQUEST (%s)", |
| 741 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 742 | |
| 743 | /* IRQ arrives from ID pin sense or (later, if VBUS power |
| 744 | * is removed) SRP. responses are time critical: |
| 745 | * - turn on VBUS (with silicon-specific mechanism) |
| 746 | * - go through A_WAIT_VRISE |
| 747 | * - ... to A_WAIT_BCON. |
| 748 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions |
| 749 | */ |
| 750 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); |
| 751 | musb->ep0_stage = MUSB_EP0_START; |
| 752 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
| 753 | MUSB_HST_MODE(musb); |
| 754 | musb_platform_set_vbus(musb, 1); |
| 755 | |
| 756 | return IRQ_NONE; |
| 757 | } |
| 758 | |
| 759 | static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl) |
| 760 | { |
| 761 | int ignore = 0; |
| 762 | |
| 763 | /* During connection as an A-Device, we may see a short |
| 764 | * current spikes causing voltage drop, because of cable |
| 765 | * and peripheral capacitance combined with vbus draw. |
| 766 | * (So: less common with truly self-powered devices, where |
| 767 | * vbus doesn't act like a power supply.) |
| 768 | * |
| 769 | * Such spikes are short; usually less than ~500 usec, max |
| 770 | * of ~2 msec. That is, they're not sustained overcurrent |
| 771 | * errors, though they're reported using VBUSERROR irqs. |
| 772 | * |
| 773 | * Workarounds: (a) hardware: use self powered devices. |
| 774 | * (b) software: ignore non-repeated VBUS errors. |
| 775 | * |
| 776 | * REVISIT: do delays from lots of DEBUG_KERNEL checks |
| 777 | * make trouble here, keeping VBUS < 4.4V ? |
| 778 | */ |
| 779 | switch (musb->xceiv->otg->state) { |
| 780 | case OTG_STATE_A_HOST: |
| 781 | /* recovery is dicey once we've gotten past the |
| 782 | * initial stages of enumeration, but if VBUS |
| 783 | * stayed ok at the other end of the link, and |
| 784 | * another reset is due (at least for high speed, |
| 785 | * to redo the chirp etc), it might work OK... |
| 786 | */ |
| 787 | case OTG_STATE_A_WAIT_BCON: |
| 788 | case OTG_STATE_A_WAIT_VRISE: |
| 789 | if (musb->vbuserr_retry) { |
| 790 | void __iomem *mbase = musb->mregs; |
| 791 | |
| 792 | musb->vbuserr_retry--; |
| 793 | ignore = 1; |
| 794 | devctl |= MUSB_DEVCTL_SESSION; |
| 795 | musb_writeb(mbase, MUSB_DEVCTL, devctl); |
| 796 | } else { |
| 797 | musb->port1_status |= |
| 798 | USB_PORT_STAT_OVERCURRENT |
| 799 | | (USB_PORT_STAT_C_OVERCURRENT << 16); |
| 800 | } |
| 801 | break; |
| 802 | default: |
| 803 | break; |
| 804 | } |
| 805 | |
| 806 | dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, |
| 807 | "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", |
| 808 | usb_otg_state_string(musb->xceiv->otg->state), |
| 809 | devctl, |
| 810 | ({ char *s; |
| 811 | switch (devctl & MUSB_DEVCTL_VBUS) { |
| 812 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: |
| 813 | s = "<SessEnd"; break; |
| 814 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: |
| 815 | s = "<AValid"; break; |
| 816 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: |
| 817 | s = "<VBusValid"; break; |
| 818 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ |
| 819 | default: |
| 820 | s = "VALID"; break; |
| 821 | } s; }), |
| 822 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, |
| 823 | musb->port1_status); |
| 824 | |
| 825 | /* go through A_WAIT_VFALL then start a new session */ |
| 826 | if (!ignore) |
| 827 | musb_platform_set_vbus(musb, 0); |
| 828 | } |
| 829 | |
| 830 | static void musb_handle_intr_suspend(struct musb *musb, u8 devctl) |
| 831 | { |
| 832 | musb_dbg(musb, "SUSPEND (%s) devctl %02x", |
| 833 | usb_otg_state_string(musb->xceiv->otg->state), devctl); |
| 834 | |
| 835 | switch (musb->xceiv->otg->state) { |
| 836 | case OTG_STATE_A_PERIPHERAL: |
| 837 | /* We also come here if the cable is removed, since |
| 838 | * this silicon doesn't report ID-no-longer-grounded. |
| 839 | * |
| 840 | * We depend on T(a_wait_bcon) to shut us down, and |
| 841 | * hope users don't do anything dicey during this |
| 842 | * undesired detour through A_WAIT_BCON. |
| 843 | */ |
| 844 | musb_hnp_stop(musb); |
| 845 | musb_host_resume_root_hub(musb); |
| 846 | musb_root_disconnect(musb); |
| 847 | musb_platform_try_idle(musb, jiffies |
| 848 | + msecs_to_jiffies(musb->a_wait_bcon |
| 849 | ? : OTG_TIME_A_WAIT_BCON)); |
| 850 | |
| 851 | break; |
| 852 | case OTG_STATE_B_IDLE: |
| 853 | if (!musb->is_active) |
| 854 | break; |
| 855 | /* fall through */ |
| 856 | case OTG_STATE_B_PERIPHERAL: |
| 857 | musb_g_suspend(musb); |
| 858 | musb->is_active = musb->g.b_hnp_enable; |
| 859 | if (musb->is_active) { |
| 860 | musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON; |
| 861 | musb_dbg(musb, "HNP: Setting timer for b_ase0_brst"); |
| 862 | mod_timer(&musb->otg_timer, jiffies |
| 863 | + msecs_to_jiffies( |
| 864 | OTG_TIME_B_ASE0_BRST)); |
| 865 | } |
| 866 | break; |
| 867 | case OTG_STATE_A_WAIT_BCON: |
| 868 | if (musb->a_wait_bcon != 0) |
| 869 | musb_platform_try_idle(musb, jiffies |
| 870 | + msecs_to_jiffies(musb->a_wait_bcon)); |
| 871 | break; |
| 872 | case OTG_STATE_A_HOST: |
| 873 | musb->xceiv->otg->state = OTG_STATE_A_SUSPEND; |
| 874 | musb->is_active = musb->hcd->self.b_hnp_enable; |
| 875 | break; |
| 876 | case OTG_STATE_B_HOST: |
| 877 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ |
| 878 | musb_dbg(musb, "REVISIT: SUSPEND as B_HOST"); |
| 879 | break; |
| 880 | default: |
| 881 | /* "should not happen" */ |
| 882 | musb->is_active = 0; |
| 883 | break; |
| 884 | } |
| 885 | } |
| 886 | |
| 887 | static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb) |
| 888 | { |
| 889 | struct usb_hcd *hcd = musb->hcd; |
| 890 | |
| 891 | musb->is_active = 1; |
| 892 | musb->ep0_stage = MUSB_EP0_START; |
| 893 | |
| 894 | musb->intrtxe = musb->epmask; |
| 895 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); |
| 896 | musb->intrrxe = musb->epmask & 0xfffe; |
| 897 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); |
| 898 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); |
| 899 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
| 900 | |USB_PORT_STAT_HIGH_SPEED |
| 901 | |USB_PORT_STAT_ENABLE |
| 902 | ); |
| 903 | musb->port1_status |= USB_PORT_STAT_CONNECTION |
| 904 | |(USB_PORT_STAT_C_CONNECTION << 16); |
| 905 | |
| 906 | /* high vs full speed is just a guess until after reset */ |
| 907 | if (devctl & MUSB_DEVCTL_LSDEV) |
| 908 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; |
| 909 | |
| 910 | /* indicate new connection to OTG machine */ |
| 911 | switch (musb->xceiv->otg->state) { |
| 912 | case OTG_STATE_B_PERIPHERAL: |
| 913 | if (int_usb & MUSB_INTR_SUSPEND) { |
| 914 | musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host"); |
| 915 | int_usb &= ~MUSB_INTR_SUSPEND; |
| 916 | goto b_host; |
| 917 | } else |
| 918 | musb_dbg(musb, "CONNECT as b_peripheral???"); |
| 919 | break; |
| 920 | case OTG_STATE_B_WAIT_ACON: |
| 921 | musb_dbg(musb, "HNP: CONNECT, now b_host"); |
| 922 | b_host: |
| 923 | musb->xceiv->otg->state = OTG_STATE_B_HOST; |
| 924 | if (musb->hcd) |
| 925 | musb->hcd->self.is_b_host = 1; |
| 926 | del_timer(&musb->otg_timer); |
| 927 | break; |
| 928 | default: |
| 929 | if ((devctl & MUSB_DEVCTL_VBUS) |
| 930 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { |
| 931 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
| 932 | if (hcd) |
| 933 | hcd->self.is_b_host = 0; |
| 934 | } |
| 935 | break; |
| 936 | } |
| 937 | |
| 938 | musb_host_poke_root_hub(musb); |
| 939 | |
| 940 | musb_dbg(musb, "CONNECT (%s) devctl %02x", |
| 941 | usb_otg_state_string(musb->xceiv->otg->state), devctl); |
| 942 | } |
| 943 | |
| 944 | static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl) |
| 945 | { |
| 946 | musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x", |
| 947 | usb_otg_state_string(musb->xceiv->otg->state), |
| 948 | MUSB_MODE(musb), devctl); |
| 949 | |
| 950 | switch (musb->xceiv->otg->state) { |
| 951 | case OTG_STATE_A_HOST: |
| 952 | case OTG_STATE_A_SUSPEND: |
| 953 | musb_host_resume_root_hub(musb); |
| 954 | musb_root_disconnect(musb); |
| 955 | if (musb->a_wait_bcon != 0) |
| 956 | musb_platform_try_idle(musb, jiffies |
| 957 | + msecs_to_jiffies(musb->a_wait_bcon)); |
| 958 | break; |
| 959 | case OTG_STATE_B_HOST: |
| 960 | /* REVISIT this behaves for "real disconnect" |
| 961 | * cases; make sure the other transitions from |
| 962 | * from B_HOST act right too. The B_HOST code |
| 963 | * in hnp_stop() is currently not used... |
| 964 | */ |
| 965 | musb_root_disconnect(musb); |
| 966 | if (musb->hcd) |
| 967 | musb->hcd->self.is_b_host = 0; |
| 968 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
| 969 | MUSB_DEV_MODE(musb); |
| 970 | musb_g_disconnect(musb); |
| 971 | break; |
| 972 | case OTG_STATE_A_PERIPHERAL: |
| 973 | musb_hnp_stop(musb); |
| 974 | musb_root_disconnect(musb); |
| 975 | /* FALLTHROUGH */ |
| 976 | case OTG_STATE_B_WAIT_ACON: |
| 977 | /* FALLTHROUGH */ |
| 978 | case OTG_STATE_B_PERIPHERAL: |
| 979 | case OTG_STATE_B_IDLE: |
| 980 | musb_g_disconnect(musb); |
| 981 | break; |
| 982 | default: |
| 983 | WARNING("unhandled DISCONNECT transition (%s)\n", |
| 984 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 985 | break; |
| 986 | } |
| 987 | } |
| 988 | |
| 989 | /* |
| 990 | * mentor saves a bit: bus reset and babble share the same irq. |
| 991 | * only host sees babble; only peripheral sees bus reset. |
| 992 | */ |
| 993 | static void musb_handle_intr_reset(struct musb *musb) |
| 994 | { |
| 995 | if (is_host_active(musb)) { |
| 996 | /* |
| 997 | * When BABBLE happens what we can depends on which |
| 998 | * platform MUSB is running, because some platforms |
| 999 | * implemented proprietary means for 'recovering' from |
| 1000 | * Babble conditions. One such platform is AM335x. In |
| 1001 | * most cases, however, the only thing we can do is |
| 1002 | * drop the session. |
| 1003 | */ |
| 1004 | dev_err(musb->controller, "Babble\n"); |
| 1005 | musb_recover_from_babble(musb); |
| 1006 | } else { |
| 1007 | musb_dbg(musb, "BUS RESET as %s", |
| 1008 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 1009 | switch (musb->xceiv->otg->state) { |
| 1010 | case OTG_STATE_A_SUSPEND: |
| 1011 | musb_g_reset(musb); |
| 1012 | /* FALLTHROUGH */ |
| 1013 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ |
| 1014 | /* never use invalid T(a_wait_bcon) */ |
| 1015 | musb_dbg(musb, "HNP: in %s, %d msec timeout", |
| 1016 | usb_otg_state_string(musb->xceiv->otg->state), |
| 1017 | TA_WAIT_BCON(musb)); |
| 1018 | mod_timer(&musb->otg_timer, jiffies |
| 1019 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); |
| 1020 | break; |
| 1021 | case OTG_STATE_A_PERIPHERAL: |
| 1022 | del_timer(&musb->otg_timer); |
| 1023 | musb_g_reset(musb); |
| 1024 | break; |
| 1025 | case OTG_STATE_B_WAIT_ACON: |
| 1026 | musb_dbg(musb, "HNP: RESET (%s), to b_peripheral", |
| 1027 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 1028 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
| 1029 | musb_g_reset(musb); |
| 1030 | break; |
| 1031 | case OTG_STATE_B_IDLE: |
| 1032 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
| 1033 | /* FALLTHROUGH */ |
| 1034 | case OTG_STATE_B_PERIPHERAL: |
| 1035 | musb_g_reset(musb); |
| 1036 | break; |
| 1037 | default: |
| 1038 | musb_dbg(musb, "Unhandled BUS RESET as %s", |
| 1039 | usb_otg_state_string(musb->xceiv->otg->state)); |
| 1040 | } |
| 1041 | } |
| 1042 | } |
| 1043 | |
| 1044 | /* |
| 1045 | * Interrupt Service Routine to record USB "global" interrupts. |
| 1046 | * Since these do not happen often and signify things of |
| 1047 | * paramount importance, it seems OK to check them individually; |
| 1048 | * the order of the tests is specified in the manual |
| 1049 | * |
| 1050 | * @param musb instance pointer |
| 1051 | * @param int_usb register contents |
| 1052 | * @param devctl |
| 1053 | */ |
| 1054 | |
| 1055 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
| 1056 | u8 devctl) |
| 1057 | { |
| 1058 | irqreturn_t handled = IRQ_NONE; |
| 1059 | |
| 1060 | musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb); |
| 1061 | |
| 1062 | /* in host mode, the peripheral may issue remote wakeup. |
| 1063 | * in peripheral mode, the host may resume the link. |
| 1064 | * spurious RESUME irqs happen too, paired with SUSPEND. |
| 1065 | */ |
| 1066 | if (int_usb & MUSB_INTR_RESUME) { |
| 1067 | musb_handle_intr_resume(musb, devctl); |
| 1068 | handled = IRQ_HANDLED; |
| 1069 | } |
| 1070 | |
| 1071 | /* see manual for the order of the tests */ |
| 1072 | if (int_usb & MUSB_INTR_SESSREQ) { |
| 1073 | if (musb_handle_intr_sessreq(musb, devctl)) |
| 1074 | return IRQ_HANDLED; |
| 1075 | handled = IRQ_HANDLED; |
| 1076 | } |
| 1077 | |
| 1078 | if (int_usb & MUSB_INTR_VBUSERROR) { |
| 1079 | musb_handle_intr_vbuserr(musb, devctl); |
| 1080 | handled = IRQ_HANDLED; |
| 1081 | } |
| 1082 | |
| 1083 | if (int_usb & MUSB_INTR_SUSPEND) { |
| 1084 | musb_handle_intr_suspend(musb, devctl); |
| 1085 | handled = IRQ_HANDLED; |
| 1086 | } |
| 1087 | |
| 1088 | if (int_usb & MUSB_INTR_CONNECT) { |
| 1089 | musb_handle_intr_connect(musb, devctl, int_usb); |
| 1090 | handled = IRQ_HANDLED; |
| 1091 | } |
| 1092 | |
| 1093 | if (int_usb & MUSB_INTR_DISCONNECT) { |
| 1094 | musb_handle_intr_disconnect(musb, devctl); |
| 1095 | handled = IRQ_HANDLED; |
| 1096 | } |
| 1097 | |
| 1098 | if (int_usb & MUSB_INTR_RESET) { |
| 1099 | musb_handle_intr_reset(musb); |
| 1100 | handled = IRQ_HANDLED; |
| 1101 | } |
| 1102 | |
| 1103 | #if 0 |
| 1104 | /* REVISIT ... this would be for multiplexing periodic endpoints, or |
| 1105 | * supporting transfer phasing to prevent exceeding ISO bandwidth |
| 1106 | * limits of a given frame or microframe. |
| 1107 | * |
| 1108 | * It's not needed for peripheral side, which dedicates endpoints; |
| 1109 | * though it _might_ use SOF irqs for other purposes. |
| 1110 | * |
| 1111 | * And it's not currently needed for host side, which also dedicates |
| 1112 | * endpoints, relies on TX/RX interval registers, and isn't claimed |
| 1113 | * to support ISO transfers yet. |
| 1114 | */ |
| 1115 | if (int_usb & MUSB_INTR_SOF) { |
| 1116 | void __iomem *mbase = musb->mregs; |
| 1117 | struct musb_hw_ep *ep; |
| 1118 | u8 epnum; |
| 1119 | u16 frame; |
| 1120 | |
| 1121 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
| 1122 | handled = IRQ_HANDLED; |
| 1123 | |
| 1124 | /* start any periodic Tx transfers waiting for current frame */ |
| 1125 | frame = musb_readw(mbase, MUSB_FRAME); |
| 1126 | ep = musb->endpoints; |
| 1127 | for (epnum = 1; (epnum < musb->nr_endpoints) |
| 1128 | && (musb->epmask >= (1 << epnum)); |
| 1129 | epnum++, ep++) { |
| 1130 | /* |
| 1131 | * FIXME handle framecounter wraps (12 bits) |
| 1132 | * eliminate duplicated StartUrb logic |
| 1133 | */ |
| 1134 | if (ep->dwWaitFrame >= frame) { |
| 1135 | ep->dwWaitFrame = 0; |
| 1136 | pr_debug("SOF --> periodic TX%s on %d\n", |
| 1137 | ep->tx_channel ? " DMA" : "", |
| 1138 | epnum); |
| 1139 | if (!ep->tx_channel) |
| 1140 | musb_h_tx_start(musb, epnum); |
| 1141 | else |
| 1142 | cppi_hostdma_start(musb, epnum); |
| 1143 | } |
| 1144 | } /* end of for loop */ |
| 1145 | } |
| 1146 | #endif |
| 1147 | |
| 1148 | schedule_delayed_work(&musb->irq_work, 0); |
| 1149 | |
| 1150 | return handled; |
| 1151 | } |
| 1152 | |
| 1153 | /*-------------------------------------------------------------------------*/ |
| 1154 | |
| 1155 | static void musb_disable_interrupts(struct musb *musb) |
| 1156 | { |
| 1157 | void __iomem *mbase = musb->mregs; |
| 1158 | |
| 1159 | /* disable interrupts */ |
| 1160 | musb_writeb(mbase, MUSB_INTRUSBE, 0); |
| 1161 | musb->intrtxe = 0; |
| 1162 | musb_writew(mbase, MUSB_INTRTXE, 0); |
| 1163 | musb->intrrxe = 0; |
| 1164 | musb_writew(mbase, MUSB_INTRRXE, 0); |
| 1165 | |
| 1166 | /* flush pending interrupts */ |
| 1167 | musb_clearb(mbase, MUSB_INTRUSB); |
| 1168 | musb_clearw(mbase, MUSB_INTRTX); |
| 1169 | musb_clearw(mbase, MUSB_INTRRX); |
| 1170 | } |
| 1171 | |
| 1172 | static void musb_enable_interrupts(struct musb *musb) |
| 1173 | { |
| 1174 | void __iomem *regs = musb->mregs; |
| 1175 | |
| 1176 | /* Set INT enable registers, enable interrupts */ |
| 1177 | musb->intrtxe = musb->epmask; |
| 1178 | musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); |
| 1179 | musb->intrrxe = musb->epmask & 0xfffe; |
| 1180 | musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); |
| 1181 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); |
| 1182 | |
| 1183 | } |
| 1184 | |
| 1185 | /* |
| 1186 | * Program the HDRC to start (enable interrupts, dma, etc.). |
| 1187 | */ |
| 1188 | void musb_start(struct musb *musb) |
| 1189 | { |
| 1190 | void __iomem *regs = musb->mregs; |
| 1191 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); |
| 1192 | u8 power; |
| 1193 | |
| 1194 | musb_dbg(musb, "<== devctl %02x", devctl); |
| 1195 | |
| 1196 | musb_enable_interrupts(musb); |
| 1197 | musb_writeb(regs, MUSB_TESTMODE, 0); |
| 1198 | |
| 1199 | power = MUSB_POWER_ISOUPDATE; |
| 1200 | /* |
| 1201 | * treating UNKNOWN as unspecified maximum speed, in which case |
| 1202 | * we will default to high-speed. |
| 1203 | */ |
| 1204 | if (musb->config->maximum_speed == USB_SPEED_HIGH || |
| 1205 | musb->config->maximum_speed == USB_SPEED_UNKNOWN) |
| 1206 | power |= MUSB_POWER_HSENAB; |
| 1207 | musb_writeb(regs, MUSB_POWER, power); |
| 1208 | |
| 1209 | musb->is_active = 0; |
| 1210 | devctl = musb_readb(regs, MUSB_DEVCTL); |
| 1211 | devctl &= ~MUSB_DEVCTL_SESSION; |
| 1212 | |
| 1213 | /* session started after: |
| 1214 | * (a) ID-grounded irq, host mode; |
| 1215 | * (b) vbus present/connect IRQ, peripheral mode; |
| 1216 | * (c) peripheral initiates, using SRP |
| 1217 | */ |
| 1218 | if (musb->port_mode != MUSB_HOST && |
| 1219 | musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON && |
| 1220 | (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { |
| 1221 | musb->is_active = 1; |
| 1222 | } else { |
| 1223 | devctl |= MUSB_DEVCTL_SESSION; |
| 1224 | } |
| 1225 | |
| 1226 | musb_platform_enable(musb); |
| 1227 | musb_writeb(regs, MUSB_DEVCTL, devctl); |
| 1228 | } |
| 1229 | |
| 1230 | /* |
| 1231 | * Make the HDRC stop (disable interrupts, etc.); |
| 1232 | * reversible by musb_start |
| 1233 | * called on gadget driver unregister |
| 1234 | * with controller locked, irqs blocked |
| 1235 | * acts as a NOP unless some role activated the hardware |
| 1236 | */ |
| 1237 | void musb_stop(struct musb *musb) |
| 1238 | { |
| 1239 | /* stop IRQs, timers, ... */ |
| 1240 | musb_platform_disable(musb); |
| 1241 | musb_disable_interrupts(musb); |
| 1242 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
| 1243 | |
| 1244 | /* FIXME |
| 1245 | * - mark host and/or peripheral drivers unusable/inactive |
| 1246 | * - disable DMA (and enable it in HdrcStart) |
| 1247 | * - make sure we can musb_start() after musb_stop(); with |
| 1248 | * OTG mode, gadget driver module rmmod/modprobe cycles that |
| 1249 | * - ... |
| 1250 | */ |
| 1251 | musb_platform_try_idle(musb, 0); |
| 1252 | } |
| 1253 | |
| 1254 | /*-------------------------------------------------------------------------*/ |
| 1255 | |
| 1256 | /* |
| 1257 | * The silicon either has hard-wired endpoint configurations, or else |
| 1258 | * "dynamic fifo" sizing. The driver has support for both, though at this |
| 1259 | * writing only the dynamic sizing is very well tested. Since we switched |
| 1260 | * away from compile-time hardware parameters, we can no longer rely on |
| 1261 | * dead code elimination to leave only the relevant one in the object file. |
| 1262 | * |
| 1263 | * We don't currently use dynamic fifo setup capability to do anything |
| 1264 | * more than selecting one of a bunch of predefined configurations. |
| 1265 | */ |
| 1266 | static ushort fifo_mode; |
| 1267 | |
| 1268 | /* "modprobe ... fifo_mode=1" etc */ |
| 1269 | module_param(fifo_mode, ushort, 0); |
| 1270 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); |
| 1271 | |
| 1272 | /* |
| 1273 | * tables defining fifo_mode values. define more if you like. |
| 1274 | * for host side, make sure both halves of ep1 are set up. |
| 1275 | */ |
| 1276 | |
| 1277 | /* mode 0 - fits in 2KB */ |
| 1278 | static struct musb_fifo_cfg mode_0_cfg[] = { |
| 1279 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
| 1280 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, |
| 1281 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, |
| 1282 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, |
| 1283 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, |
| 1284 | }; |
| 1285 | |
| 1286 | /* mode 1 - fits in 4KB */ |
| 1287 | static struct musb_fifo_cfg mode_1_cfg[] = { |
| 1288 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
| 1289 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
| 1290 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
| 1291 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, |
| 1292 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, |
| 1293 | }; |
| 1294 | |
| 1295 | /* mode 2 - fits in 4KB */ |
| 1296 | static struct musb_fifo_cfg mode_2_cfg[] = { |
| 1297 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
| 1298 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, |
| 1299 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, |
| 1300 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, |
| 1301 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, }, |
| 1302 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, }, |
| 1303 | }; |
| 1304 | |
| 1305 | /* mode 3 - fits in 4KB */ |
| 1306 | static struct musb_fifo_cfg mode_3_cfg[] = { |
| 1307 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
| 1308 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
| 1309 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, |
| 1310 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, |
| 1311 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, |
| 1312 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, |
| 1313 | }; |
| 1314 | |
| 1315 | /* mode 4 - fits in 16KB */ |
| 1316 | static struct musb_fifo_cfg mode_4_cfg[] = { |
| 1317 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
| 1318 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, |
| 1319 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, |
| 1320 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, |
| 1321 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, |
| 1322 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, |
| 1323 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, |
| 1324 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, |
| 1325 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, |
| 1326 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, |
| 1327 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, |
| 1328 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, |
| 1329 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, |
| 1330 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, |
| 1331 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, |
| 1332 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, |
| 1333 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, |
| 1334 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, |
| 1335 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
| 1336 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, |
| 1337 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, |
| 1338 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, |
| 1339 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, |
| 1340 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, |
| 1341 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, |
| 1342 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
| 1343 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, |
| 1344 | }; |
| 1345 | |
| 1346 | /* mode 5 - fits in 8KB */ |
| 1347 | static struct musb_fifo_cfg mode_5_cfg[] = { |
| 1348 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
| 1349 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, |
| 1350 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, |
| 1351 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, |
| 1352 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, |
| 1353 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, |
| 1354 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, |
| 1355 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, |
| 1356 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, |
| 1357 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, |
| 1358 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, |
| 1359 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, |
| 1360 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, |
| 1361 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, |
| 1362 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, |
| 1363 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, |
| 1364 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, |
| 1365 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, |
| 1366 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, |
| 1367 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, |
| 1368 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, |
| 1369 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, |
| 1370 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, |
| 1371 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, |
| 1372 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, |
| 1373 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
| 1374 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, |
| 1375 | }; |
| 1376 | |
| 1377 | /* |
| 1378 | * configure a fifo; for non-shared endpoints, this may be called |
| 1379 | * once for a tx fifo and once for an rx fifo. |
| 1380 | * |
| 1381 | * returns negative errno or offset for next fifo. |
| 1382 | */ |
| 1383 | static int |
| 1384 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
| 1385 | const struct musb_fifo_cfg *cfg, u16 offset) |
| 1386 | { |
| 1387 | void __iomem *mbase = musb->mregs; |
| 1388 | int size = 0; |
| 1389 | u16 maxpacket = cfg->maxpacket; |
| 1390 | u16 c_off = offset >> 3; |
| 1391 | u8 c_size; |
| 1392 | |
| 1393 | /* expect hw_ep has already been zero-initialized */ |
| 1394 | |
| 1395 | size = ffs(max(maxpacket, (u16) 8)) - 1; |
| 1396 | maxpacket = 1 << size; |
| 1397 | |
| 1398 | c_size = size - 3; |
| 1399 | if (cfg->mode == BUF_DOUBLE) { |
| 1400 | if ((offset + (maxpacket << 1)) > |
| 1401 | (1 << (musb->config->ram_bits + 2))) |
| 1402 | return -EMSGSIZE; |
| 1403 | c_size |= MUSB_FIFOSZ_DPB; |
| 1404 | } else { |
| 1405 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
| 1406 | return -EMSGSIZE; |
| 1407 | } |
| 1408 | |
| 1409 | /* configure the FIFO */ |
| 1410 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); |
| 1411 | |
| 1412 | /* EP0 reserved endpoint for control, bidirectional; |
| 1413 | * EP1 reserved for bulk, two unidirectional halves. |
| 1414 | */ |
| 1415 | if (hw_ep->epnum == 1) |
| 1416 | musb->bulk_ep = hw_ep; |
| 1417 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ |
| 1418 | switch (cfg->style) { |
| 1419 | case FIFO_TX: |
| 1420 | musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); |
| 1421 | musb_writew(mbase, MUSB_TXFIFOADD, c_off); |
| 1422 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
| 1423 | hw_ep->max_packet_sz_tx = maxpacket; |
| 1424 | break; |
| 1425 | case FIFO_RX: |
| 1426 | musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); |
| 1427 | musb_writew(mbase, MUSB_RXFIFOADD, c_off); |
| 1428 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
| 1429 | hw_ep->max_packet_sz_rx = maxpacket; |
| 1430 | break; |
| 1431 | case FIFO_RXTX: |
| 1432 | musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); |
| 1433 | musb_writew(mbase, MUSB_TXFIFOADD, c_off); |
| 1434 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
| 1435 | hw_ep->max_packet_sz_rx = maxpacket; |
| 1436 | |
| 1437 | musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); |
| 1438 | musb_writew(mbase, MUSB_RXFIFOADD, c_off); |
| 1439 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
| 1440 | hw_ep->max_packet_sz_tx = maxpacket; |
| 1441 | |
| 1442 | hw_ep->is_shared_fifo = true; |
| 1443 | break; |
| 1444 | } |
| 1445 | |
| 1446 | /* NOTE rx and tx endpoint irqs aren't managed separately, |
| 1447 | * which happens to be ok |
| 1448 | */ |
| 1449 | musb->epmask |= (1 << hw_ep->epnum); |
| 1450 | |
| 1451 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); |
| 1452 | } |
| 1453 | |
| 1454 | static struct musb_fifo_cfg ep0_cfg = { |
| 1455 | .style = FIFO_RXTX, .maxpacket = 64, |
| 1456 | }; |
| 1457 | |
| 1458 | static int ep_config_from_table(struct musb *musb) |
| 1459 | { |
| 1460 | const struct musb_fifo_cfg *cfg; |
| 1461 | unsigned i, n; |
| 1462 | int offset; |
| 1463 | struct musb_hw_ep *hw_ep = musb->endpoints; |
| 1464 | |
| 1465 | if (musb->config->fifo_cfg) { |
| 1466 | cfg = musb->config->fifo_cfg; |
| 1467 | n = musb->config->fifo_cfg_size; |
| 1468 | goto done; |
| 1469 | } |
| 1470 | |
| 1471 | switch (fifo_mode) { |
| 1472 | default: |
| 1473 | fifo_mode = 0; |
| 1474 | /* FALLTHROUGH */ |
| 1475 | case 0: |
| 1476 | cfg = mode_0_cfg; |
| 1477 | n = ARRAY_SIZE(mode_0_cfg); |
| 1478 | break; |
| 1479 | case 1: |
| 1480 | cfg = mode_1_cfg; |
| 1481 | n = ARRAY_SIZE(mode_1_cfg); |
| 1482 | break; |
| 1483 | case 2: |
| 1484 | cfg = mode_2_cfg; |
| 1485 | n = ARRAY_SIZE(mode_2_cfg); |
| 1486 | break; |
| 1487 | case 3: |
| 1488 | cfg = mode_3_cfg; |
| 1489 | n = ARRAY_SIZE(mode_3_cfg); |
| 1490 | break; |
| 1491 | case 4: |
| 1492 | cfg = mode_4_cfg; |
| 1493 | n = ARRAY_SIZE(mode_4_cfg); |
| 1494 | break; |
| 1495 | case 5: |
| 1496 | cfg = mode_5_cfg; |
| 1497 | n = ARRAY_SIZE(mode_5_cfg); |
| 1498 | break; |
| 1499 | } |
| 1500 | |
| 1501 | pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); |
| 1502 | |
| 1503 | |
| 1504 | done: |
| 1505 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
| 1506 | /* assert(offset > 0) */ |
| 1507 | |
| 1508 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would |
| 1509 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
| 1510 | */ |
| 1511 | |
| 1512 | for (i = 0; i < n; i++) { |
| 1513 | u8 epn = cfg->hw_ep_num; |
| 1514 | |
| 1515 | if (epn >= musb->config->num_eps) { |
| 1516 | pr_debug("%s: invalid ep %d\n", |
| 1517 | musb_driver_name, epn); |
| 1518 | return -EINVAL; |
| 1519 | } |
| 1520 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); |
| 1521 | if (offset < 0) { |
| 1522 | pr_debug("%s: mem overrun, ep %d\n", |
| 1523 | musb_driver_name, epn); |
| 1524 | return offset; |
| 1525 | } |
| 1526 | epn++; |
| 1527 | musb->nr_endpoints = max(epn, musb->nr_endpoints); |
| 1528 | } |
| 1529 | |
| 1530 | pr_debug("%s: %d/%d max ep, %d/%d memory\n", |
| 1531 | musb_driver_name, |
| 1532 | n + 1, musb->config->num_eps * 2 - 1, |
| 1533 | offset, (1 << (musb->config->ram_bits + 2))); |
| 1534 | |
| 1535 | if (!musb->bulk_ep) { |
| 1536 | pr_debug("%s: missing bulk\n", musb_driver_name); |
| 1537 | return -EINVAL; |
| 1538 | } |
| 1539 | |
| 1540 | return 0; |
| 1541 | } |
| 1542 | |
| 1543 | |
| 1544 | /* |
| 1545 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false |
| 1546 | * @param musb the controller |
| 1547 | */ |
| 1548 | static int ep_config_from_hw(struct musb *musb) |
| 1549 | { |
| 1550 | u8 epnum = 0; |
| 1551 | struct musb_hw_ep *hw_ep; |
| 1552 | void __iomem *mbase = musb->mregs; |
| 1553 | int ret = 0; |
| 1554 | |
| 1555 | musb_dbg(musb, "<== static silicon ep config"); |
| 1556 | |
| 1557 | /* FIXME pick up ep0 maxpacket size */ |
| 1558 | |
| 1559 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
| 1560 | musb_ep_select(mbase, epnum); |
| 1561 | hw_ep = musb->endpoints + epnum; |
| 1562 | |
| 1563 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
| 1564 | if (ret < 0) |
| 1565 | break; |
| 1566 | |
| 1567 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ |
| 1568 | |
| 1569 | /* pick an RX/TX endpoint for bulk */ |
| 1570 | if (hw_ep->max_packet_sz_tx < 512 |
| 1571 | || hw_ep->max_packet_sz_rx < 512) |
| 1572 | continue; |
| 1573 | |
| 1574 | /* REVISIT: this algorithm is lazy, we should at least |
| 1575 | * try to pick a double buffered endpoint. |
| 1576 | */ |
| 1577 | if (musb->bulk_ep) |
| 1578 | continue; |
| 1579 | musb->bulk_ep = hw_ep; |
| 1580 | } |
| 1581 | |
| 1582 | if (!musb->bulk_ep) { |
| 1583 | pr_debug("%s: missing bulk\n", musb_driver_name); |
| 1584 | return -EINVAL; |
| 1585 | } |
| 1586 | |
| 1587 | return 0; |
| 1588 | } |
| 1589 | |
| 1590 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; |
| 1591 | |
| 1592 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; |
| 1593 | * configure endpoints, or take their config from silicon |
| 1594 | */ |
| 1595 | static int musb_core_init(u16 musb_type, struct musb *musb) |
| 1596 | { |
| 1597 | u8 reg; |
| 1598 | char *type; |
| 1599 | char aInfo[90]; |
| 1600 | void __iomem *mbase = musb->mregs; |
| 1601 | int status = 0; |
| 1602 | int i; |
| 1603 | |
| 1604 | /* log core options (read using indexed model) */ |
| 1605 | reg = musb_read_configdata(mbase); |
| 1606 | |
| 1607 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); |
| 1608 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
| 1609 | strcat(aInfo, ", dyn FIFOs"); |
| 1610 | musb->dyn_fifo = true; |
| 1611 | } |
| 1612 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
| 1613 | strcat(aInfo, ", bulk combine"); |
| 1614 | musb->bulk_combine = true; |
| 1615 | } |
| 1616 | if (reg & MUSB_CONFIGDATA_MPTXE) { |
| 1617 | strcat(aInfo, ", bulk split"); |
| 1618 | musb->bulk_split = true; |
| 1619 | } |
| 1620 | if (reg & MUSB_CONFIGDATA_HBRXE) { |
| 1621 | strcat(aInfo, ", HB-ISO Rx"); |
| 1622 | musb->hb_iso_rx = true; |
| 1623 | } |
| 1624 | if (reg & MUSB_CONFIGDATA_HBTXE) { |
| 1625 | strcat(aInfo, ", HB-ISO Tx"); |
| 1626 | musb->hb_iso_tx = true; |
| 1627 | } |
| 1628 | if (reg & MUSB_CONFIGDATA_SOFTCONE) |
| 1629 | strcat(aInfo, ", SoftConn"); |
| 1630 | |
| 1631 | pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); |
| 1632 | |
| 1633 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
| 1634 | musb->is_multipoint = 1; |
| 1635 | type = "M"; |
| 1636 | } else { |
| 1637 | musb->is_multipoint = 0; |
| 1638 | type = ""; |
| 1639 | if (IS_ENABLED(CONFIG_USB) && |
| 1640 | !IS_ENABLED(CONFIG_USB_OTG_BLACKLIST_HUB)) { |
| 1641 | pr_err("%s: kernel must blacklist external hubs\n", |
| 1642 | musb_driver_name); |
| 1643 | } |
| 1644 | } |
| 1645 | |
| 1646 | /* log release info */ |
| 1647 | musb->hwvers = musb_readw(mbase, MUSB_HWVERS); |
| 1648 | pr_debug("%s: %sHDRC RTL version %d.%d%s\n", |
| 1649 | musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers), |
| 1650 | MUSB_HWVERS_MINOR(musb->hwvers), |
| 1651 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); |
| 1652 | |
| 1653 | /* configure ep0 */ |
| 1654 | musb_configure_ep0(musb); |
| 1655 | |
| 1656 | /* discover endpoint configuration */ |
| 1657 | musb->nr_endpoints = 1; |
| 1658 | musb->epmask = 1; |
| 1659 | |
| 1660 | if (musb->dyn_fifo) |
| 1661 | status = ep_config_from_table(musb); |
| 1662 | else |
| 1663 | status = ep_config_from_hw(musb); |
| 1664 | |
| 1665 | if (status < 0) |
| 1666 | return status; |
| 1667 | |
| 1668 | /* finish init, and print endpoint config */ |
| 1669 | for (i = 0; i < musb->nr_endpoints; i++) { |
| 1670 | struct musb_hw_ep *hw_ep = musb->endpoints + i; |
| 1671 | |
| 1672 | hw_ep->fifo = musb->io.fifo_offset(i) + mbase; |
| 1673 | #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) |
| 1674 | if (musb->ops->quirks & MUSB_IN_TUSB) { |
| 1675 | hw_ep->fifo_async = musb->async + 0x400 + |
| 1676 | musb->io.fifo_offset(i); |
| 1677 | hw_ep->fifo_sync = musb->sync + 0x400 + |
| 1678 | musb->io.fifo_offset(i); |
| 1679 | hw_ep->fifo_sync_va = |
| 1680 | musb->sync_va + 0x400 + musb->io.fifo_offset(i); |
| 1681 | |
| 1682 | if (i == 0) |
| 1683 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; |
| 1684 | else |
| 1685 | hw_ep->conf = mbase + 0x400 + |
| 1686 | (((i - 1) & 0xf) << 2); |
| 1687 | } |
| 1688 | #endif |
| 1689 | |
| 1690 | hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; |
| 1691 | hw_ep->rx_reinit = 1; |
| 1692 | hw_ep->tx_reinit = 1; |
| 1693 | |
| 1694 | if (hw_ep->max_packet_sz_tx) { |
| 1695 | musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", |
| 1696 | musb_driver_name, i, |
| 1697 | hw_ep->is_shared_fifo ? "shared" : "tx", |
| 1698 | hw_ep->tx_double_buffered |
| 1699 | ? "doublebuffer, " : "", |
| 1700 | hw_ep->max_packet_sz_tx); |
| 1701 | } |
| 1702 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { |
| 1703 | musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", |
| 1704 | musb_driver_name, i, |
| 1705 | "rx", |
| 1706 | hw_ep->rx_double_buffered |
| 1707 | ? "doublebuffer, " : "", |
| 1708 | hw_ep->max_packet_sz_rx); |
| 1709 | } |
| 1710 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) |
| 1711 | musb_dbg(musb, "hw_ep %d not configured", i); |
| 1712 | } |
| 1713 | |
| 1714 | return 0; |
| 1715 | } |
| 1716 | |
| 1717 | /*-------------------------------------------------------------------------*/ |
| 1718 | |
| 1719 | /* |
| 1720 | * handle all the irqs defined by the HDRC core. for now we expect: other |
| 1721 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values |
| 1722 | * will be assigned, and the irq will already have been acked. |
| 1723 | * |
| 1724 | * called in irq context with spinlock held, irqs blocked |
| 1725 | */ |
| 1726 | irqreturn_t musb_interrupt(struct musb *musb) |
| 1727 | { |
| 1728 | irqreturn_t retval = IRQ_NONE; |
| 1729 | unsigned long status; |
| 1730 | unsigned long epnum; |
| 1731 | u8 devctl; |
| 1732 | |
| 1733 | if (!musb->int_usb && !musb->int_tx && !musb->int_rx) |
| 1734 | return IRQ_NONE; |
| 1735 | |
| 1736 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 1737 | |
| 1738 | trace_musb_isr(musb); |
| 1739 | |
| 1740 | /** |
| 1741 | * According to Mentor Graphics' documentation, flowchart on page 98, |
| 1742 | * IRQ should be handled as follows: |
| 1743 | * |
| 1744 | * . Resume IRQ |
| 1745 | * . Session Request IRQ |
| 1746 | * . VBUS Error IRQ |
| 1747 | * . Suspend IRQ |
| 1748 | * . Connect IRQ |
| 1749 | * . Disconnect IRQ |
| 1750 | * . Reset/Babble IRQ |
| 1751 | * . SOF IRQ (we're not using this one) |
| 1752 | * . Endpoint 0 IRQ |
| 1753 | * . TX Endpoints |
| 1754 | * . RX Endpoints |
| 1755 | * |
| 1756 | * We will be following that flowchart in order to avoid any problems |
| 1757 | * that might arise with internal Finite State Machine. |
| 1758 | */ |
| 1759 | |
| 1760 | if (musb->int_usb) |
| 1761 | retval |= musb_stage0_irq(musb, musb->int_usb, devctl); |
| 1762 | |
| 1763 | if (musb->int_tx & 1) { |
| 1764 | if (is_host_active(musb)) |
| 1765 | retval |= musb_h_ep0_irq(musb); |
| 1766 | else |
| 1767 | retval |= musb_g_ep0_irq(musb); |
| 1768 | |
| 1769 | /* we have just handled endpoint 0 IRQ, clear it */ |
| 1770 | musb->int_tx &= ~BIT(0); |
| 1771 | } |
| 1772 | |
| 1773 | status = musb->int_tx; |
| 1774 | |
| 1775 | for_each_set_bit(epnum, &status, 16) { |
| 1776 | retval = IRQ_HANDLED; |
| 1777 | if (is_host_active(musb)) |
| 1778 | musb_host_tx(musb, epnum); |
| 1779 | else |
| 1780 | musb_g_tx(musb, epnum); |
| 1781 | } |
| 1782 | |
| 1783 | status = musb->int_rx; |
| 1784 | |
| 1785 | for_each_set_bit(epnum, &status, 16) { |
| 1786 | retval = IRQ_HANDLED; |
| 1787 | if (is_host_active(musb)) |
| 1788 | musb_host_rx(musb, epnum); |
| 1789 | else |
| 1790 | musb_g_rx(musb, epnum); |
| 1791 | } |
| 1792 | |
| 1793 | return retval; |
| 1794 | } |
| 1795 | EXPORT_SYMBOL_GPL(musb_interrupt); |
| 1796 | |
| 1797 | #ifndef CONFIG_MUSB_PIO_ONLY |
| 1798 | static bool use_dma = 1; |
| 1799 | |
| 1800 | /* "modprobe ... use_dma=0" etc */ |
| 1801 | module_param(use_dma, bool, 0644); |
| 1802 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); |
| 1803 | |
| 1804 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) |
| 1805 | { |
| 1806 | /* called with controller lock already held */ |
| 1807 | |
| 1808 | if (!epnum) { |
| 1809 | if (!is_cppi_enabled(musb)) { |
| 1810 | /* endpoint 0 */ |
| 1811 | if (is_host_active(musb)) |
| 1812 | musb_h_ep0_irq(musb); |
| 1813 | else |
| 1814 | musb_g_ep0_irq(musb); |
| 1815 | } |
| 1816 | } else { |
| 1817 | /* endpoints 1..15 */ |
| 1818 | if (transmit) { |
| 1819 | if (is_host_active(musb)) |
| 1820 | musb_host_tx(musb, epnum); |
| 1821 | else |
| 1822 | musb_g_tx(musb, epnum); |
| 1823 | } else { |
| 1824 | /* receive */ |
| 1825 | if (is_host_active(musb)) |
| 1826 | musb_host_rx(musb, epnum); |
| 1827 | else |
| 1828 | musb_g_rx(musb, epnum); |
| 1829 | } |
| 1830 | } |
| 1831 | } |
| 1832 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
| 1833 | |
| 1834 | #else |
| 1835 | #define use_dma 0 |
| 1836 | #endif |
| 1837 | |
| 1838 | static int (*musb_phy_callback)(enum musb_vbus_id_status status); |
| 1839 | |
| 1840 | /* |
| 1841 | * musb_mailbox - optional phy notifier function |
| 1842 | * @status phy state change |
| 1843 | * |
| 1844 | * Optionally gets called from the USB PHY. Note that the USB PHY must be |
| 1845 | * disabled at the point the phy_callback is registered or unregistered. |
| 1846 | */ |
| 1847 | int musb_mailbox(enum musb_vbus_id_status status) |
| 1848 | { |
| 1849 | if (musb_phy_callback) |
| 1850 | return musb_phy_callback(status); |
| 1851 | |
| 1852 | return -ENODEV; |
| 1853 | }; |
| 1854 | EXPORT_SYMBOL_GPL(musb_mailbox); |
| 1855 | |
| 1856 | /*-------------------------------------------------------------------------*/ |
| 1857 | |
| 1858 | static ssize_t |
| 1859 | mode_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 1860 | { |
| 1861 | struct musb *musb = dev_to_musb(dev); |
| 1862 | unsigned long flags; |
| 1863 | int ret; |
| 1864 | |
| 1865 | spin_lock_irqsave(&musb->lock, flags); |
| 1866 | ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state)); |
| 1867 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1868 | |
| 1869 | return ret; |
| 1870 | } |
| 1871 | |
| 1872 | static ssize_t |
| 1873 | mode_store(struct device *dev, struct device_attribute *attr, |
| 1874 | const char *buf, size_t n) |
| 1875 | { |
| 1876 | struct musb *musb = dev_to_musb(dev); |
| 1877 | unsigned long flags; |
| 1878 | int status; |
| 1879 | |
| 1880 | spin_lock_irqsave(&musb->lock, flags); |
| 1881 | if (sysfs_streq(buf, "host")) |
| 1882 | status = musb_platform_set_mode(musb, MUSB_HOST); |
| 1883 | else if (sysfs_streq(buf, "peripheral")) |
| 1884 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); |
| 1885 | else if (sysfs_streq(buf, "otg")) |
| 1886 | status = musb_platform_set_mode(musb, MUSB_OTG); |
| 1887 | else |
| 1888 | status = -EINVAL; |
| 1889 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1890 | |
| 1891 | return (status == 0) ? n : status; |
| 1892 | } |
| 1893 | static DEVICE_ATTR_RW(mode); |
| 1894 | |
| 1895 | static ssize_t |
| 1896 | vbus_store(struct device *dev, struct device_attribute *attr, |
| 1897 | const char *buf, size_t n) |
| 1898 | { |
| 1899 | struct musb *musb = dev_to_musb(dev); |
| 1900 | unsigned long flags; |
| 1901 | unsigned long val; |
| 1902 | |
| 1903 | if (sscanf(buf, "%lu", &val) < 1) { |
| 1904 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
| 1905 | return -EINVAL; |
| 1906 | } |
| 1907 | |
| 1908 | spin_lock_irqsave(&musb->lock, flags); |
| 1909 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
| 1910 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; |
| 1911 | if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) |
| 1912 | musb->is_active = 0; |
| 1913 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); |
| 1914 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1915 | |
| 1916 | return n; |
| 1917 | } |
| 1918 | |
| 1919 | static ssize_t |
| 1920 | vbus_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 1921 | { |
| 1922 | struct musb *musb = dev_to_musb(dev); |
| 1923 | unsigned long flags; |
| 1924 | unsigned long val; |
| 1925 | int vbus; |
| 1926 | u8 devctl; |
| 1927 | |
| 1928 | pm_runtime_get_sync(dev); |
| 1929 | spin_lock_irqsave(&musb->lock, flags); |
| 1930 | val = musb->a_wait_bcon; |
| 1931 | vbus = musb_platform_get_vbus_status(musb); |
| 1932 | if (vbus < 0) { |
| 1933 | /* Use default MUSB method by means of DEVCTL register */ |
| 1934 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 1935 | if ((devctl & MUSB_DEVCTL_VBUS) |
| 1936 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) |
| 1937 | vbus = 1; |
| 1938 | else |
| 1939 | vbus = 0; |
| 1940 | } |
| 1941 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1942 | pm_runtime_put_sync(dev); |
| 1943 | |
| 1944 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
| 1945 | vbus ? "on" : "off", val); |
| 1946 | } |
| 1947 | static DEVICE_ATTR_RW(vbus); |
| 1948 | |
| 1949 | /* Gadget drivers can't know that a host is connected so they might want |
| 1950 | * to start SRP, but users can. This allows userspace to trigger SRP. |
| 1951 | */ |
| 1952 | static ssize_t srp_store(struct device *dev, struct device_attribute *attr, |
| 1953 | const char *buf, size_t n) |
| 1954 | { |
| 1955 | struct musb *musb = dev_to_musb(dev); |
| 1956 | unsigned short srp; |
| 1957 | |
| 1958 | if (sscanf(buf, "%hu", &srp) != 1 |
| 1959 | || (srp != 1)) { |
| 1960 | dev_err(dev, "SRP: Value must be 1\n"); |
| 1961 | return -EINVAL; |
| 1962 | } |
| 1963 | |
| 1964 | if (srp == 1) |
| 1965 | musb_g_wakeup(musb); |
| 1966 | |
| 1967 | return n; |
| 1968 | } |
| 1969 | static DEVICE_ATTR_WO(srp); |
| 1970 | |
| 1971 | static struct attribute *musb_attrs[] = { |
| 1972 | &dev_attr_mode.attr, |
| 1973 | &dev_attr_vbus.attr, |
| 1974 | &dev_attr_srp.attr, |
| 1975 | NULL |
| 1976 | }; |
| 1977 | ATTRIBUTE_GROUPS(musb); |
| 1978 | |
| 1979 | #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \ |
| 1980 | (2 << MUSB_DEVCTL_VBUS_SHIFT) | \ |
| 1981 | MUSB_DEVCTL_SESSION) |
| 1982 | #define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \ |
| 1983 | (3 << MUSB_DEVCTL_VBUS_SHIFT) | \ |
| 1984 | MUSB_DEVCTL_SESSION) |
| 1985 | #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \ |
| 1986 | MUSB_DEVCTL_SESSION) |
| 1987 | |
| 1988 | /* |
| 1989 | * Check the musb devctl session bit to determine if we want to |
| 1990 | * allow PM runtime for the device. In general, we want to keep things |
| 1991 | * active when the session bit is set except after host disconnect. |
| 1992 | * |
| 1993 | * Only called from musb_irq_work. If this ever needs to get called |
| 1994 | * elsewhere, proper locking must be implemented for musb->session. |
| 1995 | */ |
| 1996 | static void musb_pm_runtime_check_session(struct musb *musb) |
| 1997 | { |
| 1998 | u8 devctl, s; |
| 1999 | int error; |
| 2000 | |
| 2001 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 2002 | |
| 2003 | /* Handle session status quirks first */ |
| 2004 | s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV | |
| 2005 | MUSB_DEVCTL_HR; |
| 2006 | switch (devctl & ~s) { |
| 2007 | case MUSB_QUIRK_B_DISCONNECT_99: |
| 2008 | musb_dbg(musb, "Poll devctl in case of suspend after disconnect\n"); |
| 2009 | schedule_delayed_work(&musb->irq_work, |
| 2010 | msecs_to_jiffies(1000)); |
| 2011 | break; |
| 2012 | case MUSB_QUIRK_B_INVALID_VBUS_91: |
| 2013 | if (musb->quirk_retries && !musb->flush_irq_work) { |
| 2014 | musb_dbg(musb, |
| 2015 | "Poll devctl on invalid vbus, assume no session"); |
| 2016 | schedule_delayed_work(&musb->irq_work, |
| 2017 | msecs_to_jiffies(1000)); |
| 2018 | musb->quirk_retries--; |
| 2019 | return; |
| 2020 | } |
| 2021 | /* fall through */ |
| 2022 | case MUSB_QUIRK_A_DISCONNECT_19: |
| 2023 | if (musb->quirk_retries && !musb->flush_irq_work) { |
| 2024 | musb_dbg(musb, |
| 2025 | "Poll devctl on possible host mode disconnect"); |
| 2026 | schedule_delayed_work(&musb->irq_work, |
| 2027 | msecs_to_jiffies(1000)); |
| 2028 | musb->quirk_retries--; |
| 2029 | return; |
| 2030 | } |
| 2031 | if (!musb->session) |
| 2032 | break; |
| 2033 | musb_dbg(musb, "Allow PM on possible host mode disconnect"); |
| 2034 | pm_runtime_mark_last_busy(musb->controller); |
| 2035 | pm_runtime_put_autosuspend(musb->controller); |
| 2036 | musb->session = false; |
| 2037 | return; |
| 2038 | default: |
| 2039 | break; |
| 2040 | } |
| 2041 | |
| 2042 | /* No need to do anything if session has not changed */ |
| 2043 | s = devctl & MUSB_DEVCTL_SESSION; |
| 2044 | if (s == musb->session) |
| 2045 | return; |
| 2046 | |
| 2047 | /* Block PM or allow PM? */ |
| 2048 | if (s) { |
| 2049 | musb_dbg(musb, "Block PM on active session: %02x", devctl); |
| 2050 | error = pm_runtime_get_sync(musb->controller); |
| 2051 | if (error < 0) |
| 2052 | dev_err(musb->controller, "Could not enable: %i\n", |
| 2053 | error); |
| 2054 | musb->quirk_retries = 3; |
| 2055 | } else { |
| 2056 | musb_dbg(musb, "Allow PM with no session: %02x", devctl); |
| 2057 | pm_runtime_mark_last_busy(musb->controller); |
| 2058 | pm_runtime_put_autosuspend(musb->controller); |
| 2059 | } |
| 2060 | |
| 2061 | musb->session = s; |
| 2062 | } |
| 2063 | |
| 2064 | /* Only used to provide driver mode change events */ |
| 2065 | static void musb_irq_work(struct work_struct *data) |
| 2066 | { |
| 2067 | struct musb *musb = container_of(data, struct musb, irq_work.work); |
| 2068 | int error; |
| 2069 | |
| 2070 | error = pm_runtime_get_sync(musb->controller); |
| 2071 | if (error < 0) { |
| 2072 | dev_err(musb->controller, "Could not enable: %i\n", error); |
| 2073 | |
| 2074 | return; |
| 2075 | } |
| 2076 | |
| 2077 | musb_pm_runtime_check_session(musb); |
| 2078 | |
| 2079 | if (musb->xceiv->otg->state != musb->xceiv_old_state) { |
| 2080 | musb->xceiv_old_state = musb->xceiv->otg->state; |
| 2081 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
| 2082 | } |
| 2083 | |
| 2084 | pm_runtime_mark_last_busy(musb->controller); |
| 2085 | pm_runtime_put_autosuspend(musb->controller); |
| 2086 | } |
| 2087 | |
| 2088 | static void musb_recover_from_babble(struct musb *musb) |
| 2089 | { |
| 2090 | int ret; |
| 2091 | u8 devctl; |
| 2092 | |
| 2093 | musb_disable_interrupts(musb); |
| 2094 | |
| 2095 | /* |
| 2096 | * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give |
| 2097 | * it some slack and wait for 10us. |
| 2098 | */ |
| 2099 | udelay(10); |
| 2100 | |
| 2101 | ret = musb_platform_recover(musb); |
| 2102 | if (ret) { |
| 2103 | musb_enable_interrupts(musb); |
| 2104 | return; |
| 2105 | } |
| 2106 | |
| 2107 | /* drop session bit */ |
| 2108 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 2109 | devctl &= ~MUSB_DEVCTL_SESSION; |
| 2110 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); |
| 2111 | |
| 2112 | /* tell usbcore about it */ |
| 2113 | musb_root_disconnect(musb); |
| 2114 | |
| 2115 | /* |
| 2116 | * When a babble condition occurs, the musb controller |
| 2117 | * removes the session bit and the endpoint config is lost. |
| 2118 | */ |
| 2119 | if (musb->dyn_fifo) |
| 2120 | ret = ep_config_from_table(musb); |
| 2121 | else |
| 2122 | ret = ep_config_from_hw(musb); |
| 2123 | |
| 2124 | /* restart session */ |
| 2125 | if (ret == 0) |
| 2126 | musb_start(musb); |
| 2127 | } |
| 2128 | |
| 2129 | /* -------------------------------------------------------------------------- |
| 2130 | * Init support |
| 2131 | */ |
| 2132 | |
| 2133 | static struct musb *allocate_instance(struct device *dev, |
| 2134 | const struct musb_hdrc_config *config, void __iomem *mbase) |
| 2135 | { |
| 2136 | struct musb *musb; |
| 2137 | struct musb_hw_ep *ep; |
| 2138 | int epnum; |
| 2139 | int ret; |
| 2140 | |
| 2141 | musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); |
| 2142 | if (!musb) |
| 2143 | return NULL; |
| 2144 | |
| 2145 | INIT_LIST_HEAD(&musb->control); |
| 2146 | INIT_LIST_HEAD(&musb->in_bulk); |
| 2147 | INIT_LIST_HEAD(&musb->out_bulk); |
| 2148 | INIT_LIST_HEAD(&musb->pending_list); |
| 2149 | |
| 2150 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; |
| 2151 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
| 2152 | musb->mregs = mbase; |
| 2153 | musb->ctrl_base = mbase; |
| 2154 | musb->nIrq = -ENODEV; |
| 2155 | musb->config = config; |
| 2156 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
| 2157 | for (epnum = 0, ep = musb->endpoints; |
| 2158 | epnum < musb->config->num_eps; |
| 2159 | epnum++, ep++) { |
| 2160 | ep->musb = musb; |
| 2161 | ep->epnum = epnum; |
| 2162 | } |
| 2163 | |
| 2164 | musb->controller = dev; |
| 2165 | |
| 2166 | ret = musb_host_alloc(musb); |
| 2167 | if (ret < 0) |
| 2168 | goto err_free; |
| 2169 | |
| 2170 | dev_set_drvdata(dev, musb); |
| 2171 | |
| 2172 | return musb; |
| 2173 | |
| 2174 | err_free: |
| 2175 | return NULL; |
| 2176 | } |
| 2177 | |
| 2178 | static void musb_free(struct musb *musb) |
| 2179 | { |
| 2180 | /* this has multiple entry modes. it handles fault cleanup after |
| 2181 | * probe(), where things may be partially set up, as well as rmmod |
| 2182 | * cleanup after everything's been de-activated. |
| 2183 | */ |
| 2184 | |
| 2185 | if (musb->nIrq >= 0) { |
| 2186 | if (musb->irq_wake) |
| 2187 | disable_irq_wake(musb->nIrq); |
| 2188 | free_irq(musb->nIrq, musb); |
| 2189 | } |
| 2190 | |
| 2191 | musb_host_free(musb); |
| 2192 | } |
| 2193 | |
| 2194 | struct musb_pending_work { |
| 2195 | int (*callback)(struct musb *musb, void *data); |
| 2196 | void *data; |
| 2197 | struct list_head node; |
| 2198 | }; |
| 2199 | |
| 2200 | #ifdef CONFIG_PM |
| 2201 | /* |
| 2202 | * Called from musb_runtime_resume(), musb_resume(), and |
| 2203 | * musb_queue_resume_work(). Callers must take musb->lock. |
| 2204 | */ |
| 2205 | static int musb_run_resume_work(struct musb *musb) |
| 2206 | { |
| 2207 | struct musb_pending_work *w, *_w; |
| 2208 | unsigned long flags; |
| 2209 | int error = 0; |
| 2210 | |
| 2211 | spin_lock_irqsave(&musb->list_lock, flags); |
| 2212 | list_for_each_entry_safe(w, _w, &musb->pending_list, node) { |
| 2213 | if (w->callback) { |
| 2214 | error = w->callback(musb, w->data); |
| 2215 | if (error < 0) { |
| 2216 | dev_err(musb->controller, |
| 2217 | "resume callback %p failed: %i\n", |
| 2218 | w->callback, error); |
| 2219 | } |
| 2220 | } |
| 2221 | list_del(&w->node); |
| 2222 | devm_kfree(musb->controller, w); |
| 2223 | } |
| 2224 | spin_unlock_irqrestore(&musb->list_lock, flags); |
| 2225 | |
| 2226 | return error; |
| 2227 | } |
| 2228 | #endif |
| 2229 | |
| 2230 | /* |
| 2231 | * Called to run work if device is active or else queue the work to happen |
| 2232 | * on resume. Caller must take musb->lock and must hold an RPM reference. |
| 2233 | * |
| 2234 | * Note that we cowardly refuse queuing work after musb PM runtime |
| 2235 | * resume is done calling musb_run_resume_work() and return -EINPROGRESS |
| 2236 | * instead. |
| 2237 | */ |
| 2238 | int musb_queue_resume_work(struct musb *musb, |
| 2239 | int (*callback)(struct musb *musb, void *data), |
| 2240 | void *data) |
| 2241 | { |
| 2242 | struct musb_pending_work *w; |
| 2243 | unsigned long flags; |
| 2244 | int error; |
| 2245 | |
| 2246 | if (WARN_ON(!callback)) |
| 2247 | return -EINVAL; |
| 2248 | |
| 2249 | if (pm_runtime_active(musb->controller)) |
| 2250 | return callback(musb, data); |
| 2251 | |
| 2252 | w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC); |
| 2253 | if (!w) |
| 2254 | return -ENOMEM; |
| 2255 | |
| 2256 | w->callback = callback; |
| 2257 | w->data = data; |
| 2258 | spin_lock_irqsave(&musb->list_lock, flags); |
| 2259 | if (musb->is_runtime_suspended) { |
| 2260 | list_add_tail(&w->node, &musb->pending_list); |
| 2261 | error = 0; |
| 2262 | } else { |
| 2263 | dev_err(musb->controller, "could not add resume work %p\n", |
| 2264 | callback); |
| 2265 | devm_kfree(musb->controller, w); |
| 2266 | error = -EINPROGRESS; |
| 2267 | } |
| 2268 | spin_unlock_irqrestore(&musb->list_lock, flags); |
| 2269 | |
| 2270 | return error; |
| 2271 | } |
| 2272 | EXPORT_SYMBOL_GPL(musb_queue_resume_work); |
| 2273 | |
| 2274 | static void musb_deassert_reset(struct work_struct *work) |
| 2275 | { |
| 2276 | struct musb *musb; |
| 2277 | unsigned long flags; |
| 2278 | |
| 2279 | musb = container_of(work, struct musb, deassert_reset_work.work); |
| 2280 | |
| 2281 | spin_lock_irqsave(&musb->lock, flags); |
| 2282 | |
| 2283 | if (musb->port1_status & USB_PORT_STAT_RESET) |
| 2284 | musb_port_reset(musb, false); |
| 2285 | |
| 2286 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2287 | } |
| 2288 | |
| 2289 | /* |
| 2290 | * Perform generic per-controller initialization. |
| 2291 | * |
| 2292 | * @dev: the controller (already clocked, etc) |
| 2293 | * @nIrq: IRQ number |
| 2294 | * @ctrl: virtual address of controller registers, |
| 2295 | * not yet corrected for platform-specific offsets |
| 2296 | */ |
| 2297 | static int |
| 2298 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
| 2299 | { |
| 2300 | int status; |
| 2301 | struct musb *musb; |
| 2302 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
| 2303 | |
| 2304 | /* The driver might handle more features than the board; OK. |
| 2305 | * Fail when the board needs a feature that's not enabled. |
| 2306 | */ |
| 2307 | if (!plat) { |
| 2308 | dev_err(dev, "no platform_data?\n"); |
| 2309 | status = -ENODEV; |
| 2310 | goto fail0; |
| 2311 | } |
| 2312 | |
| 2313 | /* allocate */ |
| 2314 | musb = allocate_instance(dev, plat->config, ctrl); |
| 2315 | if (!musb) { |
| 2316 | status = -ENOMEM; |
| 2317 | goto fail0; |
| 2318 | } |
| 2319 | |
| 2320 | spin_lock_init(&musb->lock); |
| 2321 | spin_lock_init(&musb->list_lock); |
| 2322 | musb->board_set_power = plat->set_power; |
| 2323 | musb->min_power = plat->min_power; |
| 2324 | musb->ops = plat->platform_ops; |
| 2325 | musb->port_mode = plat->mode; |
| 2326 | |
| 2327 | /* |
| 2328 | * Initialize the default IO functions. At least omap2430 needs |
| 2329 | * these early. We initialize the platform specific IO functions |
| 2330 | * later on. |
| 2331 | */ |
| 2332 | musb_readb = musb_default_readb; |
| 2333 | musb_writeb = musb_default_writeb; |
| 2334 | musb_readw = musb_default_readw; |
| 2335 | musb_writew = musb_default_writew; |
| 2336 | |
| 2337 | /* The musb_platform_init() call: |
| 2338 | * - adjusts musb->mregs |
| 2339 | * - sets the musb->isr |
| 2340 | * - may initialize an integrated transceiver |
| 2341 | * - initializes musb->xceiv, usually by otg_get_phy() |
| 2342 | * - stops powering VBUS |
| 2343 | * |
| 2344 | * There are various transceiver configurations. |
| 2345 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
| 2346 | * external/discrete ones in various flavors (twl4030 family, |
| 2347 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. |
| 2348 | */ |
| 2349 | status = musb_platform_init(musb); |
| 2350 | if (status < 0) |
| 2351 | goto fail1; |
| 2352 | |
| 2353 | if (!musb->isr) { |
| 2354 | status = -ENODEV; |
| 2355 | goto fail2; |
| 2356 | } |
| 2357 | |
| 2358 | |
| 2359 | /* Most devices use indexed offset or flat offset */ |
| 2360 | if (musb->ops->quirks & MUSB_INDEXED_EP) { |
| 2361 | musb->io.ep_offset = musb_indexed_ep_offset; |
| 2362 | musb->io.ep_select = musb_indexed_ep_select; |
| 2363 | } else { |
| 2364 | musb->io.ep_offset = musb_flat_ep_offset; |
| 2365 | musb->io.ep_select = musb_flat_ep_select; |
| 2366 | } |
| 2367 | |
| 2368 | if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE) |
| 2369 | musb->g.quirk_avoids_skb_reserve = 1; |
| 2370 | |
| 2371 | /* At least tusb6010 has its own offsets */ |
| 2372 | if (musb->ops->ep_offset) |
| 2373 | musb->io.ep_offset = musb->ops->ep_offset; |
| 2374 | if (musb->ops->ep_select) |
| 2375 | musb->io.ep_select = musb->ops->ep_select; |
| 2376 | |
| 2377 | if (musb->ops->fifo_mode) |
| 2378 | fifo_mode = musb->ops->fifo_mode; |
| 2379 | else |
| 2380 | fifo_mode = 4; |
| 2381 | |
| 2382 | if (musb->ops->fifo_offset) |
| 2383 | musb->io.fifo_offset = musb->ops->fifo_offset; |
| 2384 | else |
| 2385 | musb->io.fifo_offset = musb_default_fifo_offset; |
| 2386 | |
| 2387 | if (musb->ops->busctl_offset) |
| 2388 | musb->io.busctl_offset = musb->ops->busctl_offset; |
| 2389 | else |
| 2390 | musb->io.busctl_offset = musb_default_busctl_offset; |
| 2391 | |
| 2392 | if (musb->ops->readb) |
| 2393 | musb_readb = musb->ops->readb; |
| 2394 | if (musb->ops->writeb) |
| 2395 | musb_writeb = musb->ops->writeb; |
| 2396 | if (musb->ops->clearb) |
| 2397 | musb_clearb = musb->ops->clearb; |
| 2398 | else |
| 2399 | musb_clearb = musb_readb; |
| 2400 | |
| 2401 | if (musb->ops->readw) |
| 2402 | musb_readw = musb->ops->readw; |
| 2403 | if (musb->ops->writew) |
| 2404 | musb_writew = musb->ops->writew; |
| 2405 | if (musb->ops->clearw) |
| 2406 | musb_clearw = musb->ops->clearw; |
| 2407 | else |
| 2408 | musb_clearw = musb_readw; |
| 2409 | |
| 2410 | #ifndef CONFIG_MUSB_PIO_ONLY |
| 2411 | if (!musb->ops->dma_init || !musb->ops->dma_exit) { |
| 2412 | dev_err(dev, "DMA controller not set\n"); |
| 2413 | status = -ENODEV; |
| 2414 | goto fail2; |
| 2415 | } |
| 2416 | musb_dma_controller_create = musb->ops->dma_init; |
| 2417 | musb_dma_controller_destroy = musb->ops->dma_exit; |
| 2418 | #endif |
| 2419 | |
| 2420 | if (musb->ops->read_fifo) |
| 2421 | musb->io.read_fifo = musb->ops->read_fifo; |
| 2422 | else |
| 2423 | musb->io.read_fifo = musb_default_read_fifo; |
| 2424 | |
| 2425 | if (musb->ops->write_fifo) |
| 2426 | musb->io.write_fifo = musb->ops->write_fifo; |
| 2427 | else |
| 2428 | musb->io.write_fifo = musb_default_write_fifo; |
| 2429 | |
| 2430 | if (musb->ops->get_toggle) |
| 2431 | musb->io.get_toggle = musb->ops->get_toggle; |
| 2432 | else |
| 2433 | musb->io.get_toggle = musb_default_get_toggle; |
| 2434 | |
| 2435 | if (musb->ops->set_toggle) |
| 2436 | musb->io.set_toggle = musb->ops->set_toggle; |
| 2437 | else |
| 2438 | musb->io.set_toggle = musb_default_set_toggle; |
| 2439 | |
| 2440 | if (!musb->xceiv->io_ops) { |
| 2441 | musb->xceiv->io_dev = musb->controller; |
| 2442 | musb->xceiv->io_priv = musb->mregs; |
| 2443 | musb->xceiv->io_ops = &musb_ulpi_access; |
| 2444 | } |
| 2445 | |
| 2446 | if (musb->ops->phy_callback) |
| 2447 | musb_phy_callback = musb->ops->phy_callback; |
| 2448 | |
| 2449 | /* |
| 2450 | * We need musb_read/write functions initialized for PM. |
| 2451 | * Note that at least 2430 glue needs autosuspend delay |
| 2452 | * somewhere above 300 ms for the hardware to idle properly |
| 2453 | * after disconnecting the cable in host mode. Let's use |
| 2454 | * 500 ms for some margin. |
| 2455 | */ |
| 2456 | pm_runtime_use_autosuspend(musb->controller); |
| 2457 | pm_runtime_set_autosuspend_delay(musb->controller, 500); |
| 2458 | pm_runtime_enable(musb->controller); |
| 2459 | pm_runtime_get_sync(musb->controller); |
| 2460 | |
| 2461 | status = usb_phy_init(musb->xceiv); |
| 2462 | if (status < 0) |
| 2463 | goto err_usb_phy_init; |
| 2464 | |
| 2465 | if (use_dma && dev->dma_mask) { |
| 2466 | musb->dma_controller = |
| 2467 | musb_dma_controller_create(musb, musb->mregs); |
| 2468 | if (IS_ERR(musb->dma_controller)) { |
| 2469 | status = PTR_ERR(musb->dma_controller); |
| 2470 | goto fail2_5; |
| 2471 | } |
| 2472 | } |
| 2473 | |
| 2474 | /* be sure interrupts are disabled before connecting ISR */ |
| 2475 | musb_platform_disable(musb); |
| 2476 | musb_disable_interrupts(musb); |
| 2477 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
| 2478 | |
| 2479 | /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */ |
| 2480 | musb_writeb(musb->mregs, MUSB_POWER, 0); |
| 2481 | |
| 2482 | /* Init IRQ workqueue before request_irq */ |
| 2483 | INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work); |
| 2484 | INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); |
| 2485 | INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); |
| 2486 | |
| 2487 | /* setup musb parts of the core (especially endpoints) */ |
| 2488 | status = musb_core_init(plat->config->multipoint |
| 2489 | ? MUSB_CONTROLLER_MHDRC |
| 2490 | : MUSB_CONTROLLER_HDRC, musb); |
| 2491 | if (status < 0) |
| 2492 | goto fail3; |
| 2493 | |
| 2494 | timer_setup(&musb->otg_timer, musb_otg_timer_func, 0); |
| 2495 | |
| 2496 | /* attach to the IRQ */ |
| 2497 | if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) { |
| 2498 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
| 2499 | status = -ENODEV; |
| 2500 | goto fail3; |
| 2501 | } |
| 2502 | musb->nIrq = nIrq; |
| 2503 | /* FIXME this handles wakeup irqs wrong */ |
| 2504 | if (enable_irq_wake(nIrq) == 0) { |
| 2505 | musb->irq_wake = 1; |
| 2506 | device_init_wakeup(dev, 1); |
| 2507 | } else { |
| 2508 | musb->irq_wake = 0; |
| 2509 | } |
| 2510 | |
| 2511 | /* program PHY to use external vBus if required */ |
| 2512 | if (plat->extvbus) { |
| 2513 | u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL); |
| 2514 | busctl |= MUSB_ULPI_USE_EXTVBUS; |
| 2515 | musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl); |
| 2516 | } |
| 2517 | |
| 2518 | MUSB_DEV_MODE(musb); |
| 2519 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
| 2520 | |
| 2521 | switch (musb->port_mode) { |
| 2522 | case MUSB_HOST: |
| 2523 | status = musb_host_setup(musb, plat->power); |
| 2524 | if (status < 0) |
| 2525 | goto fail3; |
| 2526 | status = musb_platform_set_mode(musb, MUSB_HOST); |
| 2527 | break; |
| 2528 | case MUSB_PERIPHERAL: |
| 2529 | status = musb_gadget_setup(musb); |
| 2530 | if (status < 0) |
| 2531 | goto fail3; |
| 2532 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); |
| 2533 | break; |
| 2534 | case MUSB_OTG: |
| 2535 | status = musb_host_setup(musb, plat->power); |
| 2536 | if (status < 0) |
| 2537 | goto fail3; |
| 2538 | status = musb_gadget_setup(musb); |
| 2539 | if (status) { |
| 2540 | musb_host_cleanup(musb); |
| 2541 | goto fail3; |
| 2542 | } |
| 2543 | status = musb_platform_set_mode(musb, MUSB_OTG); |
| 2544 | break; |
| 2545 | default: |
| 2546 | dev_err(dev, "unsupported port mode %d\n", musb->port_mode); |
| 2547 | break; |
| 2548 | } |
| 2549 | |
| 2550 | if (status < 0) |
| 2551 | goto fail3; |
| 2552 | |
| 2553 | musb_init_debugfs(musb); |
| 2554 | |
| 2555 | musb->is_initialized = 1; |
| 2556 | pm_runtime_mark_last_busy(musb->controller); |
| 2557 | pm_runtime_put_autosuspend(musb->controller); |
| 2558 | |
| 2559 | return 0; |
| 2560 | |
| 2561 | fail3: |
| 2562 | cancel_delayed_work_sync(&musb->irq_work); |
| 2563 | cancel_delayed_work_sync(&musb->finish_resume_work); |
| 2564 | cancel_delayed_work_sync(&musb->deassert_reset_work); |
| 2565 | if (musb->dma_controller) |
| 2566 | musb_dma_controller_destroy(musb->dma_controller); |
| 2567 | |
| 2568 | fail2_5: |
| 2569 | usb_phy_shutdown(musb->xceiv); |
| 2570 | |
| 2571 | err_usb_phy_init: |
| 2572 | pm_runtime_dont_use_autosuspend(musb->controller); |
| 2573 | pm_runtime_put_sync(musb->controller); |
| 2574 | pm_runtime_disable(musb->controller); |
| 2575 | |
| 2576 | fail2: |
| 2577 | if (musb->irq_wake) |
| 2578 | device_init_wakeup(dev, 0); |
| 2579 | musb_platform_exit(musb); |
| 2580 | |
| 2581 | fail1: |
| 2582 | if (status != -EPROBE_DEFER) |
| 2583 | dev_err(musb->controller, |
| 2584 | "%s failed with status %d\n", __func__, status); |
| 2585 | |
| 2586 | musb_free(musb); |
| 2587 | |
| 2588 | fail0: |
| 2589 | |
| 2590 | return status; |
| 2591 | |
| 2592 | } |
| 2593 | |
| 2594 | /*-------------------------------------------------------------------------*/ |
| 2595 | |
| 2596 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just |
| 2597 | * bridge to a platform device; this driver then suffices. |
| 2598 | */ |
| 2599 | static int musb_probe(struct platform_device *pdev) |
| 2600 | { |
| 2601 | struct device *dev = &pdev->dev; |
| 2602 | int irq = platform_get_irq_byname(pdev, "mc"); |
| 2603 | void __iomem *base; |
| 2604 | |
| 2605 | if (irq <= 0) |
| 2606 | return -ENODEV; |
| 2607 | |
| 2608 | base = devm_platform_ioremap_resource(pdev, 0); |
| 2609 | if (IS_ERR(base)) |
| 2610 | return PTR_ERR(base); |
| 2611 | |
| 2612 | return musb_init_controller(dev, irq, base); |
| 2613 | } |
| 2614 | |
| 2615 | static int musb_remove(struct platform_device *pdev) |
| 2616 | { |
| 2617 | struct device *dev = &pdev->dev; |
| 2618 | struct musb *musb = dev_to_musb(dev); |
| 2619 | unsigned long flags; |
| 2620 | |
| 2621 | /* this gets called on rmmod. |
| 2622 | * - Host mode: host may still be active |
| 2623 | * - Peripheral mode: peripheral is deactivated (or never-activated) |
| 2624 | * - OTG mode: both roles are deactivated (or never-activated) |
| 2625 | */ |
| 2626 | musb_exit_debugfs(musb); |
| 2627 | |
| 2628 | cancel_delayed_work_sync(&musb->irq_work); |
| 2629 | cancel_delayed_work_sync(&musb->finish_resume_work); |
| 2630 | cancel_delayed_work_sync(&musb->deassert_reset_work); |
| 2631 | pm_runtime_get_sync(musb->controller); |
| 2632 | musb_host_cleanup(musb); |
| 2633 | musb_gadget_cleanup(musb); |
| 2634 | |
| 2635 | musb_platform_disable(musb); |
| 2636 | spin_lock_irqsave(&musb->lock, flags); |
| 2637 | musb_disable_interrupts(musb); |
| 2638 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
| 2639 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2640 | musb_platform_exit(musb); |
| 2641 | |
| 2642 | pm_runtime_dont_use_autosuspend(musb->controller); |
| 2643 | pm_runtime_put_sync(musb->controller); |
| 2644 | pm_runtime_disable(musb->controller); |
| 2645 | musb_phy_callback = NULL; |
| 2646 | if (musb->dma_controller) |
| 2647 | musb_dma_controller_destroy(musb->dma_controller); |
| 2648 | usb_phy_shutdown(musb->xceiv); |
| 2649 | musb_free(musb); |
| 2650 | device_init_wakeup(dev, 0); |
| 2651 | return 0; |
| 2652 | } |
| 2653 | |
| 2654 | #ifdef CONFIG_PM |
| 2655 | |
| 2656 | static void musb_save_context(struct musb *musb) |
| 2657 | { |
| 2658 | int i; |
| 2659 | void __iomem *musb_base = musb->mregs; |
| 2660 | void __iomem *epio; |
| 2661 | |
| 2662 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
| 2663 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); |
| 2664 | musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL); |
| 2665 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
| 2666 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); |
| 2667 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); |
| 2668 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); |
| 2669 | |
| 2670 | for (i = 0; i < musb->config->num_eps; ++i) { |
| 2671 | struct musb_hw_ep *hw_ep; |
| 2672 | |
| 2673 | hw_ep = &musb->endpoints[i]; |
| 2674 | if (!hw_ep) |
| 2675 | continue; |
| 2676 | |
| 2677 | epio = hw_ep->regs; |
| 2678 | if (!epio) |
| 2679 | continue; |
| 2680 | |
| 2681 | musb_writeb(musb_base, MUSB_INDEX, i); |
| 2682 | musb->context.index_regs[i].txmaxp = |
| 2683 | musb_readw(epio, MUSB_TXMAXP); |
| 2684 | musb->context.index_regs[i].txcsr = |
| 2685 | musb_readw(epio, MUSB_TXCSR); |
| 2686 | musb->context.index_regs[i].rxmaxp = |
| 2687 | musb_readw(epio, MUSB_RXMAXP); |
| 2688 | musb->context.index_regs[i].rxcsr = |
| 2689 | musb_readw(epio, MUSB_RXCSR); |
| 2690 | |
| 2691 | if (musb->dyn_fifo) { |
| 2692 | musb->context.index_regs[i].txfifoadd = |
| 2693 | musb_readw(musb_base, MUSB_TXFIFOADD); |
| 2694 | musb->context.index_regs[i].rxfifoadd = |
| 2695 | musb_readw(musb_base, MUSB_RXFIFOADD); |
| 2696 | musb->context.index_regs[i].txfifosz = |
| 2697 | musb_readb(musb_base, MUSB_TXFIFOSZ); |
| 2698 | musb->context.index_regs[i].rxfifosz = |
| 2699 | musb_readb(musb_base, MUSB_RXFIFOSZ); |
| 2700 | } |
| 2701 | |
| 2702 | musb->context.index_regs[i].txtype = |
| 2703 | musb_readb(epio, MUSB_TXTYPE); |
| 2704 | musb->context.index_regs[i].txinterval = |
| 2705 | musb_readb(epio, MUSB_TXINTERVAL); |
| 2706 | musb->context.index_regs[i].rxtype = |
| 2707 | musb_readb(epio, MUSB_RXTYPE); |
| 2708 | musb->context.index_regs[i].rxinterval = |
| 2709 | musb_readb(epio, MUSB_RXINTERVAL); |
| 2710 | |
| 2711 | musb->context.index_regs[i].txfunaddr = |
| 2712 | musb_read_txfunaddr(musb, i); |
| 2713 | musb->context.index_regs[i].txhubaddr = |
| 2714 | musb_read_txhubaddr(musb, i); |
| 2715 | musb->context.index_regs[i].txhubport = |
| 2716 | musb_read_txhubport(musb, i); |
| 2717 | |
| 2718 | musb->context.index_regs[i].rxfunaddr = |
| 2719 | musb_read_rxfunaddr(musb, i); |
| 2720 | musb->context.index_regs[i].rxhubaddr = |
| 2721 | musb_read_rxhubaddr(musb, i); |
| 2722 | musb->context.index_regs[i].rxhubport = |
| 2723 | musb_read_rxhubport(musb, i); |
| 2724 | } |
| 2725 | } |
| 2726 | |
| 2727 | static void musb_restore_context(struct musb *musb) |
| 2728 | { |
| 2729 | int i; |
| 2730 | void __iomem *musb_base = musb->mregs; |
| 2731 | void __iomem *epio; |
| 2732 | u8 power; |
| 2733 | |
| 2734 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
| 2735 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); |
| 2736 | musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl); |
| 2737 | |
| 2738 | /* Don't affect SUSPENDM/RESUME bits in POWER reg */ |
| 2739 | power = musb_readb(musb_base, MUSB_POWER); |
| 2740 | power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; |
| 2741 | musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); |
| 2742 | power |= musb->context.power; |
| 2743 | musb_writeb(musb_base, MUSB_POWER, power); |
| 2744 | |
| 2745 | musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); |
| 2746 | musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); |
| 2747 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); |
| 2748 | if (musb->context.devctl & MUSB_DEVCTL_SESSION) |
| 2749 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); |
| 2750 | |
| 2751 | for (i = 0; i < musb->config->num_eps; ++i) { |
| 2752 | struct musb_hw_ep *hw_ep; |
| 2753 | |
| 2754 | hw_ep = &musb->endpoints[i]; |
| 2755 | if (!hw_ep) |
| 2756 | continue; |
| 2757 | |
| 2758 | epio = hw_ep->regs; |
| 2759 | if (!epio) |
| 2760 | continue; |
| 2761 | |
| 2762 | musb_writeb(musb_base, MUSB_INDEX, i); |
| 2763 | musb_writew(epio, MUSB_TXMAXP, |
| 2764 | musb->context.index_regs[i].txmaxp); |
| 2765 | musb_writew(epio, MUSB_TXCSR, |
| 2766 | musb->context.index_regs[i].txcsr); |
| 2767 | musb_writew(epio, MUSB_RXMAXP, |
| 2768 | musb->context.index_regs[i].rxmaxp); |
| 2769 | musb_writew(epio, MUSB_RXCSR, |
| 2770 | musb->context.index_regs[i].rxcsr); |
| 2771 | |
| 2772 | if (musb->dyn_fifo) { |
| 2773 | musb_writeb(musb_base, MUSB_TXFIFOSZ, |
| 2774 | musb->context.index_regs[i].txfifosz); |
| 2775 | musb_writeb(musb_base, MUSB_RXFIFOSZ, |
| 2776 | musb->context.index_regs[i].rxfifosz); |
| 2777 | musb_writew(musb_base, MUSB_TXFIFOADD, |
| 2778 | musb->context.index_regs[i].txfifoadd); |
| 2779 | musb_writew(musb_base, MUSB_RXFIFOADD, |
| 2780 | musb->context.index_regs[i].rxfifoadd); |
| 2781 | } |
| 2782 | |
| 2783 | musb_writeb(epio, MUSB_TXTYPE, |
| 2784 | musb->context.index_regs[i].txtype); |
| 2785 | musb_writeb(epio, MUSB_TXINTERVAL, |
| 2786 | musb->context.index_regs[i].txinterval); |
| 2787 | musb_writeb(epio, MUSB_RXTYPE, |
| 2788 | musb->context.index_regs[i].rxtype); |
| 2789 | musb_writeb(epio, MUSB_RXINTERVAL, |
| 2790 | |
| 2791 | musb->context.index_regs[i].rxinterval); |
| 2792 | musb_write_txfunaddr(musb, i, |
| 2793 | musb->context.index_regs[i].txfunaddr); |
| 2794 | musb_write_txhubaddr(musb, i, |
| 2795 | musb->context.index_regs[i].txhubaddr); |
| 2796 | musb_write_txhubport(musb, i, |
| 2797 | musb->context.index_regs[i].txhubport); |
| 2798 | |
| 2799 | musb_write_rxfunaddr(musb, i, |
| 2800 | musb->context.index_regs[i].rxfunaddr); |
| 2801 | musb_write_rxhubaddr(musb, i, |
| 2802 | musb->context.index_regs[i].rxhubaddr); |
| 2803 | musb_write_rxhubport(musb, i, |
| 2804 | musb->context.index_regs[i].rxhubport); |
| 2805 | } |
| 2806 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
| 2807 | } |
| 2808 | |
| 2809 | static int musb_suspend(struct device *dev) |
| 2810 | { |
| 2811 | struct musb *musb = dev_to_musb(dev); |
| 2812 | unsigned long flags; |
| 2813 | int ret; |
| 2814 | |
| 2815 | ret = pm_runtime_get_sync(dev); |
| 2816 | if (ret < 0) { |
| 2817 | pm_runtime_put_noidle(dev); |
| 2818 | return ret; |
| 2819 | } |
| 2820 | |
| 2821 | musb_platform_disable(musb); |
| 2822 | musb_disable_interrupts(musb); |
| 2823 | |
| 2824 | musb->flush_irq_work = true; |
| 2825 | while (flush_delayed_work(&musb->irq_work)) |
| 2826 | ; |
| 2827 | musb->flush_irq_work = false; |
| 2828 | |
| 2829 | if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION)) |
| 2830 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
| 2831 | |
| 2832 | WARN_ON(!list_empty(&musb->pending_list)); |
| 2833 | |
| 2834 | spin_lock_irqsave(&musb->lock, flags); |
| 2835 | |
| 2836 | if (is_peripheral_active(musb)) { |
| 2837 | /* FIXME force disconnect unless we know USB will wake |
| 2838 | * the system up quickly enough to respond ... |
| 2839 | */ |
| 2840 | } else if (is_host_active(musb)) { |
| 2841 | /* we know all the children are suspended; sometimes |
| 2842 | * they will even be wakeup-enabled. |
| 2843 | */ |
| 2844 | } |
| 2845 | |
| 2846 | musb_save_context(musb); |
| 2847 | |
| 2848 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2849 | return 0; |
| 2850 | } |
| 2851 | |
| 2852 | static int musb_resume(struct device *dev) |
| 2853 | { |
| 2854 | struct musb *musb = dev_to_musb(dev); |
| 2855 | unsigned long flags; |
| 2856 | int error; |
| 2857 | u8 devctl; |
| 2858 | u8 mask; |
| 2859 | |
| 2860 | /* |
| 2861 | * For static cmos like DaVinci, register values were preserved |
| 2862 | * unless for some reason the whole soc powered down or the USB |
| 2863 | * module got reset through the PSC (vs just being disabled). |
| 2864 | * |
| 2865 | * For the DSPS glue layer though, a full register restore has to |
| 2866 | * be done. As it shouldn't harm other platforms, we do it |
| 2867 | * unconditionally. |
| 2868 | */ |
| 2869 | |
| 2870 | musb_restore_context(musb); |
| 2871 | |
| 2872 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 2873 | mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; |
| 2874 | if ((devctl & mask) != (musb->context.devctl & mask)) |
| 2875 | musb->port1_status = 0; |
| 2876 | |
| 2877 | musb_enable_interrupts(musb); |
| 2878 | musb_platform_enable(musb); |
| 2879 | |
| 2880 | spin_lock_irqsave(&musb->lock, flags); |
| 2881 | error = musb_run_resume_work(musb); |
| 2882 | if (error) |
| 2883 | dev_err(musb->controller, "resume work failed with %i\n", |
| 2884 | error); |
| 2885 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2886 | |
| 2887 | pm_runtime_mark_last_busy(dev); |
| 2888 | pm_runtime_put_autosuspend(dev); |
| 2889 | |
| 2890 | return 0; |
| 2891 | } |
| 2892 | |
| 2893 | static int musb_runtime_suspend(struct device *dev) |
| 2894 | { |
| 2895 | struct musb *musb = dev_to_musb(dev); |
| 2896 | |
| 2897 | musb_save_context(musb); |
| 2898 | musb->is_runtime_suspended = 1; |
| 2899 | |
| 2900 | return 0; |
| 2901 | } |
| 2902 | |
| 2903 | static int musb_runtime_resume(struct device *dev) |
| 2904 | { |
| 2905 | struct musb *musb = dev_to_musb(dev); |
| 2906 | unsigned long flags; |
| 2907 | int error; |
| 2908 | |
| 2909 | /* |
| 2910 | * When pm_runtime_get_sync called for the first time in driver |
| 2911 | * init, some of the structure is still not initialized which is |
| 2912 | * used in restore function. But clock needs to be |
| 2913 | * enabled before any register access, so |
| 2914 | * pm_runtime_get_sync has to be called. |
| 2915 | * Also context restore without save does not make |
| 2916 | * any sense |
| 2917 | */ |
| 2918 | if (!musb->is_initialized) |
| 2919 | return 0; |
| 2920 | |
| 2921 | musb_restore_context(musb); |
| 2922 | |
| 2923 | spin_lock_irqsave(&musb->lock, flags); |
| 2924 | error = musb_run_resume_work(musb); |
| 2925 | if (error) |
| 2926 | dev_err(musb->controller, "resume work failed with %i\n", |
| 2927 | error); |
| 2928 | musb->is_runtime_suspended = 0; |
| 2929 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2930 | |
| 2931 | return 0; |
| 2932 | } |
| 2933 | |
| 2934 | static const struct dev_pm_ops musb_dev_pm_ops = { |
| 2935 | .suspend = musb_suspend, |
| 2936 | .resume = musb_resume, |
| 2937 | .runtime_suspend = musb_runtime_suspend, |
| 2938 | .runtime_resume = musb_runtime_resume, |
| 2939 | }; |
| 2940 | |
| 2941 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) |
| 2942 | #else |
| 2943 | #define MUSB_DEV_PM_OPS NULL |
| 2944 | #endif |
| 2945 | |
| 2946 | static struct platform_driver musb_driver = { |
| 2947 | .driver = { |
| 2948 | .name = musb_driver_name, |
| 2949 | .bus = &platform_bus_type, |
| 2950 | .pm = MUSB_DEV_PM_OPS, |
| 2951 | .dev_groups = musb_groups, |
| 2952 | }, |
| 2953 | .probe = musb_probe, |
| 2954 | .remove = musb_remove, |
| 2955 | }; |
| 2956 | |
| 2957 | module_platform_driver(musb_driver); |