| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * core.h - DesignWare USB3 DRD Core Header |
| 4 | * |
| 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
| 6 | * |
| 7 | * Authors: Felipe Balbi <balbi@ti.com>, |
| 8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
| 9 | */ |
| 10 | |
| 11 | #ifndef __DRIVERS_USB_DWC3_CORE_H |
| 12 | #define __DRIVERS_USB_DWC3_CORE_H |
| 13 | |
| 14 | #include <linux/device.h> |
| 15 | #include <linux/spinlock.h> |
| 16 | #include <linux/mutex.h> |
| 17 | #include <linux/ioport.h> |
| 18 | #include <linux/list.h> |
| 19 | #include <linux/bitops.h> |
| 20 | #include <linux/dma-mapping.h> |
| 21 | #include <linux/mm.h> |
| 22 | #include <linux/debugfs.h> |
| 23 | #include <linux/wait.h> |
| 24 | #include <linux/workqueue.h> |
| 25 | |
| 26 | #include <linux/usb/ch9.h> |
| 27 | #include <linux/usb/gadget.h> |
| 28 | #include <linux/usb/otg.h> |
| 29 | #include <linux/usb/role.h> |
| 30 | #include <linux/ulpi/interface.h> |
| 31 | |
| 32 | #include <linux/phy/phy.h> |
| 33 | |
| 34 | #include <linux/power_supply.h> |
| 35 | |
| 36 | #define DWC3_MSG_MAX 500 |
| 37 | |
| 38 | /* Global constants */ |
| 39 | #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ |
| 40 | #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ |
| 41 | #define DWC3_EP0_SETUP_SIZE 512 |
| 42 | #define DWC3_ENDPOINTS_NUM 32 |
| 43 | #define DWC3_XHCI_RESOURCES_NUM 2 |
| 44 | #define DWC3_ISOC_MAX_RETRIES 5 |
| 45 | |
| 46 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
| 47 | #define DWC3_EVENT_BUFFERS_SIZE 4096 |
| 48 | #define DWC3_EVENT_TYPE_MASK 0xfe |
| 49 | |
| 50 | #define DWC3_EVENT_TYPE_DEV 0 |
| 51 | #define DWC3_EVENT_TYPE_CARKIT 3 |
| 52 | #define DWC3_EVENT_TYPE_I2C 4 |
| 53 | |
| 54 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 |
| 55 | #define DWC3_DEVICE_EVENT_RESET 1 |
| 56 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 |
| 57 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 |
| 58 | #define DWC3_DEVICE_EVENT_WAKEUP 4 |
| 59 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
| 60 | #define DWC3_DEVICE_EVENT_SUSPEND 6 |
| 61 | #define DWC3_DEVICE_EVENT_SOF 7 |
| 62 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 |
| 63 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 |
| 64 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 |
| 65 | |
| 66 | /* Controller's role while using the OTG block */ |
| 67 | #define DWC3_OTG_ROLE_IDLE 0 |
| 68 | #define DWC3_OTG_ROLE_HOST 1 |
| 69 | #define DWC3_OTG_ROLE_DEVICE 2 |
| 70 | |
| 71 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
| 72 | #define DWC3_GEVNTCOUNT_EHB BIT(31) |
| 73 | #define DWC3_GSNPSID_MASK 0xffff0000 |
| 74 | #define DWC3_GSNPSREV_MASK 0xffff |
| 75 | #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) |
| 76 | |
| 77 | /* DWC3 registers memory space boundries */ |
| 78 | #define DWC3_XHCI_REGS_START 0x0 |
| 79 | #define DWC3_XHCI_REGS_END 0x7fff |
| 80 | #define DWC3_GLOBALS_REGS_START 0xc100 |
| 81 | #define DWC3_GLOBALS_REGS_END 0xc6ff |
| 82 | #define DWC3_DEVICE_REGS_START 0xc700 |
| 83 | #define DWC3_DEVICE_REGS_END 0xcbff |
| 84 | #define DWC3_OTG_REGS_START 0xcc00 |
| 85 | #define DWC3_OTG_REGS_END 0xccff |
| 86 | |
| 87 | /* Global Registers */ |
| 88 | #define DWC3_GSBUSCFG0 0xc100 |
| 89 | #define DWC3_GSBUSCFG1 0xc104 |
| 90 | #define DWC3_GTXTHRCFG 0xc108 |
| 91 | #define DWC3_GRXTHRCFG 0xc10c |
| 92 | #define DWC3_GCTL 0xc110 |
| 93 | #define DWC3_GEVTEN 0xc114 |
| 94 | #define DWC3_GSTS 0xc118 |
| 95 | #define DWC3_GUCTL1 0xc11c |
| 96 | #define DWC3_GSNPSID 0xc120 |
| 97 | #define DWC3_GGPIO 0xc124 |
| 98 | #define DWC3_GUID 0xc128 |
| 99 | #define DWC3_GUCTL 0xc12c |
| 100 | #define DWC3_GBUSERRADDR0 0xc130 |
| 101 | #define DWC3_GBUSERRADDR1 0xc134 |
| 102 | #define DWC3_GPRTBIMAP0 0xc138 |
| 103 | #define DWC3_GPRTBIMAP1 0xc13c |
| 104 | #define DWC3_GHWPARAMS0 0xc140 |
| 105 | #define DWC3_GHWPARAMS1 0xc144 |
| 106 | #define DWC3_GHWPARAMS2 0xc148 |
| 107 | #define DWC3_GHWPARAMS3 0xc14c |
| 108 | #define DWC3_GHWPARAMS4 0xc150 |
| 109 | #define DWC3_GHWPARAMS5 0xc154 |
| 110 | #define DWC3_GHWPARAMS6 0xc158 |
| 111 | #define DWC3_GHWPARAMS7 0xc15c |
| 112 | #define DWC3_GDBGFIFOSPACE 0xc160 |
| 113 | #define DWC3_GDBGLTSSM 0xc164 |
| 114 | #define DWC3_GDBGBMU 0xc16c |
| 115 | #define DWC3_GDBGLSPMUX 0xc170 |
| 116 | #define DWC3_GDBGLSP 0xc174 |
| 117 | #define DWC3_GDBGEPINFO0 0xc178 |
| 118 | #define DWC3_GDBGEPINFO1 0xc17c |
| 119 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
| 120 | #define DWC3_GPRTBIMAP_HS1 0xc184 |
| 121 | #define DWC3_GPRTBIMAP_FS0 0xc188 |
| 122 | #define DWC3_GPRTBIMAP_FS1 0xc18c |
| 123 | #define DWC3_GUCTL2 0xc19c |
| 124 | |
| 125 | #define DWC3_VER_NUMBER 0xc1a0 |
| 126 | #define DWC3_VER_TYPE 0xc1a4 |
| 127 | |
| 128 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) |
| 129 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) |
| 130 | |
| 131 | #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) |
| 132 | |
| 133 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) |
| 134 | |
| 135 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) |
| 136 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) |
| 137 | |
| 138 | #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) |
| 139 | #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) |
| 140 | #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) |
| 141 | #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) |
| 142 | |
| 143 | #define DWC3_GHWPARAMS8 0xc600 |
| 144 | #define DWC3_GUCTL3 0xc60c |
| 145 | #define DWC3_GFLADJ 0xc630 |
| 146 | #define DWC3_GHWPARAMS9 0xc6e0 |
| 147 | |
| 148 | /* Device Registers */ |
| 149 | #define DWC3_DCFG 0xc700 |
| 150 | #define DWC3_DCTL 0xc704 |
| 151 | #define DWC3_DEVTEN 0xc708 |
| 152 | #define DWC3_DSTS 0xc70c |
| 153 | #define DWC3_DGCMDPAR 0xc710 |
| 154 | #define DWC3_DGCMD 0xc714 |
| 155 | #define DWC3_DALEPENA 0xc720 |
| 156 | #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */ |
| 157 | |
| 158 | #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) |
| 159 | #define DWC3_DEPCMDPAR2 0x00 |
| 160 | #define DWC3_DEPCMDPAR1 0x04 |
| 161 | #define DWC3_DEPCMDPAR0 0x08 |
| 162 | #define DWC3_DEPCMD 0x0c |
| 163 | |
| 164 | #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) |
| 165 | |
| 166 | /* OTG Registers */ |
| 167 | #define DWC3_OCFG 0xcc00 |
| 168 | #define DWC3_OCTL 0xcc04 |
| 169 | #define DWC3_OEVT 0xcc08 |
| 170 | #define DWC3_OEVTEN 0xcc0C |
| 171 | #define DWC3_OSTS 0xcc10 |
| 172 | |
| 173 | /* Bit fields */ |
| 174 | |
| 175 | /* Global SoC Bus Configuration INCRx Register 0 */ |
| 176 | #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ |
| 177 | #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ |
| 178 | #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ |
| 179 | #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ |
| 180 | #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ |
| 181 | #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ |
| 182 | #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ |
| 183 | #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ |
| 184 | #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff |
| 185 | |
| 186 | /* Global Debug LSP MUX Select */ |
| 187 | #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ |
| 188 | #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) |
| 189 | #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) |
| 190 | #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) |
| 191 | |
| 192 | /* Global Debug Queue/FIFO Space Available Register */ |
| 193 | #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) |
| 194 | #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) |
| 195 | #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) |
| 196 | |
| 197 | #define DWC3_TXFIFO 0 |
| 198 | #define DWC3_RXFIFO 1 |
| 199 | #define DWC3_TXREQQ 2 |
| 200 | #define DWC3_RXREQQ 3 |
| 201 | #define DWC3_RXINFOQ 4 |
| 202 | #define DWC3_PSTATQ 5 |
| 203 | #define DWC3_DESCFETCHQ 6 |
| 204 | #define DWC3_EVENTQ 7 |
| 205 | #define DWC3_AUXEVENTQ 8 |
| 206 | |
| 207 | /* Global RX Threshold Configuration Register */ |
| 208 | #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) |
| 209 | #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) |
| 210 | #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) |
| 211 | |
| 212 | /* Global RX Threshold Configuration Register for DWC_usb31 only */ |
| 213 | #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) |
| 214 | #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) |
| 215 | #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) |
| 216 | #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) |
| 217 | #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) |
| 218 | #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) |
| 219 | #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) |
| 220 | #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) |
| 221 | |
| 222 | /* Global TX Threshold Configuration Register for DWC_usb31 only */ |
| 223 | #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) |
| 224 | #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) |
| 225 | #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) |
| 226 | #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) |
| 227 | #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) |
| 228 | #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) |
| 229 | #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) |
| 230 | #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) |
| 231 | |
| 232 | /* Global Configuration Register */ |
| 233 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
| 234 | #define DWC3_GCTL_U2RSTECN BIT(16) |
| 235 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
| 236 | #define DWC3_GCTL_CLK_BUS (0) |
| 237 | #define DWC3_GCTL_CLK_PIPE (1) |
| 238 | #define DWC3_GCTL_CLK_PIPEHALF (2) |
| 239 | #define DWC3_GCTL_CLK_MASK (3) |
| 240 | |
| 241 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
| 242 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
| 243 | #define DWC3_GCTL_PRTCAP_HOST 1 |
| 244 | #define DWC3_GCTL_PRTCAP_DEVICE 2 |
| 245 | #define DWC3_GCTL_PRTCAP_OTG 3 |
| 246 | |
| 247 | #define DWC3_GCTL_CORESOFTRESET BIT(11) |
| 248 | #define DWC3_GCTL_SOFITPSYNC BIT(10) |
| 249 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
| 250 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) |
| 251 | #define DWC3_GCTL_DISSCRAMBLE BIT(3) |
| 252 | #define DWC3_GCTL_U2EXIT_LFPS BIT(2) |
| 253 | #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) |
| 254 | #define DWC3_GCTL_DSBLCLKGTNG BIT(0) |
| 255 | |
| 256 | /* Global User Control Register */ |
| 257 | #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) |
| 258 | |
| 259 | /* Global User Control 1 Register */ |
| 260 | #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) |
| 261 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) |
| 262 | #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) |
| 263 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) |
| 264 | #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) |
| 265 | |
| 266 | /* Global Status Register */ |
| 267 | #define DWC3_GSTS_OTG_IP BIT(10) |
| 268 | #define DWC3_GSTS_BC_IP BIT(9) |
| 269 | #define DWC3_GSTS_ADP_IP BIT(8) |
| 270 | #define DWC3_GSTS_HOST_IP BIT(7) |
| 271 | #define DWC3_GSTS_DEVICE_IP BIT(6) |
| 272 | #define DWC3_GSTS_CSR_TIMEOUT BIT(5) |
| 273 | #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) |
| 274 | #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) |
| 275 | #define DWC3_GSTS_CURMOD_DEVICE 0 |
| 276 | #define DWC3_GSTS_CURMOD_HOST 1 |
| 277 | |
| 278 | /* Global USB2 PHY Configuration Register */ |
| 279 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) |
| 280 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) |
| 281 | #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) |
| 282 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) |
| 283 | #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) |
| 284 | #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) |
| 285 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) |
| 286 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) |
| 287 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) |
| 288 | #define USBTRDTIM_UTMI_8_BIT 9 |
| 289 | #define USBTRDTIM_UTMI_16_BIT 5 |
| 290 | #define UTMI_PHYIF_16_BIT 1 |
| 291 | #define UTMI_PHYIF_8_BIT 0 |
| 292 | |
| 293 | /* Global USB2 PHY Vendor Control Register */ |
| 294 | #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) |
| 295 | #define DWC3_GUSB2PHYACC_DONE BIT(24) |
| 296 | #define DWC3_GUSB2PHYACC_BUSY BIT(23) |
| 297 | #define DWC3_GUSB2PHYACC_WRITE BIT(22) |
| 298 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) |
| 299 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) |
| 300 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) |
| 301 | |
| 302 | /* Global USB3 PIPE Control Register */ |
| 303 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) |
| 304 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) |
| 305 | #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) |
| 306 | #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) |
| 307 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) |
| 308 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
| 309 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) |
| 310 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) |
| 311 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) |
| 312 | #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) |
| 313 | #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) |
| 314 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) |
| 315 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
| 316 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) |
| 317 | |
| 318 | /* Global TX Fifo Size Register */ |
| 319 | #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ |
| 320 | #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
| 321 | #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) |
| 322 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
| 323 | |
| 324 | /* Global RX Fifo Size Register */ |
| 325 | #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
| 326 | #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) |
| 327 | |
| 328 | /* Global Event Size Registers */ |
| 329 | #define DWC3_GEVNTSIZ_INTMASK BIT(31) |
| 330 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
| 331 | |
| 332 | /* Global HWPARAMS0 Register */ |
| 333 | #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) |
| 334 | #define DWC3_GHWPARAMS0_MODE_GADGET 0 |
| 335 | #define DWC3_GHWPARAMS0_MODE_HOST 1 |
| 336 | #define DWC3_GHWPARAMS0_MODE_DRD 2 |
| 337 | #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) |
| 338 | #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) |
| 339 | #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) |
| 340 | #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) |
| 341 | #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) |
| 342 | |
| 343 | /* Global HWPARAMS1 Register */ |
| 344 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
| 345 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
| 346 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 |
| 347 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
| 348 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) |
| 349 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) |
| 350 | #define DWC3_GHWPARAMS1_ENDBC BIT(31) |
| 351 | |
| 352 | /* Global HWPARAMS3 Register */ |
| 353 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) |
| 354 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 |
| 355 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 |
| 356 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ |
| 357 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
| 358 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 |
| 359 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 |
| 360 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 |
| 361 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 |
| 362 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) |
| 363 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 |
| 364 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 |
| 365 | |
| 366 | /* Global HWPARAMS4 Register */ |
| 367 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) |
| 368 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 |
| 369 | |
| 370 | /* Global HWPARAMS6 Register */ |
| 371 | #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) |
| 372 | #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) |
| 373 | #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) |
| 374 | #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) |
| 375 | #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) |
| 376 | #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) |
| 377 | |
| 378 | /* DWC_usb32 only */ |
| 379 | #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) |
| 380 | |
| 381 | /* Global HWPARAMS7 Register */ |
| 382 | #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) |
| 383 | #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) |
| 384 | |
| 385 | /* Global HWPARAMS9 Register */ |
| 386 | #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0) |
| 387 | #define DWC3_GHWPARAMS9_DEV_MST BIT(1) |
| 388 | |
| 389 | /* Global Frame Length Adjustment Register */ |
| 390 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) |
| 391 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f |
| 392 | #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) |
| 393 | #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) |
| 394 | #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) |
| 395 | |
| 396 | /* Global User Control Register*/ |
| 397 | #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 |
| 398 | #define DWC3_GUCTL_REFCLKPER_SEL 22 |
| 399 | |
| 400 | /* Global User Control Register 2 */ |
| 401 | #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) |
| 402 | |
| 403 | /* Global User Control Register 3 */ |
| 404 | #define DWC3_GUCTL3_SPLITDISABLE BIT(14) |
| 405 | |
| 406 | /* Device Configuration Register */ |
| 407 | #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ |
| 408 | |
| 409 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
| 410 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) |
| 411 | |
| 412 | #define DWC3_DCFG_SPEED_MASK (7 << 0) |
| 413 | #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
| 414 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
| 415 | #define DWC3_DCFG_HIGHSPEED (0 << 0) |
| 416 | #define DWC3_DCFG_FULLSPEED BIT(0) |
| 417 | |
| 418 | #define DWC3_DCFG_NUMP_SHIFT 17 |
| 419 | #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) |
| 420 | #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) |
| 421 | #define DWC3_DCFG_LPM_CAP BIT(22) |
| 422 | #define DWC3_DCFG_IGNSTRMPP BIT(23) |
| 423 | |
| 424 | /* Device Control Register */ |
| 425 | #define DWC3_DCTL_RUN_STOP BIT(31) |
| 426 | #define DWC3_DCTL_CSFTRST BIT(30) |
| 427 | #define DWC3_DCTL_LSFTRST BIT(29) |
| 428 | |
| 429 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) |
| 430 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
| 431 | |
| 432 | #define DWC3_DCTL_APPL1RES BIT(23) |
| 433 | |
| 434 | /* These apply for core versions 1.87a and earlier */ |
| 435 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) |
| 436 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) |
| 437 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) |
| 438 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) |
| 439 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) |
| 440 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) |
| 441 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) |
| 442 | |
| 443 | /* These apply for core versions 1.94a and later */ |
| 444 | #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) |
| 445 | |
| 446 | #define DWC3_DCTL_KEEP_CONNECT BIT(19) |
| 447 | #define DWC3_DCTL_L1_HIBER_EN BIT(18) |
| 448 | #define DWC3_DCTL_CRS BIT(17) |
| 449 | #define DWC3_DCTL_CSS BIT(16) |
| 450 | |
| 451 | #define DWC3_DCTL_INITU2ENA BIT(12) |
| 452 | #define DWC3_DCTL_ACCEPTU2ENA BIT(11) |
| 453 | #define DWC3_DCTL_INITU1ENA BIT(10) |
| 454 | #define DWC3_DCTL_ACCEPTU1ENA BIT(9) |
| 455 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
| 456 | |
| 457 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) |
| 458 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) |
| 459 | |
| 460 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) |
| 461 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) |
| 462 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) |
| 463 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) |
| 464 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) |
| 465 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) |
| 466 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) |
| 467 | |
| 468 | /* Device Event Enable Register */ |
| 469 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) |
| 470 | #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) |
| 471 | #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) |
| 472 | #define DWC3_DEVTEN_ERRTICERREN BIT(9) |
| 473 | #define DWC3_DEVTEN_SOFEN BIT(7) |
| 474 | #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6) |
| 475 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) |
| 476 | #define DWC3_DEVTEN_WKUPEVTEN BIT(4) |
| 477 | #define DWC3_DEVTEN_ULSTCNGEN BIT(3) |
| 478 | #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) |
| 479 | #define DWC3_DEVTEN_USBRSTEN BIT(1) |
| 480 | #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) |
| 481 | |
| 482 | #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ |
| 483 | |
| 484 | /* Device Status Register */ |
| 485 | #define DWC3_DSTS_DCNRD BIT(29) |
| 486 | |
| 487 | /* This applies for core versions 1.87a and earlier */ |
| 488 | #define DWC3_DSTS_PWRUPREQ BIT(24) |
| 489 | |
| 490 | /* These apply for core versions 1.94a and later */ |
| 491 | #define DWC3_DSTS_RSS BIT(25) |
| 492 | #define DWC3_DSTS_SSS BIT(24) |
| 493 | |
| 494 | #define DWC3_DSTS_COREIDLE BIT(23) |
| 495 | #define DWC3_DSTS_DEVCTRLHLT BIT(22) |
| 496 | |
| 497 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) |
| 498 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) |
| 499 | |
| 500 | #define DWC3_DSTS_RXFIFOEMPTY BIT(17) |
| 501 | |
| 502 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
| 503 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
| 504 | |
| 505 | #define DWC3_DSTS_CONNECTSPD (7 << 0) |
| 506 | |
| 507 | #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
| 508 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
| 509 | #define DWC3_DSTS_HIGHSPEED (0 << 0) |
| 510 | #define DWC3_DSTS_FULLSPEED BIT(0) |
| 511 | |
| 512 | /* Device Generic Command Register */ |
| 513 | #define DWC3_DGCMD_SET_LMP 0x01 |
| 514 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 |
| 515 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 |
| 516 | |
| 517 | /* These apply for core versions 1.94a and later */ |
| 518 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 |
| 519 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 |
| 520 | |
| 521 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
| 522 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a |
| 523 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c |
| 524 | #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d |
| 525 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 |
| 526 | |
| 527 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
| 528 | #define DWC3_DGCMD_CMDACT BIT(10) |
| 529 | #define DWC3_DGCMD_CMDIOC BIT(8) |
| 530 | |
| 531 | /* Device Generic Command Parameter Register */ |
| 532 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) |
| 533 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
| 534 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) |
| 535 | #define DWC3_DGCMDPAR_TX_FIFO BIT(5) |
| 536 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
| 537 | #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) |
| 538 | |
| 539 | /* Device Endpoint Command Register */ |
| 540 | #define DWC3_DEPCMD_PARAM_SHIFT 16 |
| 541 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
| 542 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
| 543 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
| 544 | #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) |
| 545 | #define DWC3_DEPCMD_CLEARPENDIN BIT(11) |
| 546 | #define DWC3_DEPCMD_CMDACT BIT(10) |
| 547 | #define DWC3_DEPCMD_CMDIOC BIT(8) |
| 548 | |
| 549 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) |
| 550 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) |
| 551 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) |
| 552 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) |
| 553 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) |
| 554 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) |
| 555 | /* This applies for core versions 1.90a and earlier */ |
| 556 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
| 557 | /* This applies for core versions 1.94a and later */ |
| 558 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) |
| 559 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
| 560 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) |
| 561 | |
| 562 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
| 563 | |
| 564 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
| 565 | #define DWC3_DALEPENA_EP(n) BIT(n) |
| 566 | |
| 567 | /* DWC_usb32 DCFG1 config */ |
| 568 | #define DWC3_DCFG1_DIS_MST_ENH BIT(1) |
| 569 | |
| 570 | #define DWC3_DEPCMD_TYPE_CONTROL 0 |
| 571 | #define DWC3_DEPCMD_TYPE_ISOC 1 |
| 572 | #define DWC3_DEPCMD_TYPE_BULK 2 |
| 573 | #define DWC3_DEPCMD_TYPE_INTR 3 |
| 574 | |
| 575 | #define DWC3_DEV_IMOD_COUNT_SHIFT 16 |
| 576 | #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) |
| 577 | #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 |
| 578 | #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) |
| 579 | |
| 580 | /* OTG Configuration Register */ |
| 581 | #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) |
| 582 | #define DWC3_OCFG_HIBDISMASK BIT(4) |
| 583 | #define DWC3_OCFG_SFTRSTMASK BIT(3) |
| 584 | #define DWC3_OCFG_OTGVERSION BIT(2) |
| 585 | #define DWC3_OCFG_HNPCAP BIT(1) |
| 586 | #define DWC3_OCFG_SRPCAP BIT(0) |
| 587 | |
| 588 | /* OTG CTL Register */ |
| 589 | #define DWC3_OCTL_OTG3GOERR BIT(7) |
| 590 | #define DWC3_OCTL_PERIMODE BIT(6) |
| 591 | #define DWC3_OCTL_PRTPWRCTL BIT(5) |
| 592 | #define DWC3_OCTL_HNPREQ BIT(4) |
| 593 | #define DWC3_OCTL_SESREQ BIT(3) |
| 594 | #define DWC3_OCTL_TERMSELIDPULSE BIT(2) |
| 595 | #define DWC3_OCTL_DEVSETHNPEN BIT(1) |
| 596 | #define DWC3_OCTL_HSTSETHNPEN BIT(0) |
| 597 | |
| 598 | /* OTG Event Register */ |
| 599 | #define DWC3_OEVT_DEVICEMODE BIT(31) |
| 600 | #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) |
| 601 | #define DWC3_OEVT_DEVRUNSTPSET BIT(26) |
| 602 | #define DWC3_OEVT_HIBENTRY BIT(25) |
| 603 | #define DWC3_OEVT_CONIDSTSCHNG BIT(24) |
| 604 | #define DWC3_OEVT_HRRCONFNOTIF BIT(23) |
| 605 | #define DWC3_OEVT_HRRINITNOTIF BIT(22) |
| 606 | #define DWC3_OEVT_ADEVIDLE BIT(21) |
| 607 | #define DWC3_OEVT_ADEVBHOSTEND BIT(20) |
| 608 | #define DWC3_OEVT_ADEVHOST BIT(19) |
| 609 | #define DWC3_OEVT_ADEVHNPCHNG BIT(18) |
| 610 | #define DWC3_OEVT_ADEVSRPDET BIT(17) |
| 611 | #define DWC3_OEVT_ADEVSESSENDDET BIT(16) |
| 612 | #define DWC3_OEVT_BDEVBHOSTEND BIT(11) |
| 613 | #define DWC3_OEVT_BDEVHNPCHNG BIT(10) |
| 614 | #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) |
| 615 | #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) |
| 616 | #define DWC3_OEVT_BSESSVLD BIT(3) |
| 617 | #define DWC3_OEVT_HSTNEGSTS BIT(2) |
| 618 | #define DWC3_OEVT_SESREQSTS BIT(1) |
| 619 | #define DWC3_OEVT_ERROR BIT(0) |
| 620 | |
| 621 | /* OTG Event Enable Register */ |
| 622 | #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) |
| 623 | #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) |
| 624 | #define DWC3_OEVTEN_HIBENTRYEN BIT(25) |
| 625 | #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) |
| 626 | #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) |
| 627 | #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) |
| 628 | #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) |
| 629 | #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) |
| 630 | #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) |
| 631 | #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) |
| 632 | #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) |
| 633 | #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) |
| 634 | #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) |
| 635 | #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) |
| 636 | #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) |
| 637 | #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) |
| 638 | |
| 639 | /* OTG Status Register */ |
| 640 | #define DWC3_OSTS_DEVRUNSTP BIT(13) |
| 641 | #define DWC3_OSTS_XHCIRUNSTP BIT(12) |
| 642 | #define DWC3_OSTS_PERIPHERALSTATE BIT(4) |
| 643 | #define DWC3_OSTS_XHCIPRTPOWER BIT(3) |
| 644 | #define DWC3_OSTS_BSESVLD BIT(2) |
| 645 | #define DWC3_OSTS_VBUSVLD BIT(1) |
| 646 | #define DWC3_OSTS_CONIDSTS BIT(0) |
| 647 | |
| 648 | /* Structures */ |
| 649 | |
| 650 | struct dwc3_trb; |
| 651 | |
| 652 | /** |
| 653 | * struct dwc3_event_buffer - Software event buffer representation |
| 654 | * @buf: _THE_ buffer |
| 655 | * @cache: The buffer cache used in the threaded interrupt |
| 656 | * @length: size of this buffer |
| 657 | * @lpos: event offset |
| 658 | * @count: cache of last read event count register |
| 659 | * @flags: flags related to this event buffer |
| 660 | * @dma: dma_addr_t |
| 661 | * @dwc: pointer to DWC controller |
| 662 | */ |
| 663 | struct dwc3_event_buffer { |
| 664 | void *buf; |
| 665 | void *cache; |
| 666 | unsigned int length; |
| 667 | unsigned int lpos; |
| 668 | unsigned int count; |
| 669 | unsigned int flags; |
| 670 | |
| 671 | #define DWC3_EVENT_PENDING BIT(0) |
| 672 | |
| 673 | dma_addr_t dma; |
| 674 | |
| 675 | struct dwc3 *dwc; |
| 676 | }; |
| 677 | |
| 678 | #define DWC3_EP_FLAG_STALLED BIT(0) |
| 679 | #define DWC3_EP_FLAG_WEDGED BIT(1) |
| 680 | |
| 681 | #define DWC3_EP_DIRECTION_TX true |
| 682 | #define DWC3_EP_DIRECTION_RX false |
| 683 | |
| 684 | #define DWC3_TRB_NUM 256 |
| 685 | |
| 686 | /** |
| 687 | * struct dwc3_ep - device side endpoint representation |
| 688 | * @endpoint: usb endpoint |
| 689 | * @cancelled_list: list of cancelled requests for this endpoint |
| 690 | * @pending_list: list of pending requests for this endpoint |
| 691 | * @started_list: list of started requests on this endpoint |
| 692 | * @regs: pointer to first endpoint register |
| 693 | * @trb_pool: array of transaction buffers |
| 694 | * @trb_pool_dma: dma address of @trb_pool |
| 695 | * @trb_enqueue: enqueue 'pointer' into TRB array |
| 696 | * @trb_dequeue: dequeue 'pointer' into TRB array |
| 697 | * @dwc: pointer to DWC controller |
| 698 | * @saved_state: ep state saved during hibernation |
| 699 | * @flags: endpoint flags (wedged, stalled, ...) |
| 700 | * @number: endpoint number (1 - 15) |
| 701 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK |
| 702 | * @resource_index: Resource transfer index |
| 703 | * @frame_number: set to the frame number we want this transfer to start (ISOC) |
| 704 | * @interval: the interval on which the ISOC transfer is started |
| 705 | * @name: a human readable name e.g. ep1out-bulk |
| 706 | * @direction: true for TX, false for RX |
| 707 | * @stream_capable: true when streams are enabled |
| 708 | * @combo_num: the test combination BIT[15:14] of the frame number to test |
| 709 | * isochronous START TRANSFER command failure workaround |
| 710 | * @start_cmd_status: the status of testing START TRANSFER command with |
| 711 | * combo_num = 'b00 |
| 712 | */ |
| 713 | struct dwc3_ep { |
| 714 | struct usb_ep endpoint; |
| 715 | struct list_head cancelled_list; |
| 716 | struct list_head pending_list; |
| 717 | struct list_head started_list; |
| 718 | |
| 719 | void __iomem *regs; |
| 720 | |
| 721 | struct dwc3_trb *trb_pool; |
| 722 | dma_addr_t trb_pool_dma; |
| 723 | struct dwc3 *dwc; |
| 724 | |
| 725 | u32 saved_state; |
| 726 | unsigned int flags; |
| 727 | #define DWC3_EP_ENABLED BIT(0) |
| 728 | #define DWC3_EP_STALL BIT(1) |
| 729 | #define DWC3_EP_WEDGE BIT(2) |
| 730 | #define DWC3_EP_TRANSFER_STARTED BIT(3) |
| 731 | #define DWC3_EP_END_TRANSFER_PENDING BIT(4) |
| 732 | #define DWC3_EP_PENDING_REQUEST BIT(5) |
| 733 | #define DWC3_EP_DELAY_START BIT(6) |
| 734 | #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) |
| 735 | #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) |
| 736 | #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) |
| 737 | #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) |
| 738 | #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) |
| 739 | #define DWC3_EP_TXFIFO_RESIZED BIT(12) |
| 740 | #define DWC3_EP_DELAY_STOP BIT(13) |
| 741 | |
| 742 | /* This last one is specific to EP0 */ |
| 743 | #define DWC3_EP0_DIR_IN BIT(31) |
| 744 | |
| 745 | /* |
| 746 | * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will |
| 747 | * use a u8 type here. If anybody decides to increase number of TRBs to |
| 748 | * anything larger than 256 - I can't see why people would want to do |
| 749 | * this though - then this type needs to be changed. |
| 750 | * |
| 751 | * By using u8 types we ensure that our % operator when incrementing |
| 752 | * enqueue and dequeue get optimized away by the compiler. |
| 753 | */ |
| 754 | u8 trb_enqueue; |
| 755 | u8 trb_dequeue; |
| 756 | |
| 757 | u8 number; |
| 758 | u8 type; |
| 759 | u8 resource_index; |
| 760 | u32 frame_number; |
| 761 | u32 interval; |
| 762 | |
| 763 | char name[20]; |
| 764 | |
| 765 | unsigned direction:1; |
| 766 | unsigned stream_capable:1; |
| 767 | |
| 768 | /* For isochronous START TRANSFER workaround only */ |
| 769 | u8 combo_num; |
| 770 | int start_cmd_status; |
| 771 | }; |
| 772 | |
| 773 | enum dwc3_phy { |
| 774 | DWC3_PHY_UNKNOWN = 0, |
| 775 | DWC3_PHY_USB3, |
| 776 | DWC3_PHY_USB2, |
| 777 | }; |
| 778 | |
| 779 | enum dwc3_ep0_next { |
| 780 | DWC3_EP0_UNKNOWN = 0, |
| 781 | DWC3_EP0_COMPLETE, |
| 782 | DWC3_EP0_NRDY_DATA, |
| 783 | DWC3_EP0_NRDY_STATUS, |
| 784 | }; |
| 785 | |
| 786 | enum dwc3_ep0_state { |
| 787 | EP0_UNCONNECTED = 0, |
| 788 | EP0_SETUP_PHASE, |
| 789 | EP0_DATA_PHASE, |
| 790 | EP0_STATUS_PHASE, |
| 791 | }; |
| 792 | |
| 793 | enum dwc3_link_state { |
| 794 | /* In SuperSpeed */ |
| 795 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ |
| 796 | DWC3_LINK_STATE_U1 = 0x01, |
| 797 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ |
| 798 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ |
| 799 | DWC3_LINK_STATE_SS_DIS = 0x04, |
| 800 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ |
| 801 | DWC3_LINK_STATE_SS_INACT = 0x06, |
| 802 | DWC3_LINK_STATE_POLL = 0x07, |
| 803 | DWC3_LINK_STATE_RECOV = 0x08, |
| 804 | DWC3_LINK_STATE_HRESET = 0x09, |
| 805 | DWC3_LINK_STATE_CMPLY = 0x0a, |
| 806 | DWC3_LINK_STATE_LPBK = 0x0b, |
| 807 | DWC3_LINK_STATE_RESET = 0x0e, |
| 808 | DWC3_LINK_STATE_RESUME = 0x0f, |
| 809 | DWC3_LINK_STATE_MASK = 0x0f, |
| 810 | }; |
| 811 | |
| 812 | /* TRB Length, PCM and Status */ |
| 813 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) |
| 814 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) |
| 815 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) |
| 816 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
| 817 | |
| 818 | #define DWC3_TRBSTS_OK 0 |
| 819 | #define DWC3_TRBSTS_MISSED_ISOC 1 |
| 820 | #define DWC3_TRBSTS_SETUP_PENDING 2 |
| 821 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
| 822 | |
| 823 | /* TRB Control */ |
| 824 | #define DWC3_TRB_CTRL_HWO BIT(0) |
| 825 | #define DWC3_TRB_CTRL_LST BIT(1) |
| 826 | #define DWC3_TRB_CTRL_CHN BIT(2) |
| 827 | #define DWC3_TRB_CTRL_CSP BIT(3) |
| 828 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
| 829 | #define DWC3_TRB_CTRL_ISP_IMI BIT(10) |
| 830 | #define DWC3_TRB_CTRL_IOC BIT(11) |
| 831 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
| 832 | #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) |
| 833 | |
| 834 | #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) |
| 835 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
| 836 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) |
| 837 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) |
| 838 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) |
| 839 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) |
| 840 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) |
| 841 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) |
| 842 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) |
| 843 | |
| 844 | /** |
| 845 | * struct dwc3_trb - transfer request block (hw format) |
| 846 | * @bpl: DW0-3 |
| 847 | * @bph: DW4-7 |
| 848 | * @size: DW8-B |
| 849 | * @ctrl: DWC-F |
| 850 | */ |
| 851 | struct dwc3_trb { |
| 852 | u32 bpl; |
| 853 | u32 bph; |
| 854 | u32 size; |
| 855 | u32 ctrl; |
| 856 | } __packed; |
| 857 | |
| 858 | /** |
| 859 | * struct dwc3_hwparams - copy of HWPARAMS registers |
| 860 | * @hwparams0: GHWPARAMS0 |
| 861 | * @hwparams1: GHWPARAMS1 |
| 862 | * @hwparams2: GHWPARAMS2 |
| 863 | * @hwparams3: GHWPARAMS3 |
| 864 | * @hwparams4: GHWPARAMS4 |
| 865 | * @hwparams5: GHWPARAMS5 |
| 866 | * @hwparams6: GHWPARAMS6 |
| 867 | * @hwparams7: GHWPARAMS7 |
| 868 | * @hwparams8: GHWPARAMS8 |
| 869 | * @hwparams9: GHWPARAMS9 |
| 870 | */ |
| 871 | struct dwc3_hwparams { |
| 872 | u32 hwparams0; |
| 873 | u32 hwparams1; |
| 874 | u32 hwparams2; |
| 875 | u32 hwparams3; |
| 876 | u32 hwparams4; |
| 877 | u32 hwparams5; |
| 878 | u32 hwparams6; |
| 879 | u32 hwparams7; |
| 880 | u32 hwparams8; |
| 881 | u32 hwparams9; |
| 882 | }; |
| 883 | |
| 884 | /* HWPARAMS0 */ |
| 885 | #define DWC3_MODE(n) ((n) & 0x7) |
| 886 | |
| 887 | /* HWPARAMS1 */ |
| 888 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
| 889 | |
| 890 | /* HWPARAMS3 */ |
| 891 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) |
| 892 | #define DWC3_NUM_EPS_MASK (0x3f << 12) |
| 893 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ |
| 894 | (DWC3_NUM_EPS_MASK)) >> 12) |
| 895 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ |
| 896 | (DWC3_NUM_IN_EPS_MASK)) >> 18) |
| 897 | |
| 898 | /* HWPARAMS7 */ |
| 899 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) |
| 900 | |
| 901 | /* HWPARAMS9 */ |
| 902 | #define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \ |
| 903 | DWC3_GHWPARAMS9_DEV_MST)) |
| 904 | |
| 905 | /** |
| 906 | * struct dwc3_request - representation of a transfer request |
| 907 | * @request: struct usb_request to be transferred |
| 908 | * @list: a list_head used for request queueing |
| 909 | * @dep: struct dwc3_ep owning this request |
| 910 | * @sg: pointer to first incomplete sg |
| 911 | * @start_sg: pointer to the sg which should be queued next |
| 912 | * @num_pending_sgs: counter to pending sgs |
| 913 | * @num_queued_sgs: counter to the number of sgs which already got queued |
| 914 | * @remaining: amount of data remaining |
| 915 | * @status: internal dwc3 request status tracking |
| 916 | * @epnum: endpoint number to which this request refers |
| 917 | * @trb: pointer to struct dwc3_trb |
| 918 | * @trb_dma: DMA address of @trb |
| 919 | * @num_trbs: number of TRBs used by this request |
| 920 | * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP |
| 921 | * or unaligned OUT) |
| 922 | * @direction: IN or OUT direction flag |
| 923 | * @mapped: true when request has been dma-mapped |
| 924 | */ |
| 925 | struct dwc3_request { |
| 926 | struct usb_request request; |
| 927 | struct list_head list; |
| 928 | struct dwc3_ep *dep; |
| 929 | struct scatterlist *sg; |
| 930 | struct scatterlist *start_sg; |
| 931 | |
| 932 | unsigned int num_pending_sgs; |
| 933 | unsigned int num_queued_sgs; |
| 934 | unsigned int remaining; |
| 935 | |
| 936 | unsigned int status; |
| 937 | #define DWC3_REQUEST_STATUS_QUEUED 0 |
| 938 | #define DWC3_REQUEST_STATUS_STARTED 1 |
| 939 | #define DWC3_REQUEST_STATUS_DISCONNECTED 2 |
| 940 | #define DWC3_REQUEST_STATUS_DEQUEUED 3 |
| 941 | #define DWC3_REQUEST_STATUS_STALLED 4 |
| 942 | #define DWC3_REQUEST_STATUS_COMPLETED 5 |
| 943 | #define DWC3_REQUEST_STATUS_UNKNOWN -1 |
| 944 | |
| 945 | u8 epnum; |
| 946 | struct dwc3_trb *trb; |
| 947 | dma_addr_t trb_dma; |
| 948 | |
| 949 | unsigned int num_trbs; |
| 950 | |
| 951 | unsigned int needs_extra_trb:1; |
| 952 | unsigned int direction:1; |
| 953 | unsigned int mapped:1; |
| 954 | }; |
| 955 | |
| 956 | /* |
| 957 | * struct dwc3_scratchpad_array - hibernation scratchpad array |
| 958 | * (format defined by hw) |
| 959 | */ |
| 960 | struct dwc3_scratchpad_array { |
| 961 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; |
| 962 | }; |
| 963 | |
| 964 | /** |
| 965 | * struct dwc3 - representation of our controller |
| 966 | * @drd_work: workqueue used for role swapping |
| 967 | * @ep0_trb: trb which is used for the ctrl_req |
| 968 | * @bounce: address of bounce buffer |
| 969 | * @scratchbuf: address of scratch buffer |
| 970 | * @setup_buf: used while precessing STD USB requests |
| 971 | * @ep0_trb_addr: dma address of @ep0_trb |
| 972 | * @bounce_addr: dma address of @bounce |
| 973 | * @ep0_usb_req: dummy req used while handling STD USB requests |
| 974 | * @scratch_addr: dma address of scratchbuf |
| 975 | * @ep0_in_setup: one control transfer is completed and enter setup phase |
| 976 | * @lock: for synchronizing |
| 977 | * @mutex: for mode switching |
| 978 | * @dev: pointer to our struct device |
| 979 | * @sysdev: pointer to the DMA-capable device |
| 980 | * @xhci: pointer to our xHCI child |
| 981 | * @xhci_resources: struct resources for our @xhci child |
| 982 | * @ev_buf: struct dwc3_event_buffer pointer |
| 983 | * @eps: endpoint array |
| 984 | * @gadget: device side representation of the peripheral controller |
| 985 | * @gadget_driver: pointer to the gadget driver |
| 986 | * @bus_clk: clock for accessing the registers |
| 987 | * @ref_clk: reference clock |
| 988 | * @susp_clk: clock used when the SS phy is in low power (S3) state |
| 989 | * @reset: reset control |
| 990 | * @regs: base address for our registers |
| 991 | * @regs_size: address space size |
| 992 | * @fladj: frame length adjustment |
| 993 | * @ref_clk_per: reference clock period configuration |
| 994 | * @irq_gadget: peripheral controller's IRQ number |
| 995 | * @otg_irq: IRQ number for OTG IRQs |
| 996 | * @current_otg_role: current role of operation while using the OTG block |
| 997 | * @desired_otg_role: desired role of operation while using the OTG block |
| 998 | * @otg_restart_host: flag that OTG controller needs to restart host |
| 999 | * @nr_scratch: number of scratch buffers |
| 1000 | * @u1u2: only used on revisions <1.83a for workaround |
| 1001 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
| 1002 | * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count |
| 1003 | * @gadget_max_speed: maximum gadget speed requested |
| 1004 | * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling |
| 1005 | * rate and lane count. |
| 1006 | * @ip: controller's ID |
| 1007 | * @revision: controller's version of an IP |
| 1008 | * @version_type: VERSIONTYPE register contents, a sub release of a revision |
| 1009 | * @dr_mode: requested mode of operation |
| 1010 | * @current_dr_role: current role of operation when in dual-role mode |
| 1011 | * @desired_dr_role: desired role of operation when in dual-role mode |
| 1012 | * @edev: extcon handle |
| 1013 | * @edev_nb: extcon notifier |
| 1014 | * @hsphy_mode: UTMI phy mode, one of following: |
| 1015 | * - USBPHY_INTERFACE_MODE_UTMI |
| 1016 | * - USBPHY_INTERFACE_MODE_UTMIW |
| 1017 | * @role_sw: usb_role_switch handle |
| 1018 | * @role_switch_default_mode: default operation mode of controller while |
| 1019 | * usb role is USB_ROLE_NONE. |
| 1020 | * @usb_psy: pointer to power supply interface. |
| 1021 | * @usb2_phy: pointer to USB2 PHY |
| 1022 | * @usb3_phy: pointer to USB3 PHY |
| 1023 | * @usb2_generic_phy: pointer to USB2 PHY |
| 1024 | * @usb3_generic_phy: pointer to USB3 PHY |
| 1025 | * @phys_ready: flag to indicate that PHYs are ready |
| 1026 | * @ulpi: pointer to ulpi interface |
| 1027 | * @ulpi_ready: flag to indicate that ULPI is initialized |
| 1028 | * @u2sel: parameter from Set SEL request. |
| 1029 | * @u2pel: parameter from Set SEL request. |
| 1030 | * @u1sel: parameter from Set SEL request. |
| 1031 | * @u1pel: parameter from Set SEL request. |
| 1032 | * @num_eps: number of endpoints |
| 1033 | * @ep0_next_event: hold the next expected event |
| 1034 | * @ep0state: state of endpoint zero |
| 1035 | * @link_state: link state |
| 1036 | * @speed: device speed (super, high, full, low) |
| 1037 | * @hwparams: copy of hwparams registers |
| 1038 | * @regset: debugfs pointer to regdump file |
| 1039 | * @dbg_lsp_select: current debug lsp mux register selection |
| 1040 | * @test_mode: true when we're entering a USB test mode |
| 1041 | * @test_mode_nr: test feature selector |
| 1042 | * @lpm_nyet_threshold: LPM NYET response threshold |
| 1043 | * @hird_threshold: HIRD threshold |
| 1044 | * @rx_thr_num_pkt_prd: periodic ESS receive packet count |
| 1045 | * @rx_max_burst_prd: max periodic ESS receive burst size |
| 1046 | * @tx_thr_num_pkt_prd: periodic ESS transmit packet count |
| 1047 | * @tx_max_burst_prd: max periodic ESS transmit burst size |
| 1048 | * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize |
| 1049 | * @hsphy_interface: "utmi" or "ulpi" |
| 1050 | * @connected: true when we're connected to a host, false otherwise |
| 1051 | * @softconnect: true when gadget connect is called, false when disconnect runs |
| 1052 | * @delayed_status: true when gadget driver asks for delayed status |
| 1053 | * @ep0_bounced: true when we used bounce buffer |
| 1054 | * @ep0_expect_in: true when we expect a DATA IN transfer |
| 1055 | * @has_hibernation: true when dwc3 was configured with Hibernation |
| 1056 | * @sysdev_is_parent: true when dwc3 device has a parent driver |
| 1057 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
| 1058 | * there's now way for software to detect this in runtime. |
| 1059 | * @is_utmi_l1_suspend: the core asserts output signal |
| 1060 | * 0 - utmi_sleep_n |
| 1061 | * 1 - utmi_l1_suspend_n |
| 1062 | * @is_fpga: true when we are using the FPGA board |
| 1063 | * @pending_events: true when we have pending IRQs to be handled |
| 1064 | * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints |
| 1065 | * @pullups_connected: true when Run/Stop bit is set |
| 1066 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
| 1067 | * @three_stage_setup: set if we perform a three phase setup |
| 1068 | * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is |
| 1069 | * not needed for DWC_usb31 version 1.70a-ea06 and below |
| 1070 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
| 1071 | * @usb2_lpm_disable: set to disable usb2 lpm for host |
| 1072 | * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget |
| 1073 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
| 1074 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
| 1075 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
| 1076 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
| 1077 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
| 1078 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
| 1079 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
| 1080 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
| 1081 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
| 1082 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
| 1083 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
| 1084 | * disabling the suspend signal to the PHY. |
| 1085 | * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. |
| 1086 | * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. |
| 1087 | * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 |
| 1088 | * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists |
| 1089 | * in GUSB2PHYCFG, specify that USB2 PHY doesn't |
| 1090 | * provide a free-running PHY clock. |
| 1091 | * @dis_del_phy_power_chg_quirk: set if we disable delay phy power |
| 1092 | * change quirk. |
| 1093 | * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate |
| 1094 | * check during HS transmit. |
| 1095 | * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed |
| 1096 | * instances in park mode. |
| 1097 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
| 1098 | * @tx_de_emphasis: Tx de-emphasis value |
| 1099 | * 0 - -6dB de-emphasis |
| 1100 | * 1 - -3.5dB de-emphasis |
| 1101 | * 2 - No de-emphasis |
| 1102 | * 3 - Reserved |
| 1103 | * @dis_metastability_quirk: set to disable metastability quirk. |
| 1104 | * @dis_split_quirk: set to disable split boundary. |
| 1105 | * @imod_interval: set the interrupt moderation interval in 250ns |
| 1106 | * increments or 0 to disable. |
| 1107 | * @max_cfg_eps: current max number of IN eps used across all USB configs. |
| 1108 | * @last_fifo_depth: last fifo depth used to determine next fifo ram start |
| 1109 | * address. |
| 1110 | * @num_ep_resized: carries the current number endpoints which have had its tx |
| 1111 | * fifo resized. |
| 1112 | */ |
| 1113 | struct dwc3 { |
| 1114 | struct work_struct drd_work; |
| 1115 | struct dwc3_trb *ep0_trb; |
| 1116 | void *bounce; |
| 1117 | void *scratchbuf; |
| 1118 | u8 *setup_buf; |
| 1119 | dma_addr_t ep0_trb_addr; |
| 1120 | dma_addr_t bounce_addr; |
| 1121 | dma_addr_t scratch_addr; |
| 1122 | struct dwc3_request ep0_usb_req; |
| 1123 | struct completion ep0_in_setup; |
| 1124 | |
| 1125 | /* device lock */ |
| 1126 | spinlock_t lock; |
| 1127 | |
| 1128 | /* mode switching lock */ |
| 1129 | struct mutex mutex; |
| 1130 | |
| 1131 | struct device *dev; |
| 1132 | struct device *sysdev; |
| 1133 | |
| 1134 | struct platform_device *xhci; |
| 1135 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
| 1136 | |
| 1137 | struct dwc3_event_buffer *ev_buf; |
| 1138 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
| 1139 | |
| 1140 | struct usb_gadget *gadget; |
| 1141 | struct usb_gadget_driver *gadget_driver; |
| 1142 | |
| 1143 | struct clk *bus_clk; |
| 1144 | struct clk *ref_clk; |
| 1145 | struct clk *susp_clk; |
| 1146 | |
| 1147 | struct reset_control *reset; |
| 1148 | |
| 1149 | struct usb_phy *usb2_phy; |
| 1150 | struct usb_phy *usb3_phy; |
| 1151 | |
| 1152 | struct phy *usb2_generic_phy; |
| 1153 | struct phy *usb3_generic_phy; |
| 1154 | |
| 1155 | bool phys_ready; |
| 1156 | |
| 1157 | struct ulpi *ulpi; |
| 1158 | bool ulpi_ready; |
| 1159 | |
| 1160 | void __iomem *regs; |
| 1161 | size_t regs_size; |
| 1162 | |
| 1163 | enum usb_dr_mode dr_mode; |
| 1164 | u32 current_dr_role; |
| 1165 | u32 desired_dr_role; |
| 1166 | struct extcon_dev *edev; |
| 1167 | struct notifier_block edev_nb; |
| 1168 | enum usb_phy_interface hsphy_mode; |
| 1169 | struct usb_role_switch *role_sw; |
| 1170 | enum usb_dr_mode role_switch_default_mode; |
| 1171 | |
| 1172 | struct power_supply *usb_psy; |
| 1173 | |
| 1174 | u32 fladj; |
| 1175 | u32 ref_clk_per; |
| 1176 | u32 irq_gadget; |
| 1177 | u32 otg_irq; |
| 1178 | u32 current_otg_role; |
| 1179 | u32 desired_otg_role; |
| 1180 | bool otg_restart_host; |
| 1181 | u32 nr_scratch; |
| 1182 | u32 u1u2; |
| 1183 | u32 maximum_speed; |
| 1184 | u32 gadget_max_speed; |
| 1185 | enum usb_ssp_rate max_ssp_rate; |
| 1186 | enum usb_ssp_rate gadget_ssp_rate; |
| 1187 | |
| 1188 | u32 ip; |
| 1189 | |
| 1190 | #define DWC3_IP 0x5533 |
| 1191 | #define DWC31_IP 0x3331 |
| 1192 | #define DWC32_IP 0x3332 |
| 1193 | |
| 1194 | u32 revision; |
| 1195 | |
| 1196 | #define DWC3_REVISION_ANY 0x0 |
| 1197 | #define DWC3_REVISION_173A 0x5533173a |
| 1198 | #define DWC3_REVISION_175A 0x5533175a |
| 1199 | #define DWC3_REVISION_180A 0x5533180a |
| 1200 | #define DWC3_REVISION_183A 0x5533183a |
| 1201 | #define DWC3_REVISION_185A 0x5533185a |
| 1202 | #define DWC3_REVISION_187A 0x5533187a |
| 1203 | #define DWC3_REVISION_188A 0x5533188a |
| 1204 | #define DWC3_REVISION_190A 0x5533190a |
| 1205 | #define DWC3_REVISION_194A 0x5533194a |
| 1206 | #define DWC3_REVISION_200A 0x5533200a |
| 1207 | #define DWC3_REVISION_202A 0x5533202a |
| 1208 | #define DWC3_REVISION_210A 0x5533210a |
| 1209 | #define DWC3_REVISION_220A 0x5533220a |
| 1210 | #define DWC3_REVISION_230A 0x5533230a |
| 1211 | #define DWC3_REVISION_240A 0x5533240a |
| 1212 | #define DWC3_REVISION_250A 0x5533250a |
| 1213 | #define DWC3_REVISION_260A 0x5533260a |
| 1214 | #define DWC3_REVISION_270A 0x5533270a |
| 1215 | #define DWC3_REVISION_280A 0x5533280a |
| 1216 | #define DWC3_REVISION_290A 0x5533290a |
| 1217 | #define DWC3_REVISION_300A 0x5533300a |
| 1218 | #define DWC3_REVISION_310A 0x5533310a |
| 1219 | #define DWC3_REVISION_330A 0x5533330a |
| 1220 | |
| 1221 | #define DWC31_REVISION_ANY 0x0 |
| 1222 | #define DWC31_REVISION_110A 0x3131302a |
| 1223 | #define DWC31_REVISION_120A 0x3132302a |
| 1224 | #define DWC31_REVISION_160A 0x3136302a |
| 1225 | #define DWC31_REVISION_170A 0x3137302a |
| 1226 | #define DWC31_REVISION_180A 0x3138302a |
| 1227 | #define DWC31_REVISION_190A 0x3139302a |
| 1228 | |
| 1229 | #define DWC32_REVISION_ANY 0x0 |
| 1230 | #define DWC32_REVISION_100A 0x3130302a |
| 1231 | |
| 1232 | u32 version_type; |
| 1233 | |
| 1234 | #define DWC31_VERSIONTYPE_ANY 0x0 |
| 1235 | #define DWC31_VERSIONTYPE_EA01 0x65613031 |
| 1236 | #define DWC31_VERSIONTYPE_EA02 0x65613032 |
| 1237 | #define DWC31_VERSIONTYPE_EA03 0x65613033 |
| 1238 | #define DWC31_VERSIONTYPE_EA04 0x65613034 |
| 1239 | #define DWC31_VERSIONTYPE_EA05 0x65613035 |
| 1240 | #define DWC31_VERSIONTYPE_EA06 0x65613036 |
| 1241 | |
| 1242 | enum dwc3_ep0_next ep0_next_event; |
| 1243 | enum dwc3_ep0_state ep0state; |
| 1244 | enum dwc3_link_state link_state; |
| 1245 | |
| 1246 | u16 u2sel; |
| 1247 | u16 u2pel; |
| 1248 | u8 u1sel; |
| 1249 | u8 u1pel; |
| 1250 | |
| 1251 | u8 speed; |
| 1252 | |
| 1253 | u8 num_eps; |
| 1254 | |
| 1255 | struct dwc3_hwparams hwparams; |
| 1256 | struct debugfs_regset32 *regset; |
| 1257 | |
| 1258 | u32 dbg_lsp_select; |
| 1259 | |
| 1260 | u8 test_mode; |
| 1261 | u8 test_mode_nr; |
| 1262 | u8 lpm_nyet_threshold; |
| 1263 | u8 hird_threshold; |
| 1264 | u8 rx_thr_num_pkt_prd; |
| 1265 | u8 rx_max_burst_prd; |
| 1266 | u8 tx_thr_num_pkt_prd; |
| 1267 | u8 tx_max_burst_prd; |
| 1268 | u8 tx_fifo_resize_max_num; |
| 1269 | |
| 1270 | const char *hsphy_interface; |
| 1271 | |
| 1272 | unsigned connected:1; |
| 1273 | unsigned softconnect:1; |
| 1274 | unsigned delayed_status:1; |
| 1275 | unsigned ep0_bounced:1; |
| 1276 | unsigned ep0_expect_in:1; |
| 1277 | unsigned has_hibernation:1; |
| 1278 | unsigned sysdev_is_parent:1; |
| 1279 | unsigned has_lpm_erratum:1; |
| 1280 | unsigned is_utmi_l1_suspend:1; |
| 1281 | unsigned is_fpga:1; |
| 1282 | unsigned pending_events:1; |
| 1283 | unsigned do_fifo_resize:1; |
| 1284 | unsigned pullups_connected:1; |
| 1285 | unsigned setup_packet_pending:1; |
| 1286 | unsigned three_stage_setup:1; |
| 1287 | unsigned dis_start_transfer_quirk:1; |
| 1288 | unsigned usb3_lpm_capable:1; |
| 1289 | unsigned usb2_lpm_disable:1; |
| 1290 | unsigned usb2_gadget_lpm_disable:1; |
| 1291 | |
| 1292 | unsigned disable_scramble_quirk:1; |
| 1293 | unsigned u2exit_lfps_quirk:1; |
| 1294 | unsigned u2ss_inp3_quirk:1; |
| 1295 | unsigned req_p1p2p3_quirk:1; |
| 1296 | unsigned del_p1p2p3_quirk:1; |
| 1297 | unsigned del_phy_power_chg_quirk:1; |
| 1298 | unsigned lfps_filter_quirk:1; |
| 1299 | unsigned rx_detect_poll_quirk:1; |
| 1300 | unsigned dis_u3_susphy_quirk:1; |
| 1301 | unsigned dis_u2_susphy_quirk:1; |
| 1302 | unsigned dis_enblslpm_quirk:1; |
| 1303 | unsigned dis_u1_entry_quirk:1; |
| 1304 | unsigned dis_u2_entry_quirk:1; |
| 1305 | unsigned dis_rxdet_inp3_quirk:1; |
| 1306 | unsigned dis_u2_freeclk_exists_quirk:1; |
| 1307 | unsigned dis_del_phy_power_chg_quirk:1; |
| 1308 | unsigned dis_tx_ipgap_linecheck_quirk:1; |
| 1309 | unsigned parkmode_disable_ss_quirk:1; |
| 1310 | |
| 1311 | unsigned tx_de_emphasis_quirk:1; |
| 1312 | unsigned tx_de_emphasis:2; |
| 1313 | |
| 1314 | unsigned dis_metastability_quirk:1; |
| 1315 | |
| 1316 | unsigned dis_split_quirk:1; |
| 1317 | unsigned async_callbacks:1; |
| 1318 | |
| 1319 | u16 imod_interval; |
| 1320 | |
| 1321 | int max_cfg_eps; |
| 1322 | int last_fifo_depth; |
| 1323 | int num_ep_resized; |
| 1324 | }; |
| 1325 | |
| 1326 | #define INCRX_BURST_MODE 0 |
| 1327 | #define INCRX_UNDEF_LENGTH_BURST_MODE 1 |
| 1328 | |
| 1329 | #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) |
| 1330 | |
| 1331 | /* -------------------------------------------------------------------------- */ |
| 1332 | |
| 1333 | struct dwc3_event_type { |
| 1334 | u32 is_devspec:1; |
| 1335 | u32 type:7; |
| 1336 | u32 reserved8_31:24; |
| 1337 | } __packed; |
| 1338 | |
| 1339 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 |
| 1340 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 |
| 1341 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 |
| 1342 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 |
| 1343 | #define DWC3_DEPEVT_STREAMEVT 0x06 |
| 1344 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 |
| 1345 | |
| 1346 | /** |
| 1347 | * struct dwc3_event_depevt - Device Endpoint Events |
| 1348 | * @one_bit: indicates this is an endpoint event (not used) |
| 1349 | * @endpoint_number: number of the endpoint |
| 1350 | * @endpoint_event: The event we have: |
| 1351 | * 0x00 - Reserved |
| 1352 | * 0x01 - XferComplete |
| 1353 | * 0x02 - XferInProgress |
| 1354 | * 0x03 - XferNotReady |
| 1355 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) |
| 1356 | * 0x05 - Reserved |
| 1357 | * 0x06 - StreamEvt |
| 1358 | * 0x07 - EPCmdCmplt |
| 1359 | * @reserved11_10: Reserved, don't use. |
| 1360 | * @status: Indicates the status of the event. Refer to databook for |
| 1361 | * more information. |
| 1362 | * @parameters: Parameters of the current event. Refer to databook for |
| 1363 | * more information. |
| 1364 | */ |
| 1365 | struct dwc3_event_depevt { |
| 1366 | u32 one_bit:1; |
| 1367 | u32 endpoint_number:5; |
| 1368 | u32 endpoint_event:4; |
| 1369 | u32 reserved11_10:2; |
| 1370 | u32 status:4; |
| 1371 | |
| 1372 | /* Within XferNotReady */ |
| 1373 | #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) |
| 1374 | |
| 1375 | /* Within XferComplete or XferInProgress */ |
| 1376 | #define DEPEVT_STATUS_BUSERR BIT(0) |
| 1377 | #define DEPEVT_STATUS_SHORT BIT(1) |
| 1378 | #define DEPEVT_STATUS_IOC BIT(2) |
| 1379 | #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ |
| 1380 | #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ |
| 1381 | |
| 1382 | /* Stream event only */ |
| 1383 | #define DEPEVT_STREAMEVT_FOUND 1 |
| 1384 | #define DEPEVT_STREAMEVT_NOTFOUND 2 |
| 1385 | |
| 1386 | /* Stream event parameter */ |
| 1387 | #define DEPEVT_STREAM_PRIME 0xfffe |
| 1388 | #define DEPEVT_STREAM_NOSTREAM 0x0 |
| 1389 | |
| 1390 | /* Control-only Status */ |
| 1391 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
| 1392 | #define DEPEVT_STATUS_CONTROL_STATUS 2 |
| 1393 | #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) |
| 1394 | |
| 1395 | /* In response to Start Transfer */ |
| 1396 | #define DEPEVT_TRANSFER_NO_RESOURCE 1 |
| 1397 | #define DEPEVT_TRANSFER_BUS_EXPIRY 2 |
| 1398 | |
| 1399 | u32 parameters:16; |
| 1400 | |
| 1401 | /* For Command Complete Events */ |
| 1402 | #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) |
| 1403 | } __packed; |
| 1404 | |
| 1405 | /** |
| 1406 | * struct dwc3_event_devt - Device Events |
| 1407 | * @one_bit: indicates this is a non-endpoint event (not used) |
| 1408 | * @device_event: indicates it's a device event. Should read as 0x00 |
| 1409 | * @type: indicates the type of device event. |
| 1410 | * 0 - DisconnEvt |
| 1411 | * 1 - USBRst |
| 1412 | * 2 - ConnectDone |
| 1413 | * 3 - ULStChng |
| 1414 | * 4 - WkUpEvt |
| 1415 | * 5 - Reserved |
| 1416 | * 6 - Suspend (EOPF on revisions 2.10a and prior) |
| 1417 | * 7 - SOF |
| 1418 | * 8 - Reserved |
| 1419 | * 9 - ErrticErr |
| 1420 | * 10 - CmdCmplt |
| 1421 | * 11 - EvntOverflow |
| 1422 | * 12 - VndrDevTstRcved |
| 1423 | * @reserved15_12: Reserved, not used |
| 1424 | * @event_info: Information about this event |
| 1425 | * @reserved31_25: Reserved, not used |
| 1426 | */ |
| 1427 | struct dwc3_event_devt { |
| 1428 | u32 one_bit:1; |
| 1429 | u32 device_event:7; |
| 1430 | u32 type:4; |
| 1431 | u32 reserved15_12:4; |
| 1432 | u32 event_info:9; |
| 1433 | u32 reserved31_25:7; |
| 1434 | } __packed; |
| 1435 | |
| 1436 | /** |
| 1437 | * struct dwc3_event_gevt - Other Core Events |
| 1438 | * @one_bit: indicates this is a non-endpoint event (not used) |
| 1439 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. |
| 1440 | * @phy_port_number: self-explanatory |
| 1441 | * @reserved31_12: Reserved, not used. |
| 1442 | */ |
| 1443 | struct dwc3_event_gevt { |
| 1444 | u32 one_bit:1; |
| 1445 | u32 device_event:7; |
| 1446 | u32 phy_port_number:4; |
| 1447 | u32 reserved31_12:20; |
| 1448 | } __packed; |
| 1449 | |
| 1450 | /** |
| 1451 | * union dwc3_event - representation of Event Buffer contents |
| 1452 | * @raw: raw 32-bit event |
| 1453 | * @type: the type of the event |
| 1454 | * @depevt: Device Endpoint Event |
| 1455 | * @devt: Device Event |
| 1456 | * @gevt: Global Event |
| 1457 | */ |
| 1458 | union dwc3_event { |
| 1459 | u32 raw; |
| 1460 | struct dwc3_event_type type; |
| 1461 | struct dwc3_event_depevt depevt; |
| 1462 | struct dwc3_event_devt devt; |
| 1463 | struct dwc3_event_gevt gevt; |
| 1464 | }; |
| 1465 | |
| 1466 | /** |
| 1467 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command |
| 1468 | * parameters |
| 1469 | * @param2: third parameter |
| 1470 | * @param1: second parameter |
| 1471 | * @param0: first parameter |
| 1472 | */ |
| 1473 | struct dwc3_gadget_ep_cmd_params { |
| 1474 | u32 param2; |
| 1475 | u32 param1; |
| 1476 | u32 param0; |
| 1477 | }; |
| 1478 | |
| 1479 | /* |
| 1480 | * DWC3 Features to be used as Driver Data |
| 1481 | */ |
| 1482 | |
| 1483 | #define DWC3_HAS_PERIPHERAL BIT(0) |
| 1484 | #define DWC3_HAS_XHCI BIT(1) |
| 1485 | #define DWC3_HAS_OTG BIT(3) |
| 1486 | |
| 1487 | /* prototypes */ |
| 1488 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); |
| 1489 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
| 1490 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); |
| 1491 | |
| 1492 | #define DWC3_IP_IS(_ip) \ |
| 1493 | (dwc->ip == _ip##_IP) |
| 1494 | |
| 1495 | #define DWC3_VER_IS(_ip, _ver) \ |
| 1496 | (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) |
| 1497 | |
| 1498 | #define DWC3_VER_IS_PRIOR(_ip, _ver) \ |
| 1499 | (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) |
| 1500 | |
| 1501 | #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ |
| 1502 | (DWC3_IP_IS(_ip) && \ |
| 1503 | dwc->revision >= _ip##_REVISION_##_from && \ |
| 1504 | (!(_ip##_REVISION_##_to) || \ |
| 1505 | dwc->revision <= _ip##_REVISION_##_to)) |
| 1506 | |
| 1507 | #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ |
| 1508 | (DWC3_VER_IS(_ip, _ver) && \ |
| 1509 | dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ |
| 1510 | (!(_ip##_VERSIONTYPE_##_to) || \ |
| 1511 | dwc->version_type <= _ip##_VERSIONTYPE_##_to)) |
| 1512 | |
| 1513 | /** |
| 1514 | * dwc3_mdwidth - get MDWIDTH value in bits |
| 1515 | * @dwc: pointer to our context structure |
| 1516 | * |
| 1517 | * Return MDWIDTH configuration value in bits. |
| 1518 | */ |
| 1519 | static inline u32 dwc3_mdwidth(struct dwc3 *dwc) |
| 1520 | { |
| 1521 | u32 mdwidth; |
| 1522 | |
| 1523 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); |
| 1524 | if (DWC3_IP_IS(DWC32)) |
| 1525 | mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); |
| 1526 | |
| 1527 | return mdwidth; |
| 1528 | } |
| 1529 | |
| 1530 | bool dwc3_has_imod(struct dwc3 *dwc); |
| 1531 | |
| 1532 | int dwc3_event_buffers_setup(struct dwc3 *dwc); |
| 1533 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc); |
| 1534 | |
| 1535 | int dwc3_core_soft_reset(struct dwc3 *dwc); |
| 1536 | |
| 1537 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
| 1538 | int dwc3_host_init(struct dwc3 *dwc); |
| 1539 | void dwc3_host_exit(struct dwc3 *dwc); |
| 1540 | #else |
| 1541 | static inline int dwc3_host_init(struct dwc3 *dwc) |
| 1542 | { return 0; } |
| 1543 | static inline void dwc3_host_exit(struct dwc3 *dwc) |
| 1544 | { } |
| 1545 | #endif |
| 1546 | |
| 1547 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
| 1548 | int dwc3_gadget_init(struct dwc3 *dwc); |
| 1549 | void dwc3_gadget_exit(struct dwc3 *dwc); |
| 1550 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
| 1551 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); |
| 1552 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); |
| 1553 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
| 1554 | struct dwc3_gadget_ep_cmd_params *params); |
| 1555 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
| 1556 | u32 param); |
| 1557 | void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); |
| 1558 | #else |
| 1559 | static inline int dwc3_gadget_init(struct dwc3 *dwc) |
| 1560 | { return 0; } |
| 1561 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) |
| 1562 | { } |
| 1563 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
| 1564 | { return 0; } |
| 1565 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) |
| 1566 | { return 0; } |
| 1567 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, |
| 1568 | enum dwc3_link_state state) |
| 1569 | { return 0; } |
| 1570 | |
| 1571 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
| 1572 | struct dwc3_gadget_ep_cmd_params *params) |
| 1573 | { return 0; } |
| 1574 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, |
| 1575 | int cmd, u32 param) |
| 1576 | { return 0; } |
| 1577 | static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) |
| 1578 | { } |
| 1579 | #endif |
| 1580 | |
| 1581 | #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
| 1582 | int dwc3_drd_init(struct dwc3 *dwc); |
| 1583 | void dwc3_drd_exit(struct dwc3 *dwc); |
| 1584 | void dwc3_otg_init(struct dwc3 *dwc); |
| 1585 | void dwc3_otg_exit(struct dwc3 *dwc); |
| 1586 | void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); |
| 1587 | void dwc3_otg_host_init(struct dwc3 *dwc); |
| 1588 | #else |
| 1589 | static inline int dwc3_drd_init(struct dwc3 *dwc) |
| 1590 | { return 0; } |
| 1591 | static inline void dwc3_drd_exit(struct dwc3 *dwc) |
| 1592 | { } |
| 1593 | static inline void dwc3_otg_init(struct dwc3 *dwc) |
| 1594 | { } |
| 1595 | static inline void dwc3_otg_exit(struct dwc3 *dwc) |
| 1596 | { } |
| 1597 | static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) |
| 1598 | { } |
| 1599 | static inline void dwc3_otg_host_init(struct dwc3 *dwc) |
| 1600 | { } |
| 1601 | #endif |
| 1602 | |
| 1603 | /* power management interface */ |
| 1604 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) |
| 1605 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
| 1606 | int dwc3_gadget_resume(struct dwc3 *dwc); |
| 1607 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc); |
| 1608 | #else |
| 1609 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
| 1610 | { |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
| 1614 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) |
| 1615 | { |
| 1616 | return 0; |
| 1617 | } |
| 1618 | |
| 1619 | static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) |
| 1620 | { |
| 1621 | } |
| 1622 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
| 1623 | |
| 1624 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
| 1625 | int dwc3_ulpi_init(struct dwc3 *dwc); |
| 1626 | void dwc3_ulpi_exit(struct dwc3 *dwc); |
| 1627 | #else |
| 1628 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) |
| 1629 | { return 0; } |
| 1630 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) |
| 1631 | { } |
| 1632 | #endif |
| 1633 | |
| 1634 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |