| 1 | /** |
| 2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com |
| 4 | * |
| 5 | * Copyright 2008 Openmoko, Inc. |
| 6 | * Copyright 2008 Simtec Electronics |
| 7 | * Ben Dooks <ben@simtec.co.uk> |
| 8 | * http://armlinux.simtec.co.uk/ |
| 9 | * |
| 10 | * S3C USB2.0 High-speed / OtG driver |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/dma-mapping.h> |
| 23 | #include <linux/mutex.h> |
| 24 | #include <linux/seq_file.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/of_platform.h> |
| 29 | |
| 30 | #include <linux/usb/ch9.h> |
| 31 | #include <linux/usb/gadget.h> |
| 32 | #include <linux/usb/phy.h> |
| 33 | |
| 34 | #include "core.h" |
| 35 | #include "hw.h" |
| 36 | |
| 37 | /* conversion functions */ |
| 38 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
| 39 | { |
| 40 | return container_of(req, struct dwc2_hsotg_req, req); |
| 41 | } |
| 42 | |
| 43 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
| 44 | { |
| 45 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
| 46 | } |
| 47 | |
| 48 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
| 49 | { |
| 50 | return container_of(gadget, struct dwc2_hsotg, gadget); |
| 51 | } |
| 52 | |
| 53 | static inline void __orr32(void __iomem *ptr, u32 val) |
| 54 | { |
| 55 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
| 56 | } |
| 57 | |
| 58 | static inline void __bic32(void __iomem *ptr, u32 val) |
| 59 | { |
| 60 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
| 61 | } |
| 62 | |
| 63 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
| 64 | u32 ep_index, u32 dir_in) |
| 65 | { |
| 66 | if (dir_in) |
| 67 | return hsotg->eps_in[ep_index]; |
| 68 | else |
| 69 | return hsotg->eps_out[ep_index]; |
| 70 | } |
| 71 | |
| 72 | /* forward declaration of functions */ |
| 73 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
| 74 | |
| 75 | /** |
| 76 | * using_dma - return the DMA status of the driver. |
| 77 | * @hsotg: The driver state. |
| 78 | * |
| 79 | * Return true if we're using DMA. |
| 80 | * |
| 81 | * Currently, we have the DMA support code worked into everywhere |
| 82 | * that needs it, but the AMBA DMA implementation in the hardware can |
| 83 | * only DMA from 32bit aligned addresses. This means that gadgets such |
| 84 | * as the CDC Ethernet cannot work as they often pass packets which are |
| 85 | * not 32bit aligned. |
| 86 | * |
| 87 | * Unfortunately the choice to use DMA or not is global to the controller |
| 88 | * and seems to be only settable when the controller is being put through |
| 89 | * a core reset. This means we either need to fix the gadgets to take |
| 90 | * account of DMA alignment, or add bounce buffers (yuerk). |
| 91 | * |
| 92 | * g_using_dma is set depending on dts flag. |
| 93 | */ |
| 94 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
| 95 | { |
| 96 | return hsotg->params.g_dma; |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * using_desc_dma - return the descriptor DMA status of the driver. |
| 101 | * @hsotg: The driver state. |
| 102 | * |
| 103 | * Return true if we're using descriptor DMA. |
| 104 | */ |
| 105 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) |
| 106 | { |
| 107 | return hsotg->params.g_dma_desc; |
| 108 | } |
| 109 | |
| 110 | /** |
| 111 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. |
| 112 | * @hs_ep: The endpoint |
| 113 | * @increment: The value to increment by |
| 114 | * |
| 115 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. |
| 116 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. |
| 117 | */ |
| 118 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) |
| 119 | { |
| 120 | hs_ep->target_frame += hs_ep->interval; |
| 121 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { |
| 122 | hs_ep->frame_overrun = 1; |
| 123 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
| 124 | } else { |
| 125 | hs_ep->frame_overrun = 0; |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | /** |
| 130 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
| 131 | * @hsotg: The device state |
| 132 | * @ints: A bitmask of the interrupts to enable |
| 133 | */ |
| 134 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
| 135 | { |
| 136 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
| 137 | u32 new_gsintmsk; |
| 138 | |
| 139 | new_gsintmsk = gsintmsk | ints; |
| 140 | |
| 141 | if (new_gsintmsk != gsintmsk) { |
| 142 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); |
| 143 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | /** |
| 148 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
| 149 | * @hsotg: The device state |
| 150 | * @ints: A bitmask of the interrupts to enable |
| 151 | */ |
| 152 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
| 153 | { |
| 154 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
| 155 | u32 new_gsintmsk; |
| 156 | |
| 157 | new_gsintmsk = gsintmsk & ~ints; |
| 158 | |
| 159 | if (new_gsintmsk != gsintmsk) |
| 160 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
| 161 | } |
| 162 | |
| 163 | /** |
| 164 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
| 165 | * @hsotg: The device state |
| 166 | * @ep: The endpoint index |
| 167 | * @dir_in: True if direction is in. |
| 168 | * @en: The enable value, true to enable |
| 169 | * |
| 170 | * Set or clear the mask for an individual endpoint's interrupt |
| 171 | * request. |
| 172 | */ |
| 173 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
| 174 | unsigned int ep, unsigned int dir_in, |
| 175 | unsigned int en) |
| 176 | { |
| 177 | unsigned long flags; |
| 178 | u32 bit = 1 << ep; |
| 179 | u32 daint; |
| 180 | |
| 181 | if (!dir_in) |
| 182 | bit <<= 16; |
| 183 | |
| 184 | local_irq_save(flags); |
| 185 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
| 186 | if (en) |
| 187 | daint |= bit; |
| 188 | else |
| 189 | daint &= ~bit; |
| 190 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
| 191 | local_irq_restore(flags); |
| 192 | } |
| 193 | |
| 194 | /** |
| 195 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
| 196 | * @hsotg: The device instance. |
| 197 | */ |
| 198 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
| 199 | { |
| 200 | unsigned int ep; |
| 201 | unsigned int addr; |
| 202 | int timeout; |
| 203 | u32 val; |
| 204 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
| 205 | |
| 206 | /* Reset fifo map if not correctly cleared during previous session */ |
| 207 | WARN_ON(hsotg->fifo_map); |
| 208 | hsotg->fifo_map = 0; |
| 209 | |
| 210 | /* set RX/NPTX FIFO sizes */ |
| 211 | dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); |
| 212 | dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | |
| 213 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
| 214 | hsotg->regs + GNPTXFSIZ); |
| 215 | |
| 216 | /* |
| 217 | * arange all the rest of the TX FIFOs, as some versions of this |
| 218 | * block have overlapping default addresses. This also ensures |
| 219 | * that if the settings have been changed, then they are set to |
| 220 | * known values. |
| 221 | */ |
| 222 | |
| 223 | /* start at the end of the GNPTXFSIZ, rounded up */ |
| 224 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
| 225 | |
| 226 | /* |
| 227 | * Configure fifos sizes from provided configuration and assign |
| 228 | * them to endpoints dynamically according to maxpacket size value of |
| 229 | * given endpoint. |
| 230 | */ |
| 231 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
| 232 | if (!txfsz[ep]) |
| 233 | continue; |
| 234 | val = addr; |
| 235 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
| 236 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, |
| 237 | "insufficient fifo memory"); |
| 238 | addr += txfsz[ep]; |
| 239 | |
| 240 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
| 241 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * according to p428 of the design guide, we need to ensure that |
| 246 | * all fifos are flushed before continuing |
| 247 | */ |
| 248 | |
| 249 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
| 250 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
| 251 | |
| 252 | /* wait until the fifos are both flushed */ |
| 253 | timeout = 100; |
| 254 | while (1) { |
| 255 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
| 256 | |
| 257 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
| 258 | break; |
| 259 | |
| 260 | if (--timeout == 0) { |
| 261 | dev_err(hsotg->dev, |
| 262 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", |
| 263 | __func__, val); |
| 264 | break; |
| 265 | } |
| 266 | |
| 267 | udelay(1); |
| 268 | } |
| 269 | |
| 270 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); |
| 271 | } |
| 272 | |
| 273 | /** |
| 274 | * @ep: USB endpoint to allocate request for. |
| 275 | * @flags: Allocation flags |
| 276 | * |
| 277 | * Allocate a new USB request structure appropriate for the specified endpoint |
| 278 | */ |
| 279 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
| 280 | gfp_t flags) |
| 281 | { |
| 282 | struct dwc2_hsotg_req *req; |
| 283 | |
| 284 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
| 285 | if (!req) |
| 286 | return NULL; |
| 287 | |
| 288 | INIT_LIST_HEAD(&req->queue); |
| 289 | |
| 290 | return &req->req; |
| 291 | } |
| 292 | |
| 293 | /** |
| 294 | * is_ep_periodic - return true if the endpoint is in periodic mode. |
| 295 | * @hs_ep: The endpoint to query. |
| 296 | * |
| 297 | * Returns true if the endpoint is in periodic mode, meaning it is being |
| 298 | * used for an Interrupt or ISO transfer. |
| 299 | */ |
| 300 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
| 301 | { |
| 302 | return hs_ep->periodic; |
| 303 | } |
| 304 | |
| 305 | /** |
| 306 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
| 307 | * @hsotg: The device state. |
| 308 | * @hs_ep: The endpoint for the request |
| 309 | * @hs_req: The request being processed. |
| 310 | * |
| 311 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
| 312 | * of a request to ensure the buffer is ready for access by the caller. |
| 313 | */ |
| 314 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
| 315 | struct dwc2_hsotg_ep *hs_ep, |
| 316 | struct dwc2_hsotg_req *hs_req) |
| 317 | { |
| 318 | struct usb_request *req = &hs_req->req; |
| 319 | |
| 320 | /* ignore this if we're not moving any data */ |
| 321 | if (hs_req->req.length == 0) |
| 322 | return; |
| 323 | |
| 324 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
| 325 | } |
| 326 | |
| 327 | /* |
| 328 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains |
| 329 | * for Control endpoint |
| 330 | * @hsotg: The device state. |
| 331 | * |
| 332 | * This function will allocate 4 descriptor chains for EP 0: 2 for |
| 333 | * Setup stage, per one for IN and OUT data/status transactions. |
| 334 | */ |
| 335 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) |
| 336 | { |
| 337 | hsotg->setup_desc[0] = |
| 338 | dmam_alloc_coherent(hsotg->dev, |
| 339 | sizeof(struct dwc2_dma_desc), |
| 340 | &hsotg->setup_desc_dma[0], |
| 341 | GFP_KERNEL); |
| 342 | if (!hsotg->setup_desc[0]) |
| 343 | goto fail; |
| 344 | |
| 345 | hsotg->setup_desc[1] = |
| 346 | dmam_alloc_coherent(hsotg->dev, |
| 347 | sizeof(struct dwc2_dma_desc), |
| 348 | &hsotg->setup_desc_dma[1], |
| 349 | GFP_KERNEL); |
| 350 | if (!hsotg->setup_desc[1]) |
| 351 | goto fail; |
| 352 | |
| 353 | hsotg->ctrl_in_desc = |
| 354 | dmam_alloc_coherent(hsotg->dev, |
| 355 | sizeof(struct dwc2_dma_desc), |
| 356 | &hsotg->ctrl_in_desc_dma, |
| 357 | GFP_KERNEL); |
| 358 | if (!hsotg->ctrl_in_desc) |
| 359 | goto fail; |
| 360 | |
| 361 | hsotg->ctrl_out_desc = |
| 362 | dmam_alloc_coherent(hsotg->dev, |
| 363 | sizeof(struct dwc2_dma_desc), |
| 364 | &hsotg->ctrl_out_desc_dma, |
| 365 | GFP_KERNEL); |
| 366 | if (!hsotg->ctrl_out_desc) |
| 367 | goto fail; |
| 368 | |
| 369 | return 0; |
| 370 | |
| 371 | fail: |
| 372 | return -ENOMEM; |
| 373 | } |
| 374 | |
| 375 | /** |
| 376 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
| 377 | * @hsotg: The controller state. |
| 378 | * @hs_ep: The endpoint we're going to write for. |
| 379 | * @hs_req: The request to write data for. |
| 380 | * |
| 381 | * This is called when the TxFIFO has some space in it to hold a new |
| 382 | * transmission and we have something to give it. The actual setup of |
| 383 | * the data size is done elsewhere, so all we have to do is to actually |
| 384 | * write the data. |
| 385 | * |
| 386 | * The return value is zero if there is more space (or nothing was done) |
| 387 | * otherwise -ENOSPC is returned if the FIFO space was used up. |
| 388 | * |
| 389 | * This routine is only needed for PIO |
| 390 | */ |
| 391 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
| 392 | struct dwc2_hsotg_ep *hs_ep, |
| 393 | struct dwc2_hsotg_req *hs_req) |
| 394 | { |
| 395 | bool periodic = is_ep_periodic(hs_ep); |
| 396 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
| 397 | int buf_pos = hs_req->req.actual; |
| 398 | int to_write = hs_ep->size_loaded; |
| 399 | void *data; |
| 400 | int can_write; |
| 401 | int pkt_round; |
| 402 | int max_transfer; |
| 403 | |
| 404 | to_write -= (buf_pos - hs_ep->last_load); |
| 405 | |
| 406 | /* if there's nothing to write, get out early */ |
| 407 | if (to_write == 0) |
| 408 | return 0; |
| 409 | |
| 410 | if (periodic && !hsotg->dedicated_fifos) { |
| 411 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
| 412 | int size_left; |
| 413 | int size_done; |
| 414 | |
| 415 | /* |
| 416 | * work out how much data was loaded so we can calculate |
| 417 | * how much data is left in the fifo. |
| 418 | */ |
| 419 | |
| 420 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
| 421 | |
| 422 | /* |
| 423 | * if shared fifo, we cannot write anything until the |
| 424 | * previous data has been completely sent. |
| 425 | */ |
| 426 | if (hs_ep->fifo_load != 0) { |
| 427 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
| 428 | return -ENOSPC; |
| 429 | } |
| 430 | |
| 431 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
| 432 | __func__, size_left, |
| 433 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); |
| 434 | |
| 435 | /* how much of the data has moved */ |
| 436 | size_done = hs_ep->size_loaded - size_left; |
| 437 | |
| 438 | /* how much data is left in the fifo */ |
| 439 | can_write = hs_ep->fifo_load - size_done; |
| 440 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", |
| 441 | __func__, can_write); |
| 442 | |
| 443 | can_write = hs_ep->fifo_size - can_write; |
| 444 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", |
| 445 | __func__, can_write); |
| 446 | |
| 447 | if (can_write <= 0) { |
| 448 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
| 449 | return -ENOSPC; |
| 450 | } |
| 451 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
| 452 | can_write = dwc2_readl(hsotg->regs + |
| 453 | DTXFSTS(hs_ep->fifo_index)); |
| 454 | |
| 455 | can_write &= 0xffff; |
| 456 | can_write *= 4; |
| 457 | } else { |
| 458 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
| 459 | dev_dbg(hsotg->dev, |
| 460 | "%s: no queue slots available (0x%08x)\n", |
| 461 | __func__, gnptxsts); |
| 462 | |
| 463 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
| 464 | return -ENOSPC; |
| 465 | } |
| 466 | |
| 467 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
| 468 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
| 469 | } |
| 470 | |
| 471 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
| 472 | |
| 473 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", |
| 474 | __func__, gnptxsts, can_write, to_write, max_transfer); |
| 475 | |
| 476 | /* |
| 477 | * limit to 512 bytes of data, it seems at least on the non-periodic |
| 478 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
| 479 | * fragment of the end of the transfer in it. |
| 480 | */ |
| 481 | if (can_write > 512 && !periodic) |
| 482 | can_write = 512; |
| 483 | |
| 484 | /* |
| 485 | * limit the write to one max-packet size worth of data, but allow |
| 486 | * the transfer to return that it did not run out of fifo space |
| 487 | * doing it. |
| 488 | */ |
| 489 | if (to_write > max_transfer) { |
| 490 | to_write = max_transfer; |
| 491 | |
| 492 | /* it's needed only when we do not use dedicated fifos */ |
| 493 | if (!hsotg->dedicated_fifos) |
| 494 | dwc2_hsotg_en_gsint(hsotg, |
| 495 | periodic ? GINTSTS_PTXFEMP : |
| 496 | GINTSTS_NPTXFEMP); |
| 497 | } |
| 498 | |
| 499 | /* see if we can write data */ |
| 500 | |
| 501 | if (to_write > can_write) { |
| 502 | to_write = can_write; |
| 503 | pkt_round = to_write % max_transfer; |
| 504 | |
| 505 | /* |
| 506 | * Round the write down to an |
| 507 | * exact number of packets. |
| 508 | * |
| 509 | * Note, we do not currently check to see if we can ever |
| 510 | * write a full packet or not to the FIFO. |
| 511 | */ |
| 512 | |
| 513 | if (pkt_round) |
| 514 | to_write -= pkt_round; |
| 515 | |
| 516 | /* |
| 517 | * enable correct FIFO interrupt to alert us when there |
| 518 | * is more room left. |
| 519 | */ |
| 520 | |
| 521 | /* it's needed only when we do not use dedicated fifos */ |
| 522 | if (!hsotg->dedicated_fifos) |
| 523 | dwc2_hsotg_en_gsint(hsotg, |
| 524 | periodic ? GINTSTS_PTXFEMP : |
| 525 | GINTSTS_NPTXFEMP); |
| 526 | } |
| 527 | |
| 528 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", |
| 529 | to_write, hs_req->req.length, can_write, buf_pos); |
| 530 | |
| 531 | if (to_write <= 0) |
| 532 | return -ENOSPC; |
| 533 | |
| 534 | hs_req->req.actual = buf_pos + to_write; |
| 535 | hs_ep->total_data += to_write; |
| 536 | |
| 537 | if (periodic) |
| 538 | hs_ep->fifo_load += to_write; |
| 539 | |
| 540 | to_write = DIV_ROUND_UP(to_write, 4); |
| 541 | data = hs_req->req.buf + buf_pos; |
| 542 | |
| 543 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
| 544 | |
| 545 | return (to_write >= can_write) ? -ENOSPC : 0; |
| 546 | } |
| 547 | |
| 548 | /** |
| 549 | * get_ep_limit - get the maximum data legnth for this endpoint |
| 550 | * @hs_ep: The endpoint |
| 551 | * |
| 552 | * Return the maximum data that can be queued in one go on a given endpoint |
| 553 | * so that transfers that are too long can be split. |
| 554 | */ |
| 555 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
| 556 | { |
| 557 | int index = hs_ep->index; |
| 558 | unsigned maxsize; |
| 559 | unsigned maxpkt; |
| 560 | |
| 561 | if (index != 0) { |
| 562 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
| 563 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; |
| 564 | } else { |
| 565 | maxsize = 64+64; |
| 566 | if (hs_ep->dir_in) |
| 567 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
| 568 | else |
| 569 | maxpkt = 2; |
| 570 | } |
| 571 | |
| 572 | /* we made the constant loading easier above by using +1 */ |
| 573 | maxpkt--; |
| 574 | maxsize--; |
| 575 | |
| 576 | /* |
| 577 | * constrain by packet count if maxpkts*pktsize is greater |
| 578 | * than the length register size. |
| 579 | */ |
| 580 | |
| 581 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) |
| 582 | maxsize = maxpkt * hs_ep->ep.maxpacket; |
| 583 | |
| 584 | return maxsize; |
| 585 | } |
| 586 | |
| 587 | /** |
| 588 | * dwc2_hsotg_read_frameno - read current frame number |
| 589 | * @hsotg: The device instance |
| 590 | * |
| 591 | * Return the current frame number |
| 592 | */ |
| 593 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
| 594 | { |
| 595 | u32 dsts; |
| 596 | |
| 597 | dsts = dwc2_readl(hsotg->regs + DSTS); |
| 598 | dsts &= DSTS_SOFFN_MASK; |
| 599 | dsts >>= DSTS_SOFFN_SHIFT; |
| 600 | |
| 601 | return dsts; |
| 602 | } |
| 603 | |
| 604 | /** |
| 605 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the |
| 606 | * DMA descriptor chain prepared for specific endpoint |
| 607 | * @hs_ep: The endpoint |
| 608 | * |
| 609 | * Return the maximum data that can be queued in one go on a given endpoint |
| 610 | * depending on its descriptor chain capacity so that transfers that |
| 611 | * are too long can be split. |
| 612 | */ |
| 613 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) |
| 614 | { |
| 615 | int is_isoc = hs_ep->isochronous; |
| 616 | unsigned int maxsize; |
| 617 | |
| 618 | if (is_isoc) |
| 619 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : |
| 620 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; |
| 621 | else |
| 622 | maxsize = DEV_DMA_NBYTES_LIMIT; |
| 623 | |
| 624 | /* Above size of one descriptor was chosen, multiple it */ |
| 625 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; |
| 626 | |
| 627 | return maxsize; |
| 628 | } |
| 629 | |
| 630 | /* |
| 631 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. |
| 632 | * @hs_ep: The endpoint |
| 633 | * @mask: RX/TX bytes mask to be defined |
| 634 | * |
| 635 | * Returns maximum data payload for one descriptor after analyzing endpoint |
| 636 | * characteristics. |
| 637 | * DMA descriptor transfer bytes limit depends on EP type: |
| 638 | * Control out - MPS, |
| 639 | * Isochronous - descriptor rx/tx bytes bitfield limit, |
| 640 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not |
| 641 | * have concatenations from various descriptors within one packet. |
| 642 | * |
| 643 | * Selects corresponding mask for RX/TX bytes as well. |
| 644 | */ |
| 645 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) |
| 646 | { |
| 647 | u32 mps = hs_ep->ep.maxpacket; |
| 648 | int dir_in = hs_ep->dir_in; |
| 649 | u32 desc_size = 0; |
| 650 | |
| 651 | if (!hs_ep->index && !dir_in) { |
| 652 | desc_size = mps; |
| 653 | *mask = DEV_DMA_NBYTES_MASK; |
| 654 | } else if (hs_ep->isochronous) { |
| 655 | if (dir_in) { |
| 656 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; |
| 657 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; |
| 658 | } else { |
| 659 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; |
| 660 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; |
| 661 | } |
| 662 | } else { |
| 663 | desc_size = DEV_DMA_NBYTES_LIMIT; |
| 664 | *mask = DEV_DMA_NBYTES_MASK; |
| 665 | |
| 666 | /* Round down desc_size to be mps multiple */ |
| 667 | desc_size -= desc_size % mps; |
| 668 | } |
| 669 | |
| 670 | return desc_size; |
| 671 | } |
| 672 | |
| 673 | /* |
| 674 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. |
| 675 | * @hs_ep: The endpoint |
| 676 | * @dma_buff: DMA address to use |
| 677 | * @len: Length of the transfer |
| 678 | * |
| 679 | * This function will iterate over descriptor chain and fill its entries |
| 680 | * with corresponding information based on transfer data. |
| 681 | */ |
| 682 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, |
| 683 | dma_addr_t dma_buff, |
| 684 | unsigned int len) |
| 685 | { |
| 686 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 687 | int dir_in = hs_ep->dir_in; |
| 688 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
| 689 | u32 mps = hs_ep->ep.maxpacket; |
| 690 | u32 maxsize = 0; |
| 691 | u32 offset = 0; |
| 692 | u32 mask = 0; |
| 693 | int i; |
| 694 | |
| 695 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); |
| 696 | |
| 697 | hs_ep->desc_count = (len / maxsize) + |
| 698 | ((len % maxsize) ? 1 : 0); |
| 699 | if (len == 0) |
| 700 | hs_ep->desc_count = 1; |
| 701 | |
| 702 | for (i = 0; i < hs_ep->desc_count; ++i) { |
| 703 | desc->status = 0; |
| 704 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY |
| 705 | << DEV_DMA_BUFF_STS_SHIFT); |
| 706 | |
| 707 | if (len > maxsize) { |
| 708 | if (!hs_ep->index && !dir_in) |
| 709 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); |
| 710 | |
| 711 | desc->status |= (maxsize << |
| 712 | DEV_DMA_NBYTES_SHIFT & mask); |
| 713 | desc->buf = dma_buff + offset; |
| 714 | |
| 715 | len -= maxsize; |
| 716 | offset += maxsize; |
| 717 | } else { |
| 718 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); |
| 719 | |
| 720 | if (dir_in) |
| 721 | desc->status |= (len % mps) ? DEV_DMA_SHORT : |
| 722 | ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); |
| 723 | if (len > maxsize) |
| 724 | dev_err(hsotg->dev, "wrong len %d\n", len); |
| 725 | |
| 726 | desc->status |= |
| 727 | len << DEV_DMA_NBYTES_SHIFT & mask; |
| 728 | desc->buf = dma_buff + offset; |
| 729 | } |
| 730 | |
| 731 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; |
| 732 | desc->status |= (DEV_DMA_BUFF_STS_HREADY |
| 733 | << DEV_DMA_BUFF_STS_SHIFT); |
| 734 | desc++; |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | /** |
| 739 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
| 740 | * @hsotg: The controller state. |
| 741 | * @hs_ep: The endpoint to process a request for |
| 742 | * @hs_req: The request to start. |
| 743 | * @continuing: True if we are doing more for the current request. |
| 744 | * |
| 745 | * Start the given request running by setting the endpoint registers |
| 746 | * appropriately, and writing any data to the FIFOs. |
| 747 | */ |
| 748 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
| 749 | struct dwc2_hsotg_ep *hs_ep, |
| 750 | struct dwc2_hsotg_req *hs_req, |
| 751 | bool continuing) |
| 752 | { |
| 753 | struct usb_request *ureq = &hs_req->req; |
| 754 | int index = hs_ep->index; |
| 755 | int dir_in = hs_ep->dir_in; |
| 756 | u32 epctrl_reg; |
| 757 | u32 epsize_reg; |
| 758 | u32 epsize; |
| 759 | u32 ctrl; |
| 760 | unsigned length; |
| 761 | unsigned packets; |
| 762 | unsigned maxreq; |
| 763 | unsigned int dma_reg; |
| 764 | |
| 765 | if (index != 0) { |
| 766 | if (hs_ep->req && !continuing) { |
| 767 | dev_err(hsotg->dev, "%s: active request\n", __func__); |
| 768 | WARN_ON(1); |
| 769 | return; |
| 770 | } else if (hs_ep->req != hs_req && continuing) { |
| 771 | dev_err(hsotg->dev, |
| 772 | "%s: continue different req\n", __func__); |
| 773 | WARN_ON(1); |
| 774 | return; |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
| 779 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
| 780 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); |
| 781 | |
| 782 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", |
| 783 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
| 784 | hs_ep->dir_in ? "in" : "out"); |
| 785 | |
| 786 | /* If endpoint is stalled, we will restart request later */ |
| 787 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
| 788 | |
| 789 | if (index && ctrl & DXEPCTL_STALL) { |
| 790 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
| 791 | return; |
| 792 | } |
| 793 | |
| 794 | length = ureq->length - ureq->actual; |
| 795 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
| 796 | ureq->length, ureq->actual); |
| 797 | |
| 798 | if (!using_desc_dma(hsotg)) |
| 799 | maxreq = get_ep_limit(hs_ep); |
| 800 | else |
| 801 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); |
| 802 | |
| 803 | if (length > maxreq) { |
| 804 | int round = maxreq % hs_ep->ep.maxpacket; |
| 805 | |
| 806 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", |
| 807 | __func__, length, maxreq, round); |
| 808 | |
| 809 | /* round down to multiple of packets */ |
| 810 | if (round) |
| 811 | maxreq -= round; |
| 812 | |
| 813 | length = maxreq; |
| 814 | } |
| 815 | |
| 816 | if (length) |
| 817 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); |
| 818 | else |
| 819 | packets = 1; /* send one packet if length is zero. */ |
| 820 | |
| 821 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
| 822 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); |
| 823 | return; |
| 824 | } |
| 825 | |
| 826 | if (dir_in && index != 0) |
| 827 | if (hs_ep->isochronous) |
| 828 | epsize = DXEPTSIZ_MC(packets); |
| 829 | else |
| 830 | epsize = DXEPTSIZ_MC(1); |
| 831 | else |
| 832 | epsize = 0; |
| 833 | |
| 834 | /* |
| 835 | * zero length packet should be programmed on its own and should not |
| 836 | * be counted in DIEPTSIZ.PktCnt with other packets. |
| 837 | */ |
| 838 | if (dir_in && ureq->zero && !continuing) { |
| 839 | /* Test if zlp is actually required. */ |
| 840 | if ((ureq->length >= hs_ep->ep.maxpacket) && |
| 841 | !(ureq->length % hs_ep->ep.maxpacket)) |
| 842 | hs_ep->send_zlp = 1; |
| 843 | } |
| 844 | |
| 845 | epsize |= DXEPTSIZ_PKTCNT(packets); |
| 846 | epsize |= DXEPTSIZ_XFERSIZE(length); |
| 847 | |
| 848 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", |
| 849 | __func__, packets, length, ureq->length, epsize, epsize_reg); |
| 850 | |
| 851 | /* store the request as the current one we're doing */ |
| 852 | hs_ep->req = hs_req; |
| 853 | |
| 854 | if (using_desc_dma(hsotg)) { |
| 855 | u32 offset = 0; |
| 856 | u32 mps = hs_ep->ep.maxpacket; |
| 857 | |
| 858 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ |
| 859 | if (!dir_in) { |
| 860 | if (!index) |
| 861 | length = mps; |
| 862 | else if (length % mps) |
| 863 | length += (mps - (length % mps)); |
| 864 | } |
| 865 | |
| 866 | /* |
| 867 | * If more data to send, adjust DMA for EP0 out data stage. |
| 868 | * ureq->dma stays unchanged, hence increment it by already |
| 869 | * passed passed data count before starting new transaction. |
| 870 | */ |
| 871 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
| 872 | continuing) |
| 873 | offset = ureq->actual; |
| 874 | |
| 875 | /* Fill DDMA chain entries */ |
| 876 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, |
| 877 | length); |
| 878 | |
| 879 | /* write descriptor chain address to control register */ |
| 880 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); |
| 881 | |
| 882 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
| 883 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); |
| 884 | } else { |
| 885 | /* write size / packets */ |
| 886 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
| 887 | |
| 888 | if (using_dma(hsotg) && !continuing) { |
| 889 | /* |
| 890 | * write DMA address to control register, buffer |
| 891 | * already synced by dwc2_hsotg_ep_queue(). |
| 892 | */ |
| 893 | |
| 894 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
| 895 | |
| 896 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
| 897 | __func__, &ureq->dma, dma_reg); |
| 898 | } |
| 899 | } |
| 900 | |
| 901 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
| 902 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); |
| 903 | dwc2_gadget_incr_frame_num(hs_ep); |
| 904 | |
| 905 | if (hs_ep->target_frame & 0x1) |
| 906 | ctrl |= DXEPCTL_SETODDFR; |
| 907 | else |
| 908 | ctrl |= DXEPCTL_SETEVENFR; |
| 909 | } |
| 910 | |
| 911 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
| 912 | |
| 913 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
| 914 | |
| 915 | /* For Setup request do not clear NAK */ |
| 916 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
| 917 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
| 918 | |
| 919 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
| 920 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
| 921 | |
| 922 | /* |
| 923 | * set these, it seems that DMA support increments past the end |
| 924 | * of the packet buffer so we need to calculate the length from |
| 925 | * this information. |
| 926 | */ |
| 927 | hs_ep->size_loaded = length; |
| 928 | hs_ep->last_load = ureq->actual; |
| 929 | |
| 930 | if (dir_in && !using_dma(hsotg)) { |
| 931 | /* set these anyway, we may need them for non-periodic in */ |
| 932 | hs_ep->fifo_load = 0; |
| 933 | |
| 934 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
| 935 | } |
| 936 | |
| 937 | /* |
| 938 | * Note, trying to clear the NAK here causes problems with transmit |
| 939 | * on the S3C6400 ending up with the TXFIFO becoming full. |
| 940 | */ |
| 941 | |
| 942 | /* check ep is enabled */ |
| 943 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
| 944 | dev_dbg(hsotg->dev, |
| 945 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
| 946 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
| 947 | |
| 948 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
| 949 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
| 950 | |
| 951 | /* enable ep interrupts */ |
| 952 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
| 953 | } |
| 954 | |
| 955 | /** |
| 956 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
| 957 | * @hsotg: The device state. |
| 958 | * @hs_ep: The endpoint the request is on. |
| 959 | * @req: The request being processed. |
| 960 | * |
| 961 | * We've been asked to queue a request, so ensure that the memory buffer |
| 962 | * is correctly setup for DMA. If we've been passed an extant DMA address |
| 963 | * then ensure the buffer has been synced to memory. If our buffer has no |
| 964 | * DMA memory, then we map the memory and mark our request to allow us to |
| 965 | * cleanup on completion. |
| 966 | */ |
| 967 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
| 968 | struct dwc2_hsotg_ep *hs_ep, |
| 969 | struct usb_request *req) |
| 970 | { |
| 971 | struct dwc2_hsotg_req *hs_req = our_req(req); |
| 972 | int ret; |
| 973 | |
| 974 | /* if the length is zero, ignore the DMA data */ |
| 975 | if (hs_req->req.length == 0) |
| 976 | return 0; |
| 977 | |
| 978 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
| 979 | if (ret) |
| 980 | goto dma_error; |
| 981 | |
| 982 | return 0; |
| 983 | |
| 984 | dma_error: |
| 985 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", |
| 986 | __func__, req->buf, req->length); |
| 987 | |
| 988 | return -EIO; |
| 989 | } |
| 990 | |
| 991 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
| 992 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) |
| 993 | { |
| 994 | void *req_buf = hs_req->req.buf; |
| 995 | |
| 996 | /* If dma is not being used or buffer is aligned */ |
| 997 | if (!using_dma(hsotg) || !((long)req_buf & 3)) |
| 998 | return 0; |
| 999 | |
| 1000 | WARN_ON(hs_req->saved_req_buf); |
| 1001 | |
| 1002 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, |
| 1003 | hs_ep->ep.name, req_buf, hs_req->req.length); |
| 1004 | |
| 1005 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); |
| 1006 | if (!hs_req->req.buf) { |
| 1007 | hs_req->req.buf = req_buf; |
| 1008 | dev_err(hsotg->dev, |
| 1009 | "%s: unable to allocate memory for bounce buffer\n", |
| 1010 | __func__); |
| 1011 | return -ENOMEM; |
| 1012 | } |
| 1013 | |
| 1014 | /* Save actual buffer */ |
| 1015 | hs_req->saved_req_buf = req_buf; |
| 1016 | |
| 1017 | if (hs_ep->dir_in) |
| 1018 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); |
| 1019 | return 0; |
| 1020 | } |
| 1021 | |
| 1022 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
| 1023 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) |
| 1024 | { |
| 1025 | /* If dma is not being used or buffer was aligned */ |
| 1026 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) |
| 1027 | return; |
| 1028 | |
| 1029 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, |
| 1030 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); |
| 1031 | |
| 1032 | /* Copy data from bounce buffer on successful out transfer */ |
| 1033 | if (!hs_ep->dir_in && !hs_req->req.status) |
| 1034 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, |
| 1035 | hs_req->req.actual); |
| 1036 | |
| 1037 | /* Free bounce buffer */ |
| 1038 | kfree(hs_req->req.buf); |
| 1039 | |
| 1040 | hs_req->req.buf = hs_req->saved_req_buf; |
| 1041 | hs_req->saved_req_buf = NULL; |
| 1042 | } |
| 1043 | |
| 1044 | /** |
| 1045 | * dwc2_gadget_target_frame_elapsed - Checks target frame |
| 1046 | * @hs_ep: The driver endpoint to check |
| 1047 | * |
| 1048 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop |
| 1049 | * corresponding transfer. |
| 1050 | */ |
| 1051 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) |
| 1052 | { |
| 1053 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 1054 | u32 target_frame = hs_ep->target_frame; |
| 1055 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); |
| 1056 | bool frame_overrun = hs_ep->frame_overrun; |
| 1057 | |
| 1058 | if (!frame_overrun && current_frame >= target_frame) |
| 1059 | return true; |
| 1060 | |
| 1061 | if (frame_overrun && current_frame >= target_frame && |
| 1062 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) |
| 1063 | return true; |
| 1064 | |
| 1065 | return false; |
| 1066 | } |
| 1067 | |
| 1068 | /* |
| 1069 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers |
| 1070 | * @hsotg: The driver state |
| 1071 | * @hs_ep: the ep descriptor chain is for |
| 1072 | * |
| 1073 | * Called to update EP0 structure's pointers depend on stage of |
| 1074 | * control transfer. |
| 1075 | */ |
| 1076 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, |
| 1077 | struct dwc2_hsotg_ep *hs_ep) |
| 1078 | { |
| 1079 | switch (hsotg->ep0_state) { |
| 1080 | case DWC2_EP0_SETUP: |
| 1081 | case DWC2_EP0_STATUS_OUT: |
| 1082 | hs_ep->desc_list = hsotg->setup_desc[0]; |
| 1083 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; |
| 1084 | break; |
| 1085 | case DWC2_EP0_DATA_IN: |
| 1086 | case DWC2_EP0_STATUS_IN: |
| 1087 | hs_ep->desc_list = hsotg->ctrl_in_desc; |
| 1088 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; |
| 1089 | break; |
| 1090 | case DWC2_EP0_DATA_OUT: |
| 1091 | hs_ep->desc_list = hsotg->ctrl_out_desc; |
| 1092 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; |
| 1093 | break; |
| 1094 | default: |
| 1095 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", |
| 1096 | hsotg->ep0_state); |
| 1097 | return -EINVAL; |
| 1098 | } |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
| 1104 | gfp_t gfp_flags) |
| 1105 | { |
| 1106 | struct dwc2_hsotg_req *hs_req = our_req(req); |
| 1107 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 1108 | struct dwc2_hsotg *hs = hs_ep->parent; |
| 1109 | bool first; |
| 1110 | int ret; |
| 1111 | |
| 1112 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", |
| 1113 | ep->name, req, req->length, req->buf, req->no_interrupt, |
| 1114 | req->zero, req->short_not_ok); |
| 1115 | |
| 1116 | /* Prevent new request submission when controller is suspended */ |
| 1117 | if (hs->lx_state == DWC2_L2) { |
| 1118 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", |
| 1119 | __func__); |
| 1120 | return -EAGAIN; |
| 1121 | } |
| 1122 | |
| 1123 | /* initialise status of the request */ |
| 1124 | INIT_LIST_HEAD(&hs_req->queue); |
| 1125 | req->actual = 0; |
| 1126 | req->status = -EINPROGRESS; |
| 1127 | |
| 1128 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
| 1129 | if (ret) |
| 1130 | return ret; |
| 1131 | |
| 1132 | /* if we're using DMA, sync the buffers as necessary */ |
| 1133 | if (using_dma(hs)) { |
| 1134 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
| 1135 | if (ret) |
| 1136 | return ret; |
| 1137 | } |
| 1138 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
| 1139 | if (using_desc_dma(hs) && !hs_ep->index) { |
| 1140 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); |
| 1141 | if (ret) |
| 1142 | return ret; |
| 1143 | } |
| 1144 | |
| 1145 | first = list_empty(&hs_ep->queue); |
| 1146 | list_add_tail(&hs_req->queue, &hs_ep->queue); |
| 1147 | |
| 1148 | if (first) { |
| 1149 | if (!hs_ep->isochronous) { |
| 1150 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); |
| 1151 | return 0; |
| 1152 | } |
| 1153 | |
| 1154 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) |
| 1155 | dwc2_gadget_incr_frame_num(hs_ep); |
| 1156 | |
| 1157 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
| 1158 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); |
| 1159 | } |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
| 1164 | gfp_t gfp_flags) |
| 1165 | { |
| 1166 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 1167 | struct dwc2_hsotg *hs = hs_ep->parent; |
| 1168 | unsigned long flags = 0; |
| 1169 | int ret = 0; |
| 1170 | |
| 1171 | spin_lock_irqsave(&hs->lock, flags); |
| 1172 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
| 1173 | spin_unlock_irqrestore(&hs->lock, flags); |
| 1174 | |
| 1175 | return ret; |
| 1176 | } |
| 1177 | |
| 1178 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
| 1179 | struct usb_request *req) |
| 1180 | { |
| 1181 | struct dwc2_hsotg_req *hs_req = our_req(req); |
| 1182 | |
| 1183 | kfree(hs_req); |
| 1184 | } |
| 1185 | |
| 1186 | /** |
| 1187 | * dwc2_hsotg_complete_oursetup - setup completion callback |
| 1188 | * @ep: The endpoint the request was on. |
| 1189 | * @req: The request completed. |
| 1190 | * |
| 1191 | * Called on completion of any requests the driver itself |
| 1192 | * submitted that need cleaning up. |
| 1193 | */ |
| 1194 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
| 1195 | struct usb_request *req) |
| 1196 | { |
| 1197 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 1198 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 1199 | |
| 1200 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); |
| 1201 | |
| 1202 | dwc2_hsotg_ep_free_request(ep, req); |
| 1203 | } |
| 1204 | |
| 1205 | /** |
| 1206 | * ep_from_windex - convert control wIndex value to endpoint |
| 1207 | * @hsotg: The driver state. |
| 1208 | * @windex: The control request wIndex field (in host order). |
| 1209 | * |
| 1210 | * Convert the given wIndex into a pointer to an driver endpoint |
| 1211 | * structure, or return NULL if it is not a valid endpoint. |
| 1212 | */ |
| 1213 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
| 1214 | u32 windex) |
| 1215 | { |
| 1216 | struct dwc2_hsotg_ep *ep; |
| 1217 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
| 1218 | int idx = windex & 0x7F; |
| 1219 | |
| 1220 | if (windex >= 0x100) |
| 1221 | return NULL; |
| 1222 | |
| 1223 | if (idx > hsotg->num_of_eps) |
| 1224 | return NULL; |
| 1225 | |
| 1226 | ep = index_to_ep(hsotg, idx, dir); |
| 1227 | |
| 1228 | if (idx && ep->dir_in != dir) |
| 1229 | return NULL; |
| 1230 | |
| 1231 | return ep; |
| 1232 | } |
| 1233 | |
| 1234 | /** |
| 1235 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
| 1236 | * @hsotg: The driver state. |
| 1237 | * @testmode: requested usb test mode |
| 1238 | * Enable usb Test Mode requested by the Host. |
| 1239 | */ |
| 1240 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
| 1241 | { |
| 1242 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
| 1243 | |
| 1244 | dctl &= ~DCTL_TSTCTL_MASK; |
| 1245 | switch (testmode) { |
| 1246 | case TEST_J: |
| 1247 | case TEST_K: |
| 1248 | case TEST_SE0_NAK: |
| 1249 | case TEST_PACKET: |
| 1250 | case TEST_FORCE_EN: |
| 1251 | dctl |= testmode << DCTL_TSTCTL_SHIFT; |
| 1252 | break; |
| 1253 | default: |
| 1254 | return -EINVAL; |
| 1255 | } |
| 1256 | dwc2_writel(dctl, hsotg->regs + DCTL); |
| 1257 | return 0; |
| 1258 | } |
| 1259 | |
| 1260 | /** |
| 1261 | * dwc2_hsotg_send_reply - send reply to control request |
| 1262 | * @hsotg: The device state |
| 1263 | * @ep: Endpoint 0 |
| 1264 | * @buff: Buffer for request |
| 1265 | * @length: Length of reply. |
| 1266 | * |
| 1267 | * Create a request and queue it on the given endpoint. This is useful as |
| 1268 | * an internal method of sending replies to certain control requests, etc. |
| 1269 | */ |
| 1270 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
| 1271 | struct dwc2_hsotg_ep *ep, |
| 1272 | void *buff, |
| 1273 | int length) |
| 1274 | { |
| 1275 | struct usb_request *req; |
| 1276 | int ret; |
| 1277 | |
| 1278 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); |
| 1279 | |
| 1280 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
| 1281 | hsotg->ep0_reply = req; |
| 1282 | if (!req) { |
| 1283 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); |
| 1284 | return -ENOMEM; |
| 1285 | } |
| 1286 | |
| 1287 | req->buf = hsotg->ep0_buff; |
| 1288 | req->length = length; |
| 1289 | /* |
| 1290 | * zero flag is for sending zlp in DATA IN stage. It has no impact on |
| 1291 | * STATUS stage. |
| 1292 | */ |
| 1293 | req->zero = 0; |
| 1294 | req->complete = dwc2_hsotg_complete_oursetup; |
| 1295 | |
| 1296 | if (length) |
| 1297 | memcpy(req->buf, buff, length); |
| 1298 | |
| 1299 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
| 1300 | if (ret) { |
| 1301 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); |
| 1302 | return ret; |
| 1303 | } |
| 1304 | |
| 1305 | return 0; |
| 1306 | } |
| 1307 | |
| 1308 | /** |
| 1309 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
| 1310 | * @hsotg: The device state |
| 1311 | * @ctrl: USB control request |
| 1312 | */ |
| 1313 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
| 1314 | struct usb_ctrlrequest *ctrl) |
| 1315 | { |
| 1316 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
| 1317 | struct dwc2_hsotg_ep *ep; |
| 1318 | __le16 reply; |
| 1319 | int ret; |
| 1320 | |
| 1321 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); |
| 1322 | |
| 1323 | if (!ep0->dir_in) { |
| 1324 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); |
| 1325 | return -EINVAL; |
| 1326 | } |
| 1327 | |
| 1328 | switch (ctrl->bRequestType & USB_RECIP_MASK) { |
| 1329 | case USB_RECIP_DEVICE: |
| 1330 | reply = cpu_to_le16(0); /* bit 0 => self powered, |
| 1331 | * bit 1 => remote wakeup */ |
| 1332 | break; |
| 1333 | |
| 1334 | case USB_RECIP_INTERFACE: |
| 1335 | /* currently, the data result should be zero */ |
| 1336 | reply = cpu_to_le16(0); |
| 1337 | break; |
| 1338 | |
| 1339 | case USB_RECIP_ENDPOINT: |
| 1340 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); |
| 1341 | if (!ep) |
| 1342 | return -ENOENT; |
| 1343 | |
| 1344 | reply = cpu_to_le16(ep->halted ? 1 : 0); |
| 1345 | break; |
| 1346 | |
| 1347 | default: |
| 1348 | return 0; |
| 1349 | } |
| 1350 | |
| 1351 | if (le16_to_cpu(ctrl->wLength) != 2) |
| 1352 | return -EINVAL; |
| 1353 | |
| 1354 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
| 1355 | if (ret) { |
| 1356 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); |
| 1357 | return ret; |
| 1358 | } |
| 1359 | |
| 1360 | return 1; |
| 1361 | } |
| 1362 | |
| 1363 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
| 1364 | |
| 1365 | /** |
| 1366 | * get_ep_head - return the first request on the endpoint |
| 1367 | * @hs_ep: The controller endpoint to get |
| 1368 | * |
| 1369 | * Get the first request on the endpoint. |
| 1370 | */ |
| 1371 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
| 1372 | { |
| 1373 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
| 1374 | queue); |
| 1375 | } |
| 1376 | |
| 1377 | /** |
| 1378 | * dwc2_gadget_start_next_request - Starts next request from ep queue |
| 1379 | * @hs_ep: Endpoint structure |
| 1380 | * |
| 1381 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked |
| 1382 | * in its handler. Hence we need to unmask it here to be able to do |
| 1383 | * resynchronization. |
| 1384 | */ |
| 1385 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) |
| 1386 | { |
| 1387 | u32 mask; |
| 1388 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 1389 | int dir_in = hs_ep->dir_in; |
| 1390 | struct dwc2_hsotg_req *hs_req; |
| 1391 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; |
| 1392 | |
| 1393 | if (!list_empty(&hs_ep->queue)) { |
| 1394 | hs_req = get_ep_head(hs_ep); |
| 1395 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); |
| 1396 | return; |
| 1397 | } |
| 1398 | if (!hs_ep->isochronous) |
| 1399 | return; |
| 1400 | |
| 1401 | if (dir_in) { |
| 1402 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", |
| 1403 | __func__); |
| 1404 | } else { |
| 1405 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", |
| 1406 | __func__); |
| 1407 | mask = dwc2_readl(hsotg->regs + epmsk_reg); |
| 1408 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
| 1409 | dwc2_writel(mask, hsotg->regs + epmsk_reg); |
| 1410 | } |
| 1411 | } |
| 1412 | |
| 1413 | /** |
| 1414 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
| 1415 | * @hsotg: The device state |
| 1416 | * @ctrl: USB control request |
| 1417 | */ |
| 1418 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
| 1419 | struct usb_ctrlrequest *ctrl) |
| 1420 | { |
| 1421 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
| 1422 | struct dwc2_hsotg_req *hs_req; |
| 1423 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
| 1424 | struct dwc2_hsotg_ep *ep; |
| 1425 | int ret; |
| 1426 | bool halted; |
| 1427 | u32 recip; |
| 1428 | u32 wValue; |
| 1429 | u32 wIndex; |
| 1430 | |
| 1431 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", |
| 1432 | __func__, set ? "SET" : "CLEAR"); |
| 1433 | |
| 1434 | wValue = le16_to_cpu(ctrl->wValue); |
| 1435 | wIndex = le16_to_cpu(ctrl->wIndex); |
| 1436 | recip = ctrl->bRequestType & USB_RECIP_MASK; |
| 1437 | |
| 1438 | switch (recip) { |
| 1439 | case USB_RECIP_DEVICE: |
| 1440 | switch (wValue) { |
| 1441 | case USB_DEVICE_TEST_MODE: |
| 1442 | if ((wIndex & 0xff) != 0) |
| 1443 | return -EINVAL; |
| 1444 | if (!set) |
| 1445 | return -EINVAL; |
| 1446 | |
| 1447 | hsotg->test_mode = wIndex >> 8; |
| 1448 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
| 1449 | if (ret) { |
| 1450 | dev_err(hsotg->dev, |
| 1451 | "%s: failed to send reply\n", __func__); |
| 1452 | return ret; |
| 1453 | } |
| 1454 | break; |
| 1455 | default: |
| 1456 | return -ENOENT; |
| 1457 | } |
| 1458 | break; |
| 1459 | |
| 1460 | case USB_RECIP_ENDPOINT: |
| 1461 | ep = ep_from_windex(hsotg, wIndex); |
| 1462 | if (!ep) { |
| 1463 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", |
| 1464 | __func__, wIndex); |
| 1465 | return -ENOENT; |
| 1466 | } |
| 1467 | |
| 1468 | switch (wValue) { |
| 1469 | case USB_ENDPOINT_HALT: |
| 1470 | halted = ep->halted; |
| 1471 | |
| 1472 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
| 1473 | |
| 1474 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
| 1475 | if (ret) { |
| 1476 | dev_err(hsotg->dev, |
| 1477 | "%s: failed to send reply\n", __func__); |
| 1478 | return ret; |
| 1479 | } |
| 1480 | |
| 1481 | /* |
| 1482 | * we have to complete all requests for ep if it was |
| 1483 | * halted, and the halt was cleared by CLEAR_FEATURE |
| 1484 | */ |
| 1485 | |
| 1486 | if (!set && halted) { |
| 1487 | /* |
| 1488 | * If we have request in progress, |
| 1489 | * then complete it |
| 1490 | */ |
| 1491 | if (ep->req) { |
| 1492 | hs_req = ep->req; |
| 1493 | ep->req = NULL; |
| 1494 | list_del_init(&hs_req->queue); |
| 1495 | if (hs_req->req.complete) { |
| 1496 | spin_unlock(&hsotg->lock); |
| 1497 | usb_gadget_giveback_request( |
| 1498 | &ep->ep, &hs_req->req); |
| 1499 | spin_lock(&hsotg->lock); |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | /* If we have pending request, then start it */ |
| 1504 | if (!ep->req) { |
| 1505 | dwc2_gadget_start_next_request(ep); |
| 1506 | } |
| 1507 | } |
| 1508 | |
| 1509 | break; |
| 1510 | |
| 1511 | default: |
| 1512 | return -ENOENT; |
| 1513 | } |
| 1514 | break; |
| 1515 | default: |
| 1516 | return -ENOENT; |
| 1517 | } |
| 1518 | return 1; |
| 1519 | } |
| 1520 | |
| 1521 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
| 1522 | |
| 1523 | /** |
| 1524 | * dwc2_hsotg_stall_ep0 - stall ep0 |
| 1525 | * @hsotg: The device state |
| 1526 | * |
| 1527 | * Set stall for ep0 as response for setup request. |
| 1528 | */ |
| 1529 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
| 1530 | { |
| 1531 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
| 1532 | u32 reg; |
| 1533 | u32 ctrl; |
| 1534 | |
| 1535 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); |
| 1536 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; |
| 1537 | |
| 1538 | /* |
| 1539 | * DxEPCTL_Stall will be cleared by EP once it has |
| 1540 | * taken effect, so no need to clear later. |
| 1541 | */ |
| 1542 | |
| 1543 | ctrl = dwc2_readl(hsotg->regs + reg); |
| 1544 | ctrl |= DXEPCTL_STALL; |
| 1545 | ctrl |= DXEPCTL_CNAK; |
| 1546 | dwc2_writel(ctrl, hsotg->regs + reg); |
| 1547 | |
| 1548 | dev_dbg(hsotg->dev, |
| 1549 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
| 1550 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
| 1551 | |
| 1552 | /* |
| 1553 | * complete won't be called, so we enqueue |
| 1554 | * setup request here |
| 1555 | */ |
| 1556 | dwc2_hsotg_enqueue_setup(hsotg); |
| 1557 | } |
| 1558 | |
| 1559 | /** |
| 1560 | * dwc2_hsotg_process_control - process a control request |
| 1561 | * @hsotg: The device state |
| 1562 | * @ctrl: The control request received |
| 1563 | * |
| 1564 | * The controller has received the SETUP phase of a control request, and |
| 1565 | * needs to work out what to do next (and whether to pass it on to the |
| 1566 | * gadget driver). |
| 1567 | */ |
| 1568 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
| 1569 | struct usb_ctrlrequest *ctrl) |
| 1570 | { |
| 1571 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
| 1572 | int ret = 0; |
| 1573 | u32 dcfg; |
| 1574 | |
| 1575 | dev_dbg(hsotg->dev, |
| 1576 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", |
| 1577 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, |
| 1578 | ctrl->wIndex, ctrl->wLength); |
| 1579 | |
| 1580 | if (ctrl->wLength == 0) { |
| 1581 | ep0->dir_in = 1; |
| 1582 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; |
| 1583 | } else if (ctrl->bRequestType & USB_DIR_IN) { |
| 1584 | ep0->dir_in = 1; |
| 1585 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
| 1586 | } else { |
| 1587 | ep0->dir_in = 0; |
| 1588 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; |
| 1589 | } |
| 1590 | |
| 1591 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { |
| 1592 | switch (ctrl->bRequest) { |
| 1593 | case USB_REQ_SET_ADDRESS: |
| 1594 | hsotg->connected = 1; |
| 1595 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
| 1596 | dcfg &= ~DCFG_DEVADDR_MASK; |
| 1597 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
| 1598 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; |
| 1599 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
| 1600 | |
| 1601 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); |
| 1602 | |
| 1603 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
| 1604 | return; |
| 1605 | |
| 1606 | case USB_REQ_GET_STATUS: |
| 1607 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
| 1608 | break; |
| 1609 | |
| 1610 | case USB_REQ_CLEAR_FEATURE: |
| 1611 | case USB_REQ_SET_FEATURE: |
| 1612 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
| 1613 | break; |
| 1614 | } |
| 1615 | } |
| 1616 | |
| 1617 | /* as a fallback, try delivering it to the driver to deal with */ |
| 1618 | |
| 1619 | if (ret == 0 && hsotg->driver) { |
| 1620 | spin_unlock(&hsotg->lock); |
| 1621 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
| 1622 | spin_lock(&hsotg->lock); |
| 1623 | if (ret < 0) |
| 1624 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); |
| 1625 | } |
| 1626 | |
| 1627 | /* |
| 1628 | * the request is either unhandlable, or is not formatted correctly |
| 1629 | * so respond with a STALL for the status stage to indicate failure. |
| 1630 | */ |
| 1631 | |
| 1632 | if (ret < 0) |
| 1633 | dwc2_hsotg_stall_ep0(hsotg); |
| 1634 | } |
| 1635 | |
| 1636 | /** |
| 1637 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
| 1638 | * @ep: The endpoint the request was on. |
| 1639 | * @req: The request completed. |
| 1640 | * |
| 1641 | * Called on completion of any requests the driver itself submitted for |
| 1642 | * EP0 setup packets |
| 1643 | */ |
| 1644 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
| 1645 | struct usb_request *req) |
| 1646 | { |
| 1647 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 1648 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 1649 | |
| 1650 | if (req->status < 0) { |
| 1651 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); |
| 1652 | return; |
| 1653 | } |
| 1654 | |
| 1655 | spin_lock(&hsotg->lock); |
| 1656 | if (req->actual == 0) |
| 1657 | dwc2_hsotg_enqueue_setup(hsotg); |
| 1658 | else |
| 1659 | dwc2_hsotg_process_control(hsotg, req->buf); |
| 1660 | spin_unlock(&hsotg->lock); |
| 1661 | } |
| 1662 | |
| 1663 | /** |
| 1664 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
| 1665 | * @hsotg: The device state. |
| 1666 | * |
| 1667 | * Enqueue a request on EP0 if necessary to received any SETUP packets |
| 1668 | * received from the host. |
| 1669 | */ |
| 1670 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
| 1671 | { |
| 1672 | struct usb_request *req = hsotg->ctrl_req; |
| 1673 | struct dwc2_hsotg_req *hs_req = our_req(req); |
| 1674 | int ret; |
| 1675 | |
| 1676 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); |
| 1677 | |
| 1678 | req->zero = 0; |
| 1679 | req->length = 8; |
| 1680 | req->buf = hsotg->ctrl_buff; |
| 1681 | req->complete = dwc2_hsotg_complete_setup; |
| 1682 | |
| 1683 | if (!list_empty(&hs_req->queue)) { |
| 1684 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); |
| 1685 | return; |
| 1686 | } |
| 1687 | |
| 1688 | hsotg->eps_out[0]->dir_in = 0; |
| 1689 | hsotg->eps_out[0]->send_zlp = 0; |
| 1690 | hsotg->ep0_state = DWC2_EP0_SETUP; |
| 1691 | |
| 1692 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
| 1693 | if (ret < 0) { |
| 1694 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); |
| 1695 | /* |
| 1696 | * Don't think there's much we can do other than watch the |
| 1697 | * driver fail. |
| 1698 | */ |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
| 1703 | struct dwc2_hsotg_ep *hs_ep) |
| 1704 | { |
| 1705 | u32 ctrl; |
| 1706 | u8 index = hs_ep->index; |
| 1707 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
| 1708 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); |
| 1709 | |
| 1710 | if (hs_ep->dir_in) |
| 1711 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", |
| 1712 | index); |
| 1713 | else |
| 1714 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", |
| 1715 | index); |
| 1716 | if (using_desc_dma(hsotg)) { |
| 1717 | /* Not specific buffer needed for ep0 ZLP */ |
| 1718 | dma_addr_t dma = hs_ep->desc_list_dma; |
| 1719 | |
| 1720 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); |
| 1721 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
| 1722 | } else { |
| 1723 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
| 1724 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + |
| 1725 | epsiz_reg); |
| 1726 | } |
| 1727 | |
| 1728 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
| 1729 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
| 1730 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
| 1731 | ctrl |= DXEPCTL_USBACTEP; |
| 1732 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
| 1733 | } |
| 1734 | |
| 1735 | /** |
| 1736 | * dwc2_hsotg_complete_request - complete a request given to us |
| 1737 | * @hsotg: The device state. |
| 1738 | * @hs_ep: The endpoint the request was on. |
| 1739 | * @hs_req: The request to complete. |
| 1740 | * @result: The result code (0 => Ok, otherwise errno) |
| 1741 | * |
| 1742 | * The given request has finished, so call the necessary completion |
| 1743 | * if it has one and then look to see if we can start a new request |
| 1744 | * on the endpoint. |
| 1745 | * |
| 1746 | * Note, expects the ep to already be locked as appropriate. |
| 1747 | */ |
| 1748 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
| 1749 | struct dwc2_hsotg_ep *hs_ep, |
| 1750 | struct dwc2_hsotg_req *hs_req, |
| 1751 | int result) |
| 1752 | { |
| 1753 | |
| 1754 | if (!hs_req) { |
| 1755 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); |
| 1756 | return; |
| 1757 | } |
| 1758 | |
| 1759 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", |
| 1760 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); |
| 1761 | |
| 1762 | /* |
| 1763 | * only replace the status if we've not already set an error |
| 1764 | * from a previous transaction |
| 1765 | */ |
| 1766 | |
| 1767 | if (hs_req->req.status == -EINPROGRESS) |
| 1768 | hs_req->req.status = result; |
| 1769 | |
| 1770 | if (using_dma(hsotg)) |
| 1771 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); |
| 1772 | |
| 1773 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
| 1774 | |
| 1775 | hs_ep->req = NULL; |
| 1776 | list_del_init(&hs_req->queue); |
| 1777 | |
| 1778 | /* |
| 1779 | * call the complete request with the locks off, just in case the |
| 1780 | * request tries to queue more work for this endpoint. |
| 1781 | */ |
| 1782 | |
| 1783 | if (hs_req->req.complete) { |
| 1784 | spin_unlock(&hsotg->lock); |
| 1785 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
| 1786 | spin_lock(&hsotg->lock); |
| 1787 | } |
| 1788 | |
| 1789 | /* |
| 1790 | * Look to see if there is anything else to do. Note, the completion |
| 1791 | * of the previous request may have caused a new request to be started |
| 1792 | * so be careful when doing this. |
| 1793 | */ |
| 1794 | |
| 1795 | if (!hs_ep->req && result >= 0) { |
| 1796 | dwc2_gadget_start_next_request(hs_ep); |
| 1797 | } |
| 1798 | } |
| 1799 | |
| 1800 | /** |
| 1801 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
| 1802 | * @hsotg: The device state. |
| 1803 | * @ep_idx: The endpoint index for the data |
| 1804 | * @size: The size of data in the fifo, in bytes |
| 1805 | * |
| 1806 | * The FIFO status shows there is data to read from the FIFO for a given |
| 1807 | * endpoint, so sort out whether we need to read the data into a request |
| 1808 | * that has been made for that endpoint. |
| 1809 | */ |
| 1810 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
| 1811 | { |
| 1812 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
| 1813 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
| 1814 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
| 1815 | int to_read; |
| 1816 | int max_req; |
| 1817 | int read_ptr; |
| 1818 | |
| 1819 | |
| 1820 | if (!hs_req) { |
| 1821 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
| 1822 | int ptr; |
| 1823 | |
| 1824 | dev_dbg(hsotg->dev, |
| 1825 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
| 1826 | __func__, size, ep_idx, epctl); |
| 1827 | |
| 1828 | /* dump the data from the FIFO, we've nothing we can do */ |
| 1829 | for (ptr = 0; ptr < size; ptr += 4) |
| 1830 | (void)dwc2_readl(fifo); |
| 1831 | |
| 1832 | return; |
| 1833 | } |
| 1834 | |
| 1835 | to_read = size; |
| 1836 | read_ptr = hs_req->req.actual; |
| 1837 | max_req = hs_req->req.length - read_ptr; |
| 1838 | |
| 1839 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
| 1840 | __func__, to_read, max_req, read_ptr, hs_req->req.length); |
| 1841 | |
| 1842 | if (to_read > max_req) { |
| 1843 | /* |
| 1844 | * more data appeared than we where willing |
| 1845 | * to deal with in this request. |
| 1846 | */ |
| 1847 | |
| 1848 | /* currently we don't deal this */ |
| 1849 | WARN_ON_ONCE(1); |
| 1850 | } |
| 1851 | |
| 1852 | hs_ep->total_data += to_read; |
| 1853 | hs_req->req.actual += to_read; |
| 1854 | to_read = DIV_ROUND_UP(to_read, 4); |
| 1855 | |
| 1856 | /* |
| 1857 | * note, we might over-write the buffer end by 3 bytes depending on |
| 1858 | * alignment of the data. |
| 1859 | */ |
| 1860 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
| 1861 | } |
| 1862 | |
| 1863 | /** |
| 1864 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
| 1865 | * @hsotg: The device instance |
| 1866 | * @dir_in: If IN zlp |
| 1867 | * |
| 1868 | * Generate a zero-length IN packet request for terminating a SETUP |
| 1869 | * transaction. |
| 1870 | * |
| 1871 | * Note, since we don't write any data to the TxFIFO, then it is |
| 1872 | * currently believed that we do not need to wait for any space in |
| 1873 | * the TxFIFO. |
| 1874 | */ |
| 1875 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
| 1876 | { |
| 1877 | /* eps_out[0] is used in both directions */ |
| 1878 | hsotg->eps_out[0]->dir_in = dir_in; |
| 1879 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; |
| 1880 | |
| 1881 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
| 1882 | } |
| 1883 | |
| 1884 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
| 1885 | u32 epctl_reg) |
| 1886 | { |
| 1887 | u32 ctrl; |
| 1888 | |
| 1889 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
| 1890 | if (ctrl & DXEPCTL_EOFRNUM) |
| 1891 | ctrl |= DXEPCTL_SETEVENFR; |
| 1892 | else |
| 1893 | ctrl |= DXEPCTL_SETODDFR; |
| 1894 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
| 1895 | } |
| 1896 | |
| 1897 | /* |
| 1898 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc |
| 1899 | * @hs_ep - The endpoint on which transfer went |
| 1900 | * |
| 1901 | * Iterate over endpoints descriptor chain and get info on bytes remained |
| 1902 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. |
| 1903 | */ |
| 1904 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) |
| 1905 | { |
| 1906 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 1907 | unsigned int bytes_rem = 0; |
| 1908 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
| 1909 | int i; |
| 1910 | u32 status; |
| 1911 | |
| 1912 | if (!desc) |
| 1913 | return -EINVAL; |
| 1914 | |
| 1915 | for (i = 0; i < hs_ep->desc_count; ++i) { |
| 1916 | status = desc->status; |
| 1917 | bytes_rem += status & DEV_DMA_NBYTES_MASK; |
| 1918 | |
| 1919 | if (status & DEV_DMA_STS_MASK) |
| 1920 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", |
| 1921 | i, status & DEV_DMA_STS_MASK); |
| 1922 | } |
| 1923 | |
| 1924 | return bytes_rem; |
| 1925 | } |
| 1926 | |
| 1927 | /** |
| 1928 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
| 1929 | * @hsotg: The device instance |
| 1930 | * @epnum: The endpoint received from |
| 1931 | * |
| 1932 | * The RXFIFO has delivered an OutDone event, which means that the data |
| 1933 | * transfer for an OUT endpoint has been completed, either by a short |
| 1934 | * packet or by the finish of a transfer. |
| 1935 | */ |
| 1936 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
| 1937 | { |
| 1938 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
| 1939 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
| 1940 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
| 1941 | struct usb_request *req = &hs_req->req; |
| 1942 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
| 1943 | int result = 0; |
| 1944 | |
| 1945 | if (!hs_req) { |
| 1946 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); |
| 1947 | return; |
| 1948 | } |
| 1949 | |
| 1950 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
| 1951 | dev_dbg(hsotg->dev, "zlp packet received\n"); |
| 1952 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
| 1953 | dwc2_hsotg_enqueue_setup(hsotg); |
| 1954 | return; |
| 1955 | } |
| 1956 | |
| 1957 | if (using_desc_dma(hsotg)) |
| 1958 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); |
| 1959 | |
| 1960 | if (using_dma(hsotg)) { |
| 1961 | unsigned size_done; |
| 1962 | |
| 1963 | /* |
| 1964 | * Calculate the size of the transfer by checking how much |
| 1965 | * is left in the endpoint size register and then working it |
| 1966 | * out from the amount we loaded for the transfer. |
| 1967 | * |
| 1968 | * We need to do this as DMA pointers are always 32bit aligned |
| 1969 | * so may overshoot/undershoot the transfer. |
| 1970 | */ |
| 1971 | |
| 1972 | size_done = hs_ep->size_loaded - size_left; |
| 1973 | size_done += hs_ep->last_load; |
| 1974 | |
| 1975 | req->actual = size_done; |
| 1976 | } |
| 1977 | |
| 1978 | /* if there is more request to do, schedule new transfer */ |
| 1979 | if (req->actual < req->length && size_left == 0) { |
| 1980 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
| 1981 | return; |
| 1982 | } |
| 1983 | |
| 1984 | if (req->actual < req->length && req->short_not_ok) { |
| 1985 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", |
| 1986 | __func__, req->actual, req->length); |
| 1987 | |
| 1988 | /* |
| 1989 | * todo - what should we return here? there's no one else |
| 1990 | * even bothering to check the status. |
| 1991 | */ |
| 1992 | } |
| 1993 | |
| 1994 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
| 1995 | /* Move to STATUS IN */ |
| 1996 | dwc2_hsotg_ep0_zlp(hsotg, true); |
| 1997 | return; |
| 1998 | } |
| 1999 | |
| 2000 | /* |
| 2001 | * Slave mode OUT transfers do not go through XferComplete so |
| 2002 | * adjust the ISOC parity here. |
| 2003 | */ |
| 2004 | if (!using_dma(hsotg)) { |
| 2005 | if (hs_ep->isochronous && hs_ep->interval == 1) |
| 2006 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); |
| 2007 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
| 2008 | dwc2_gadget_incr_frame_num(hs_ep); |
| 2009 | } |
| 2010 | |
| 2011 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
| 2012 | } |
| 2013 | |
| 2014 | /** |
| 2015 | * dwc2_hsotg_handle_rx - RX FIFO has data |
| 2016 | * @hsotg: The device instance |
| 2017 | * |
| 2018 | * The IRQ handler has detected that the RX FIFO has some data in it |
| 2019 | * that requires processing, so find out what is in there and do the |
| 2020 | * appropriate read. |
| 2021 | * |
| 2022 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
| 2023 | * chunks, so if you have x packets received on an endpoint you'll get x |
| 2024 | * FIFO events delivered, each with a packet's worth of data in it. |
| 2025 | * |
| 2026 | * When using DMA, we should not be processing events from the RXFIFO |
| 2027 | * as the actual data should be sent to the memory directly and we turn |
| 2028 | * on the completion interrupts to get notifications of transfer completion. |
| 2029 | */ |
| 2030 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
| 2031 | { |
| 2032 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
| 2033 | u32 epnum, status, size; |
| 2034 | |
| 2035 | WARN_ON(using_dma(hsotg)); |
| 2036 | |
| 2037 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
| 2038 | status = grxstsr & GRXSTS_PKTSTS_MASK; |
| 2039 | |
| 2040 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
| 2041 | size >>= GRXSTS_BYTECNT_SHIFT; |
| 2042 | |
| 2043 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
| 2044 | __func__, grxstsr, size, epnum); |
| 2045 | |
| 2046 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
| 2047 | case GRXSTS_PKTSTS_GLOBALOUTNAK: |
| 2048 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); |
| 2049 | break; |
| 2050 | |
| 2051 | case GRXSTS_PKTSTS_OUTDONE: |
| 2052 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
| 2053 | dwc2_hsotg_read_frameno(hsotg)); |
| 2054 | |
| 2055 | if (!using_dma(hsotg)) |
| 2056 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
| 2057 | break; |
| 2058 | |
| 2059 | case GRXSTS_PKTSTS_SETUPDONE: |
| 2060 | dev_dbg(hsotg->dev, |
| 2061 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", |
| 2062 | dwc2_hsotg_read_frameno(hsotg), |
| 2063 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
| 2064 | /* |
| 2065 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
| 2066 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
| 2067 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. |
| 2068 | */ |
| 2069 | if (hsotg->ep0_state == DWC2_EP0_SETUP) |
| 2070 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
| 2071 | break; |
| 2072 | |
| 2073 | case GRXSTS_PKTSTS_OUTRX: |
| 2074 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
| 2075 | break; |
| 2076 | |
| 2077 | case GRXSTS_PKTSTS_SETUPRX: |
| 2078 | dev_dbg(hsotg->dev, |
| 2079 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", |
| 2080 | dwc2_hsotg_read_frameno(hsotg), |
| 2081 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
| 2082 | |
| 2083 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
| 2084 | |
| 2085 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
| 2086 | break; |
| 2087 | |
| 2088 | default: |
| 2089 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", |
| 2090 | __func__, grxstsr); |
| 2091 | |
| 2092 | dwc2_hsotg_dump(hsotg); |
| 2093 | break; |
| 2094 | } |
| 2095 | } |
| 2096 | |
| 2097 | /** |
| 2098 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
| 2099 | * @mps: The maximum packet size in bytes. |
| 2100 | */ |
| 2101 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
| 2102 | { |
| 2103 | switch (mps) { |
| 2104 | case 64: |
| 2105 | return D0EPCTL_MPS_64; |
| 2106 | case 32: |
| 2107 | return D0EPCTL_MPS_32; |
| 2108 | case 16: |
| 2109 | return D0EPCTL_MPS_16; |
| 2110 | case 8: |
| 2111 | return D0EPCTL_MPS_8; |
| 2112 | } |
| 2113 | |
| 2114 | /* bad max packet size, warn and return invalid result */ |
| 2115 | WARN_ON(1); |
| 2116 | return (u32)-1; |
| 2117 | } |
| 2118 | |
| 2119 | /** |
| 2120 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
| 2121 | * @hsotg: The driver state. |
| 2122 | * @ep: The index number of the endpoint |
| 2123 | * @mps: The maximum packet size in bytes |
| 2124 | * @mc: The multicount value |
| 2125 | * |
| 2126 | * Configure the maximum packet size for the given endpoint, updating |
| 2127 | * the hardware control registers to reflect this. |
| 2128 | */ |
| 2129 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
| 2130 | unsigned int ep, unsigned int mps, |
| 2131 | unsigned int mc, unsigned int dir_in) |
| 2132 | { |
| 2133 | struct dwc2_hsotg_ep *hs_ep; |
| 2134 | void __iomem *regs = hsotg->regs; |
| 2135 | u32 reg; |
| 2136 | |
| 2137 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
| 2138 | if (!hs_ep) |
| 2139 | return; |
| 2140 | |
| 2141 | if (ep == 0) { |
| 2142 | u32 mps_bytes = mps; |
| 2143 | |
| 2144 | /* EP0 is a special case */ |
| 2145 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
| 2146 | if (mps > 3) |
| 2147 | goto bad_mps; |
| 2148 | hs_ep->ep.maxpacket = mps_bytes; |
| 2149 | hs_ep->mc = 1; |
| 2150 | } else { |
| 2151 | if (mps > 1024) |
| 2152 | goto bad_mps; |
| 2153 | hs_ep->mc = mc; |
| 2154 | if (mc > 3) |
| 2155 | goto bad_mps; |
| 2156 | hs_ep->ep.maxpacket = mps; |
| 2157 | } |
| 2158 | |
| 2159 | if (dir_in) { |
| 2160 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
| 2161 | reg &= ~DXEPCTL_MPS_MASK; |
| 2162 | reg |= mps; |
| 2163 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
| 2164 | } else { |
| 2165 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
| 2166 | reg &= ~DXEPCTL_MPS_MASK; |
| 2167 | reg |= mps; |
| 2168 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
| 2169 | } |
| 2170 | |
| 2171 | return; |
| 2172 | |
| 2173 | bad_mps: |
| 2174 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); |
| 2175 | } |
| 2176 | |
| 2177 | /** |
| 2178 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
| 2179 | * @hsotg: The driver state |
| 2180 | * @idx: The index for the endpoint (0..15) |
| 2181 | */ |
| 2182 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
| 2183 | { |
| 2184 | int timeout; |
| 2185 | int val; |
| 2186 | |
| 2187 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
| 2188 | hsotg->regs + GRSTCTL); |
| 2189 | |
| 2190 | /* wait until the fifo is flushed */ |
| 2191 | timeout = 100; |
| 2192 | |
| 2193 | while (1) { |
| 2194 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
| 2195 | |
| 2196 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
| 2197 | break; |
| 2198 | |
| 2199 | if (--timeout == 0) { |
| 2200 | dev_err(hsotg->dev, |
| 2201 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", |
| 2202 | __func__, val); |
| 2203 | break; |
| 2204 | } |
| 2205 | |
| 2206 | udelay(1); |
| 2207 | } |
| 2208 | } |
| 2209 | |
| 2210 | /** |
| 2211 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
| 2212 | * @hsotg: The driver state |
| 2213 | * @hs_ep: The driver endpoint to check. |
| 2214 | * |
| 2215 | * Check to see if there is a request that has data to send, and if so |
| 2216 | * make an attempt to write data into the FIFO. |
| 2217 | */ |
| 2218 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
| 2219 | struct dwc2_hsotg_ep *hs_ep) |
| 2220 | { |
| 2221 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
| 2222 | |
| 2223 | if (!hs_ep->dir_in || !hs_req) { |
| 2224 | /** |
| 2225 | * if request is not enqueued, we disable interrupts |
| 2226 | * for endpoints, excepting ep0 |
| 2227 | */ |
| 2228 | if (hs_ep->index != 0) |
| 2229 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
| 2230 | hs_ep->dir_in, 0); |
| 2231 | return 0; |
| 2232 | } |
| 2233 | |
| 2234 | if (hs_req->req.actual < hs_req->req.length) { |
| 2235 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", |
| 2236 | hs_ep->index); |
| 2237 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
| 2238 | } |
| 2239 | |
| 2240 | return 0; |
| 2241 | } |
| 2242 | |
| 2243 | /** |
| 2244 | * dwc2_hsotg_complete_in - complete IN transfer |
| 2245 | * @hsotg: The device state. |
| 2246 | * @hs_ep: The endpoint that has just completed. |
| 2247 | * |
| 2248 | * An IN transfer has been completed, update the transfer's state and then |
| 2249 | * call the relevant completion routines. |
| 2250 | */ |
| 2251 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
| 2252 | struct dwc2_hsotg_ep *hs_ep) |
| 2253 | { |
| 2254 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
| 2255 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
| 2256 | int size_left, size_done; |
| 2257 | |
| 2258 | if (!hs_req) { |
| 2259 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); |
| 2260 | return; |
| 2261 | } |
| 2262 | |
| 2263 | /* Finish ZLP handling for IN EP0 transactions */ |
| 2264 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
| 2265 | dev_dbg(hsotg->dev, "zlp packet sent\n"); |
| 2266 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
| 2267 | if (hsotg->test_mode) { |
| 2268 | int ret; |
| 2269 | |
| 2270 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
| 2271 | if (ret < 0) { |
| 2272 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", |
| 2273 | hsotg->test_mode); |
| 2274 | dwc2_hsotg_stall_ep0(hsotg); |
| 2275 | return; |
| 2276 | } |
| 2277 | } |
| 2278 | dwc2_hsotg_enqueue_setup(hsotg); |
| 2279 | return; |
| 2280 | } |
| 2281 | |
| 2282 | /* |
| 2283 | * Calculate the size of the transfer by checking how much is left |
| 2284 | * in the endpoint size register and then working it out from |
| 2285 | * the amount we loaded for the transfer. |
| 2286 | * |
| 2287 | * We do this even for DMA, as the transfer may have incremented |
| 2288 | * past the end of the buffer (DMA transfers are always 32bit |
| 2289 | * aligned). |
| 2290 | */ |
| 2291 | if (using_desc_dma(hsotg)) { |
| 2292 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); |
| 2293 | if (size_left < 0) |
| 2294 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", |
| 2295 | size_left); |
| 2296 | } else { |
| 2297 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
| 2298 | } |
| 2299 | |
| 2300 | size_done = hs_ep->size_loaded - size_left; |
| 2301 | size_done += hs_ep->last_load; |
| 2302 | |
| 2303 | if (hs_req->req.actual != size_done) |
| 2304 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", |
| 2305 | __func__, hs_req->req.actual, size_done); |
| 2306 | |
| 2307 | hs_req->req.actual = size_done; |
| 2308 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
| 2309 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); |
| 2310 | |
| 2311 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
| 2312 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); |
| 2313 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
| 2314 | return; |
| 2315 | } |
| 2316 | |
| 2317 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
| 2318 | if (hs_ep->send_zlp) { |
| 2319 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
| 2320 | hs_ep->send_zlp = 0; |
| 2321 | /* transfer will be completed on next complete interrupt */ |
| 2322 | return; |
| 2323 | } |
| 2324 | |
| 2325 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
| 2326 | /* Move to STATUS OUT */ |
| 2327 | dwc2_hsotg_ep0_zlp(hsotg, false); |
| 2328 | return; |
| 2329 | } |
| 2330 | |
| 2331 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
| 2332 | } |
| 2333 | |
| 2334 | /** |
| 2335 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep |
| 2336 | * @hsotg: The device state. |
| 2337 | * @idx: Index of ep. |
| 2338 | * @dir_in: Endpoint direction 1-in 0-out. |
| 2339 | * |
| 2340 | * Reads for endpoint with given index and direction, by masking |
| 2341 | * epint_reg with coresponding mask. |
| 2342 | */ |
| 2343 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, |
| 2344 | unsigned int idx, int dir_in) |
| 2345 | { |
| 2346 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; |
| 2347 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
| 2348 | u32 ints; |
| 2349 | u32 mask; |
| 2350 | u32 diepempmsk; |
| 2351 | |
| 2352 | mask = dwc2_readl(hsotg->regs + epmsk_reg); |
| 2353 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); |
| 2354 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
| 2355 | mask |= DXEPINT_SETUP_RCVD; |
| 2356 | |
| 2357 | ints = dwc2_readl(hsotg->regs + epint_reg); |
| 2358 | ints &= mask; |
| 2359 | return ints; |
| 2360 | } |
| 2361 | |
| 2362 | /** |
| 2363 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD |
| 2364 | * @hs_ep: The endpoint on which interrupt is asserted. |
| 2365 | * |
| 2366 | * This interrupt indicates that the endpoint has been disabled per the |
| 2367 | * application's request. |
| 2368 | * |
| 2369 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, |
| 2370 | * in case of ISOC completes current request. |
| 2371 | * |
| 2372 | * For ISOC-OUT endpoints completes expired requests. If there is remaining |
| 2373 | * request starts it. |
| 2374 | */ |
| 2375 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) |
| 2376 | { |
| 2377 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 2378 | struct dwc2_hsotg_req *hs_req; |
| 2379 | unsigned char idx = hs_ep->index; |
| 2380 | int dir_in = hs_ep->dir_in; |
| 2381 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); |
| 2382 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
| 2383 | |
| 2384 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
| 2385 | |
| 2386 | if (dir_in) { |
| 2387 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); |
| 2388 | |
| 2389 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
| 2390 | |
| 2391 | if (hs_ep->isochronous) { |
| 2392 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
| 2393 | return; |
| 2394 | } |
| 2395 | |
| 2396 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { |
| 2397 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
| 2398 | |
| 2399 | dctl |= DCTL_CGNPINNAK; |
| 2400 | dwc2_writel(dctl, hsotg->regs + DCTL); |
| 2401 | } |
| 2402 | return; |
| 2403 | } |
| 2404 | |
| 2405 | if (dctl & DCTL_GOUTNAKSTS) { |
| 2406 | dctl |= DCTL_CGOUTNAK; |
| 2407 | dwc2_writel(dctl, hsotg->regs + DCTL); |
| 2408 | } |
| 2409 | |
| 2410 | if (!hs_ep->isochronous) |
| 2411 | return; |
| 2412 | |
| 2413 | if (list_empty(&hs_ep->queue)) { |
| 2414 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", |
| 2415 | __func__, hs_ep); |
| 2416 | return; |
| 2417 | } |
| 2418 | |
| 2419 | do { |
| 2420 | hs_req = get_ep_head(hs_ep); |
| 2421 | if (hs_req) |
| 2422 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, |
| 2423 | -ENODATA); |
| 2424 | dwc2_gadget_incr_frame_num(hs_ep); |
| 2425 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
| 2426 | |
| 2427 | dwc2_gadget_start_next_request(hs_ep); |
| 2428 | } |
| 2429 | |
| 2430 | /** |
| 2431 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS |
| 2432 | * @hs_ep: The endpoint on which interrupt is asserted. |
| 2433 | * |
| 2434 | * This is starting point for ISOC-OUT transfer, synchronization done with |
| 2435 | * first out token received from host while corresponding EP is disabled. |
| 2436 | * |
| 2437 | * Device does not know initial frame in which out token will come. For this |
| 2438 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon |
| 2439 | * getting this interrupt SW starts calculation for next transfer frame. |
| 2440 | */ |
| 2441 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) |
| 2442 | { |
| 2443 | struct dwc2_hsotg *hsotg = ep->parent; |
| 2444 | int dir_in = ep->dir_in; |
| 2445 | u32 doepmsk; |
| 2446 | |
| 2447 | if (dir_in || !ep->isochronous) |
| 2448 | return; |
| 2449 | |
| 2450 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); |
| 2451 | |
| 2452 | if (ep->interval > 1 && |
| 2453 | ep->target_frame == TARGET_FRAME_INITIAL) { |
| 2454 | u32 dsts; |
| 2455 | u32 ctrl; |
| 2456 | |
| 2457 | dsts = dwc2_readl(hsotg->regs + DSTS); |
| 2458 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); |
| 2459 | dwc2_gadget_incr_frame_num(ep); |
| 2460 | |
| 2461 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); |
| 2462 | if (ep->target_frame & 0x1) |
| 2463 | ctrl |= DXEPCTL_SETODDFR; |
| 2464 | else |
| 2465 | ctrl |= DXEPCTL_SETEVENFR; |
| 2466 | |
| 2467 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); |
| 2468 | } |
| 2469 | |
| 2470 | dwc2_gadget_start_next_request(ep); |
| 2471 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); |
| 2472 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; |
| 2473 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); |
| 2474 | } |
| 2475 | |
| 2476 | /** |
| 2477 | * dwc2_gadget_handle_nak - handle NAK interrupt |
| 2478 | * @hs_ep: The endpoint on which interrupt is asserted. |
| 2479 | * |
| 2480 | * This is starting point for ISOC-IN transfer, synchronization done with |
| 2481 | * first IN token received from host while corresponding EP is disabled. |
| 2482 | * |
| 2483 | * Device does not know when first one token will arrive from host. On first |
| 2484 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' |
| 2485 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was |
| 2486 | * sent in response to that as there was no data in FIFO. SW is basing on this |
| 2487 | * interrupt to obtain frame in which token has come and then based on the |
| 2488 | * interval calculates next frame for transfer. |
| 2489 | */ |
| 2490 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
| 2491 | { |
| 2492 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 2493 | int dir_in = hs_ep->dir_in; |
| 2494 | |
| 2495 | if (!dir_in || !hs_ep->isochronous) |
| 2496 | return; |
| 2497 | |
| 2498 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { |
| 2499 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); |
| 2500 | if (hs_ep->interval > 1) { |
| 2501 | u32 ctrl = dwc2_readl(hsotg->regs + |
| 2502 | DIEPCTL(hs_ep->index)); |
| 2503 | if (hs_ep->target_frame & 0x1) |
| 2504 | ctrl |= DXEPCTL_SETODDFR; |
| 2505 | else |
| 2506 | ctrl |= DXEPCTL_SETEVENFR; |
| 2507 | |
| 2508 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); |
| 2509 | } |
| 2510 | |
| 2511 | dwc2_hsotg_complete_request(hsotg, hs_ep, |
| 2512 | get_ep_head(hs_ep), 0); |
| 2513 | } |
| 2514 | |
| 2515 | dwc2_gadget_incr_frame_num(hs_ep); |
| 2516 | } |
| 2517 | |
| 2518 | /** |
| 2519 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
| 2520 | * @hsotg: The driver state |
| 2521 | * @idx: The index for the endpoint (0..15) |
| 2522 | * @dir_in: Set if this is an IN endpoint |
| 2523 | * |
| 2524 | * Process and clear any interrupt pending for an individual endpoint |
| 2525 | */ |
| 2526 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
| 2527 | int dir_in) |
| 2528 | { |
| 2529 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
| 2530 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
| 2531 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); |
| 2532 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); |
| 2533 | u32 ints; |
| 2534 | u32 ctrl; |
| 2535 | |
| 2536 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
| 2537 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
| 2538 | |
| 2539 | /* Clear endpoint interrupts */ |
| 2540 | dwc2_writel(ints, hsotg->regs + epint_reg); |
| 2541 | |
| 2542 | if (!hs_ep) { |
| 2543 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", |
| 2544 | __func__, idx, dir_in ? "in" : "out"); |
| 2545 | return; |
| 2546 | } |
| 2547 | |
| 2548 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
| 2549 | __func__, idx, dir_in ? "in" : "out", ints); |
| 2550 | |
| 2551 | /* Don't process XferCompl interrupt if it is a setup packet */ |
| 2552 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) |
| 2553 | ints &= ~DXEPINT_XFERCOMPL; |
| 2554 | |
| 2555 | if (ints & DXEPINT_XFERCOMPL) { |
| 2556 | dev_dbg(hsotg->dev, |
| 2557 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
| 2558 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
| 2559 | dwc2_readl(hsotg->regs + epsiz_reg)); |
| 2560 | |
| 2561 | /* |
| 2562 | * we get OutDone from the FIFO, so we only need to look |
| 2563 | * at completing IN requests here |
| 2564 | */ |
| 2565 | if (dir_in) { |
| 2566 | if (hs_ep->isochronous && hs_ep->interval > 1) |
| 2567 | dwc2_gadget_incr_frame_num(hs_ep); |
| 2568 | |
| 2569 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
| 2570 | if (ints & DXEPINT_NAKINTRPT) |
| 2571 | ints &= ~DXEPINT_NAKINTRPT; |
| 2572 | |
| 2573 | if (idx == 0 && !hs_ep->req) |
| 2574 | dwc2_hsotg_enqueue_setup(hsotg); |
| 2575 | } else if (using_dma(hsotg)) { |
| 2576 | /* |
| 2577 | * We're using DMA, we need to fire an OutDone here |
| 2578 | * as we ignore the RXFIFO. |
| 2579 | */ |
| 2580 | if (hs_ep->isochronous && hs_ep->interval > 1) |
| 2581 | dwc2_gadget_incr_frame_num(hs_ep); |
| 2582 | |
| 2583 | dwc2_hsotg_handle_outdone(hsotg, idx); |
| 2584 | } |
| 2585 | } |
| 2586 | |
| 2587 | if (ints & DXEPINT_EPDISBLD) |
| 2588 | dwc2_gadget_handle_ep_disabled(hs_ep); |
| 2589 | |
| 2590 | if (ints & DXEPINT_OUTTKNEPDIS) |
| 2591 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); |
| 2592 | |
| 2593 | if (ints & DXEPINT_NAKINTRPT) |
| 2594 | dwc2_gadget_handle_nak(hs_ep); |
| 2595 | |
| 2596 | if (ints & DXEPINT_AHBERR) |
| 2597 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
| 2598 | |
| 2599 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
| 2600 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
| 2601 | |
| 2602 | if (using_dma(hsotg) && idx == 0) { |
| 2603 | /* |
| 2604 | * this is the notification we've received a |
| 2605 | * setup packet. In non-DMA mode we'd get this |
| 2606 | * from the RXFIFO, instead we need to process |
| 2607 | * the setup here. |
| 2608 | */ |
| 2609 | |
| 2610 | if (dir_in) |
| 2611 | WARN_ON_ONCE(1); |
| 2612 | else |
| 2613 | dwc2_hsotg_handle_outdone(hsotg, 0); |
| 2614 | } |
| 2615 | } |
| 2616 | |
| 2617 | if (ints & DXEPINT_STSPHSERCVD) |
| 2618 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
| 2619 | |
| 2620 | if (ints & DXEPINT_BACK2BACKSETUP) |
| 2621 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
| 2622 | |
| 2623 | if (dir_in && !hs_ep->isochronous) { |
| 2624 | /* not sure if this is important, but we'll clear it anyway */ |
| 2625 | if (ints & DXEPINT_INTKNTXFEMP) { |
| 2626 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
| 2627 | __func__, idx); |
| 2628 | } |
| 2629 | |
| 2630 | /* this probably means something bad is happening */ |
| 2631 | if (ints & DXEPINT_INTKNEPMIS) { |
| 2632 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
| 2633 | __func__, idx); |
| 2634 | } |
| 2635 | |
| 2636 | /* FIFO has space or is empty (see GAHBCFG) */ |
| 2637 | if (hsotg->dedicated_fifos && |
| 2638 | ints & DXEPINT_TXFEMP) { |
| 2639 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
| 2640 | __func__, idx); |
| 2641 | if (!using_dma(hsotg)) |
| 2642 | dwc2_hsotg_trytx(hsotg, hs_ep); |
| 2643 | } |
| 2644 | } |
| 2645 | } |
| 2646 | |
| 2647 | /** |
| 2648 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
| 2649 | * @hsotg: The device state. |
| 2650 | * |
| 2651 | * Handle updating the device settings after the enumeration phase has |
| 2652 | * been completed. |
| 2653 | */ |
| 2654 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
| 2655 | { |
| 2656 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
| 2657 | int ep0_mps = 0, ep_mps = 8; |
| 2658 | |
| 2659 | /* |
| 2660 | * This should signal the finish of the enumeration phase |
| 2661 | * of the USB handshaking, so we should now know what rate |
| 2662 | * we connected at. |
| 2663 | */ |
| 2664 | |
| 2665 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); |
| 2666 | |
| 2667 | /* |
| 2668 | * note, since we're limited by the size of transfer on EP0, and |
| 2669 | * it seems IN transfers must be a even number of packets we do |
| 2670 | * not advertise a 64byte MPS on EP0. |
| 2671 | */ |
| 2672 | |
| 2673 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ |
| 2674 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
| 2675 | case DSTS_ENUMSPD_FS: |
| 2676 | case DSTS_ENUMSPD_FS48: |
| 2677 | hsotg->gadget.speed = USB_SPEED_FULL; |
| 2678 | ep0_mps = EP0_MPS_LIMIT; |
| 2679 | ep_mps = 1023; |
| 2680 | break; |
| 2681 | |
| 2682 | case DSTS_ENUMSPD_HS: |
| 2683 | hsotg->gadget.speed = USB_SPEED_HIGH; |
| 2684 | ep0_mps = EP0_MPS_LIMIT; |
| 2685 | ep_mps = 1024; |
| 2686 | break; |
| 2687 | |
| 2688 | case DSTS_ENUMSPD_LS: |
| 2689 | hsotg->gadget.speed = USB_SPEED_LOW; |
| 2690 | /* |
| 2691 | * note, we don't actually support LS in this driver at the |
| 2692 | * moment, and the documentation seems to imply that it isn't |
| 2693 | * supported by the PHYs on some of the devices. |
| 2694 | */ |
| 2695 | break; |
| 2696 | } |
| 2697 | dev_info(hsotg->dev, "new device is %s\n", |
| 2698 | usb_speed_string(hsotg->gadget.speed)); |
| 2699 | |
| 2700 | /* |
| 2701 | * we should now know the maximum packet size for an |
| 2702 | * endpoint, so set the endpoints to a default value. |
| 2703 | */ |
| 2704 | |
| 2705 | if (ep0_mps) { |
| 2706 | int i; |
| 2707 | /* Initialize ep0 for both in and out directions */ |
| 2708 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
| 2709 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); |
| 2710 | for (i = 1; i < hsotg->num_of_eps; i++) { |
| 2711 | if (hsotg->eps_in[i]) |
| 2712 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
| 2713 | 0, 1); |
| 2714 | if (hsotg->eps_out[i]) |
| 2715 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
| 2716 | 0, 0); |
| 2717 | } |
| 2718 | } |
| 2719 | |
| 2720 | /* ensure after enumeration our EP0 is active */ |
| 2721 | |
| 2722 | dwc2_hsotg_enqueue_setup(hsotg); |
| 2723 | |
| 2724 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", |
| 2725 | dwc2_readl(hsotg->regs + DIEPCTL0), |
| 2726 | dwc2_readl(hsotg->regs + DOEPCTL0)); |
| 2727 | } |
| 2728 | |
| 2729 | /** |
| 2730 | * kill_all_requests - remove all requests from the endpoint's queue |
| 2731 | * @hsotg: The device state. |
| 2732 | * @ep: The endpoint the requests may be on. |
| 2733 | * @result: The result code to use. |
| 2734 | * |
| 2735 | * Go through the requests on the given endpoint and mark them |
| 2736 | * completed with the given result code. |
| 2737 | */ |
| 2738 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
| 2739 | struct dwc2_hsotg_ep *ep, |
| 2740 | int result) |
| 2741 | { |
| 2742 | struct dwc2_hsotg_req *req, *treq; |
| 2743 | unsigned size; |
| 2744 | |
| 2745 | ep->req = NULL; |
| 2746 | |
| 2747 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
| 2748 | dwc2_hsotg_complete_request(hsotg, ep, req, |
| 2749 | result); |
| 2750 | |
| 2751 | if (!hsotg->dedicated_fifos) |
| 2752 | return; |
| 2753 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
| 2754 | if (size < ep->fifo_size) |
| 2755 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
| 2756 | } |
| 2757 | |
| 2758 | /** |
| 2759 | * dwc2_hsotg_disconnect - disconnect service |
| 2760 | * @hsotg: The device state. |
| 2761 | * |
| 2762 | * The device has been disconnected. Remove all current |
| 2763 | * transactions and signal the gadget driver that this |
| 2764 | * has happened. |
| 2765 | */ |
| 2766 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
| 2767 | { |
| 2768 | unsigned ep; |
| 2769 | |
| 2770 | if (!hsotg->connected) |
| 2771 | return; |
| 2772 | |
| 2773 | hsotg->connected = 0; |
| 2774 | hsotg->test_mode = 0; |
| 2775 | |
| 2776 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
| 2777 | if (hsotg->eps_in[ep]) |
| 2778 | kill_all_requests(hsotg, hsotg->eps_in[ep], |
| 2779 | -ESHUTDOWN); |
| 2780 | if (hsotg->eps_out[ep]) |
| 2781 | kill_all_requests(hsotg, hsotg->eps_out[ep], |
| 2782 | -ESHUTDOWN); |
| 2783 | } |
| 2784 | |
| 2785 | call_gadget(hsotg, disconnect); |
| 2786 | hsotg->lx_state = DWC2_L3; |
| 2787 | } |
| 2788 | |
| 2789 | /** |
| 2790 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
| 2791 | * @hsotg: The device state: |
| 2792 | * @periodic: True if this is a periodic FIFO interrupt |
| 2793 | */ |
| 2794 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
| 2795 | { |
| 2796 | struct dwc2_hsotg_ep *ep; |
| 2797 | int epno, ret; |
| 2798 | |
| 2799 | /* look through for any more data to transmit */ |
| 2800 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
| 2801 | ep = index_to_ep(hsotg, epno, 1); |
| 2802 | |
| 2803 | if (!ep) |
| 2804 | continue; |
| 2805 | |
| 2806 | if (!ep->dir_in) |
| 2807 | continue; |
| 2808 | |
| 2809 | if ((periodic && !ep->periodic) || |
| 2810 | (!periodic && ep->periodic)) |
| 2811 | continue; |
| 2812 | |
| 2813 | ret = dwc2_hsotg_trytx(hsotg, ep); |
| 2814 | if (ret < 0) |
| 2815 | break; |
| 2816 | } |
| 2817 | } |
| 2818 | |
| 2819 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
| 2820 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
| 2821 | GINTSTS_PTXFEMP | \ |
| 2822 | GINTSTS_RXFLVL) |
| 2823 | |
| 2824 | /** |
| 2825 | * dwc2_hsotg_core_init - issue softreset to the core |
| 2826 | * @hsotg: The device state |
| 2827 | * |
| 2828 | * Issue a soft reset to the core, and await the core finishing it. |
| 2829 | */ |
| 2830 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
| 2831 | bool is_usb_reset) |
| 2832 | { |
| 2833 | u32 intmsk; |
| 2834 | u32 val; |
| 2835 | u32 usbcfg; |
| 2836 | |
| 2837 | /* Kill any ep0 requests as controller will be reinitialized */ |
| 2838 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); |
| 2839 | |
| 2840 | if (!is_usb_reset) |
| 2841 | if (dwc2_core_reset(hsotg)) |
| 2842 | return; |
| 2843 | |
| 2844 | /* |
| 2845 | * we must now enable ep0 ready for host detection and then |
| 2846 | * set configuration. |
| 2847 | */ |
| 2848 | |
| 2849 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
| 2850 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); |
| 2851 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | |
| 2852 | GUSBCFG_HNPCAP); |
| 2853 | |
| 2854 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
| 2855 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
| 2856 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
| 2857 | (val << GUSBCFG_USBTRDTIM_SHIFT); |
| 2858 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
| 2859 | |
| 2860 | dwc2_hsotg_init_fifo(hsotg); |
| 2861 | |
| 2862 | if (!is_usb_reset) |
| 2863 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
| 2864 | |
| 2865 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
| 2866 | |
| 2867 | /* Clear any pending OTG interrupts */ |
| 2868 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
| 2869 | |
| 2870 | /* Clear any pending interrupts */ |
| 2871 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
| 2872 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
| 2873 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
| 2874 | GINTSTS_USBRST | GINTSTS_RESETDET | |
| 2875 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | |
| 2876 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
| 2877 | GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; |
| 2878 | |
| 2879 | if (hsotg->params.external_id_pin_ctl <= 0) |
| 2880 | intmsk |= GINTSTS_CONIDSTSCHNG; |
| 2881 | |
| 2882 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); |
| 2883 | |
| 2884 | if (using_dma(hsotg)) |
| 2885 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
| 2886 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), |
| 2887 | hsotg->regs + GAHBCFG); |
| 2888 | else |
| 2889 | dwc2_writel(((hsotg->dedicated_fifos) ? |
| 2890 | (GAHBCFG_NP_TXF_EMP_LVL | |
| 2891 | GAHBCFG_P_TXF_EMP_LVL) : 0) | |
| 2892 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); |
| 2893 | |
| 2894 | /* |
| 2895 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
| 2896 | * when we have no data to transfer. Otherwise we get being flooded by |
| 2897 | * interrupts. |
| 2898 | */ |
| 2899 | |
| 2900 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
| 2901 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
| 2902 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
| 2903 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
| 2904 | hsotg->regs + DIEPMSK); |
| 2905 | |
| 2906 | /* |
| 2907 | * don't need XferCompl, we get that from RXFIFO in slave mode. In |
| 2908 | * DMA mode we may need this and StsPhseRcvd. |
| 2909 | */ |
| 2910 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
| 2911 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
| 2912 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
| 2913 | DOEPMSK_SETUPMSK, |
| 2914 | hsotg->regs + DOEPMSK); |
| 2915 | |
| 2916 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
| 2917 | |
| 2918 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", |
| 2919 | dwc2_readl(hsotg->regs + DIEPCTL0), |
| 2920 | dwc2_readl(hsotg->regs + DOEPCTL0)); |
| 2921 | |
| 2922 | /* enable in and out endpoint interrupts */ |
| 2923 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
| 2924 | |
| 2925 | /* |
| 2926 | * Enable the RXFIFO when in slave mode, as this is how we collect |
| 2927 | * the data. In DMA mode, we get events from the FIFO but also |
| 2928 | * things we cannot process, so do not use it. |
| 2929 | */ |
| 2930 | if (!using_dma(hsotg)) |
| 2931 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
| 2932 | |
| 2933 | /* Enable interrupts for EP0 in and out */ |
| 2934 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
| 2935 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); |
| 2936 | |
| 2937 | if (!is_usb_reset) { |
| 2938 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
| 2939 | udelay(10); /* see openiboot */ |
| 2940 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
| 2941 | } |
| 2942 | |
| 2943 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
| 2944 | |
| 2945 | /* |
| 2946 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
| 2947 | * writing to the EPCTL register.. |
| 2948 | */ |
| 2949 | |
| 2950 | /* set to read 1 8byte packet */ |
| 2951 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
| 2952 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
| 2953 | |
| 2954 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
| 2955 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
| 2956 | DXEPCTL_USBACTEP, |
| 2957 | hsotg->regs + DOEPCTL0); |
| 2958 | |
| 2959 | /* enable, but don't activate EP0in */ |
| 2960 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
| 2961 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
| 2962 | |
| 2963 | dwc2_hsotg_enqueue_setup(hsotg); |
| 2964 | |
| 2965 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", |
| 2966 | dwc2_readl(hsotg->regs + DIEPCTL0), |
| 2967 | dwc2_readl(hsotg->regs + DOEPCTL0)); |
| 2968 | |
| 2969 | /* clear global NAKs */ |
| 2970 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
| 2971 | if (!is_usb_reset) |
| 2972 | val |= DCTL_SFTDISCON; |
| 2973 | __orr32(hsotg->regs + DCTL, val); |
| 2974 | |
| 2975 | /* must be at-least 3ms to allow bus to see disconnect */ |
| 2976 | mdelay(3); |
| 2977 | |
| 2978 | hsotg->lx_state = DWC2_L0; |
| 2979 | } |
| 2980 | |
| 2981 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
| 2982 | { |
| 2983 | /* set the soft-disconnect bit */ |
| 2984 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
| 2985 | } |
| 2986 | |
| 2987 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
| 2988 | { |
| 2989 | /* remove the soft-disconnect and let's go */ |
| 2990 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
| 2991 | } |
| 2992 | |
| 2993 | /** |
| 2994 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. |
| 2995 | * @hsotg: The device state: |
| 2996 | * |
| 2997 | * This interrupt indicates one of the following conditions occurred while |
| 2998 | * transmitting an ISOC transaction. |
| 2999 | * - Corrupted IN Token for ISOC EP. |
| 3000 | * - Packet not complete in FIFO. |
| 3001 | * |
| 3002 | * The following actions will be taken: |
| 3003 | * - Determine the EP |
| 3004 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO |
| 3005 | */ |
| 3006 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) |
| 3007 | { |
| 3008 | struct dwc2_hsotg_ep *hs_ep; |
| 3009 | u32 epctrl; |
| 3010 | u32 idx; |
| 3011 | |
| 3012 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); |
| 3013 | |
| 3014 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { |
| 3015 | hs_ep = hsotg->eps_in[idx]; |
| 3016 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); |
| 3017 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && |
| 3018 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
| 3019 | epctrl |= DXEPCTL_SNAK; |
| 3020 | epctrl |= DXEPCTL_EPDIS; |
| 3021 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); |
| 3022 | } |
| 3023 | } |
| 3024 | |
| 3025 | /* Clear interrupt */ |
| 3026 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); |
| 3027 | } |
| 3028 | |
| 3029 | /** |
| 3030 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt |
| 3031 | * @hsotg: The device state: |
| 3032 | * |
| 3033 | * This interrupt indicates one of the following conditions occurred while |
| 3034 | * transmitting an ISOC transaction. |
| 3035 | * - Corrupted OUT Token for ISOC EP. |
| 3036 | * - Packet not complete in FIFO. |
| 3037 | * |
| 3038 | * The following actions will be taken: |
| 3039 | * - Determine the EP |
| 3040 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. |
| 3041 | */ |
| 3042 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) |
| 3043 | { |
| 3044 | u32 gintsts; |
| 3045 | u32 gintmsk; |
| 3046 | u32 epctrl; |
| 3047 | struct dwc2_hsotg_ep *hs_ep; |
| 3048 | int idx; |
| 3049 | |
| 3050 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); |
| 3051 | |
| 3052 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { |
| 3053 | hs_ep = hsotg->eps_out[idx]; |
| 3054 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); |
| 3055 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && |
| 3056 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
| 3057 | /* Unmask GOUTNAKEFF interrupt */ |
| 3058 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
| 3059 | gintmsk |= GINTSTS_GOUTNAKEFF; |
| 3060 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
| 3061 | |
| 3062 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
| 3063 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) |
| 3064 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
| 3065 | } |
| 3066 | } |
| 3067 | |
| 3068 | /* Clear interrupt */ |
| 3069 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); |
| 3070 | } |
| 3071 | |
| 3072 | /** |
| 3073 | * dwc2_hsotg_irq - handle device interrupt |
| 3074 | * @irq: The IRQ number triggered |
| 3075 | * @pw: The pw value when registered the handler. |
| 3076 | */ |
| 3077 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
| 3078 | { |
| 3079 | struct dwc2_hsotg *hsotg = pw; |
| 3080 | int retry_count = 8; |
| 3081 | u32 gintsts; |
| 3082 | u32 gintmsk; |
| 3083 | |
| 3084 | if (!dwc2_is_device_mode(hsotg)) |
| 3085 | return IRQ_NONE; |
| 3086 | |
| 3087 | spin_lock(&hsotg->lock); |
| 3088 | irq_retry: |
| 3089 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
| 3090 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
| 3091 | |
| 3092 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", |
| 3093 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); |
| 3094 | |
| 3095 | gintsts &= gintmsk; |
| 3096 | |
| 3097 | if (gintsts & GINTSTS_RESETDET) { |
| 3098 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); |
| 3099 | |
| 3100 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); |
| 3101 | |
| 3102 | /* This event must be used only if controller is suspended */ |
| 3103 | if (hsotg->lx_state == DWC2_L2) { |
| 3104 | dwc2_exit_hibernation(hsotg, true); |
| 3105 | hsotg->lx_state = DWC2_L0; |
| 3106 | } |
| 3107 | } |
| 3108 | |
| 3109 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { |
| 3110 | |
| 3111 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); |
| 3112 | u32 connected = hsotg->connected; |
| 3113 | |
| 3114 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); |
| 3115 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", |
| 3116 | dwc2_readl(hsotg->regs + GNPTXSTS)); |
| 3117 | |
| 3118 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
| 3119 | |
| 3120 | /* Report disconnection if it is not already done. */ |
| 3121 | dwc2_hsotg_disconnect(hsotg); |
| 3122 | |
| 3123 | if (usb_status & GOTGCTL_BSESVLD && connected) |
| 3124 | dwc2_hsotg_core_init_disconnected(hsotg, true); |
| 3125 | } |
| 3126 | |
| 3127 | if (gintsts & GINTSTS_ENUMDONE) { |
| 3128 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
| 3129 | |
| 3130 | dwc2_hsotg_irq_enumdone(hsotg); |
| 3131 | } |
| 3132 | |
| 3133 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
| 3134 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
| 3135 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
| 3136 | u32 daint_out, daint_in; |
| 3137 | int ep; |
| 3138 | |
| 3139 | daint &= daintmsk; |
| 3140 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
| 3141 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); |
| 3142 | |
| 3143 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
| 3144 | |
| 3145 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
| 3146 | ep++, daint_out >>= 1) { |
| 3147 | if (daint_out & 1) |
| 3148 | dwc2_hsotg_epint(hsotg, ep, 0); |
| 3149 | } |
| 3150 | |
| 3151 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
| 3152 | ep++, daint_in >>= 1) { |
| 3153 | if (daint_in & 1) |
| 3154 | dwc2_hsotg_epint(hsotg, ep, 1); |
| 3155 | } |
| 3156 | } |
| 3157 | |
| 3158 | /* check both FIFOs */ |
| 3159 | |
| 3160 | if (gintsts & GINTSTS_NPTXFEMP) { |
| 3161 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
| 3162 | |
| 3163 | /* |
| 3164 | * Disable the interrupt to stop it happening again |
| 3165 | * unless one of these endpoint routines decides that |
| 3166 | * it needs re-enabling |
| 3167 | */ |
| 3168 | |
| 3169 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
| 3170 | dwc2_hsotg_irq_fifoempty(hsotg, false); |
| 3171 | } |
| 3172 | |
| 3173 | if (gintsts & GINTSTS_PTXFEMP) { |
| 3174 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
| 3175 | |
| 3176 | /* See note in GINTSTS_NPTxFEmp */ |
| 3177 | |
| 3178 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
| 3179 | dwc2_hsotg_irq_fifoempty(hsotg, true); |
| 3180 | } |
| 3181 | |
| 3182 | if (gintsts & GINTSTS_RXFLVL) { |
| 3183 | /* |
| 3184 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, |
| 3185 | * we need to retry dwc2_hsotg_handle_rx if this is still |
| 3186 | * set. |
| 3187 | */ |
| 3188 | |
| 3189 | dwc2_hsotg_handle_rx(hsotg); |
| 3190 | } |
| 3191 | |
| 3192 | if (gintsts & GINTSTS_ERLYSUSP) { |
| 3193 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
| 3194 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
| 3195 | } |
| 3196 | |
| 3197 | /* |
| 3198 | * these next two seem to crop-up occasionally causing the core |
| 3199 | * to shutdown the USB transfer, so try clearing them and logging |
| 3200 | * the occurrence. |
| 3201 | */ |
| 3202 | |
| 3203 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
| 3204 | u8 idx; |
| 3205 | u32 epctrl; |
| 3206 | u32 gintmsk; |
| 3207 | struct dwc2_hsotg_ep *hs_ep; |
| 3208 | |
| 3209 | /* Mask this interrupt */ |
| 3210 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
| 3211 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
| 3212 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
| 3213 | |
| 3214 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); |
| 3215 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { |
| 3216 | hs_ep = hsotg->eps_out[idx]; |
| 3217 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); |
| 3218 | |
| 3219 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { |
| 3220 | epctrl |= DXEPCTL_SNAK; |
| 3221 | epctrl |= DXEPCTL_EPDIS; |
| 3222 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); |
| 3223 | } |
| 3224 | } |
| 3225 | |
| 3226 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
| 3227 | } |
| 3228 | |
| 3229 | if (gintsts & GINTSTS_GINNAKEFF) { |
| 3230 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
| 3231 | |
| 3232 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
| 3233 | |
| 3234 | dwc2_hsotg_dump(hsotg); |
| 3235 | } |
| 3236 | |
| 3237 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
| 3238 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); |
| 3239 | |
| 3240 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
| 3241 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); |
| 3242 | |
| 3243 | /* |
| 3244 | * if we've had fifo events, we should try and go around the |
| 3245 | * loop again to see if there's any point in returning yet. |
| 3246 | */ |
| 3247 | |
| 3248 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) |
| 3249 | goto irq_retry; |
| 3250 | |
| 3251 | spin_unlock(&hsotg->lock); |
| 3252 | |
| 3253 | return IRQ_HANDLED; |
| 3254 | } |
| 3255 | |
| 3256 | /** |
| 3257 | * dwc2_hsotg_ep_enable - enable the given endpoint |
| 3258 | * @ep: The USB endpint to configure |
| 3259 | * @desc: The USB endpoint descriptor to configure with. |
| 3260 | * |
| 3261 | * This is called from the USB gadget code's usb_ep_enable(). |
| 3262 | */ |
| 3263 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
| 3264 | const struct usb_endpoint_descriptor *desc) |
| 3265 | { |
| 3266 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 3267 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 3268 | unsigned long flags; |
| 3269 | unsigned int index = hs_ep->index; |
| 3270 | u32 epctrl_reg; |
| 3271 | u32 epctrl; |
| 3272 | u32 mps; |
| 3273 | u32 mc; |
| 3274 | u32 mask; |
| 3275 | unsigned int dir_in; |
| 3276 | unsigned int i, val, size; |
| 3277 | int ret = 0; |
| 3278 | |
| 3279 | dev_dbg(hsotg->dev, |
| 3280 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", |
| 3281 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, |
| 3282 | desc->wMaxPacketSize, desc->bInterval); |
| 3283 | |
| 3284 | /* not to be called for EP0 */ |
| 3285 | if (index == 0) { |
| 3286 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); |
| 3287 | return -EINVAL; |
| 3288 | } |
| 3289 | |
| 3290 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; |
| 3291 | if (dir_in != hs_ep->dir_in) { |
| 3292 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); |
| 3293 | return -EINVAL; |
| 3294 | } |
| 3295 | |
| 3296 | mps = usb_endpoint_maxp(desc); |
| 3297 | mc = usb_endpoint_maxp_mult(desc); |
| 3298 | |
| 3299 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
| 3300 | |
| 3301 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
| 3302 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
| 3303 | |
| 3304 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", |
| 3305 | __func__, epctrl, epctrl_reg); |
| 3306 | |
| 3307 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
| 3308 | if (using_desc_dma(hsotg)) { |
| 3309 | hs_ep->desc_list = dma_alloc_coherent(hsotg->dev, |
| 3310 | MAX_DMA_DESC_NUM_GENERIC * |
| 3311 | sizeof(struct dwc2_dma_desc), |
| 3312 | &hs_ep->desc_list_dma, GFP_KERNEL); |
| 3313 | if (!hs_ep->desc_list) { |
| 3314 | ret = -ENOMEM; |
| 3315 | goto error2; |
| 3316 | } |
| 3317 | } |
| 3318 | |
| 3319 | spin_lock_irqsave(&hsotg->lock, flags); |
| 3320 | |
| 3321 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
| 3322 | epctrl |= DXEPCTL_MPS(mps); |
| 3323 | |
| 3324 | /* |
| 3325 | * mark the endpoint as active, otherwise the core may ignore |
| 3326 | * transactions entirely for this endpoint |
| 3327 | */ |
| 3328 | epctrl |= DXEPCTL_USBACTEP; |
| 3329 | |
| 3330 | /* update the endpoint state */ |
| 3331 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
| 3332 | |
| 3333 | /* default, set to non-periodic */ |
| 3334 | hs_ep->isochronous = 0; |
| 3335 | hs_ep->periodic = 0; |
| 3336 | hs_ep->halted = 0; |
| 3337 | hs_ep->interval = desc->bInterval; |
| 3338 | |
| 3339 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
| 3340 | case USB_ENDPOINT_XFER_ISOC: |
| 3341 | epctrl |= DXEPCTL_EPTYPE_ISO; |
| 3342 | epctrl |= DXEPCTL_SETEVENFR; |
| 3343 | hs_ep->isochronous = 1; |
| 3344 | hs_ep->interval = 1 << (desc->bInterval - 1); |
| 3345 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
| 3346 | if (dir_in) { |
| 3347 | hs_ep->periodic = 1; |
| 3348 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
| 3349 | mask |= DIEPMSK_NAKMSK; |
| 3350 | dwc2_writel(mask, hsotg->regs + DIEPMSK); |
| 3351 | } else { |
| 3352 | mask = dwc2_readl(hsotg->regs + DOEPMSK); |
| 3353 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
| 3354 | dwc2_writel(mask, hsotg->regs + DOEPMSK); |
| 3355 | } |
| 3356 | break; |
| 3357 | |
| 3358 | case USB_ENDPOINT_XFER_BULK: |
| 3359 | epctrl |= DXEPCTL_EPTYPE_BULK; |
| 3360 | break; |
| 3361 | |
| 3362 | case USB_ENDPOINT_XFER_INT: |
| 3363 | if (dir_in) |
| 3364 | hs_ep->periodic = 1; |
| 3365 | |
| 3366 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
| 3367 | hs_ep->interval = 1 << (desc->bInterval - 1); |
| 3368 | |
| 3369 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
| 3370 | break; |
| 3371 | |
| 3372 | case USB_ENDPOINT_XFER_CONTROL: |
| 3373 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
| 3374 | break; |
| 3375 | } |
| 3376 | |
| 3377 | /* |
| 3378 | * if the hardware has dedicated fifos, we must give each IN EP |
| 3379 | * a unique tx-fifo even if it is non-periodic. |
| 3380 | */ |
| 3381 | if (dir_in && hsotg->dedicated_fifos) { |
| 3382 | u32 fifo_index = 0; |
| 3383 | u32 fifo_size = UINT_MAX; |
| 3384 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
| 3385 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
| 3386 | if (hsotg->fifo_map & (1<<i)) |
| 3387 | continue; |
| 3388 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
| 3389 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
| 3390 | if (val < size) |
| 3391 | continue; |
| 3392 | /* Search for smallest acceptable fifo */ |
| 3393 | if (val < fifo_size) { |
| 3394 | fifo_size = val; |
| 3395 | fifo_index = i; |
| 3396 | } |
| 3397 | } |
| 3398 | if (!fifo_index) { |
| 3399 | dev_err(hsotg->dev, |
| 3400 | "%s: No suitable fifo found\n", __func__); |
| 3401 | ret = -ENOMEM; |
| 3402 | goto error1; |
| 3403 | } |
| 3404 | hsotg->fifo_map |= 1 << fifo_index; |
| 3405 | epctrl |= DXEPCTL_TXFNUM(fifo_index); |
| 3406 | hs_ep->fifo_index = fifo_index; |
| 3407 | hs_ep->fifo_size = fifo_size; |
| 3408 | } |
| 3409 | |
| 3410 | /* for non control endpoints, set PID to D0 */ |
| 3411 | if (index && !hs_ep->isochronous) |
| 3412 | epctrl |= DXEPCTL_SETD0PID; |
| 3413 | |
| 3414 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
| 3415 | __func__, epctrl); |
| 3416 | |
| 3417 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
| 3418 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
| 3419 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
| 3420 | |
| 3421 | /* enable the endpoint interrupt */ |
| 3422 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
| 3423 | |
| 3424 | error1: |
| 3425 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 3426 | |
| 3427 | error2: |
| 3428 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { |
| 3429 | dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
| 3430 | sizeof(struct dwc2_dma_desc), |
| 3431 | hs_ep->desc_list, hs_ep->desc_list_dma); |
| 3432 | hs_ep->desc_list = NULL; |
| 3433 | } |
| 3434 | |
| 3435 | return ret; |
| 3436 | } |
| 3437 | |
| 3438 | /** |
| 3439 | * dwc2_hsotg_ep_disable - disable given endpoint |
| 3440 | * @ep: The endpoint to disable. |
| 3441 | */ |
| 3442 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
| 3443 | { |
| 3444 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 3445 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
| 3446 | int dir_in = hs_ep->dir_in; |
| 3447 | int index = hs_ep->index; |
| 3448 | unsigned long flags; |
| 3449 | u32 epctrl_reg; |
| 3450 | u32 ctrl; |
| 3451 | |
| 3452 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
| 3453 | |
| 3454 | if (ep == &hsotg->eps_out[0]->ep) { |
| 3455 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
| 3456 | return -EINVAL; |
| 3457 | } |
| 3458 | |
| 3459 | /* Remove DMA memory allocated for non-control Endpoints */ |
| 3460 | if (using_desc_dma(hsotg)) { |
| 3461 | dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
| 3462 | sizeof(struct dwc2_dma_desc), |
| 3463 | hs_ep->desc_list, hs_ep->desc_list_dma); |
| 3464 | hs_ep->desc_list = NULL; |
| 3465 | } |
| 3466 | |
| 3467 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
| 3468 | |
| 3469 | spin_lock_irqsave(&hsotg->lock, flags); |
| 3470 | |
| 3471 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
| 3472 | ctrl &= ~DXEPCTL_EPENA; |
| 3473 | ctrl &= ~DXEPCTL_USBACTEP; |
| 3474 | ctrl |= DXEPCTL_SNAK; |
| 3475 | |
| 3476 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
| 3477 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
| 3478 | |
| 3479 | /* disable endpoint interrupts */ |
| 3480 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
| 3481 | |
| 3482 | /* terminate all requests with shutdown */ |
| 3483 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); |
| 3484 | |
| 3485 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
| 3486 | hs_ep->fifo_index = 0; |
| 3487 | hs_ep->fifo_size = 0; |
| 3488 | |
| 3489 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 3490 | return 0; |
| 3491 | } |
| 3492 | |
| 3493 | /** |
| 3494 | * on_list - check request is on the given endpoint |
| 3495 | * @ep: The endpoint to check. |
| 3496 | * @test: The request to test if it is on the endpoint. |
| 3497 | */ |
| 3498 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
| 3499 | { |
| 3500 | struct dwc2_hsotg_req *req, *treq; |
| 3501 | |
| 3502 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { |
| 3503 | if (req == test) |
| 3504 | return true; |
| 3505 | } |
| 3506 | |
| 3507 | return false; |
| 3508 | } |
| 3509 | |
| 3510 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
| 3511 | u32 bit, u32 timeout) |
| 3512 | { |
| 3513 | u32 i; |
| 3514 | |
| 3515 | for (i = 0; i < timeout; i++) { |
| 3516 | if (dwc2_readl(hs_otg->regs + reg) & bit) |
| 3517 | return 0; |
| 3518 | udelay(1); |
| 3519 | } |
| 3520 | |
| 3521 | return -ETIMEDOUT; |
| 3522 | } |
| 3523 | |
| 3524 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
| 3525 | struct dwc2_hsotg_ep *hs_ep) |
| 3526 | { |
| 3527 | u32 epctrl_reg; |
| 3528 | u32 epint_reg; |
| 3529 | |
| 3530 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : |
| 3531 | DOEPCTL(hs_ep->index); |
| 3532 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : |
| 3533 | DOEPINT(hs_ep->index); |
| 3534 | |
| 3535 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, |
| 3536 | hs_ep->name); |
| 3537 | if (hs_ep->dir_in) { |
| 3538 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); |
| 3539 | /* Wait for Nak effect */ |
| 3540 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, |
| 3541 | DXEPINT_INEPNAKEFF, 100)) |
| 3542 | dev_warn(hsotg->dev, |
| 3543 | "%s: timeout DIEPINT.NAKEFF\n", __func__); |
| 3544 | } else { |
| 3545 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) |
| 3546 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
| 3547 | |
| 3548 | /* Wait for global nak to take effect */ |
| 3549 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, |
| 3550 | GINTSTS_GOUTNAKEFF, 100)) |
| 3551 | dev_warn(hsotg->dev, |
| 3552 | "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__); |
| 3553 | } |
| 3554 | |
| 3555 | /* Disable ep */ |
| 3556 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
| 3557 | |
| 3558 | /* Wait for ep to be disabled */ |
| 3559 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) |
| 3560 | dev_warn(hsotg->dev, |
| 3561 | "%s: timeout DOEPCTL.EPDisable\n", __func__); |
| 3562 | |
| 3563 | if (hs_ep->dir_in) { |
| 3564 | if (hsotg->dedicated_fifos) { |
| 3565 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | |
| 3566 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); |
| 3567 | /* Wait for fifo flush */ |
| 3568 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, |
| 3569 | GRSTCTL_TXFFLSH, 100)) |
| 3570 | dev_warn(hsotg->dev, |
| 3571 | "%s: timeout flushing fifos\n", |
| 3572 | __func__); |
| 3573 | } |
| 3574 | /* TODO: Flush shared tx fifo */ |
| 3575 | } else { |
| 3576 | /* Remove global NAKs */ |
| 3577 | __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
| 3578 | } |
| 3579 | } |
| 3580 | |
| 3581 | /** |
| 3582 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
| 3583 | * @ep: The endpoint to dequeue. |
| 3584 | * @req: The request to be removed from a queue. |
| 3585 | */ |
| 3586 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
| 3587 | { |
| 3588 | struct dwc2_hsotg_req *hs_req = our_req(req); |
| 3589 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 3590 | struct dwc2_hsotg *hs = hs_ep->parent; |
| 3591 | unsigned long flags; |
| 3592 | |
| 3593 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
| 3594 | |
| 3595 | spin_lock_irqsave(&hs->lock, flags); |
| 3596 | |
| 3597 | if (!on_list(hs_ep, hs_req)) { |
| 3598 | spin_unlock_irqrestore(&hs->lock, flags); |
| 3599 | return -EINVAL; |
| 3600 | } |
| 3601 | |
| 3602 | /* Dequeue already started request */ |
| 3603 | if (req == &hs_ep->req->req) |
| 3604 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); |
| 3605 | |
| 3606 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
| 3607 | spin_unlock_irqrestore(&hs->lock, flags); |
| 3608 | |
| 3609 | return 0; |
| 3610 | } |
| 3611 | |
| 3612 | /** |
| 3613 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
| 3614 | * @ep: The endpoint to set halt. |
| 3615 | * @value: Set or unset the halt. |
| 3616 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
| 3617 | * the endpoint is busy processing requests. |
| 3618 | * |
| 3619 | * We need to stall the endpoint immediately if request comes from set_feature |
| 3620 | * protocol command handler. |
| 3621 | */ |
| 3622 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
| 3623 | { |
| 3624 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 3625 | struct dwc2_hsotg *hs = hs_ep->parent; |
| 3626 | int index = hs_ep->index; |
| 3627 | u32 epreg; |
| 3628 | u32 epctl; |
| 3629 | u32 xfertype; |
| 3630 | |
| 3631 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); |
| 3632 | |
| 3633 | if (index == 0) { |
| 3634 | if (value) |
| 3635 | dwc2_hsotg_stall_ep0(hs); |
| 3636 | else |
| 3637 | dev_warn(hs->dev, |
| 3638 | "%s: can't clear halt on ep0\n", __func__); |
| 3639 | return 0; |
| 3640 | } |
| 3641 | |
| 3642 | if (hs_ep->isochronous) { |
| 3643 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); |
| 3644 | return -EINVAL; |
| 3645 | } |
| 3646 | |
| 3647 | if (!now && value && !list_empty(&hs_ep->queue)) { |
| 3648 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", |
| 3649 | ep->name); |
| 3650 | return -EAGAIN; |
| 3651 | } |
| 3652 | |
| 3653 | if (hs_ep->dir_in) { |
| 3654 | epreg = DIEPCTL(index); |
| 3655 | epctl = dwc2_readl(hs->regs + epreg); |
| 3656 | |
| 3657 | if (value) { |
| 3658 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
| 3659 | if (epctl & DXEPCTL_EPENA) |
| 3660 | epctl |= DXEPCTL_EPDIS; |
| 3661 | } else { |
| 3662 | epctl &= ~DXEPCTL_STALL; |
| 3663 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; |
| 3664 | if (xfertype == DXEPCTL_EPTYPE_BULK || |
| 3665 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
| 3666 | epctl |= DXEPCTL_SETD0PID; |
| 3667 | } |
| 3668 | dwc2_writel(epctl, hs->regs + epreg); |
| 3669 | } else { |
| 3670 | |
| 3671 | epreg = DOEPCTL(index); |
| 3672 | epctl = dwc2_readl(hs->regs + epreg); |
| 3673 | |
| 3674 | if (value) |
| 3675 | epctl |= DXEPCTL_STALL; |
| 3676 | else { |
| 3677 | epctl &= ~DXEPCTL_STALL; |
| 3678 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; |
| 3679 | if (xfertype == DXEPCTL_EPTYPE_BULK || |
| 3680 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
| 3681 | epctl |= DXEPCTL_SETD0PID; |
| 3682 | } |
| 3683 | dwc2_writel(epctl, hs->regs + epreg); |
| 3684 | } |
| 3685 | |
| 3686 | hs_ep->halted = value; |
| 3687 | |
| 3688 | return 0; |
| 3689 | } |
| 3690 | |
| 3691 | /** |
| 3692 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
| 3693 | * @ep: The endpoint to set halt. |
| 3694 | * @value: Set or unset the halt. |
| 3695 | */ |
| 3696 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
| 3697 | { |
| 3698 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
| 3699 | struct dwc2_hsotg *hs = hs_ep->parent; |
| 3700 | unsigned long flags = 0; |
| 3701 | int ret = 0; |
| 3702 | |
| 3703 | spin_lock_irqsave(&hs->lock, flags); |
| 3704 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
| 3705 | spin_unlock_irqrestore(&hs->lock, flags); |
| 3706 | |
| 3707 | return ret; |
| 3708 | } |
| 3709 | |
| 3710 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
| 3711 | .enable = dwc2_hsotg_ep_enable, |
| 3712 | .disable = dwc2_hsotg_ep_disable, |
| 3713 | .alloc_request = dwc2_hsotg_ep_alloc_request, |
| 3714 | .free_request = dwc2_hsotg_ep_free_request, |
| 3715 | .queue = dwc2_hsotg_ep_queue_lock, |
| 3716 | .dequeue = dwc2_hsotg_ep_dequeue, |
| 3717 | .set_halt = dwc2_hsotg_ep_sethalt_lock, |
| 3718 | /* note, don't believe we have any call for the fifo routines */ |
| 3719 | }; |
| 3720 | |
| 3721 | /** |
| 3722 | * dwc2_hsotg_init - initalize the usb core |
| 3723 | * @hsotg: The driver state |
| 3724 | */ |
| 3725 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
| 3726 | { |
| 3727 | u32 trdtim; |
| 3728 | u32 usbcfg; |
| 3729 | /* unmask subset of endpoint interrupts */ |
| 3730 | |
| 3731 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
| 3732 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
| 3733 | hsotg->regs + DIEPMSK); |
| 3734 | |
| 3735 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
| 3736 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
| 3737 | hsotg->regs + DOEPMSK); |
| 3738 | |
| 3739 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
| 3740 | |
| 3741 | /* Be in disconnected state until gadget is registered */ |
| 3742 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
| 3743 | |
| 3744 | /* setup fifos */ |
| 3745 | |
| 3746 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", |
| 3747 | dwc2_readl(hsotg->regs + GRXFSIZ), |
| 3748 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); |
| 3749 | |
| 3750 | dwc2_hsotg_init_fifo(hsotg); |
| 3751 | |
| 3752 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
| 3753 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); |
| 3754 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | |
| 3755 | GUSBCFG_HNPCAP); |
| 3756 | |
| 3757 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
| 3758 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
| 3759 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
| 3760 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); |
| 3761 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
| 3762 | |
| 3763 | if (using_dma(hsotg)) |
| 3764 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); |
| 3765 | } |
| 3766 | |
| 3767 | /** |
| 3768 | * dwc2_hsotg_udc_start - prepare the udc for work |
| 3769 | * @gadget: The usb gadget state |
| 3770 | * @driver: The usb gadget driver |
| 3771 | * |
| 3772 | * Perform initialization to prepare udc device and driver |
| 3773 | * to work. |
| 3774 | */ |
| 3775 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
| 3776 | struct usb_gadget_driver *driver) |
| 3777 | { |
| 3778 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
| 3779 | unsigned long flags; |
| 3780 | int ret; |
| 3781 | |
| 3782 | if (!hsotg) { |
| 3783 | pr_err("%s: called with no device\n", __func__); |
| 3784 | return -ENODEV; |
| 3785 | } |
| 3786 | |
| 3787 | if (!driver) { |
| 3788 | dev_err(hsotg->dev, "%s: no driver\n", __func__); |
| 3789 | return -EINVAL; |
| 3790 | } |
| 3791 | |
| 3792 | if (driver->max_speed < USB_SPEED_FULL) |
| 3793 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
| 3794 | |
| 3795 | if (!driver->setup) { |
| 3796 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
| 3797 | return -EINVAL; |
| 3798 | } |
| 3799 | |
| 3800 | WARN_ON(hsotg->driver); |
| 3801 | |
| 3802 | driver->driver.bus = NULL; |
| 3803 | hsotg->driver = driver; |
| 3804 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
| 3805 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
| 3806 | |
| 3807 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
| 3808 | ret = dwc2_lowlevel_hw_enable(hsotg); |
| 3809 | if (ret) |
| 3810 | goto err; |
| 3811 | } |
| 3812 | |
| 3813 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
| 3814 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); |
| 3815 | |
| 3816 | spin_lock_irqsave(&hsotg->lock, flags); |
| 3817 | if (dwc2_hw_is_device(hsotg)) { |
| 3818 | dwc2_hsotg_init(hsotg); |
| 3819 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
| 3820 | } |
| 3821 | |
| 3822 | hsotg->enabled = 0; |
| 3823 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 3824 | |
| 3825 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
| 3826 | |
| 3827 | return 0; |
| 3828 | |
| 3829 | err: |
| 3830 | hsotg->driver = NULL; |
| 3831 | return ret; |
| 3832 | } |
| 3833 | |
| 3834 | /** |
| 3835 | * dwc2_hsotg_udc_stop - stop the udc |
| 3836 | * @gadget: The usb gadget state |
| 3837 | * @driver: The usb gadget driver |
| 3838 | * |
| 3839 | * Stop udc hw block and stay tunned for future transmissions |
| 3840 | */ |
| 3841 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
| 3842 | { |
| 3843 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
| 3844 | unsigned long flags = 0; |
| 3845 | int ep; |
| 3846 | |
| 3847 | if (!hsotg) |
| 3848 | return -ENODEV; |
| 3849 | |
| 3850 | /* all endpoints should be shutdown */ |
| 3851 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
| 3852 | if (hsotg->eps_in[ep]) |
| 3853 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
| 3854 | if (hsotg->eps_out[ep]) |
| 3855 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
| 3856 | } |
| 3857 | |
| 3858 | spin_lock_irqsave(&hsotg->lock, flags); |
| 3859 | |
| 3860 | hsotg->driver = NULL; |
| 3861 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
| 3862 | hsotg->enabled = 0; |
| 3863 | |
| 3864 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 3865 | |
| 3866 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
| 3867 | otg_set_peripheral(hsotg->uphy->otg, NULL); |
| 3868 | |
| 3869 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
| 3870 | dwc2_lowlevel_hw_disable(hsotg); |
| 3871 | |
| 3872 | return 0; |
| 3873 | } |
| 3874 | |
| 3875 | /** |
| 3876 | * dwc2_hsotg_gadget_getframe - read the frame number |
| 3877 | * @gadget: The usb gadget state |
| 3878 | * |
| 3879 | * Read the {micro} frame number |
| 3880 | */ |
| 3881 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
| 3882 | { |
| 3883 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
| 3884 | } |
| 3885 | |
| 3886 | /** |
| 3887 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
| 3888 | * @gadget: The usb gadget state |
| 3889 | * @is_on: Current state of the USB PHY |
| 3890 | * |
| 3891 | * Connect/Disconnect the USB PHY pullup |
| 3892 | */ |
| 3893 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
| 3894 | { |
| 3895 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
| 3896 | unsigned long flags = 0; |
| 3897 | |
| 3898 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
| 3899 | hsotg->op_state); |
| 3900 | |
| 3901 | /* Don't modify pullup state while in host mode */ |
| 3902 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { |
| 3903 | hsotg->enabled = is_on; |
| 3904 | return 0; |
| 3905 | } |
| 3906 | |
| 3907 | spin_lock_irqsave(&hsotg->lock, flags); |
| 3908 | if (is_on) { |
| 3909 | hsotg->enabled = 1; |
| 3910 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
| 3911 | dwc2_hsotg_core_connect(hsotg); |
| 3912 | } else { |
| 3913 | dwc2_hsotg_core_disconnect(hsotg); |
| 3914 | dwc2_hsotg_disconnect(hsotg); |
| 3915 | hsotg->enabled = 0; |
| 3916 | } |
| 3917 | |
| 3918 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
| 3919 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 3920 | |
| 3921 | return 0; |
| 3922 | } |
| 3923 | |
| 3924 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
| 3925 | { |
| 3926 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
| 3927 | unsigned long flags; |
| 3928 | |
| 3929 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); |
| 3930 | spin_lock_irqsave(&hsotg->lock, flags); |
| 3931 | |
| 3932 | /* |
| 3933 | * If controller is hibernated, it must exit from hibernation |
| 3934 | * before being initialized / de-initialized |
| 3935 | */ |
| 3936 | if (hsotg->lx_state == DWC2_L2) |
| 3937 | dwc2_exit_hibernation(hsotg, false); |
| 3938 | |
| 3939 | if (is_active) { |
| 3940 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
| 3941 | |
| 3942 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
| 3943 | if (hsotg->enabled) |
| 3944 | dwc2_hsotg_core_connect(hsotg); |
| 3945 | } else { |
| 3946 | dwc2_hsotg_core_disconnect(hsotg); |
| 3947 | dwc2_hsotg_disconnect(hsotg); |
| 3948 | } |
| 3949 | |
| 3950 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 3951 | return 0; |
| 3952 | } |
| 3953 | |
| 3954 | /** |
| 3955 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
| 3956 | * @gadget: The usb gadget state |
| 3957 | * @mA: Amount of current |
| 3958 | * |
| 3959 | * Report how much power the device may consume to the phy. |
| 3960 | */ |
| 3961 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
| 3962 | { |
| 3963 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
| 3964 | |
| 3965 | if (IS_ERR_OR_NULL(hsotg->uphy)) |
| 3966 | return -ENOTSUPP; |
| 3967 | return usb_phy_set_power(hsotg->uphy, mA); |
| 3968 | } |
| 3969 | |
| 3970 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
| 3971 | .get_frame = dwc2_hsotg_gadget_getframe, |
| 3972 | .udc_start = dwc2_hsotg_udc_start, |
| 3973 | .udc_stop = dwc2_hsotg_udc_stop, |
| 3974 | .pullup = dwc2_hsotg_pullup, |
| 3975 | .vbus_session = dwc2_hsotg_vbus_session, |
| 3976 | .vbus_draw = dwc2_hsotg_vbus_draw, |
| 3977 | }; |
| 3978 | |
| 3979 | /** |
| 3980 | * dwc2_hsotg_initep - initialise a single endpoint |
| 3981 | * @hsotg: The device state. |
| 3982 | * @hs_ep: The endpoint to be initialised. |
| 3983 | * @epnum: The endpoint number |
| 3984 | * |
| 3985 | * Initialise the given endpoint (as part of the probe and device state |
| 3986 | * creation) to give to the gadget driver. Setup the endpoint name, any |
| 3987 | * direction information and other state that may be required. |
| 3988 | */ |
| 3989 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
| 3990 | struct dwc2_hsotg_ep *hs_ep, |
| 3991 | int epnum, |
| 3992 | bool dir_in) |
| 3993 | { |
| 3994 | char *dir; |
| 3995 | |
| 3996 | if (epnum == 0) |
| 3997 | dir = ""; |
| 3998 | else if (dir_in) |
| 3999 | dir = "in"; |
| 4000 | else |
| 4001 | dir = "out"; |
| 4002 | |
| 4003 | hs_ep->dir_in = dir_in; |
| 4004 | hs_ep->index = epnum; |
| 4005 | |
| 4006 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); |
| 4007 | |
| 4008 | INIT_LIST_HEAD(&hs_ep->queue); |
| 4009 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); |
| 4010 | |
| 4011 | /* add to the list of endpoints known by the gadget driver */ |
| 4012 | if (epnum) |
| 4013 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); |
| 4014 | |
| 4015 | hs_ep->parent = hsotg; |
| 4016 | hs_ep->ep.name = hs_ep->name; |
| 4017 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
| 4018 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
| 4019 | |
| 4020 | if (epnum == 0) { |
| 4021 | hs_ep->ep.caps.type_control = true; |
| 4022 | } else { |
| 4023 | hs_ep->ep.caps.type_iso = true; |
| 4024 | hs_ep->ep.caps.type_bulk = true; |
| 4025 | hs_ep->ep.caps.type_int = true; |
| 4026 | } |
| 4027 | |
| 4028 | if (dir_in) |
| 4029 | hs_ep->ep.caps.dir_in = true; |
| 4030 | else |
| 4031 | hs_ep->ep.caps.dir_out = true; |
| 4032 | |
| 4033 | /* |
| 4034 | * if we're using dma, we need to set the next-endpoint pointer |
| 4035 | * to be something valid. |
| 4036 | */ |
| 4037 | |
| 4038 | if (using_dma(hsotg)) { |
| 4039 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
| 4040 | if (dir_in) |
| 4041 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
| 4042 | else |
| 4043 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
| 4044 | } |
| 4045 | } |
| 4046 | |
| 4047 | /** |
| 4048 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
| 4049 | * @param: The device state |
| 4050 | * |
| 4051 | * Read the USB core HW configuration registers |
| 4052 | */ |
| 4053 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
| 4054 | { |
| 4055 | u32 cfg; |
| 4056 | u32 ep_type; |
| 4057 | u32 i; |
| 4058 | |
| 4059 | /* check hardware configuration */ |
| 4060 | |
| 4061 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
| 4062 | |
| 4063 | /* Add ep0 */ |
| 4064 | hsotg->num_of_eps++; |
| 4065 | |
| 4066 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
| 4067 | GFP_KERNEL); |
| 4068 | if (!hsotg->eps_in[0]) |
| 4069 | return -ENOMEM; |
| 4070 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
| 4071 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
| 4072 | |
| 4073 | cfg = hsotg->hw_params.dev_ep_dirs; |
| 4074 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
| 4075 | ep_type = cfg & 3; |
| 4076 | /* Direction in or both */ |
| 4077 | if (!(ep_type & 2)) { |
| 4078 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, |
| 4079 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
| 4080 | if (!hsotg->eps_in[i]) |
| 4081 | return -ENOMEM; |
| 4082 | } |
| 4083 | /* Direction out or both */ |
| 4084 | if (!(ep_type & 1)) { |
| 4085 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, |
| 4086 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
| 4087 | if (!hsotg->eps_out[i]) |
| 4088 | return -ENOMEM; |
| 4089 | } |
| 4090 | } |
| 4091 | |
| 4092 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
| 4093 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; |
| 4094 | |
| 4095 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
| 4096 | hsotg->num_of_eps, |
| 4097 | hsotg->dedicated_fifos ? "dedicated" : "shared", |
| 4098 | hsotg->fifo_mem); |
| 4099 | return 0; |
| 4100 | } |
| 4101 | |
| 4102 | /** |
| 4103 | * dwc2_hsotg_dump - dump state of the udc |
| 4104 | * @param: The device state |
| 4105 | */ |
| 4106 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
| 4107 | { |
| 4108 | #ifdef DEBUG |
| 4109 | struct device *dev = hsotg->dev; |
| 4110 | void __iomem *regs = hsotg->regs; |
| 4111 | u32 val; |
| 4112 | int idx; |
| 4113 | |
| 4114 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", |
| 4115 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
| 4116 | dwc2_readl(regs + DIEPMSK)); |
| 4117 | |
| 4118 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
| 4119 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
| 4120 | |
| 4121 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", |
| 4122 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
| 4123 | |
| 4124 | /* show periodic fifo settings */ |
| 4125 | |
| 4126 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
| 4127 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
| 4128 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
| 4129 | val >> FIFOSIZE_DEPTH_SHIFT, |
| 4130 | val & FIFOSIZE_STARTADDR_MASK); |
| 4131 | } |
| 4132 | |
| 4133 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
| 4134 | dev_info(dev, |
| 4135 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, |
| 4136 | dwc2_readl(regs + DIEPCTL(idx)), |
| 4137 | dwc2_readl(regs + DIEPTSIZ(idx)), |
| 4138 | dwc2_readl(regs + DIEPDMA(idx))); |
| 4139 | |
| 4140 | val = dwc2_readl(regs + DOEPCTL(idx)); |
| 4141 | dev_info(dev, |
| 4142 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", |
| 4143 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
| 4144 | dwc2_readl(regs + DOEPTSIZ(idx)), |
| 4145 | dwc2_readl(regs + DOEPDMA(idx))); |
| 4146 | |
| 4147 | } |
| 4148 | |
| 4149 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", |
| 4150 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
| 4151 | #endif |
| 4152 | } |
| 4153 | |
| 4154 | /** |
| 4155 | * dwc2_gadget_init - init function for gadget |
| 4156 | * @dwc2: The data structure for the DWC2 driver. |
| 4157 | * @irq: The IRQ number for the controller. |
| 4158 | */ |
| 4159 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
| 4160 | { |
| 4161 | struct device *dev = hsotg->dev; |
| 4162 | int epnum; |
| 4163 | int ret; |
| 4164 | |
| 4165 | /* Dump fifo information */ |
| 4166 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", |
| 4167 | hsotg->params.g_np_tx_fifo_size); |
| 4168 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); |
| 4169 | |
| 4170 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
| 4171 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
| 4172 | hsotg->gadget.name = dev_name(dev); |
| 4173 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
| 4174 | hsotg->gadget.is_otg = 1; |
| 4175 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
| 4176 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
| 4177 | |
| 4178 | ret = dwc2_hsotg_hw_cfg(hsotg); |
| 4179 | if (ret) { |
| 4180 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); |
| 4181 | return ret; |
| 4182 | } |
| 4183 | |
| 4184 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
| 4185 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); |
| 4186 | if (!hsotg->ctrl_buff) |
| 4187 | return -ENOMEM; |
| 4188 | |
| 4189 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, |
| 4190 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); |
| 4191 | if (!hsotg->ep0_buff) |
| 4192 | return -ENOMEM; |
| 4193 | |
| 4194 | if (using_desc_dma(hsotg)) { |
| 4195 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); |
| 4196 | if (ret < 0) |
| 4197 | return ret; |
| 4198 | } |
| 4199 | |
| 4200 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
| 4201 | dev_name(hsotg->dev), hsotg); |
| 4202 | if (ret < 0) { |
| 4203 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
| 4204 | return ret; |
| 4205 | } |
| 4206 | |
| 4207 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
| 4208 | |
| 4209 | if (hsotg->num_of_eps == 0) { |
| 4210 | dev_err(dev, "wrong number of EPs (zero)\n"); |
| 4211 | return -EINVAL; |
| 4212 | } |
| 4213 | |
| 4214 | /* setup endpoint information */ |
| 4215 | |
| 4216 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); |
| 4217 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
| 4218 | |
| 4219 | /* allocate EP0 request */ |
| 4220 | |
| 4221 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
| 4222 | GFP_KERNEL); |
| 4223 | if (!hsotg->ctrl_req) { |
| 4224 | dev_err(dev, "failed to allocate ctrl req\n"); |
| 4225 | return -ENOMEM; |
| 4226 | } |
| 4227 | |
| 4228 | /* initialise the endpoints now the core has been initialised */ |
| 4229 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
| 4230 | if (hsotg->eps_in[epnum]) |
| 4231 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
| 4232 | epnum, 1); |
| 4233 | if (hsotg->eps_out[epnum]) |
| 4234 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
| 4235 | epnum, 0); |
| 4236 | } |
| 4237 | |
| 4238 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
| 4239 | if (ret) |
| 4240 | return ret; |
| 4241 | |
| 4242 | dwc2_hsotg_dump(hsotg); |
| 4243 | |
| 4244 | return 0; |
| 4245 | } |
| 4246 | |
| 4247 | /** |
| 4248 | * dwc2_hsotg_remove - remove function for hsotg driver |
| 4249 | * @pdev: The platform information for the driver |
| 4250 | */ |
| 4251 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
| 4252 | { |
| 4253 | usb_del_gadget_udc(&hsotg->gadget); |
| 4254 | |
| 4255 | return 0; |
| 4256 | } |
| 4257 | |
| 4258 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
| 4259 | { |
| 4260 | unsigned long flags; |
| 4261 | |
| 4262 | if (hsotg->lx_state != DWC2_L0) |
| 4263 | return 0; |
| 4264 | |
| 4265 | if (hsotg->driver) { |
| 4266 | int ep; |
| 4267 | |
| 4268 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
| 4269 | hsotg->driver->driver.name); |
| 4270 | |
| 4271 | spin_lock_irqsave(&hsotg->lock, flags); |
| 4272 | if (hsotg->enabled) |
| 4273 | dwc2_hsotg_core_disconnect(hsotg); |
| 4274 | dwc2_hsotg_disconnect(hsotg); |
| 4275 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
| 4276 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 4277 | |
| 4278 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
| 4279 | if (hsotg->eps_in[ep]) |
| 4280 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
| 4281 | if (hsotg->eps_out[ep]) |
| 4282 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
| 4283 | } |
| 4284 | } |
| 4285 | |
| 4286 | return 0; |
| 4287 | } |
| 4288 | |
| 4289 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
| 4290 | { |
| 4291 | unsigned long flags; |
| 4292 | |
| 4293 | if (hsotg->lx_state == DWC2_L2) |
| 4294 | return 0; |
| 4295 | |
| 4296 | if (hsotg->driver) { |
| 4297 | dev_info(hsotg->dev, "resuming usb gadget %s\n", |
| 4298 | hsotg->driver->driver.name); |
| 4299 | |
| 4300 | spin_lock_irqsave(&hsotg->lock, flags); |
| 4301 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
| 4302 | if (hsotg->enabled) |
| 4303 | dwc2_hsotg_core_connect(hsotg); |
| 4304 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 4305 | } |
| 4306 | |
| 4307 | return 0; |
| 4308 | } |
| 4309 | |
| 4310 | /** |
| 4311 | * dwc2_backup_device_registers() - Backup controller device registers. |
| 4312 | * When suspending usb bus, registers needs to be backuped |
| 4313 | * if controller power is disabled once suspended. |
| 4314 | * |
| 4315 | * @hsotg: Programming view of the DWC_otg controller |
| 4316 | */ |
| 4317 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
| 4318 | { |
| 4319 | struct dwc2_dregs_backup *dr; |
| 4320 | int i; |
| 4321 | |
| 4322 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 4323 | |
| 4324 | /* Backup dev regs */ |
| 4325 | dr = &hsotg->dr_backup; |
| 4326 | |
| 4327 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); |
| 4328 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); |
| 4329 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
| 4330 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); |
| 4331 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); |
| 4332 | |
| 4333 | for (i = 0; i < hsotg->num_of_eps; i++) { |
| 4334 | /* Backup IN EPs */ |
| 4335 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); |
| 4336 | |
| 4337 | /* Ensure DATA PID is correctly configured */ |
| 4338 | if (dr->diepctl[i] & DXEPCTL_DPID) |
| 4339 | dr->diepctl[i] |= DXEPCTL_SETD1PID; |
| 4340 | else |
| 4341 | dr->diepctl[i] |= DXEPCTL_SETD0PID; |
| 4342 | |
| 4343 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); |
| 4344 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); |
| 4345 | |
| 4346 | /* Backup OUT EPs */ |
| 4347 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); |
| 4348 | |
| 4349 | /* Ensure DATA PID is correctly configured */ |
| 4350 | if (dr->doepctl[i] & DXEPCTL_DPID) |
| 4351 | dr->doepctl[i] |= DXEPCTL_SETD1PID; |
| 4352 | else |
| 4353 | dr->doepctl[i] |= DXEPCTL_SETD0PID; |
| 4354 | |
| 4355 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); |
| 4356 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); |
| 4357 | } |
| 4358 | dr->valid = true; |
| 4359 | return 0; |
| 4360 | } |
| 4361 | |
| 4362 | /** |
| 4363 | * dwc2_restore_device_registers() - Restore controller device registers. |
| 4364 | * When resuming usb bus, device registers needs to be restored |
| 4365 | * if controller power were disabled. |
| 4366 | * |
| 4367 | * @hsotg: Programming view of the DWC_otg controller |
| 4368 | */ |
| 4369 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) |
| 4370 | { |
| 4371 | struct dwc2_dregs_backup *dr; |
| 4372 | u32 dctl; |
| 4373 | int i; |
| 4374 | |
| 4375 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 4376 | |
| 4377 | /* Restore dev regs */ |
| 4378 | dr = &hsotg->dr_backup; |
| 4379 | if (!dr->valid) { |
| 4380 | dev_err(hsotg->dev, "%s: no device registers to restore\n", |
| 4381 | __func__); |
| 4382 | return -EINVAL; |
| 4383 | } |
| 4384 | dr->valid = false; |
| 4385 | |
| 4386 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); |
| 4387 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); |
| 4388 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); |
| 4389 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); |
| 4390 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); |
| 4391 | |
| 4392 | for (i = 0; i < hsotg->num_of_eps; i++) { |
| 4393 | /* Restore IN EPs */ |
| 4394 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); |
| 4395 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); |
| 4396 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); |
| 4397 | |
| 4398 | /* Restore OUT EPs */ |
| 4399 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); |
| 4400 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); |
| 4401 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); |
| 4402 | } |
| 4403 | |
| 4404 | /* Set the Power-On Programming done bit */ |
| 4405 | dctl = dwc2_readl(hsotg->regs + DCTL); |
| 4406 | dctl |= DCTL_PWRONPRGDONE; |
| 4407 | dwc2_writel(dctl, hsotg->regs + DCTL); |
| 4408 | |
| 4409 | return 0; |
| 4410 | } |