| 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * core.h - DesignWare HS OTG Controller common declarations |
| 4 | * |
| 5 | * Copyright (C) 2004-2013 Synopsys, Inc. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions, and the following disclaimer, |
| 12 | * without modification. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. The names of the above-listed copyright holders may not be used |
| 17 | * to endorse or promote products derived from this software without |
| 18 | * specific prior written permission. |
| 19 | * |
| 20 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 21 | * GNU General Public License ("GPL") as published by the Free Software |
| 22 | * Foundation; either version 2 of the License, or (at your option) any |
| 23 | * later version. |
| 24 | * |
| 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 26 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 32 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 33 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 34 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 36 | */ |
| 37 | |
| 38 | #ifndef __DWC2_CORE_H__ |
| 39 | #define __DWC2_CORE_H__ |
| 40 | |
| 41 | #include <linux/phy/phy.h> |
| 42 | #include <linux/regulator/consumer.h> |
| 43 | #include <linux/usb/gadget.h> |
| 44 | #include <linux/usb/otg.h> |
| 45 | #include <linux/usb/phy.h> |
| 46 | #include "hw.h" |
| 47 | |
| 48 | /* |
| 49 | * Suggested defines for tracers: |
| 50 | * - no_printk: Disable tracing |
| 51 | * - pr_info: Print this info to the console |
| 52 | * - trace_printk: Print this info to trace buffer (good for verbose logging) |
| 53 | */ |
| 54 | |
| 55 | #define DWC2_TRACE_SCHEDULER no_printk |
| 56 | #define DWC2_TRACE_SCHEDULER_VB no_printk |
| 57 | |
| 58 | /* Detailed scheduler tracing, but won't overwhelm console */ |
| 59 | #define dwc2_sch_dbg(hsotg, fmt, ...) \ |
| 60 | DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ |
| 61 | dev_name(hsotg->dev), ##__VA_ARGS__) |
| 62 | |
| 63 | /* Verbose scheduler tracing */ |
| 64 | #define dwc2_sch_vdbg(hsotg, fmt, ...) \ |
| 65 | DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ |
| 66 | dev_name(hsotg->dev), ##__VA_ARGS__) |
| 67 | |
| 68 | /* Maximum number of Endpoints/HostChannels */ |
| 69 | #define MAX_EPS_CHANNELS 16 |
| 70 | |
| 71 | /* dwc2-hsotg declarations */ |
| 72 | static const char * const dwc2_hsotg_supply_names[] = { |
| 73 | "vusb_d", /* digital USB supply, 1.2V */ |
| 74 | "vusb_a", /* analog USB supply, 1.1V */ |
| 75 | }; |
| 76 | |
| 77 | #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) |
| 78 | |
| 79 | /* |
| 80 | * EP0_MPS_LIMIT |
| 81 | * |
| 82 | * Unfortunately there seems to be a limit of the amount of data that can |
| 83 | * be transferred by IN transactions on EP0. This is either 127 bytes or 3 |
| 84 | * packets (which practically means 1 packet and 63 bytes of data) when the |
| 85 | * MPS is set to 64. |
| 86 | * |
| 87 | * This means if we are wanting to move >127 bytes of data, we need to |
| 88 | * split the transactions up, but just doing one packet at a time does |
| 89 | * not work (this may be an implicit DATA0 PID on first packet of the |
| 90 | * transaction) and doing 2 packets is outside the controller's limits. |
| 91 | * |
| 92 | * If we try to lower the MPS size for EP0, then no transfers work properly |
| 93 | * for EP0, and the system will fail basic enumeration. As no cause for this |
| 94 | * has currently been found, we cannot support any large IN transfers for |
| 95 | * EP0. |
| 96 | */ |
| 97 | #define EP0_MPS_LIMIT 64 |
| 98 | |
| 99 | struct dwc2_hsotg; |
| 100 | struct dwc2_hsotg_req; |
| 101 | |
| 102 | /** |
| 103 | * struct dwc2_hsotg_ep - driver endpoint definition. |
| 104 | * @ep: The gadget layer representation of the endpoint. |
| 105 | * @name: The driver generated name for the endpoint. |
| 106 | * @queue: Queue of requests for this endpoint. |
| 107 | * @parent: Reference back to the parent device structure. |
| 108 | * @req: The current request that the endpoint is processing. This is |
| 109 | * used to indicate an request has been loaded onto the endpoint |
| 110 | * and has yet to be completed (maybe due to data move, or simply |
| 111 | * awaiting an ack from the core all the data has been completed). |
| 112 | * @debugfs: File entry for debugfs file for this endpoint. |
| 113 | * @dir_in: Set to true if this endpoint is of the IN direction, which |
| 114 | * means that it is sending data to the Host. |
| 115 | * @index: The index for the endpoint registers. |
| 116 | * @mc: Multi Count - number of transactions per microframe |
| 117 | * @interval: Interval for periodic endpoints, in frames or microframes. |
| 118 | * @name: The name array passed to the USB core. |
| 119 | * @halted: Set if the endpoint has been halted. |
| 120 | * @periodic: Set if this is a periodic ep, such as Interrupt |
| 121 | * @isochronous: Set if this is a isochronous ep |
| 122 | * @send_zlp: Set if we need to send a zero-length packet. |
| 123 | * @desc_list_dma: The DMA address of descriptor chain currently in use. |
| 124 | * @desc_list: Pointer to descriptor DMA chain head currently in use. |
| 125 | * @desc_count: Count of entries within the DMA descriptor chain of EP. |
| 126 | * @next_desc: index of next free descriptor in the ISOC chain under SW control. |
| 127 | * @compl_desc: index of next descriptor to be completed by xFerComplete |
| 128 | * @total_data: The total number of data bytes done. |
| 129 | * @fifo_size: The size of the FIFO (for periodic IN endpoints) |
| 130 | * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. |
| 131 | * @fifo_load: The amount of data loaded into the FIFO (periodic IN) |
| 132 | * @last_load: The offset of data for the last start of request. |
| 133 | * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN |
| 134 | * @target_frame: Targeted frame num to setup next ISOC transfer |
| 135 | * @frame_overrun: Indicates SOF number overrun in DSTS |
| 136 | * |
| 137 | * This is the driver's state for each registered enpoint, allowing it |
| 138 | * to keep track of transactions that need doing. Each endpoint has a |
| 139 | * lock to protect the state, to try and avoid using an overall lock |
| 140 | * for the host controller as much as possible. |
| 141 | * |
| 142 | * For periodic IN endpoints, we have fifo_size and fifo_load to try |
| 143 | * and keep track of the amount of data in the periodic FIFO for each |
| 144 | * of these as we don't have a status register that tells us how much |
| 145 | * is in each of them. (note, this may actually be useless information |
| 146 | * as in shared-fifo mode periodic in acts like a single-frame packet |
| 147 | * buffer than a fifo) |
| 148 | */ |
| 149 | struct dwc2_hsotg_ep { |
| 150 | struct usb_ep ep; |
| 151 | struct list_head queue; |
| 152 | struct dwc2_hsotg *parent; |
| 153 | struct dwc2_hsotg_req *req; |
| 154 | struct dentry *debugfs; |
| 155 | |
| 156 | unsigned long total_data; |
| 157 | unsigned int size_loaded; |
| 158 | unsigned int last_load; |
| 159 | unsigned int fifo_load; |
| 160 | unsigned short fifo_size; |
| 161 | unsigned short fifo_index; |
| 162 | |
| 163 | unsigned char dir_in; |
| 164 | unsigned char index; |
| 165 | unsigned char mc; |
| 166 | u16 interval; |
| 167 | |
| 168 | unsigned int halted:1; |
| 169 | unsigned int periodic:1; |
| 170 | unsigned int isochronous:1; |
| 171 | unsigned int send_zlp:1; |
| 172 | unsigned int target_frame; |
| 173 | #define TARGET_FRAME_INITIAL 0xFFFFFFFF |
| 174 | bool frame_overrun; |
| 175 | |
| 176 | dma_addr_t desc_list_dma; |
| 177 | struct dwc2_dma_desc *desc_list; |
| 178 | u8 desc_count; |
| 179 | |
| 180 | unsigned int next_desc; |
| 181 | unsigned int compl_desc; |
| 182 | |
| 183 | char name[10]; |
| 184 | }; |
| 185 | |
| 186 | /** |
| 187 | * struct dwc2_hsotg_req - data transfer request |
| 188 | * @req: The USB gadget request |
| 189 | * @queue: The list of requests for the endpoint this is queued for. |
| 190 | * @saved_req_buf: variable to save req.buf when bounce buffers are used. |
| 191 | */ |
| 192 | struct dwc2_hsotg_req { |
| 193 | struct usb_request req; |
| 194 | struct list_head queue; |
| 195 | void *saved_req_buf; |
| 196 | }; |
| 197 | |
| 198 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
| 199 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 200 | #define call_gadget(_hs, _entry) \ |
| 201 | do { \ |
| 202 | if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ |
| 203 | (_hs)->driver && (_hs)->driver->_entry) { \ |
| 204 | spin_unlock(&_hs->lock); \ |
| 205 | (_hs)->driver->_entry(&(_hs)->gadget); \ |
| 206 | spin_lock(&_hs->lock); \ |
| 207 | } \ |
| 208 | } while (0) |
| 209 | #else |
| 210 | #define call_gadget(_hs, _entry) do {} while (0) |
| 211 | #endif |
| 212 | |
| 213 | struct dwc2_hsotg; |
| 214 | struct dwc2_host_chan; |
| 215 | |
| 216 | /* Device States */ |
| 217 | enum dwc2_lx_state { |
| 218 | DWC2_L0, /* On state */ |
| 219 | DWC2_L1, /* LPM sleep state */ |
| 220 | DWC2_L2, /* USB suspend state */ |
| 221 | DWC2_L3, /* Off state */ |
| 222 | }; |
| 223 | |
| 224 | /* Gadget ep0 states */ |
| 225 | enum dwc2_ep0_state { |
| 226 | DWC2_EP0_SETUP, |
| 227 | DWC2_EP0_DATA_IN, |
| 228 | DWC2_EP0_DATA_OUT, |
| 229 | DWC2_EP0_STATUS_IN, |
| 230 | DWC2_EP0_STATUS_OUT, |
| 231 | }; |
| 232 | |
| 233 | /** |
| 234 | * struct dwc2_core_params - Parameters for configuring the core |
| 235 | * |
| 236 | * @otg_cap: Specifies the OTG capabilities. |
| 237 | * 0 - HNP and SRP capable |
| 238 | * 1 - SRP Only capable |
| 239 | * 2 - No HNP/SRP capable (always available) |
| 240 | * Defaults to best available option (0, 1, then 2) |
| 241 | * @host_dma: Specifies whether to use slave or DMA mode for accessing |
| 242 | * the data FIFOs. The driver will automatically detect the |
| 243 | * value for this parameter if none is specified. |
| 244 | * 0 - Slave (always available) |
| 245 | * 1 - DMA (default, if available) |
| 246 | * @dma_desc_enable: When DMA mode is enabled, specifies whether to use |
| 247 | * address DMA mode or descriptor DMA mode for accessing |
| 248 | * the data FIFOs. The driver will automatically detect the |
| 249 | * value for this if none is specified. |
| 250 | * 0 - Address DMA |
| 251 | * 1 - Descriptor DMA (default, if available) |
| 252 | * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use |
| 253 | * address DMA mode or descriptor DMA mode for accessing |
| 254 | * the data FIFOs in Full Speed mode only. The driver |
| 255 | * will automatically detect the value for this if none is |
| 256 | * specified. |
| 257 | * 0 - Address DMA |
| 258 | * 1 - Descriptor DMA in FS (default, if available) |
| 259 | * @speed: Specifies the maximum speed of operation in host and |
| 260 | * device mode. The actual speed depends on the speed of |
| 261 | * the attached device and the value of phy_type. |
| 262 | * 0 - High Speed |
| 263 | * (default when phy_type is UTMI+ or ULPI) |
| 264 | * 1 - Full Speed |
| 265 | * (default when phy_type is Full Speed) |
| 266 | * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters |
| 267 | * 1 - Allow dynamic FIFO sizing (default, if available) |
| 268 | * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs |
| 269 | * are enabled for non-periodic IN endpoints in device |
| 270 | * mode. |
| 271 | * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when |
| 272 | * dynamic FIFO sizing is enabled |
| 273 | * 16 to 32768 |
| 274 | * Actual maximum value is autodetected and also |
| 275 | * the default. |
| 276 | * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
| 277 | * in host mode when dynamic FIFO sizing is enabled |
| 278 | * 16 to 32768 |
| 279 | * Actual maximum value is autodetected and also |
| 280 | * the default. |
| 281 | * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in |
| 282 | * host mode when dynamic FIFO sizing is enabled |
| 283 | * 16 to 32768 |
| 284 | * Actual maximum value is autodetected and also |
| 285 | * the default. |
| 286 | * @max_transfer_size: The maximum transfer size supported, in bytes |
| 287 | * 2047 to 65,535 |
| 288 | * Actual maximum value is autodetected and also |
| 289 | * the default. |
| 290 | * @max_packet_count: The maximum number of packets in a transfer |
| 291 | * 15 to 511 |
| 292 | * Actual maximum value is autodetected and also |
| 293 | * the default. |
| 294 | * @host_channels: The number of host channel registers to use |
| 295 | * 1 to 16 |
| 296 | * Actual maximum value is autodetected and also |
| 297 | * the default. |
| 298 | * @phy_type: Specifies the type of PHY interface to use. By default, |
| 299 | * the driver will automatically detect the phy_type. |
| 300 | * 0 - Full Speed Phy |
| 301 | * 1 - UTMI+ Phy |
| 302 | * 2 - ULPI Phy |
| 303 | * Defaults to best available option (2, 1, then 0) |
| 304 | * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter |
| 305 | * is applicable for a phy_type of UTMI+ or ULPI. (For a |
| 306 | * ULPI phy_type, this parameter indicates the data width |
| 307 | * between the MAC and the ULPI Wrapper.) Also, this |
| 308 | * parameter is applicable only if the OTG_HSPHY_WIDTH cC |
| 309 | * parameter was set to "8 and 16 bits", meaning that the |
| 310 | * core has been configured to work at either data path |
| 311 | * width. |
| 312 | * 8 or 16 (default 16 if available) |
| 313 | * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single |
| 314 | * data rate. This parameter is only applicable if phy_type |
| 315 | * is ULPI. |
| 316 | * 0 - single data rate ULPI interface with 8 bit wide |
| 317 | * data bus (default) |
| 318 | * 1 - double data rate ULPI interface with 4 bit wide |
| 319 | * data bus |
| 320 | * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or |
| 321 | * external supply to drive the VBus |
| 322 | * 0 - Internal supply (default) |
| 323 | * 1 - External supply |
| 324 | * @i2c_enable: Specifies whether to use the I2Cinterface for a full |
| 325 | * speed PHY. This parameter is only applicable if phy_type |
| 326 | * is FS. |
| 327 | * 0 - No (default) |
| 328 | * 1 - Yes |
| 329 | * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. |
| 330 | * 0 - Disable (default) |
| 331 | * 1 - Enable |
| 332 | * @acg_enable: For enabling Active Clock Gating in the controller |
| 333 | * 0 - No |
| 334 | * 1 - Yes |
| 335 | * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only |
| 336 | * 0 - No (default) |
| 337 | * 1 - Yes |
| 338 | * @host_support_fs_ls_low_power: Specifies whether low power mode is supported |
| 339 | * when attached to a Full Speed or Low Speed device in |
| 340 | * host mode. |
| 341 | * 0 - Don't support low power mode (default) |
| 342 | * 1 - Support low power mode |
| 343 | * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode |
| 344 | * when connected to a Low Speed device in host |
| 345 | * mode. This parameter is applicable only if |
| 346 | * host_support_fs_ls_low_power is enabled. |
| 347 | * 0 - 48 MHz |
| 348 | * (default when phy_type is UTMI+ or ULPI) |
| 349 | * 1 - 6 MHz |
| 350 | * (default when phy_type is Full Speed) |
| 351 | * @oc_disable: Flag to disable overcurrent condition. |
| 352 | * 0 - Allow overcurrent condition to get detected |
| 353 | * 1 - Disable overcurrent condtion to get detected |
| 354 | * @ts_dline: Enable Term Select Dline pulsing |
| 355 | * 0 - No (default) |
| 356 | * 1 - Yes |
| 357 | * @reload_ctl: Allow dynamic reloading of HFIR register during runtime |
| 358 | * 0 - No (default for core < 2.92a) |
| 359 | * 1 - Yes (default for core >= 2.92a) |
| 360 | * @ahbcfg: This field allows the default value of the GAHBCFG |
| 361 | * register to be overridden |
| 362 | * -1 - GAHBCFG value will be set to 0x06 |
| 363 | * (INCR, default) |
| 364 | * all others - GAHBCFG value will be overridden with |
| 365 | * this value |
| 366 | * Not all bits can be controlled like this, the |
| 367 | * bits defined by GAHBCFG_CTRL_MASK are controlled |
| 368 | * by the driver and are ignored in this |
| 369 | * configuration value. |
| 370 | * @uframe_sched: True to enable the microframe scheduler |
| 371 | * @external_id_pin_ctl: Specifies whether ID pin is handled externally. |
| 372 | * Disable CONIDSTSCHNG controller interrupt in such |
| 373 | * case. |
| 374 | * 0 - No (default) |
| 375 | * 1 - Yes |
| 376 | * @power_down: Specifies whether the controller support power_down. |
| 377 | * If power_down is enabled, the controller will enter |
| 378 | * power_down in both peripheral and host mode when |
| 379 | * needed. |
| 380 | * 0 - No (default) |
| 381 | * 1 - Partial power down |
| 382 | * 2 - Hibernation |
| 383 | * @lpm: Enable LPM support. |
| 384 | * 0 - No |
| 385 | * 1 - Yes |
| 386 | * @lpm_clock_gating: Enable core PHY clock gating. |
| 387 | * 0 - No |
| 388 | * 1 - Yes |
| 389 | * @besl: Enable LPM Errata support. |
| 390 | * 0 - No |
| 391 | * 1 - Yes |
| 392 | * @hird_threshold_en: HIRD or HIRD Threshold enable. |
| 393 | * 0 - No |
| 394 | * 1 - Yes |
| 395 | * @hird_threshold: Value of BESL or HIRD Threshold. |
| 396 | * @ref_clk_per: Indicates in terms of pico seconds the period |
| 397 | * of ref_clk. |
| 398 | * 62500 - 16MHz |
| 399 | * 58823 - 17MHz |
| 400 | * 52083 - 19.2MHz |
| 401 | * 50000 - 20MHz |
| 402 | * 41666 - 24MHz |
| 403 | * 33333 - 30MHz (default) |
| 404 | * 25000 - 40MHz |
| 405 | * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which |
| 406 | * the controller should generate an interrupt if the |
| 407 | * device had been in L1 state until that period. |
| 408 | * This is used by SW to initiate Remote WakeUp in the |
| 409 | * controller so as to sync to the uF number from the host. |
| 410 | * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO |
| 411 | * register. |
| 412 | * 0 - Deactivate the transceiver (default) |
| 413 | * 1 - Activate the transceiver |
| 414 | * @g_dma: Enables gadget dma usage (default: autodetect). |
| 415 | * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). |
| 416 | * @g_rx_fifo_size: The periodic rx fifo size for the device, in |
| 417 | * DWORDS from 16-32768 (default: 2048 if |
| 418 | * possible, otherwise autodetect). |
| 419 | * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in |
| 420 | * DWORDS from 16-32768 (default: 1024 if |
| 421 | * possible, otherwise autodetect). |
| 422 | * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo |
| 423 | * mode. Each value corresponds to one EP |
| 424 | * starting from EP1 (max 15 values). Sizes are |
| 425 | * in DWORDS with possible values from from |
| 426 | * 16-32768 (default: 256, 256, 256, 256, 768, |
| 427 | * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). |
| 428 | * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL |
| 429 | * while full&low speed device connect. And change speed |
| 430 | * back to DWC2_SPEED_PARAM_HIGH while device is gone. |
| 431 | * 0 - No (default) |
| 432 | * 1 - Yes |
| 433 | * @service_interval: Enable service interval based scheduling. |
| 434 | * 0 - No |
| 435 | * 1 - Yes |
| 436 | * |
| 437 | * The following parameters may be specified when starting the module. These |
| 438 | * parameters define how the DWC_otg controller should be configured. A |
| 439 | * value of -1 (or any other out of range value) for any parameter means |
| 440 | * to read the value from hardware (if possible) or use the builtin |
| 441 | * default described above. |
| 442 | */ |
| 443 | struct dwc2_core_params { |
| 444 | u8 otg_cap; |
| 445 | #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 |
| 446 | #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 |
| 447 | #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 |
| 448 | |
| 449 | u8 phy_type; |
| 450 | #define DWC2_PHY_TYPE_PARAM_FS 0 |
| 451 | #define DWC2_PHY_TYPE_PARAM_UTMI 1 |
| 452 | #define DWC2_PHY_TYPE_PARAM_ULPI 2 |
| 453 | |
| 454 | u8 speed; |
| 455 | #define DWC2_SPEED_PARAM_HIGH 0 |
| 456 | #define DWC2_SPEED_PARAM_FULL 1 |
| 457 | #define DWC2_SPEED_PARAM_LOW 2 |
| 458 | |
| 459 | u8 phy_utmi_width; |
| 460 | bool phy_ulpi_ddr; |
| 461 | bool phy_ulpi_ext_vbus; |
| 462 | bool enable_dynamic_fifo; |
| 463 | bool en_multiple_tx_fifo; |
| 464 | bool i2c_enable; |
| 465 | bool acg_enable; |
| 466 | bool ulpi_fs_ls; |
| 467 | bool ts_dline; |
| 468 | bool reload_ctl; |
| 469 | bool uframe_sched; |
| 470 | bool external_id_pin_ctl; |
| 471 | |
| 472 | int power_down; |
| 473 | #define DWC2_POWER_DOWN_PARAM_NONE 0 |
| 474 | #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 |
| 475 | #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 |
| 476 | |
| 477 | bool lpm; |
| 478 | bool lpm_clock_gating; |
| 479 | bool besl; |
| 480 | bool hird_threshold_en; |
| 481 | bool service_interval; |
| 482 | u8 hird_threshold; |
| 483 | bool activate_stm_fs_transceiver; |
| 484 | bool ipg_isoc_en; |
| 485 | u16 max_packet_count; |
| 486 | u32 max_transfer_size; |
| 487 | u32 ahbcfg; |
| 488 | |
| 489 | /* GREFCLK parameters */ |
| 490 | u32 ref_clk_per; |
| 491 | u16 sof_cnt_wkup_alert; |
| 492 | |
| 493 | /* Host parameters */ |
| 494 | bool host_dma; |
| 495 | bool dma_desc_enable; |
| 496 | bool dma_desc_fs_enable; |
| 497 | bool host_support_fs_ls_low_power; |
| 498 | bool host_ls_low_power_phy_clk; |
| 499 | bool oc_disable; |
| 500 | |
| 501 | u8 host_channels; |
| 502 | u16 host_rx_fifo_size; |
| 503 | u16 host_nperio_tx_fifo_size; |
| 504 | u16 host_perio_tx_fifo_size; |
| 505 | |
| 506 | /* Gadget parameters */ |
| 507 | bool g_dma; |
| 508 | bool g_dma_desc; |
| 509 | u32 g_rx_fifo_size; |
| 510 | u32 g_np_tx_fifo_size; |
| 511 | u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |
| 512 | |
| 513 | bool change_speed_quirk; |
| 514 | }; |
| 515 | |
| 516 | /** |
| 517 | * struct dwc2_hw_params - Autodetected parameters. |
| 518 | * |
| 519 | * These parameters are the various parameters read from hardware |
| 520 | * registers during initialization. They typically contain the best |
| 521 | * supported or maximum value that can be configured in the |
| 522 | * corresponding dwc2_core_params value. |
| 523 | * |
| 524 | * The values that are not in dwc2_core_params are documented below. |
| 525 | * |
| 526 | * @op_mode: Mode of Operation |
| 527 | * 0 - HNP- and SRP-Capable OTG (Host & Device) |
| 528 | * 1 - SRP-Capable OTG (Host & Device) |
| 529 | * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) |
| 530 | * 3 - SRP-Capable Device |
| 531 | * 4 - Non-OTG Device |
| 532 | * 5 - SRP-Capable Host |
| 533 | * 6 - Non-OTG Host |
| 534 | * @arch: Architecture |
| 535 | * 0 - Slave only |
| 536 | * 1 - External DMA |
| 537 | * 2 - Internal DMA |
| 538 | * @ipg_isoc_en: This feature indicates that the controller supports |
| 539 | * the worst-case scenario of Rx followed by Rx |
| 540 | * Interpacket Gap (IPG) (32 bitTimes) as per the utmi |
| 541 | * specification for any token following ISOC OUT token. |
| 542 | * 0 - Don't support |
| 543 | * 1 - Support |
| 544 | * @power_optimized: Are power optimizations enabled? |
| 545 | * @num_dev_ep: Number of device endpoints available |
| 546 | * @num_dev_in_eps: Number of device IN endpoints available |
| 547 | * @num_dev_perio_in_ep: Number of device periodic IN endpoints |
| 548 | * available |
| 549 | * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue |
| 550 | * Depth |
| 551 | * 0 to 30 |
| 552 | * @host_perio_tx_q_depth: |
| 553 | * Host Mode Periodic Request Queue Depth |
| 554 | * 2, 4 or 8 |
| 555 | * @nperio_tx_q_depth: |
| 556 | * Non-Periodic Request Queue Depth |
| 557 | * 2, 4 or 8 |
| 558 | * @hs_phy_type: High-speed PHY interface type |
| 559 | * 0 - High-speed interface not supported |
| 560 | * 1 - UTMI+ |
| 561 | * 2 - ULPI |
| 562 | * 3 - UTMI+ and ULPI |
| 563 | * @fs_phy_type: Full-speed PHY interface type |
| 564 | * 0 - Full speed interface not supported |
| 565 | * 1 - Dedicated full speed interface |
| 566 | * 2 - FS pins shared with UTMI+ pins |
| 567 | * 3 - FS pins shared with ULPI pins |
| 568 | * @total_fifo_size: Total internal RAM for FIFOs (bytes) |
| 569 | * @hibernation: Is hibernation enabled? |
| 570 | * @utmi_phy_data_width: UTMI+ PHY data width |
| 571 | * 0 - 8 bits |
| 572 | * 1 - 16 bits |
| 573 | * 2 - 8 or 16 bits |
| 574 | * @snpsid: Value from SNPSID register |
| 575 | * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) |
| 576 | * @g_tx_fifo_size: Power-on values of TxFIFO sizes |
| 577 | * @dma_desc_enable: When DMA mode is enabled, specifies whether to use |
| 578 | * address DMA mode or descriptor DMA mode for accessing |
| 579 | * the data FIFOs. The driver will automatically detect the |
| 580 | * value for this if none is specified. |
| 581 | * 0 - Address DMA |
| 582 | * 1 - Descriptor DMA (default, if available) |
| 583 | * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters |
| 584 | * 1 - Allow dynamic FIFO sizing (default, if available) |
| 585 | * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs |
| 586 | * are enabled for non-periodic IN endpoints in device |
| 587 | * mode. |
| 588 | * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
| 589 | * in host mode when dynamic FIFO sizing is enabled |
| 590 | * 16 to 32768 |
| 591 | * Actual maximum value is autodetected and also |
| 592 | * the default. |
| 593 | * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in |
| 594 | * host mode when dynamic FIFO sizing is enabled |
| 595 | * 16 to 32768 |
| 596 | * Actual maximum value is autodetected and also |
| 597 | * the default. |
| 598 | * @max_transfer_size: The maximum transfer size supported, in bytes |
| 599 | * 2047 to 65,535 |
| 600 | * Actual maximum value is autodetected and also |
| 601 | * the default. |
| 602 | * @max_packet_count: The maximum number of packets in a transfer |
| 603 | * 15 to 511 |
| 604 | * Actual maximum value is autodetected and also |
| 605 | * the default. |
| 606 | * @host_channels: The number of host channel registers to use |
| 607 | * 1 to 16 |
| 608 | * Actual maximum value is autodetected and also |
| 609 | * the default. |
| 610 | * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
| 611 | * in device mode when dynamic FIFO sizing is enabled |
| 612 | * 16 to 32768 |
| 613 | * Actual maximum value is autodetected and also |
| 614 | * the default. |
| 615 | * @i2c_enable: Specifies whether to use the I2Cinterface for a full |
| 616 | * speed PHY. This parameter is only applicable if phy_type |
| 617 | * is FS. |
| 618 | * 0 - No (default) |
| 619 | * 1 - Yes |
| 620 | * @acg_enable: For enabling Active Clock Gating in the controller |
| 621 | * 0 - Disable |
| 622 | * 1 - Enable |
| 623 | * @lpm_mode: For enabling Link Power Management in the controller |
| 624 | * 0 - Disable |
| 625 | * 1 - Enable |
| 626 | * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic |
| 627 | * FIFO sizing is enabled 16 to 32768 |
| 628 | * Actual maximum value is autodetected and also |
| 629 | * the default. |
| 630 | * @service_interval_mode: For enabling service interval based scheduling in the |
| 631 | * controller. |
| 632 | * 0 - Disable |
| 633 | * 1 - Enable |
| 634 | */ |
| 635 | struct dwc2_hw_params { |
| 636 | unsigned op_mode:3; |
| 637 | unsigned arch:2; |
| 638 | unsigned dma_desc_enable:1; |
| 639 | unsigned enable_dynamic_fifo:1; |
| 640 | unsigned en_multiple_tx_fifo:1; |
| 641 | unsigned rx_fifo_size:16; |
| 642 | unsigned host_nperio_tx_fifo_size:16; |
| 643 | unsigned dev_nperio_tx_fifo_size:16; |
| 644 | unsigned host_perio_tx_fifo_size:16; |
| 645 | unsigned nperio_tx_q_depth:3; |
| 646 | unsigned host_perio_tx_q_depth:3; |
| 647 | unsigned dev_token_q_depth:5; |
| 648 | unsigned max_transfer_size:26; |
| 649 | unsigned max_packet_count:11; |
| 650 | unsigned host_channels:5; |
| 651 | unsigned hs_phy_type:2; |
| 652 | unsigned fs_phy_type:2; |
| 653 | unsigned i2c_enable:1; |
| 654 | unsigned acg_enable:1; |
| 655 | unsigned num_dev_ep:4; |
| 656 | unsigned num_dev_in_eps : 4; |
| 657 | unsigned num_dev_perio_in_ep:4; |
| 658 | unsigned total_fifo_size:16; |
| 659 | unsigned power_optimized:1; |
| 660 | unsigned hibernation:1; |
| 661 | unsigned utmi_phy_data_width:2; |
| 662 | unsigned lpm_mode:1; |
| 663 | unsigned ipg_isoc_en:1; |
| 664 | unsigned service_interval_mode:1; |
| 665 | u32 snpsid; |
| 666 | u32 dev_ep_dirs; |
| 667 | u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |
| 668 | }; |
| 669 | |
| 670 | /* Size of control and EP0 buffers */ |
| 671 | #define DWC2_CTRL_BUFF_SIZE 8 |
| 672 | |
| 673 | /** |
| 674 | * struct dwc2_gregs_backup - Holds global registers state before |
| 675 | * entering partial power down |
| 676 | * @gotgctl: Backup of GOTGCTL register |
| 677 | * @gintmsk: Backup of GINTMSK register |
| 678 | * @gahbcfg: Backup of GAHBCFG register |
| 679 | * @gusbcfg: Backup of GUSBCFG register |
| 680 | * @grxfsiz: Backup of GRXFSIZ register |
| 681 | * @gnptxfsiz: Backup of GNPTXFSIZ register |
| 682 | * @gi2cctl: Backup of GI2CCTL register |
| 683 | * @glpmcfg: Backup of GLPMCFG register |
| 684 | * @gdfifocfg: Backup of GDFIFOCFG register |
| 685 | * @pcgcctl: Backup of PCGCCTL register |
| 686 | * @pcgcctl1: Backup of PCGCCTL1 register |
| 687 | * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint |
| 688 | * @gpwrdn: Backup of GPWRDN register |
| 689 | * @valid: True if registers values backuped. |
| 690 | */ |
| 691 | struct dwc2_gregs_backup { |
| 692 | u32 gotgctl; |
| 693 | u32 gintmsk; |
| 694 | u32 gahbcfg; |
| 695 | u32 gusbcfg; |
| 696 | u32 grxfsiz; |
| 697 | u32 gnptxfsiz; |
| 698 | u32 gi2cctl; |
| 699 | u32 glpmcfg; |
| 700 | u32 pcgcctl; |
| 701 | u32 pcgcctl1; |
| 702 | u32 gdfifocfg; |
| 703 | u32 gpwrdn; |
| 704 | bool valid; |
| 705 | }; |
| 706 | |
| 707 | /** |
| 708 | * struct dwc2_dregs_backup - Holds device registers state before |
| 709 | * entering partial power down |
| 710 | * @dcfg: Backup of DCFG register |
| 711 | * @dctl: Backup of DCTL register |
| 712 | * @daintmsk: Backup of DAINTMSK register |
| 713 | * @diepmsk: Backup of DIEPMSK register |
| 714 | * @doepmsk: Backup of DOEPMSK register |
| 715 | * @diepctl: Backup of DIEPCTL register |
| 716 | * @dieptsiz: Backup of DIEPTSIZ register |
| 717 | * @diepdma: Backup of DIEPDMA register |
| 718 | * @doepctl: Backup of DOEPCTL register |
| 719 | * @doeptsiz: Backup of DOEPTSIZ register |
| 720 | * @doepdma: Backup of DOEPDMA register |
| 721 | * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint |
| 722 | * @valid: True if registers values backuped. |
| 723 | */ |
| 724 | struct dwc2_dregs_backup { |
| 725 | u32 dcfg; |
| 726 | u32 dctl; |
| 727 | u32 daintmsk; |
| 728 | u32 diepmsk; |
| 729 | u32 doepmsk; |
| 730 | u32 diepctl[MAX_EPS_CHANNELS]; |
| 731 | u32 dieptsiz[MAX_EPS_CHANNELS]; |
| 732 | u32 diepdma[MAX_EPS_CHANNELS]; |
| 733 | u32 doepctl[MAX_EPS_CHANNELS]; |
| 734 | u32 doeptsiz[MAX_EPS_CHANNELS]; |
| 735 | u32 doepdma[MAX_EPS_CHANNELS]; |
| 736 | u32 dtxfsiz[MAX_EPS_CHANNELS]; |
| 737 | bool valid; |
| 738 | }; |
| 739 | |
| 740 | /** |
| 741 | * struct dwc2_hregs_backup - Holds host registers state before |
| 742 | * entering partial power down |
| 743 | * @hcfg: Backup of HCFG register |
| 744 | * @haintmsk: Backup of HAINTMSK register |
| 745 | * @hcintmsk: Backup of HCINTMSK register |
| 746 | * @hprt0: Backup of HPTR0 register |
| 747 | * @hfir: Backup of HFIR register |
| 748 | * @hptxfsiz: Backup of HPTXFSIZ register |
| 749 | * @valid: True if registers values backuped. |
| 750 | */ |
| 751 | struct dwc2_hregs_backup { |
| 752 | u32 hcfg; |
| 753 | u32 haintmsk; |
| 754 | u32 hcintmsk[MAX_EPS_CHANNELS]; |
| 755 | u32 hprt0; |
| 756 | u32 hfir; |
| 757 | u32 hptxfsiz; |
| 758 | bool valid; |
| 759 | }; |
| 760 | |
| 761 | /* |
| 762 | * Constants related to high speed periodic scheduling |
| 763 | * |
| 764 | * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a |
| 765 | * reservation point of view it's assumed that the schedule goes right back to |
| 766 | * the beginning after the end of the schedule. |
| 767 | * |
| 768 | * What does that mean for scheduling things with a long interval? It means |
| 769 | * we'll reserve time for them in every possible microframe that they could |
| 770 | * ever be scheduled in. ...but we'll still only actually schedule them as |
| 771 | * often as they were requested. |
| 772 | * |
| 773 | * We keep our schedule in a "bitmap" structure. This simplifies having |
| 774 | * to keep track of and merge intervals: we just let the bitmap code do most |
| 775 | * of the heavy lifting. In a way scheduling is much like memory allocation. |
| 776 | * |
| 777 | * We schedule 100us per uframe or 80% of 125us (the maximum amount you're |
| 778 | * supposed to schedule for periodic transfers). That's according to spec. |
| 779 | * |
| 780 | * Note that though we only schedule 80% of each microframe, the bitmap that we |
| 781 | * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of |
| 782 | * space for each uFrame). |
| 783 | * |
| 784 | * Requirements: |
| 785 | * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) |
| 786 | * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably |
| 787 | * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might |
| 788 | * be bugs). The 8 comes from the USB spec: number of microframes per frame. |
| 789 | */ |
| 790 | #define DWC2_US_PER_UFRAME 125 |
| 791 | #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 |
| 792 | |
| 793 | #define DWC2_HS_SCHEDULE_UFRAMES 8 |
| 794 | #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ |
| 795 | DWC2_HS_PERIODIC_US_PER_UFRAME) |
| 796 | |
| 797 | /* |
| 798 | * Constants related to low speed scheduling |
| 799 | * |
| 800 | * For high speed we schedule every 1us. For low speed that's a bit overkill, |
| 801 | * so we make up a unit called a "slice" that's worth 25us. There are 40 |
| 802 | * slices in a full frame and we can schedule 36 of those (90%) for periodic |
| 803 | * transfers. |
| 804 | * |
| 805 | * Our low speed schedule can be as short as 1 frame or could be longer. When |
| 806 | * we only schedule 1 frame it means that we'll need to reserve a time every |
| 807 | * frame even for things that only transfer very rarely, so something that runs |
| 808 | * every 2048 frames will get time reserved in every frame. Our low speed |
| 809 | * schedule can be longer and we'll be able to handle more overlap, but that |
| 810 | * will come at increased memory cost and increased time to schedule. |
| 811 | * |
| 812 | * Note: one other advantage of a short low speed schedule is that if we mess |
| 813 | * up and miss scheduling we can jump in and use any of the slots that we |
| 814 | * happened to reserve. |
| 815 | * |
| 816 | * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for |
| 817 | * the schedule. There will be one schedule per TT. |
| 818 | * |
| 819 | * Requirements: |
| 820 | * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. |
| 821 | */ |
| 822 | #define DWC2_US_PER_SLICE 25 |
| 823 | #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) |
| 824 | |
| 825 | #define DWC2_ROUND_US_TO_SLICE(us) \ |
| 826 | (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ |
| 827 | DWC2_US_PER_SLICE) |
| 828 | |
| 829 | #define DWC2_LS_PERIODIC_US_PER_FRAME \ |
| 830 | 900 |
| 831 | #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ |
| 832 | (DWC2_LS_PERIODIC_US_PER_FRAME / \ |
| 833 | DWC2_US_PER_SLICE) |
| 834 | |
| 835 | #define DWC2_LS_SCHEDULE_FRAMES 1 |
| 836 | #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ |
| 837 | DWC2_LS_PERIODIC_SLICES_PER_FRAME) |
| 838 | |
| 839 | /** |
| 840 | * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic |
| 841 | * and periodic schedules |
| 842 | * |
| 843 | * These are common for both host and peripheral modes: |
| 844 | * |
| 845 | * @dev: The struct device pointer |
| 846 | * @regs: Pointer to controller regs |
| 847 | * @hw_params: Parameters that were autodetected from the |
| 848 | * hardware registers |
| 849 | * @params: Parameters that define how the core should be configured |
| 850 | * @op_state: The operational State, during transitions (a_host=> |
| 851 | * a_peripheral and b_device=>b_host) this may not match |
| 852 | * the core, but allows the software to determine |
| 853 | * transitions |
| 854 | * @dr_mode: Requested mode of operation, one of following: |
| 855 | * - USB_DR_MODE_PERIPHERAL |
| 856 | * - USB_DR_MODE_HOST |
| 857 | * - USB_DR_MODE_OTG |
| 858 | * @hcd_enabled: Host mode sub-driver initialization indicator. |
| 859 | * @gadget_enabled: Peripheral mode sub-driver initialization indicator. |
| 860 | * @ll_hw_enabled: Status of low-level hardware resources. |
| 861 | * @hibernated: True if core is hibernated |
| 862 | * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a |
| 863 | * remote wakeup. |
| 864 | * @frame_number: Frame number read from the core. For both device |
| 865 | * and host modes. The value ranges are from 0 |
| 866 | * to HFNUM_MAX_FRNUM. |
| 867 | * @phy: The otg phy transceiver structure for phy control. |
| 868 | * @uphy: The otg phy transceiver structure for old USB phy |
| 869 | * control. |
| 870 | * @plat: The platform specific configuration data. This can be |
| 871 | * removed once all SoCs support usb transceiver. |
| 872 | * @supplies: Definition of USB power supplies |
| 873 | * @vbus_supply: Regulator supplying vbus. |
| 874 | * @lock: Spinlock that protects all the driver data structures |
| 875 | * @priv: Stores a pointer to the struct usb_hcd |
| 876 | * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth |
| 877 | * transfer are in process of being queued |
| 878 | * @srp_success: Stores status of SRP request in the case of a FS PHY |
| 879 | * with an I2C interface |
| 880 | * @wq_otg: Workqueue object used for handling of some interrupts |
| 881 | * @wf_otg: Work object for handling Connector ID Status Change |
| 882 | * interrupt |
| 883 | * @wkp_timer: Timer object for handling Wakeup Detected interrupt |
| 884 | * @lx_state: Lx state of connected device |
| 885 | * @gr_backup: Backup of global registers during suspend |
| 886 | * @dr_backup: Backup of device registers during suspend |
| 887 | * @hr_backup: Backup of host registers during suspend |
| 888 | * @needs_byte_swap: Specifies whether the opposite endianness. |
| 889 | * |
| 890 | * These are for host mode: |
| 891 | * |
| 892 | * @flags: Flags for handling root port state changes |
| 893 | * @flags.d32: Contain all root port flags |
| 894 | * @flags.b: Separate root port flags from each other |
| 895 | * @flags.b.port_connect_status_change: True if root port connect status |
| 896 | * changed |
| 897 | * @flags.b.port_connect_status: True if device connected to root port |
| 898 | * @flags.b.port_reset_change: True if root port reset status changed |
| 899 | * @flags.b.port_enable_change: True if root port enable status changed |
| 900 | * @flags.b.port_suspend_change: True if root port suspend status changed |
| 901 | * @flags.b.port_over_current_change: True if root port over current state |
| 902 | * changed. |
| 903 | * @flags.b.port_l1_change: True if root port l1 status changed |
| 904 | * @flags.b.reserved: Reserved bits of root port register |
| 905 | * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. |
| 906 | * Transfers associated with these QHs are not currently |
| 907 | * assigned to a host channel. |
| 908 | * @non_periodic_sched_active: Active QHs in the non-periodic schedule. |
| 909 | * Transfers associated with these QHs are currently |
| 910 | * assigned to a host channel. |
| 911 | * @non_periodic_qh_ptr: Pointer to next QH to process in the active |
| 912 | * non-periodic schedule |
| 913 | * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. |
| 914 | * Transfers associated with these QHs are not currently |
| 915 | * assigned to a host channel. |
| 916 | * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a |
| 917 | * list of QHs for periodic transfers that are _not_ |
| 918 | * scheduled for the next frame. Each QH in the list has an |
| 919 | * interval counter that determines when it needs to be |
| 920 | * scheduled for execution. This scheduling mechanism |
| 921 | * allows only a simple calculation for periodic bandwidth |
| 922 | * used (i.e. must assume that all periodic transfers may |
| 923 | * need to execute in the same frame). However, it greatly |
| 924 | * simplifies scheduling and should be sufficient for the |
| 925 | * vast majority of OTG hosts, which need to connect to a |
| 926 | * small number of peripherals at one time. Items move from |
| 927 | * this list to periodic_sched_ready when the QH interval |
| 928 | * counter is 0 at SOF. |
| 929 | * @periodic_sched_ready: List of periodic QHs that are ready for execution in |
| 930 | * the next frame, but have not yet been assigned to host |
| 931 | * channels. Items move from this list to |
| 932 | * periodic_sched_assigned as host channels become |
| 933 | * available during the current frame. |
| 934 | * @periodic_sched_assigned: List of periodic QHs to be executed in the next |
| 935 | * frame that are assigned to host channels. Items move |
| 936 | * from this list to periodic_sched_queued as the |
| 937 | * transactions for the QH are queued to the DWC_otg |
| 938 | * controller. |
| 939 | * @periodic_sched_queued: List of periodic QHs that have been queued for |
| 940 | * execution. Items move from this list to either |
| 941 | * periodic_sched_inactive or periodic_sched_ready when the |
| 942 | * channel associated with the transfer is released. If the |
| 943 | * interval for the QH is 1, the item moves to |
| 944 | * periodic_sched_ready because it must be rescheduled for |
| 945 | * the next frame. Otherwise, the item moves to |
| 946 | * periodic_sched_inactive. |
| 947 | * @split_order: List keeping track of channels doing splits, in order. |
| 948 | * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. |
| 949 | * This value is in microseconds per (micro)frame. The |
| 950 | * assumption is that all periodic transfers may occur in |
| 951 | * the same (micro)frame. |
| 952 | * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the |
| 953 | * host is in high speed mode; low speed schedules are |
| 954 | * stored elsewhere since we need one per TT. |
| 955 | * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for |
| 956 | * SOF enable/disable. |
| 957 | * @free_hc_list: Free host channels in the controller. This is a list of |
| 958 | * struct dwc2_host_chan items. |
| 959 | * @periodic_channels: Number of host channels assigned to periodic transfers. |
| 960 | * Currently assuming that there is a dedicated host |
| 961 | * channel for each periodic transaction and at least one |
| 962 | * host channel is available for non-periodic transactions. |
| 963 | * @non_periodic_channels: Number of host channels assigned to non-periodic |
| 964 | * transfers |
| 965 | * @available_host_channels: Number of host channels available for the |
| 966 | * microframe scheduler to use |
| 967 | * @hc_ptr_array: Array of pointers to the host channel descriptors. |
| 968 | * Allows accessing a host channel descriptor given the |
| 969 | * host channel number. This is useful in interrupt |
| 970 | * handlers. |
| 971 | * @status_buf: Buffer used for data received during the status phase of |
| 972 | * a control transfer. |
| 973 | * @status_buf_dma: DMA address for status_buf |
| 974 | * @start_work: Delayed work for handling host A-cable connection |
| 975 | * @reset_work: Delayed work for handling a port reset |
| 976 | * @phy_reset_work: Work structure for doing a PHY reset |
| 977 | * @otg_port: OTG port number |
| 978 | * @frame_list: Frame list |
| 979 | * @frame_list_dma: Frame list DMA address |
| 980 | * @frame_list_sz: Frame list size |
| 981 | * @desc_gen_cache: Kmem cache for generic descriptors |
| 982 | * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors |
| 983 | * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf |
| 984 | * |
| 985 | * These are for peripheral mode: |
| 986 | * |
| 987 | * @driver: USB gadget driver |
| 988 | * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. |
| 989 | * @num_of_eps: Number of available EPs (excluding EP0) |
| 990 | * @debug_root: Root directrory for debugfs. |
| 991 | * @ep0_reply: Request used for ep0 reply. |
| 992 | * @ep0_buff: Buffer for EP0 reply data, if needed. |
| 993 | * @ctrl_buff: Buffer for EP0 control requests. |
| 994 | * @ctrl_req: Request for EP0 control packets. |
| 995 | * @ep0_state: EP0 control transfers state |
| 996 | * @delayed_status: true when gadget driver asks for delayed status |
| 997 | * @test_mode: USB test mode requested by the host |
| 998 | * @remote_wakeup_allowed: True if device is allowed to wake-up host by |
| 999 | * remote-wakeup signalling |
| 1000 | * @setup_desc_dma: EP0 setup stage desc chain DMA address |
| 1001 | * @setup_desc: EP0 setup stage desc chain pointer |
| 1002 | * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address |
| 1003 | * @ctrl_in_desc: EP0 IN data phase desc chain pointer |
| 1004 | * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address |
| 1005 | * @ctrl_out_desc: EP0 OUT data phase desc chain pointer |
| 1006 | * @irq: Interrupt request line number |
| 1007 | * @clk: Pointer to otg clock |
| 1008 | * @reset: Pointer to dwc2 reset controller |
| 1009 | * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. |
| 1010 | * @regset: A pointer to a struct debugfs_regset32, which contains |
| 1011 | * a pointer to an array of register definitions, the |
| 1012 | * array size and the base address where the register bank |
| 1013 | * is to be found. |
| 1014 | * @bus_suspended: True if bus is suspended |
| 1015 | * @last_frame_num: Number of last frame. Range from 0 to 32768 |
| 1016 | * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is |
| 1017 | * defined, for missed SOFs tracking. Array holds that |
| 1018 | * frame numbers, which not equal to last_frame_num +1 |
| 1019 | * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is |
| 1020 | * defined, for missed SOFs tracking. |
| 1021 | * If current_frame_number != last_frame_num+1 |
| 1022 | * then last_frame_num added to this array |
| 1023 | * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array |
| 1024 | * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed |
| 1025 | * 0 - if missed SOFs frame numbers not dumbed |
| 1026 | * @fifo_mem: Total internal RAM for FIFOs (bytes) |
| 1027 | * @fifo_map: Each bit intend for concrete fifo. If that bit is set, |
| 1028 | * then that fifo is used |
| 1029 | * @gadget: Represents a usb slave device |
| 1030 | * @connected: Used in slave mode. True if device connected with host |
| 1031 | * @eps_in: The IN endpoints being supplied to the gadget framework |
| 1032 | * @eps_out: The OUT endpoints being supplied to the gadget framework |
| 1033 | * @new_connection: Used in host mode. True if there are new connected |
| 1034 | * device |
| 1035 | * @enabled: Indicates the enabling state of controller |
| 1036 | * |
| 1037 | */ |
| 1038 | struct dwc2_hsotg { |
| 1039 | struct device *dev; |
| 1040 | void __iomem *regs; |
| 1041 | /** Params detected from hardware */ |
| 1042 | struct dwc2_hw_params hw_params; |
| 1043 | /** Params to actually use */ |
| 1044 | struct dwc2_core_params params; |
| 1045 | enum usb_otg_state op_state; |
| 1046 | enum usb_dr_mode dr_mode; |
| 1047 | unsigned int hcd_enabled:1; |
| 1048 | unsigned int gadget_enabled:1; |
| 1049 | unsigned int ll_hw_enabled:1; |
| 1050 | unsigned int hibernated:1; |
| 1051 | unsigned int reset_phy_on_wake:1; |
| 1052 | u16 frame_number; |
| 1053 | |
| 1054 | struct phy *phy; |
| 1055 | struct usb_phy *uphy; |
| 1056 | struct dwc2_hsotg_plat *plat; |
| 1057 | struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; |
| 1058 | struct regulator *vbus_supply; |
| 1059 | |
| 1060 | spinlock_t lock; |
| 1061 | void *priv; |
| 1062 | int irq; |
| 1063 | struct clk *clk; |
| 1064 | struct reset_control *reset; |
| 1065 | struct reset_control *reset_ecc; |
| 1066 | |
| 1067 | unsigned int queuing_high_bandwidth:1; |
| 1068 | unsigned int srp_success:1; |
| 1069 | |
| 1070 | struct workqueue_struct *wq_otg; |
| 1071 | struct work_struct wf_otg; |
| 1072 | struct timer_list wkp_timer; |
| 1073 | enum dwc2_lx_state lx_state; |
| 1074 | struct dwc2_gregs_backup gr_backup; |
| 1075 | struct dwc2_dregs_backup dr_backup; |
| 1076 | struct dwc2_hregs_backup hr_backup; |
| 1077 | |
| 1078 | struct dentry *debug_root; |
| 1079 | struct debugfs_regset32 *regset; |
| 1080 | bool needs_byte_swap; |
| 1081 | |
| 1082 | /* DWC OTG HW Release versions */ |
| 1083 | #define DWC2_CORE_REV_2_71a 0x4f54271a |
| 1084 | #define DWC2_CORE_REV_2_72a 0x4f54272a |
| 1085 | #define DWC2_CORE_REV_2_80a 0x4f54280a |
| 1086 | #define DWC2_CORE_REV_2_90a 0x4f54290a |
| 1087 | #define DWC2_CORE_REV_2_91a 0x4f54291a |
| 1088 | #define DWC2_CORE_REV_2_92a 0x4f54292a |
| 1089 | #define DWC2_CORE_REV_2_94a 0x4f54294a |
| 1090 | #define DWC2_CORE_REV_3_00a 0x4f54300a |
| 1091 | #define DWC2_CORE_REV_3_10a 0x4f54310a |
| 1092 | #define DWC2_CORE_REV_4_00a 0x4f54400a |
| 1093 | #define DWC2_FS_IOT_REV_1_00a 0x5531100a |
| 1094 | #define DWC2_HS_IOT_REV_1_00a 0x5532100a |
| 1095 | |
| 1096 | /* DWC OTG HW Core ID */ |
| 1097 | #define DWC2_OTG_ID 0x4f540000 |
| 1098 | #define DWC2_FS_IOT_ID 0x55310000 |
| 1099 | #define DWC2_HS_IOT_ID 0x55320000 |
| 1100 | |
| 1101 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 1102 | union dwc2_hcd_internal_flags { |
| 1103 | u32 d32; |
| 1104 | struct { |
| 1105 | unsigned port_connect_status_change:1; |
| 1106 | unsigned port_connect_status:1; |
| 1107 | unsigned port_reset_change:1; |
| 1108 | unsigned port_enable_change:1; |
| 1109 | unsigned port_suspend_change:1; |
| 1110 | unsigned port_over_current_change:1; |
| 1111 | unsigned port_l1_change:1; |
| 1112 | unsigned reserved:25; |
| 1113 | } b; |
| 1114 | } flags; |
| 1115 | |
| 1116 | struct list_head non_periodic_sched_inactive; |
| 1117 | struct list_head non_periodic_sched_waiting; |
| 1118 | struct list_head non_periodic_sched_active; |
| 1119 | struct list_head *non_periodic_qh_ptr; |
| 1120 | struct list_head periodic_sched_inactive; |
| 1121 | struct list_head periodic_sched_ready; |
| 1122 | struct list_head periodic_sched_assigned; |
| 1123 | struct list_head periodic_sched_queued; |
| 1124 | struct list_head split_order; |
| 1125 | u16 periodic_usecs; |
| 1126 | unsigned long hs_periodic_bitmap[ |
| 1127 | DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; |
| 1128 | u16 periodic_qh_count; |
| 1129 | bool bus_suspended; |
| 1130 | bool new_connection; |
| 1131 | |
| 1132 | u16 last_frame_num; |
| 1133 | |
| 1134 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS |
| 1135 | #define FRAME_NUM_ARRAY_SIZE 1000 |
| 1136 | u16 *frame_num_array; |
| 1137 | u16 *last_frame_num_array; |
| 1138 | int frame_num_idx; |
| 1139 | int dumped_frame_num_array; |
| 1140 | #endif |
| 1141 | |
| 1142 | struct list_head free_hc_list; |
| 1143 | int periodic_channels; |
| 1144 | int non_periodic_channels; |
| 1145 | int available_host_channels; |
| 1146 | struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; |
| 1147 | u8 *status_buf; |
| 1148 | dma_addr_t status_buf_dma; |
| 1149 | #define DWC2_HCD_STATUS_BUF_SIZE 64 |
| 1150 | |
| 1151 | struct delayed_work start_work; |
| 1152 | struct delayed_work reset_work; |
| 1153 | struct work_struct phy_reset_work; |
| 1154 | u8 otg_port; |
| 1155 | u32 *frame_list; |
| 1156 | dma_addr_t frame_list_dma; |
| 1157 | u32 frame_list_sz; |
| 1158 | struct kmem_cache *desc_gen_cache; |
| 1159 | struct kmem_cache *desc_hsisoc_cache; |
| 1160 | struct kmem_cache *unaligned_cache; |
| 1161 | #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 |
| 1162 | |
| 1163 | #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ |
| 1164 | |
| 1165 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
| 1166 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 1167 | /* Gadget structures */ |
| 1168 | struct usb_gadget_driver *driver; |
| 1169 | int fifo_mem; |
| 1170 | unsigned int dedicated_fifos:1; |
| 1171 | unsigned char num_of_eps; |
| 1172 | u32 fifo_map; |
| 1173 | |
| 1174 | struct usb_request *ep0_reply; |
| 1175 | struct usb_request *ctrl_req; |
| 1176 | void *ep0_buff; |
| 1177 | void *ctrl_buff; |
| 1178 | enum dwc2_ep0_state ep0_state; |
| 1179 | unsigned delayed_status : 1; |
| 1180 | u8 test_mode; |
| 1181 | |
| 1182 | dma_addr_t setup_desc_dma[2]; |
| 1183 | struct dwc2_dma_desc *setup_desc[2]; |
| 1184 | dma_addr_t ctrl_in_desc_dma; |
| 1185 | struct dwc2_dma_desc *ctrl_in_desc; |
| 1186 | dma_addr_t ctrl_out_desc_dma; |
| 1187 | struct dwc2_dma_desc *ctrl_out_desc; |
| 1188 | |
| 1189 | struct usb_gadget gadget; |
| 1190 | unsigned int enabled:1; |
| 1191 | unsigned int connected:1; |
| 1192 | unsigned int remote_wakeup_allowed:1; |
| 1193 | struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; |
| 1194 | struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; |
| 1195 | #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ |
| 1196 | }; |
| 1197 | |
| 1198 | /* Normal architectures just use readl/write */ |
| 1199 | static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) |
| 1200 | { |
| 1201 | u32 val; |
| 1202 | |
| 1203 | val = readl(hsotg->regs + offset); |
| 1204 | if (hsotg->needs_byte_swap) |
| 1205 | return swab32(val); |
| 1206 | else |
| 1207 | return val; |
| 1208 | } |
| 1209 | |
| 1210 | static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) |
| 1211 | { |
| 1212 | if (hsotg->needs_byte_swap) |
| 1213 | writel(swab32(value), hsotg->regs + offset); |
| 1214 | else |
| 1215 | writel(value, hsotg->regs + offset); |
| 1216 | |
| 1217 | #ifdef DWC2_LOG_WRITES |
| 1218 | pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); |
| 1219 | #endif |
| 1220 | } |
| 1221 | |
| 1222 | static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, |
| 1223 | void *buffer, unsigned int count) |
| 1224 | { |
| 1225 | if (count) { |
| 1226 | u32 *buf = buffer; |
| 1227 | |
| 1228 | do { |
| 1229 | u32 x = dwc2_readl(hsotg, offset); |
| 1230 | *buf++ = x; |
| 1231 | } while (--count); |
| 1232 | } |
| 1233 | } |
| 1234 | |
| 1235 | static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, |
| 1236 | const void *buffer, unsigned int count) |
| 1237 | { |
| 1238 | if (count) { |
| 1239 | const u32 *buf = buffer; |
| 1240 | |
| 1241 | do { |
| 1242 | dwc2_writel(hsotg, *buf++, offset); |
| 1243 | } while (--count); |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | /* Reasons for halting a host channel */ |
| 1248 | enum dwc2_halt_status { |
| 1249 | DWC2_HC_XFER_NO_HALT_STATUS, |
| 1250 | DWC2_HC_XFER_COMPLETE, |
| 1251 | DWC2_HC_XFER_URB_COMPLETE, |
| 1252 | DWC2_HC_XFER_ACK, |
| 1253 | DWC2_HC_XFER_NAK, |
| 1254 | DWC2_HC_XFER_NYET, |
| 1255 | DWC2_HC_XFER_STALL, |
| 1256 | DWC2_HC_XFER_XACT_ERR, |
| 1257 | DWC2_HC_XFER_FRAME_OVERRUN, |
| 1258 | DWC2_HC_XFER_BABBLE_ERR, |
| 1259 | DWC2_HC_XFER_DATA_TOGGLE_ERR, |
| 1260 | DWC2_HC_XFER_AHB_ERR, |
| 1261 | DWC2_HC_XFER_PERIODIC_INCOMPLETE, |
| 1262 | DWC2_HC_XFER_URB_DEQUEUE, |
| 1263 | }; |
| 1264 | |
| 1265 | /* Core version information */ |
| 1266 | static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) |
| 1267 | { |
| 1268 | return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; |
| 1269 | } |
| 1270 | |
| 1271 | static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) |
| 1272 | { |
| 1273 | return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; |
| 1274 | } |
| 1275 | |
| 1276 | static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) |
| 1277 | { |
| 1278 | return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; |
| 1279 | } |
| 1280 | |
| 1281 | /* |
| 1282 | * The following functions support initialization of the core driver component |
| 1283 | * and the DWC_otg controller |
| 1284 | */ |
| 1285 | int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); |
| 1286 | int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); |
| 1287 | int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); |
| 1288 | int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); |
| 1289 | int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, |
| 1290 | int reset, int is_host); |
| 1291 | void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); |
| 1292 | int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); |
| 1293 | |
| 1294 | void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); |
| 1295 | void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); |
| 1296 | |
| 1297 | bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); |
| 1298 | |
| 1299 | /* |
| 1300 | * Common core Functions. |
| 1301 | * The following functions support managing the DWC_otg controller in either |
| 1302 | * device or host mode. |
| 1303 | */ |
| 1304 | void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); |
| 1305 | void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); |
| 1306 | void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); |
| 1307 | |
| 1308 | void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); |
| 1309 | void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); |
| 1310 | |
| 1311 | void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, |
| 1312 | int is_host); |
| 1313 | int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); |
| 1314 | int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); |
| 1315 | |
| 1316 | void dwc2_enable_acg(struct dwc2_hsotg *hsotg); |
| 1317 | |
| 1318 | /* This function should be called on every hardware interrupt. */ |
| 1319 | irqreturn_t dwc2_handle_common_intr(int irq, void *dev); |
| 1320 | |
| 1321 | /* The device ID match table */ |
| 1322 | extern const struct of_device_id dwc2_of_match_table[]; |
| 1323 | |
| 1324 | int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); |
| 1325 | int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); |
| 1326 | |
| 1327 | /* Common polling functions */ |
| 1328 | int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, |
| 1329 | u32 timeout); |
| 1330 | int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, |
| 1331 | u32 timeout); |
| 1332 | /* Parameters */ |
| 1333 | int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); |
| 1334 | int dwc2_init_params(struct dwc2_hsotg *hsotg); |
| 1335 | |
| 1336 | /* |
| 1337 | * The following functions check the controller's OTG operation mode |
| 1338 | * capability (GHWCFG2.OTG_MODE). |
| 1339 | * |
| 1340 | * These functions can be used before the internal hsotg->hw_params |
| 1341 | * are read in and cached so they always read directly from the |
| 1342 | * GHWCFG2 register. |
| 1343 | */ |
| 1344 | unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); |
| 1345 | bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); |
| 1346 | bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); |
| 1347 | bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); |
| 1348 | |
| 1349 | /* |
| 1350 | * Returns the mode of operation, host or device |
| 1351 | */ |
| 1352 | static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) |
| 1353 | { |
| 1354 | return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; |
| 1355 | } |
| 1356 | |
| 1357 | static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) |
| 1358 | { |
| 1359 | return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; |
| 1360 | } |
| 1361 | |
| 1362 | /* |
| 1363 | * Dump core registers and SPRAM |
| 1364 | */ |
| 1365 | void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); |
| 1366 | void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); |
| 1367 | void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); |
| 1368 | |
| 1369 | /* Gadget defines */ |
| 1370 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
| 1371 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 1372 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); |
| 1373 | int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); |
| 1374 | int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); |
| 1375 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg); |
| 1376 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
| 1377 | bool reset); |
| 1378 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); |
| 1379 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); |
| 1380 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); |
| 1381 | #define dwc2_is_device_connected(hsotg) (hsotg->connected) |
| 1382 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); |
| 1383 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); |
| 1384 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); |
| 1385 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, |
| 1386 | int rem_wakeup, int reset); |
| 1387 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); |
| 1388 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); |
| 1389 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); |
| 1390 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); |
| 1391 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); |
| 1392 | #else |
| 1393 | static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) |
| 1394 | { return 0; } |
| 1395 | static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) |
| 1396 | { return 0; } |
| 1397 | static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) |
| 1398 | { return 0; } |
| 1399 | static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
| 1400 | { return 0; } |
| 1401 | static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
| 1402 | bool reset) {} |
| 1403 | static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} |
| 1404 | static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} |
| 1405 | static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, |
| 1406 | int testmode) |
| 1407 | { return 0; } |
| 1408 | #define dwc2_is_device_connected(hsotg) (0) |
| 1409 | static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
| 1410 | { return 0; } |
| 1411 | static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, |
| 1412 | int remote_wakeup) |
| 1413 | { return 0; } |
| 1414 | static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) |
| 1415 | { return 0; } |
| 1416 | static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, |
| 1417 | int rem_wakeup, int reset) |
| 1418 | { return 0; } |
| 1419 | static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) |
| 1420 | { return 0; } |
| 1421 | static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) |
| 1422 | { return 0; } |
| 1423 | static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) |
| 1424 | { return 0; } |
| 1425 | static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} |
| 1426 | static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} |
| 1427 | #endif |
| 1428 | |
| 1429 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 1430 | int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); |
| 1431 | int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); |
| 1432 | void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); |
| 1433 | void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); |
| 1434 | void dwc2_hcd_start(struct dwc2_hsotg *hsotg); |
| 1435 | int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); |
| 1436 | int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); |
| 1437 | int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); |
| 1438 | int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); |
| 1439 | int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, |
| 1440 | int rem_wakeup, int reset); |
| 1441 | static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) |
| 1442 | { schedule_work(&hsotg->phy_reset_work); } |
| 1443 | #else |
| 1444 | static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) |
| 1445 | { return 0; } |
| 1446 | static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, |
| 1447 | int us) |
| 1448 | { return 0; } |
| 1449 | static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} |
| 1450 | static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} |
| 1451 | static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} |
| 1452 | static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} |
| 1453 | static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) |
| 1454 | { return 0; } |
| 1455 | static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) |
| 1456 | { return 0; } |
| 1457 | static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) |
| 1458 | { return 0; } |
| 1459 | static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) |
| 1460 | { return 0; } |
| 1461 | static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) |
| 1462 | { return 0; } |
| 1463 | static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, |
| 1464 | int rem_wakeup, int reset) |
| 1465 | { return 0; } |
| 1466 | static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} |
| 1467 | |
| 1468 | #endif |
| 1469 | |
| 1470 | #endif /* __DWC2_CORE_H__ */ |