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Merge tag 'mm-hotfixes-stable-2025-07-11-16-16' of git://git.kernel.org/pub/scm/linux...
[linux-2.6-block.git] / drivers / spi / spi-pxa2xx.c
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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#include <linux/atomic.h>
8#include <linux/bitops.h>
9#include <linux/bug.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/dmaengine.h>
14#include <linux/err.h>
15#include <linux/gpio/consumer.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/math64.h>
20#include <linux/minmax.h>
21#include <linux/module.h>
22#include <linux/pm_runtime.h>
23#include <linux/property.h>
24#include <linux/slab.h>
25#include <linux/types.h>
26
27#include <linux/spi/spi.h>
28
29#include "internals.h"
30#include "spi-pxa2xx.h"
31
32#define TIMOUT_DFLT 1000
33
34/*
35 * For testing SSCR1 changes that require SSP restart, basically
36 * everything except the service and interrupt enables, the PXA270 developer
37 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
38 * list, but the PXA255 developer manual says all bits without really meaning
39 * the service and interrupt enables.
40 */
41#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
42 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
43 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
44 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
45 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
46 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
47
48#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
49 | QUARK_X1000_SSCR1_EFWR \
50 | QUARK_X1000_SSCR1_RFT \
51 | QUARK_X1000_SSCR1_TFT \
52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
53
54#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
56 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
57 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
58 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
60
61struct chip_data {
62 u32 cr1;
63 u32 dds_rate;
64 u32 threshold;
65 u16 lpss_rx_threshold;
66 u16 lpss_tx_threshold;
67};
68
69#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
70#define LPSS_CS_CONTROL_SW_MODE BIT(0)
71#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
72#define LPSS_CAPS_CS_EN_SHIFT 9
73#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
74
75#define LPSS_PRIV_CLOCK_GATE 0x38
76#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
77#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
78#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF 0x0
79
80struct lpss_config {
81 /* LPSS offset from drv_data->ioaddr */
82 unsigned offset;
83 /* Register offsets from drv_data->lpss_base or -1 */
84 int reg_general;
85 int reg_ssp;
86 int reg_cs_ctrl;
87 int reg_capabilities;
88 /* FIFO thresholds */
89 u32 rx_threshold;
90 u32 tx_threshold_lo;
91 u32 tx_threshold_hi;
92 /* Chip select control */
93 unsigned cs_sel_shift;
94 unsigned cs_sel_mask;
95 /* Quirks */
96 unsigned cs_clk_stays_gated : 1;
97};
98
99/* Keep these sorted with enum pxa_ssp_type */
100static const struct lpss_config lpss_platforms[] = {
101 { /* LPSS_LPT_SSP */
102 .offset = 0x800,
103 .reg_general = 0x08,
104 .reg_ssp = 0x0c,
105 .reg_cs_ctrl = 0x18,
106 .reg_capabilities = -1,
107 .rx_threshold = 64,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
110 },
111 { /* LPSS_BYT_SSP */
112 .offset = 0x400,
113 .reg_general = 0x08,
114 .reg_ssp = 0x0c,
115 .reg_cs_ctrl = 0x18,
116 .reg_capabilities = -1,
117 .rx_threshold = 64,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
120 },
121 { /* LPSS_BSW_SSP */
122 .offset = 0x400,
123 .reg_general = 0x08,
124 .reg_ssp = 0x0c,
125 .reg_cs_ctrl = 0x18,
126 .reg_capabilities = -1,
127 .rx_threshold = 64,
128 .tx_threshold_lo = 160,
129 .tx_threshold_hi = 224,
130 .cs_sel_shift = 2,
131 .cs_sel_mask = 1 << 2,
132 },
133 { /* LPSS_SPT_SSP */
134 .offset = 0x200,
135 .reg_general = -1,
136 .reg_ssp = 0x20,
137 .reg_cs_ctrl = 0x24,
138 .reg_capabilities = -1,
139 .rx_threshold = 1,
140 .tx_threshold_lo = 32,
141 .tx_threshold_hi = 56,
142 },
143 { /* LPSS_BXT_SSP */
144 .offset = 0x200,
145 .reg_general = -1,
146 .reg_ssp = 0x20,
147 .reg_cs_ctrl = 0x24,
148 .reg_capabilities = 0xfc,
149 .rx_threshold = 1,
150 .tx_threshold_lo = 16,
151 .tx_threshold_hi = 48,
152 .cs_sel_shift = 8,
153 .cs_sel_mask = 3 << 8,
154 .cs_clk_stays_gated = true,
155 },
156 { /* LPSS_CNL_SSP */
157 .offset = 0x200,
158 .reg_general = -1,
159 .reg_ssp = 0x20,
160 .reg_cs_ctrl = 0x24,
161 .reg_capabilities = 0xfc,
162 .rx_threshold = 1,
163 .tx_threshold_lo = 32,
164 .tx_threshold_hi = 56,
165 .cs_sel_shift = 8,
166 .cs_sel_mask = 3 << 8,
167 .cs_clk_stays_gated = true,
168 },
169};
170
171static inline const struct lpss_config
172*lpss_get_config(const struct driver_data *drv_data)
173{
174 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
175}
176
177static bool is_lpss_ssp(const struct driver_data *drv_data)
178{
179 switch (drv_data->ssp_type) {
180 case LPSS_LPT_SSP:
181 case LPSS_BYT_SSP:
182 case LPSS_BSW_SSP:
183 case LPSS_SPT_SSP:
184 case LPSS_BXT_SSP:
185 case LPSS_CNL_SSP:
186 return true;
187 default:
188 return false;
189 }
190}
191
192static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
193{
194 return drv_data->ssp_type == QUARK_X1000_SSP;
195}
196
197static bool is_mmp2_ssp(const struct driver_data *drv_data)
198{
199 return drv_data->ssp_type == MMP2_SSP;
200}
201
202static bool is_mrfld_ssp(const struct driver_data *drv_data)
203{
204 return drv_data->ssp_type == MRFLD_SSP;
205}
206
207static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
208{
209 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
210 pxa2xx_spi_write(drv_data, reg, value & mask);
211}
212
213static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
214{
215 switch (drv_data->ssp_type) {
216 case QUARK_X1000_SSP:
217 return QUARK_X1000_SSCR1_CHANGE_MASK;
218 case CE4100_SSP:
219 return CE4100_SSCR1_CHANGE_MASK;
220 default:
221 return SSCR1_CHANGE_MASK;
222 }
223}
224
225static u32
226pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
227{
228 switch (drv_data->ssp_type) {
229 case QUARK_X1000_SSP:
230 return RX_THRESH_QUARK_X1000_DFLT;
231 case CE4100_SSP:
232 return RX_THRESH_CE4100_DFLT;
233 default:
234 return RX_THRESH_DFLT;
235 }
236}
237
238static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
239{
240 u32 mask;
241
242 switch (drv_data->ssp_type) {
243 case QUARK_X1000_SSP:
244 mask = QUARK_X1000_SSSR_TFL_MASK;
245 break;
246 case CE4100_SSP:
247 mask = CE4100_SSSR_TFL_MASK;
248 break;
249 default:
250 mask = SSSR_TFL_MASK;
251 break;
252 }
253
254 return read_SSSR_bits(drv_data, mask) == mask;
255}
256
257static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
258 u32 *sccr1_reg)
259{
260 u32 mask;
261
262 switch (drv_data->ssp_type) {
263 case QUARK_X1000_SSP:
264 mask = QUARK_X1000_SSCR1_RFT;
265 break;
266 case CE4100_SSP:
267 mask = CE4100_SSCR1_RFT;
268 break;
269 default:
270 mask = SSCR1_RFT;
271 break;
272 }
273 *sccr1_reg &= ~mask;
274}
275
276static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
277 u32 *sccr1_reg, u32 threshold)
278{
279 switch (drv_data->ssp_type) {
280 case QUARK_X1000_SSP:
281 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
282 break;
283 case CE4100_SSP:
284 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
285 break;
286 default:
287 *sccr1_reg |= SSCR1_RxTresh(threshold);
288 break;
289 }
290}
291
292static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
293 u32 clk_div, u8 bits)
294{
295 switch (drv_data->ssp_type) {
296 case QUARK_X1000_SSP:
297 return clk_div
298 | QUARK_X1000_SSCR0_Motorola
299 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
300 default:
301 return clk_div
302 | SSCR0_Motorola
303 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
304 | (bits > 16 ? SSCR0_EDSS : 0);
305 }
306}
307
308/*
309 * Read and write LPSS SSP private registers. Caller must first check that
310 * is_lpss_ssp() returns true before these can be called.
311 */
312static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
313{
314 WARN_ON(!drv_data->lpss_base);
315 return readl(drv_data->lpss_base + offset);
316}
317
318static void __lpss_ssp_write_priv(struct driver_data *drv_data,
319 unsigned offset, u32 value)
320{
321 WARN_ON(!drv_data->lpss_base);
322 writel(value, drv_data->lpss_base + offset);
323}
324
325static bool __lpss_ssp_update_priv(struct driver_data *drv_data, unsigned int offset,
326 u32 mask, u32 value)
327{
328 u32 new, curr;
329
330 curr = __lpss_ssp_read_priv(drv_data, offset);
331 new = (curr & ~mask) | (value & mask);
332 if (new == curr)
333 return false;
334
335 __lpss_ssp_write_priv(drv_data, offset, new);
336 return true;
337}
338
339/*
340 * lpss_ssp_setup - perform LPSS SSP specific setup
341 * @drv_data: pointer to the driver private data
342 *
343 * Perform LPSS SSP specific setup. This function must be called first if
344 * one is going to use LPSS SSP private registers.
345 */
346static void lpss_ssp_setup(struct driver_data *drv_data)
347{
348 const struct lpss_config *config;
349 u32 value;
350
351 config = lpss_get_config(drv_data);
352 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
353
354 /* Enable software chip select control */
355 value = LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
356 __lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, value, value);
357
358 /* Enable multiblock DMA transfers */
359 if (drv_data->controller_info->enable_dma) {
360 __lpss_ssp_update_priv(drv_data, config->reg_ssp, BIT(0), BIT(0));
361
362 if (config->reg_general >= 0) {
363 value = LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
364 __lpss_ssp_update_priv(drv_data, config->reg_general, value, value);
365 }
366 }
367}
368
369static void lpss_ssp_select_cs(struct spi_device *spi,
370 const struct lpss_config *config)
371{
372 struct driver_data *drv_data =
373 spi_controller_get_devdata(spi->controller);
374 u32 cs;
375
376 cs = spi_get_chipselect(spi, 0) << config->cs_sel_shift;
377 if (!__lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, config->cs_sel_mask, cs))
378 return;
379
380 /*
381 * When switching another chip select output active the output must be
382 * selected first and wait 2 ssp_clk cycles before changing state to
383 * active. Otherwise a short glitch will occur on the previous chip
384 * select since output select is latched but state control is not.
385 */
386 ndelay(1000000000 / (drv_data->controller->max_speed_hz / 2));
387}
388
389static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
390{
391 struct driver_data *drv_data =
392 spi_controller_get_devdata(spi->controller);
393 const struct lpss_config *config;
394 u32 mask;
395
396 config = lpss_get_config(drv_data);
397
398 if (enable)
399 lpss_ssp_select_cs(spi, config);
400
401 mask = LPSS_CS_CONTROL_CS_HIGH;
402 __lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, mask, enable ? 0 : mask);
403 if (config->cs_clk_stays_gated) {
404 /*
405 * Changing CS alone when dynamic clock gating is on won't
406 * actually flip CS at that time. This ruins SPI transfers
407 * that specify delays, or have no data. Toggle the clock mode
408 * to force on briefly to poke the CS pin to move.
409 */
410 mask = LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK;
411 if (__lpss_ssp_update_priv(drv_data, LPSS_PRIV_CLOCK_GATE, mask,
412 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON))
413 __lpss_ssp_update_priv(drv_data, LPSS_PRIV_CLOCK_GATE, mask,
414 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF);
415 }
416}
417
418static void cs_assert(struct spi_device *spi)
419{
420 struct driver_data *drv_data =
421 spi_controller_get_devdata(spi->controller);
422
423 if (drv_data->ssp_type == CE4100_SSP) {
424 pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0));
425 return;
426 }
427
428 if (is_lpss_ssp(drv_data))
429 lpss_ssp_cs_control(spi, true);
430}
431
432static void cs_deassert(struct spi_device *spi)
433{
434 struct driver_data *drv_data =
435 spi_controller_get_devdata(spi->controller);
436 unsigned long timeout;
437
438 if (drv_data->ssp_type == CE4100_SSP)
439 return;
440
441 /* Wait until SSP becomes idle before deasserting the CS */
442 timeout = jiffies + msecs_to_jiffies(10);
443 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
444 !time_after(jiffies, timeout))
445 cpu_relax();
446
447 if (is_lpss_ssp(drv_data))
448 lpss_ssp_cs_control(spi, false);
449}
450
451static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
452{
453 if (level)
454 cs_deassert(spi);
455 else
456 cs_assert(spi);
457}
458
459int pxa2xx_spi_flush(struct driver_data *drv_data)
460{
461 unsigned long limit = loops_per_jiffy << 1;
462
463 do {
464 while (read_SSSR_bits(drv_data, SSSR_RNE))
465 pxa2xx_spi_read(drv_data, SSDR);
466 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
467 write_SSSR_CS(drv_data, SSSR_ROR);
468
469 return limit;
470}
471
472static void pxa2xx_spi_off(struct driver_data *drv_data)
473{
474 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
475 if (is_mmp2_ssp(drv_data))
476 return;
477
478 pxa_ssp_disable(drv_data->ssp);
479}
480
481static int null_writer(struct driver_data *drv_data)
482{
483 u8 n_bytes = drv_data->n_bytes;
484
485 if (pxa2xx_spi_txfifo_full(drv_data)
486 || (drv_data->tx == drv_data->tx_end))
487 return 0;
488
489 pxa2xx_spi_write(drv_data, SSDR, 0);
490 drv_data->tx += n_bytes;
491
492 return 1;
493}
494
495static int null_reader(struct driver_data *drv_data)
496{
497 u8 n_bytes = drv_data->n_bytes;
498
499 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
500 pxa2xx_spi_read(drv_data, SSDR);
501 drv_data->rx += n_bytes;
502 }
503
504 return drv_data->rx == drv_data->rx_end;
505}
506
507static int u8_writer(struct driver_data *drv_data)
508{
509 if (pxa2xx_spi_txfifo_full(drv_data)
510 || (drv_data->tx == drv_data->tx_end))
511 return 0;
512
513 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
514 ++drv_data->tx;
515
516 return 1;
517}
518
519static int u8_reader(struct driver_data *drv_data)
520{
521 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
522 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
523 ++drv_data->rx;
524 }
525
526 return drv_data->rx == drv_data->rx_end;
527}
528
529static int u16_writer(struct driver_data *drv_data)
530{
531 if (pxa2xx_spi_txfifo_full(drv_data)
532 || (drv_data->tx == drv_data->tx_end))
533 return 0;
534
535 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
536 drv_data->tx += 2;
537
538 return 1;
539}
540
541static int u16_reader(struct driver_data *drv_data)
542{
543 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
544 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
545 drv_data->rx += 2;
546 }
547
548 return drv_data->rx == drv_data->rx_end;
549}
550
551static int u32_writer(struct driver_data *drv_data)
552{
553 if (pxa2xx_spi_txfifo_full(drv_data)
554 || (drv_data->tx == drv_data->tx_end))
555 return 0;
556
557 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
558 drv_data->tx += 4;
559
560 return 1;
561}
562
563static int u32_reader(struct driver_data *drv_data)
564{
565 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
566 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
567 drv_data->rx += 4;
568 }
569
570 return drv_data->rx == drv_data->rx_end;
571}
572
573static void reset_sccr1(struct driver_data *drv_data)
574{
575 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
576 struct chip_data *chip;
577
578 if (drv_data->controller->cur_msg) {
579 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
580 threshold = chip->threshold;
581 } else {
582 threshold = 0;
583 }
584
585 switch (drv_data->ssp_type) {
586 case QUARK_X1000_SSP:
587 mask |= QUARK_X1000_SSCR1_RFT;
588 break;
589 case CE4100_SSP:
590 mask |= CE4100_SSCR1_RFT;
591 break;
592 default:
593 mask |= SSCR1_RFT;
594 break;
595 }
596
597 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
598}
599
600static void int_stop_and_reset(struct driver_data *drv_data)
601{
602 /* Clear and disable interrupts */
603 write_SSSR_CS(drv_data, drv_data->clear_sr);
604 reset_sccr1(drv_data);
605 if (pxa25x_ssp_comp(drv_data))
606 return;
607
608 pxa2xx_spi_write(drv_data, SSTO, 0);
609}
610
611static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
612{
613 int_stop_and_reset(drv_data);
614 pxa2xx_spi_flush(drv_data);
615 pxa2xx_spi_off(drv_data);
616
617 dev_err(drv_data->ssp->dev, "%s\n", msg);
618
619 drv_data->controller->cur_msg->status = err;
620 spi_finalize_current_transfer(drv_data->controller);
621}
622
623static void int_transfer_complete(struct driver_data *drv_data)
624{
625 int_stop_and_reset(drv_data);
626
627 spi_finalize_current_transfer(drv_data->controller);
628}
629
630static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
631{
632 u32 irq_status;
633
634 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
635 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
636 irq_status &= ~SSSR_TFS;
637
638 if (irq_status & SSSR_ROR) {
639 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
640 return IRQ_HANDLED;
641 }
642
643 if (irq_status & SSSR_TUR) {
644 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
645 return IRQ_HANDLED;
646 }
647
648 if (irq_status & SSSR_TINT) {
649 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
650 if (drv_data->read(drv_data)) {
651 int_transfer_complete(drv_data);
652 return IRQ_HANDLED;
653 }
654 }
655
656 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
657 do {
658 if (drv_data->read(drv_data)) {
659 int_transfer_complete(drv_data);
660 return IRQ_HANDLED;
661 }
662 } while (drv_data->write(drv_data));
663
664 if (drv_data->read(drv_data)) {
665 int_transfer_complete(drv_data);
666 return IRQ_HANDLED;
667 }
668
669 if (drv_data->tx == drv_data->tx_end) {
670 u32 bytes_left;
671 u32 sccr1_reg;
672
673 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
674 sccr1_reg &= ~SSCR1_TIE;
675
676 /*
677 * PXA25x_SSP has no timeout, set up Rx threshold for
678 * the remaining Rx bytes.
679 */
680 if (pxa25x_ssp_comp(drv_data)) {
681 u32 rx_thre;
682
683 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
684
685 bytes_left = drv_data->rx_end - drv_data->rx;
686 switch (drv_data->n_bytes) {
687 case 4:
688 bytes_left >>= 2;
689 break;
690 case 2:
691 bytes_left >>= 1;
692 break;
693 }
694
695 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
696 if (rx_thre > bytes_left)
697 rx_thre = bytes_left;
698
699 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
700 }
701 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
702 }
703
704 /* We did something */
705 return IRQ_HANDLED;
706}
707
708static void handle_bad_msg(struct driver_data *drv_data)
709{
710 int_stop_and_reset(drv_data);
711 pxa2xx_spi_off(drv_data);
712
713 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
714}
715
716static irqreturn_t ssp_int(int irq, void *dev_id)
717{
718 struct driver_data *drv_data = dev_id;
719 u32 sccr1_reg;
720 u32 mask = drv_data->mask_sr;
721 u32 status;
722
723 /*
724 * The IRQ might be shared with other peripherals so we must first
725 * check that are we RPM suspended or not. If we are we assume that
726 * the IRQ was not for us (we shouldn't be RPM suspended when the
727 * interrupt is enabled).
728 */
729 if (pm_runtime_suspended(drv_data->ssp->dev))
730 return IRQ_NONE;
731
732 /*
733 * If the device is not yet in RPM suspended state and we get an
734 * interrupt that is meant for another device, check if status bits
735 * are all set to one. That means that the device is already
736 * powered off.
737 */
738 status = pxa2xx_spi_read(drv_data, SSSR);
739 if (status == ~0)
740 return IRQ_NONE;
741
742 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
743
744 /* Ignore possible writes if we don't need to write */
745 if (!(sccr1_reg & SSCR1_TIE))
746 mask &= ~SSSR_TFS;
747
748 /* Ignore RX timeout interrupt if it is disabled */
749 if (!(sccr1_reg & SSCR1_TINTE))
750 mask &= ~SSSR_TINT;
751
752 if (!(status & mask))
753 return IRQ_NONE;
754
755 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
756 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
757
758 if (!drv_data->controller->cur_msg) {
759 handle_bad_msg(drv_data);
760 /* Never fail */
761 return IRQ_HANDLED;
762 }
763
764 return drv_data->transfer_handler(drv_data);
765}
766
767/*
768 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
769 * input frequency by fractions of 2^24. It also has a divider by 5.
770 *
771 * There are formulas to get baud rate value for given input frequency and
772 * divider parameters, such as DDS_CLK_RATE and SCR:
773 *
774 * Fsys = 200MHz
775 *
776 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
777 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
778 *
779 * DDS_CLK_RATE either 2^n or 2^n / 5.
780 * SCR is in range 0 .. 255
781 *
782 * Divisor = 5^i * 2^j * 2 * k
783 * i = [0, 1] i = 1 iff j = 0 or j > 3
784 * j = [0, 23] j = 0 iff i = 1
785 * k = [1, 256]
786 * Special case: j = 0, i = 1: Divisor = 2 / 5
787 *
788 * Accordingly to the specification the recommended values for DDS_CLK_RATE
789 * are:
790 * Case 1: 2^n, n = [0, 23]
791 * Case 2: 2^24 * 2 / 5 (0x666666)
792 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
793 *
794 * In all cases the lowest possible value is better.
795 *
796 * The function calculates parameters for all cases and chooses the one closest
797 * to the asked baud rate.
798 */
799static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
800{
801 unsigned long xtal = 200000000;
802 unsigned long fref = xtal / 2; /* mandatory division by 2,
803 see (2) */
804 /* case 3 */
805 unsigned long fref1 = fref / 2; /* case 1 */
806 unsigned long fref2 = fref * 2 / 5; /* case 2 */
807 unsigned long scale;
808 unsigned long q, q1, q2;
809 long r, r1, r2;
810 u32 mul;
811
812 /* Case 1 */
813
814 /* Set initial value for DDS_CLK_RATE */
815 mul = (1 << 24) >> 1;
816
817 /* Calculate initial quot */
818 q1 = DIV_ROUND_UP(fref1, rate);
819
820 /* Scale q1 if it's too big */
821 if (q1 > 256) {
822 /* Scale q1 to range [1, 512] */
823 scale = fls_long(q1 - 1);
824 if (scale > 9) {
825 q1 >>= scale - 9;
826 mul >>= scale - 9;
827 }
828
829 /* Round the result if we have a remainder */
830 q1 += q1 & 1;
831 }
832
833 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
834 scale = __ffs(q1);
835 q1 >>= scale;
836 mul >>= scale;
837
838 /* Get the remainder */
839 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
840
841 /* Case 2 */
842
843 q2 = DIV_ROUND_UP(fref2, rate);
844 r2 = abs(fref2 / q2 - rate);
845
846 /*
847 * Choose the best between two: less remainder we have the better. We
848 * can't go case 2 if q2 is greater than 256 since SCR register can
849 * hold only values 0 .. 255.
850 */
851 if (r2 >= r1 || q2 > 256) {
852 /* case 1 is better */
853 r = r1;
854 q = q1;
855 } else {
856 /* case 2 is better */
857 r = r2;
858 q = q2;
859 mul = (1 << 24) * 2 / 5;
860 }
861
862 /* Check case 3 only if the divisor is big enough */
863 if (fref / rate >= 80) {
864 u64 fssp;
865 u32 m;
866
867 /* Calculate initial quot */
868 q1 = DIV_ROUND_UP(fref, rate);
869 m = (1 << 24) / q1;
870
871 /* Get the remainder */
872 fssp = (u64)fref * m;
873 do_div(fssp, 1 << 24);
874 r1 = abs(fssp - rate);
875
876 /* Choose this one if it suits better */
877 if (r1 < r) {
878 /* case 3 is better */
879 q = 1;
880 mul = m;
881 }
882 }
883
884 *dds = mul;
885 return q - 1;
886}
887
888static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
889{
890 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
891 const struct ssp_device *ssp = drv_data->ssp;
892
893 rate = min_t(int, ssp_clk, rate);
894
895 /*
896 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
897 * that the SSP transmission rate can be greater than the device rate.
898 */
899 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
900 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
901 else
902 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
903}
904
905static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
906 int rate)
907{
908 struct chip_data *chip =
909 spi_get_ctldata(drv_data->controller->cur_msg->spi);
910 unsigned int clk_div;
911
912 switch (drv_data->ssp_type) {
913 case QUARK_X1000_SSP:
914 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
915 break;
916 default:
917 clk_div = ssp_get_clk_div(drv_data, rate);
918 break;
919 }
920 return clk_div << 8;
921}
922
923static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
924 struct spi_device *spi,
925 struct spi_transfer *xfer)
926{
927 struct driver_data *drv_data = spi_controller_get_devdata(controller);
928
929 return drv_data->controller_info->enable_dma &&
930 xfer->len <= MAX_DMA_LEN &&
931 xfer->len >= drv_data->controller_info->dma_burst_size;
932}
933
934static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
935 struct spi_device *spi,
936 struct spi_transfer *transfer)
937{
938 struct driver_data *drv_data = spi_controller_get_devdata(controller);
939 struct chip_data *chip = spi_get_ctldata(spi);
940 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
941 u32 dma_thresh;
942 u32 clk_div;
943 u8 bits;
944 u32 speed;
945 u32 cr0;
946 u32 cr1;
947 int err;
948 int dma_mapped;
949
950 /* Check if we can DMA this transfer */
951 if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) {
952 /* Warn ... we force this to PIO mode */
953 dev_warn_ratelimited(&spi->dev,
954 "DMA disabled for transfer length %u greater than %d\n",
955 transfer->len, MAX_DMA_LEN);
956 }
957
958 /* Setup the transfer state based on the type of transfer */
959 if (pxa2xx_spi_flush(drv_data) == 0) {
960 dev_err(&spi->dev, "Flush failed\n");
961 return -EIO;
962 }
963 drv_data->tx = (void *)transfer->tx_buf;
964 drv_data->tx_end = drv_data->tx + transfer->len;
965 drv_data->rx = transfer->rx_buf;
966 drv_data->rx_end = drv_data->rx + transfer->len;
967
968 /* Change speed and bit per word on a per transfer */
969 bits = transfer->bits_per_word;
970 speed = transfer->speed_hz;
971
972 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
973
974 if (bits <= 8) {
975 drv_data->n_bytes = 1;
976 drv_data->read = drv_data->rx ? u8_reader : null_reader;
977 drv_data->write = drv_data->tx ? u8_writer : null_writer;
978 } else if (bits <= 16) {
979 drv_data->n_bytes = 2;
980 drv_data->read = drv_data->rx ? u16_reader : null_reader;
981 drv_data->write = drv_data->tx ? u16_writer : null_writer;
982 } else if (bits <= 32) {
983 drv_data->n_bytes = 4;
984 drv_data->read = drv_data->rx ? u32_reader : null_reader;
985 drv_data->write = drv_data->tx ? u32_writer : null_writer;
986 }
987
988 dma_thresh = SSCR1_RxTresh(RX_THRESH_DFLT) | SSCR1_TxTresh(TX_THRESH_DFLT);
989 dma_mapped = spi_xfer_is_dma_mapped(controller, spi, transfer);
990 if (dma_mapped) {
991 /* Ensure we have the correct interrupt handler */
992 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
993
994 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
995 if (err)
996 return err;
997
998 /* Clear status and start DMA engine */
999 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1000 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1001
1002 pxa2xx_spi_dma_start(drv_data);
1003 } else {
1004 /* Ensure we have the correct interrupt handler */
1005 drv_data->transfer_handler = interrupt_transfer;
1006
1007 /* Clear status */
1008 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1009 write_SSSR_CS(drv_data, drv_data->clear_sr);
1010 }
1011
1012 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1013 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1014 if (!pxa25x_ssp_comp(drv_data))
1015 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1016 controller->max_speed_hz
1017 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1018 dma_mapped ? "DMA" : "PIO");
1019 else
1020 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1021 controller->max_speed_hz / 2
1022 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1023 dma_mapped ? "DMA" : "PIO");
1024
1025 if (is_lpss_ssp(drv_data)) {
1026 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1027 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1028 }
1029
1030 if (is_mrfld_ssp(drv_data)) {
1031 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1032 u32 thresh = 0;
1033
1034 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1035 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1036
1037 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1038 }
1039
1040 if (is_quark_x1000_ssp(drv_data))
1041 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1042
1043 /* Stop the SSP */
1044 if (!is_mmp2_ssp(drv_data))
1045 pxa_ssp_disable(drv_data->ssp);
1046
1047 if (!pxa25x_ssp_comp(drv_data))
1048 pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT);
1049
1050 /* First set CR1 without interrupt and service enables */
1051 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1052
1053 /* See if we need to reload the configuration registers */
1054 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1055
1056 /* Restart the SSP */
1057 pxa_ssp_enable(drv_data->ssp);
1058
1059 if (is_mmp2_ssp(drv_data)) {
1060 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1061
1062 if (tx_level) {
1063 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1064 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1065 if (tx_level > transfer->len)
1066 tx_level = transfer->len;
1067 drv_data->tx += tx_level;
1068 }
1069 }
1070
1071 if (spi_controller_is_target(controller)) {
1072 while (drv_data->write(drv_data))
1073 ;
1074 if (drv_data->gpiod_ready) {
1075 gpiod_set_value(drv_data->gpiod_ready, 1);
1076 udelay(1);
1077 gpiod_set_value(drv_data->gpiod_ready, 0);
1078 }
1079 }
1080
1081 /*
1082 * Release the data by enabling service requests and interrupts,
1083 * without changing any mode bits.
1084 */
1085 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1086
1087 return 1;
1088}
1089
1090static int pxa2xx_spi_target_abort(struct spi_controller *controller)
1091{
1092 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1093
1094 int_error_stop(drv_data, "transfer aborted", -EINTR);
1095
1096 return 0;
1097}
1098
1099static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1100 struct spi_message *msg)
1101{
1102 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1103
1104 int_stop_and_reset(drv_data);
1105
1106 /* Disable the SSP */
1107 pxa2xx_spi_off(drv_data);
1108
1109 /*
1110 * Stop the DMA if running. Note DMA callback handler may have unset
1111 * the dma_running already, which is fine as stopping is not needed
1112 * then but we shouldn't rely this flag for anything else than
1113 * stopping. For instance to differentiate between PIO and DMA
1114 * transfers.
1115 */
1116 if (atomic_read(&drv_data->dma_running))
1117 pxa2xx_spi_dma_stop(drv_data);
1118}
1119
1120static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1121{
1122 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1123
1124 /* Disable the SSP now */
1125 pxa2xx_spi_off(drv_data);
1126
1127 return 0;
1128}
1129
1130static int setup(struct spi_device *spi)
1131{
1132 struct chip_data *chip;
1133 const struct lpss_config *config;
1134 struct driver_data *drv_data =
1135 spi_controller_get_devdata(spi->controller);
1136 uint tx_thres, tx_hi_thres, rx_thres;
1137
1138 switch (drv_data->ssp_type) {
1139 case QUARK_X1000_SSP:
1140 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1141 tx_hi_thres = 0;
1142 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1143 break;
1144 case MRFLD_SSP:
1145 tx_thres = TX_THRESH_MRFLD_DFLT;
1146 tx_hi_thres = 0;
1147 rx_thres = RX_THRESH_MRFLD_DFLT;
1148 break;
1149 case CE4100_SSP:
1150 tx_thres = TX_THRESH_CE4100_DFLT;
1151 tx_hi_thres = 0;
1152 rx_thres = RX_THRESH_CE4100_DFLT;
1153 break;
1154 case LPSS_LPT_SSP:
1155 case LPSS_BYT_SSP:
1156 case LPSS_BSW_SSP:
1157 case LPSS_SPT_SSP:
1158 case LPSS_BXT_SSP:
1159 case LPSS_CNL_SSP:
1160 config = lpss_get_config(drv_data);
1161 tx_thres = config->tx_threshold_lo;
1162 tx_hi_thres = config->tx_threshold_hi;
1163 rx_thres = config->rx_threshold;
1164 break;
1165 default:
1166 tx_hi_thres = 0;
1167 if (spi_controller_is_target(drv_data->controller)) {
1168 tx_thres = 1;
1169 rx_thres = 2;
1170 } else {
1171 tx_thres = TX_THRESH_DFLT;
1172 rx_thres = RX_THRESH_DFLT;
1173 }
1174 break;
1175 }
1176
1177 if (drv_data->ssp_type == CE4100_SSP) {
1178 if (spi_get_chipselect(spi, 0) > 4) {
1179 dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n");
1180 return -EINVAL;
1181 }
1182 }
1183
1184 /* Only allocate on the first setup */
1185 chip = spi_get_ctldata(spi);
1186 if (!chip) {
1187 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1188 if (!chip)
1189 return -ENOMEM;
1190 }
1191
1192 chip->cr1 = 0;
1193 if (spi_controller_is_target(drv_data->controller)) {
1194 chip->cr1 |= SSCR1_SCFR;
1195 chip->cr1 |= SSCR1_SCLKDIR;
1196 chip->cr1 |= SSCR1_SFRMDIR;
1197 chip->cr1 |= SSCR1_SPH;
1198 }
1199
1200 if (is_lpss_ssp(drv_data)) {
1201 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1202 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1203 SSITF_TxHiThresh(tx_hi_thres);
1204 }
1205
1206 if (is_mrfld_ssp(drv_data)) {
1207 chip->lpss_rx_threshold = rx_thres;
1208 chip->lpss_tx_threshold = tx_thres;
1209 }
1210
1211 switch (drv_data->ssp_type) {
1212 case QUARK_X1000_SSP:
1213 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1214 & QUARK_X1000_SSCR1_RFT)
1215 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1216 & QUARK_X1000_SSCR1_TFT);
1217 break;
1218 case CE4100_SSP:
1219 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1220 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1221 break;
1222 default:
1223 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1224 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1225 break;
1226 }
1227
1228 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1229 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1230 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1231
1232 if (spi->mode & SPI_LOOP)
1233 chip->cr1 |= SSCR1_LBM;
1234
1235 spi_set_ctldata(spi, chip);
1236
1237 return 0;
1238}
1239
1240static void cleanup(struct spi_device *spi)
1241{
1242 struct chip_data *chip = spi_get_ctldata(spi);
1243
1244 kfree(chip);
1245}
1246
1247static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1248 unsigned int cs)
1249{
1250 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1251
1252 switch (drv_data->ssp_type) {
1253 /*
1254 * For some of Intel Atoms the ACPI DeviceSelection used by the Windows
1255 * driver starts from 1 instead of 0 so translate it here to match what
1256 * Linux expects.
1257 */
1258 case LPSS_BYT_SSP:
1259 case LPSS_BSW_SSP:
1260 return cs - 1;
1261
1262 default:
1263 return cs;
1264 }
1265}
1266
1267static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1268{
1269 return MAX_DMA_LEN;
1270}
1271
1272int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
1273 struct pxa2xx_spi_controller *platform_info)
1274{
1275 struct spi_controller *controller;
1276 struct driver_data *drv_data;
1277 const struct lpss_config *config;
1278 int status;
1279 u32 tmp;
1280
1281 if (platform_info->is_target)
1282 controller = devm_spi_alloc_target(dev, sizeof(*drv_data));
1283 else
1284 controller = devm_spi_alloc_host(dev, sizeof(*drv_data));
1285 if (!controller)
1286 return dev_err_probe(dev, -ENOMEM, "cannot alloc spi_controller\n");
1287
1288 drv_data = spi_controller_get_devdata(controller);
1289 drv_data->controller = controller;
1290 drv_data->controller_info = platform_info;
1291 drv_data->ssp = ssp;
1292
1293 device_set_node(&controller->dev, dev_fwnode(dev));
1294
1295 /* The spi->mode bits understood by this driver: */
1296 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1297
1298 controller->bus_num = ssp->port_id;
1299 controller->dma_alignment = DMA_ALIGNMENT;
1300 controller->cleanup = cleanup;
1301 controller->setup = setup;
1302 controller->set_cs = pxa2xx_spi_set_cs;
1303 controller->transfer_one = pxa2xx_spi_transfer_one;
1304 controller->target_abort = pxa2xx_spi_target_abort;
1305 controller->handle_err = pxa2xx_spi_handle_err;
1306 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1307 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1308 controller->auto_runtime_pm = true;
1309 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1310
1311 drv_data->ssp_type = ssp->type;
1312
1313 if (pxa25x_ssp_comp(drv_data)) {
1314 switch (drv_data->ssp_type) {
1315 case QUARK_X1000_SSP:
1316 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1317 break;
1318 default:
1319 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1320 break;
1321 }
1322
1323 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1324 drv_data->dma_cr1 = 0;
1325 drv_data->clear_sr = SSSR_ROR;
1326 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1327 } else {
1328 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1329 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1330 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1331 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1332 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1333 | SSSR_ROR | SSSR_TUR;
1334 }
1335
1336 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1337 drv_data);
1338 if (status < 0)
1339 return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq);
1340
1341 /* Setup DMA if requested */
1342 if (platform_info->enable_dma) {
1343 status = pxa2xx_spi_dma_setup(drv_data);
1344 if (status) {
1345 dev_warn(dev, "no DMA channels available, using PIO\n");
1346 platform_info->enable_dma = false;
1347 } else {
1348 controller->can_dma = pxa2xx_spi_can_dma;
1349 controller->max_dma_len = MAX_DMA_LEN;
1350 controller->max_transfer_size =
1351 pxa2xx_spi_max_dma_transfer_size;
1352
1353 dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size);
1354 }
1355 }
1356
1357 /* Enable SOC clock */
1358 status = clk_prepare_enable(ssp->clk);
1359 if (status)
1360 goto out_error_dma_irq_alloc;
1361
1362 controller->max_speed_hz = clk_get_rate(ssp->clk);
1363 /*
1364 * Set minimum speed for all other platforms than Intel Quark which is
1365 * able do under 1 Hz transfers.
1366 */
1367 if (!pxa25x_ssp_comp(drv_data))
1368 controller->min_speed_hz =
1369 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1370 else if (!is_quark_x1000_ssp(drv_data))
1371 controller->min_speed_hz =
1372 DIV_ROUND_UP(controller->max_speed_hz, 512);
1373
1374 pxa_ssp_disable(ssp);
1375
1376 /* Load default SSP configuration */
1377 switch (drv_data->ssp_type) {
1378 case QUARK_X1000_SSP:
1379 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1380 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1381 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1382
1383 /* Using the Motorola SPI protocol and use 8 bit frame */
1384 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1385 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1386 break;
1387 case CE4100_SSP:
1388 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1389 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1390 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1391 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1392 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1393 break;
1394 default:
1395
1396 if (spi_controller_is_target(controller)) {
1397 tmp = SSCR1_SCFR |
1398 SSCR1_SCLKDIR |
1399 SSCR1_SFRMDIR |
1400 SSCR1_RxTresh(2) |
1401 SSCR1_TxTresh(1) |
1402 SSCR1_SPH;
1403 } else {
1404 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1405 SSCR1_TxTresh(TX_THRESH_DFLT);
1406 }
1407 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1408 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1409 if (!spi_controller_is_target(controller))
1410 tmp |= SSCR0_SCR(2);
1411 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1412 break;
1413 }
1414
1415 if (!pxa25x_ssp_comp(drv_data))
1416 pxa2xx_spi_write(drv_data, SSTO, 0);
1417
1418 if (!is_quark_x1000_ssp(drv_data))
1419 pxa2xx_spi_write(drv_data, SSPSP, 0);
1420
1421 if (is_lpss_ssp(drv_data)) {
1422 lpss_ssp_setup(drv_data);
1423 config = lpss_get_config(drv_data);
1424 if (config->reg_capabilities >= 0) {
1425 tmp = __lpss_ssp_read_priv(drv_data,
1426 config->reg_capabilities);
1427 tmp &= LPSS_CAPS_CS_EN_MASK;
1428 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1429 platform_info->num_chipselect = ffz(tmp);
1430 }
1431 }
1432 controller->num_chipselect = platform_info->num_chipselect;
1433 controller->use_gpio_descriptors = true;
1434
1435 if (platform_info->is_target) {
1436 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1437 "ready", GPIOD_OUT_LOW);
1438 if (IS_ERR(drv_data->gpiod_ready)) {
1439 status = PTR_ERR(drv_data->gpiod_ready);
1440 goto out_error_clock_enabled;
1441 }
1442 }
1443
1444 /* Register with the SPI framework */
1445 dev_set_drvdata(dev, drv_data);
1446 status = spi_register_controller(controller);
1447 if (status) {
1448 dev_err_probe(dev, status, "problem registering SPI controller\n");
1449 goto out_error_clock_enabled;
1450 }
1451
1452 return status;
1453
1454out_error_clock_enabled:
1455 clk_disable_unprepare(ssp->clk);
1456
1457out_error_dma_irq_alloc:
1458 pxa2xx_spi_dma_release(drv_data);
1459 free_irq(ssp->irq, drv_data);
1460
1461 return status;
1462}
1463EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_probe, "SPI_PXA2xx");
1464
1465void pxa2xx_spi_remove(struct device *dev)
1466{
1467 struct driver_data *drv_data = dev_get_drvdata(dev);
1468 struct ssp_device *ssp = drv_data->ssp;
1469
1470 spi_unregister_controller(drv_data->controller);
1471
1472 /* Disable the SSP at the peripheral and SOC level */
1473 pxa_ssp_disable(ssp);
1474 clk_disable_unprepare(ssp->clk);
1475
1476 /* Release DMA */
1477 if (drv_data->controller_info->enable_dma)
1478 pxa2xx_spi_dma_release(drv_data);
1479
1480 /* Release IRQ */
1481 free_irq(ssp->irq, drv_data);
1482}
1483EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx");
1484
1485static int pxa2xx_spi_suspend(struct device *dev)
1486{
1487 struct driver_data *drv_data = dev_get_drvdata(dev);
1488 struct ssp_device *ssp = drv_data->ssp;
1489 int status;
1490
1491 status = spi_controller_suspend(drv_data->controller);
1492 if (status)
1493 return status;
1494
1495 pxa_ssp_disable(ssp);
1496
1497 if (!pm_runtime_suspended(dev))
1498 clk_disable_unprepare(ssp->clk);
1499
1500 return 0;
1501}
1502
1503static int pxa2xx_spi_resume(struct device *dev)
1504{
1505 struct driver_data *drv_data = dev_get_drvdata(dev);
1506 struct ssp_device *ssp = drv_data->ssp;
1507 int status;
1508
1509 /* Enable the SSP clock */
1510 if (!pm_runtime_suspended(dev)) {
1511 status = clk_prepare_enable(ssp->clk);
1512 if (status)
1513 return status;
1514 }
1515
1516 /* Start the queue running */
1517 return spi_controller_resume(drv_data->controller);
1518}
1519
1520static int pxa2xx_spi_runtime_suspend(struct device *dev)
1521{
1522 struct driver_data *drv_data = dev_get_drvdata(dev);
1523
1524 clk_disable_unprepare(drv_data->ssp->clk);
1525 return 0;
1526}
1527
1528static int pxa2xx_spi_runtime_resume(struct device *dev)
1529{
1530 struct driver_data *drv_data = dev_get_drvdata(dev);
1531
1532 return clk_prepare_enable(drv_data->ssp->clk);
1533}
1534
1535EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) = {
1536 SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1537 RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1538};
1539
1540MODULE_AUTHOR("Stephen Street");
1541MODULE_DESCRIPTION("PXA2xx SSP SPI Controller core driver");
1542MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)