| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Universal Flash Storage Host controller driver |
| 4 | * Copyright (C) 2011-2013 Samsung India Software Operations |
| 5 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
| 6 | * |
| 7 | * Authors: |
| 8 | * Santosh Yaraganavi <santosh.sy@samsung.com> |
| 9 | * Vinayak Holikatti <h.vinayak@samsung.com> |
| 10 | */ |
| 11 | |
| 12 | #ifndef _UFSHCD_H |
| 13 | #define _UFSHCD_H |
| 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/rwsem.h> |
| 24 | #include <linux/workqueue.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <linux/types.h> |
| 27 | #include <linux/wait.h> |
| 28 | #include <linux/bitops.h> |
| 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/clk.h> |
| 31 | #include <linux/completion.h> |
| 32 | #include <linux/regulator/consumer.h> |
| 33 | #include <linux/bitfield.h> |
| 34 | #include <linux/devfreq.h> |
| 35 | #include <linux/keyslot-manager.h> |
| 36 | #include "unipro.h" |
| 37 | |
| 38 | #include <asm/irq.h> |
| 39 | #include <asm/byteorder.h> |
| 40 | #include <scsi/scsi.h> |
| 41 | #include <scsi/scsi_cmnd.h> |
| 42 | #include <scsi/scsi_host.h> |
| 43 | #include <scsi/scsi_tcq.h> |
| 44 | #include <scsi/scsi_dbg.h> |
| 45 | #include <scsi/scsi_eh.h> |
| 46 | |
| 47 | #include "ufs.h" |
| 48 | #include "ufs_quirks.h" |
| 49 | #include "ufshci.h" |
| 50 | |
| 51 | #define UFSHCD "ufshcd" |
| 52 | #define UFSHCD_DRIVER_VERSION "0.2" |
| 53 | |
| 54 | struct ufs_hba; |
| 55 | |
| 56 | enum dev_cmd_type { |
| 57 | DEV_CMD_TYPE_NOP = 0x0, |
| 58 | DEV_CMD_TYPE_QUERY = 0x1, |
| 59 | }; |
| 60 | |
| 61 | enum ufs_event_type { |
| 62 | /* uic specific errors */ |
| 63 | UFS_EVT_PA_ERR = 0, |
| 64 | UFS_EVT_DL_ERR, |
| 65 | UFS_EVT_NL_ERR, |
| 66 | UFS_EVT_TL_ERR, |
| 67 | UFS_EVT_DME_ERR, |
| 68 | |
| 69 | /* fatal errors */ |
| 70 | UFS_EVT_AUTO_HIBERN8_ERR, |
| 71 | UFS_EVT_FATAL_ERR, |
| 72 | UFS_EVT_LINK_STARTUP_FAIL, |
| 73 | UFS_EVT_RESUME_ERR, |
| 74 | UFS_EVT_SUSPEND_ERR, |
| 75 | |
| 76 | /* abnormal events */ |
| 77 | UFS_EVT_DEV_RESET, |
| 78 | UFS_EVT_HOST_RESET, |
| 79 | UFS_EVT_ABORT, |
| 80 | |
| 81 | UFS_EVT_CNT, |
| 82 | }; |
| 83 | |
| 84 | /** |
| 85 | * struct uic_command - UIC command structure |
| 86 | * @command: UIC command |
| 87 | * @argument1: UIC command argument 1 |
| 88 | * @argument2: UIC command argument 2 |
| 89 | * @argument3: UIC command argument 3 |
| 90 | * @cmd_active: Indicate if UIC command is outstanding |
| 91 | * @done: UIC command completion |
| 92 | */ |
| 93 | struct uic_command { |
| 94 | u32 command; |
| 95 | u32 argument1; |
| 96 | u32 argument2; |
| 97 | u32 argument3; |
| 98 | int cmd_active; |
| 99 | struct completion done; |
| 100 | }; |
| 101 | |
| 102 | /* Used to differentiate the power management options */ |
| 103 | enum ufs_pm_op { |
| 104 | UFS_RUNTIME_PM, |
| 105 | UFS_SYSTEM_PM, |
| 106 | UFS_SHUTDOWN_PM, |
| 107 | }; |
| 108 | |
| 109 | #define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM) |
| 110 | #define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM) |
| 111 | #define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM) |
| 112 | |
| 113 | /* Host <-> Device UniPro Link state */ |
| 114 | enum uic_link_state { |
| 115 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ |
| 116 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ |
| 117 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ |
| 118 | UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ |
| 119 | }; |
| 120 | |
| 121 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) |
| 122 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ |
| 123 | UIC_LINK_ACTIVE_STATE) |
| 124 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ |
| 125 | UIC_LINK_HIBERN8_STATE) |
| 126 | #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ |
| 127 | UIC_LINK_BROKEN_STATE) |
| 128 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) |
| 129 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ |
| 130 | UIC_LINK_ACTIVE_STATE) |
| 131 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ |
| 132 | UIC_LINK_HIBERN8_STATE) |
| 133 | #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ |
| 134 | UIC_LINK_BROKEN_STATE) |
| 135 | |
| 136 | #define ufshcd_set_ufs_dev_active(h) \ |
| 137 | ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) |
| 138 | #define ufshcd_set_ufs_dev_sleep(h) \ |
| 139 | ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) |
| 140 | #define ufshcd_set_ufs_dev_poweroff(h) \ |
| 141 | ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) |
| 142 | #define ufshcd_set_ufs_dev_deepsleep(h) \ |
| 143 | ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) |
| 144 | #define ufshcd_is_ufs_dev_active(h) \ |
| 145 | ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) |
| 146 | #define ufshcd_is_ufs_dev_sleep(h) \ |
| 147 | ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) |
| 148 | #define ufshcd_is_ufs_dev_poweroff(h) \ |
| 149 | ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) |
| 150 | #define ufshcd_is_ufs_dev_deepsleep(h) \ |
| 151 | ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) |
| 152 | |
| 153 | /* |
| 154 | * UFS Power management levels. |
| 155 | * Each level is in increasing order of power savings, except DeepSleep |
| 156 | * which is lower than PowerDown with power on but not PowerDown with |
| 157 | * power off. |
| 158 | */ |
| 159 | enum ufs_pm_level { |
| 160 | UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */ |
| 161 | UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */ |
| 162 | UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */ |
| 163 | UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */ |
| 164 | UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */ |
| 165 | UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */ |
| 166 | UFS_PM_LVL_6, /* UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE */ |
| 167 | UFS_PM_LVL_MAX |
| 168 | }; |
| 169 | |
| 170 | struct ufs_pm_lvl_states { |
| 171 | enum ufs_dev_pwr_mode dev_state; |
| 172 | enum uic_link_state link_state; |
| 173 | }; |
| 174 | |
| 175 | /** |
| 176 | * struct ufshcd_lrb - local reference block |
| 177 | * @utr_descriptor_ptr: UTRD address of the command |
| 178 | * @ucd_req_ptr: UCD address of the command |
| 179 | * @ucd_rsp_ptr: Response UPIU address for this command |
| 180 | * @ucd_prdt_ptr: PRDT address of the command |
| 181 | * @utrd_dma_addr: UTRD dma address for debug |
| 182 | * @ucd_prdt_dma_addr: PRDT dma address for debug |
| 183 | * @ucd_rsp_dma_addr: UPIU response dma address for debug |
| 184 | * @ucd_req_dma_addr: UPIU request dma address for debug |
| 185 | * @cmd: pointer to SCSI command |
| 186 | * @sense_buffer: pointer to sense buffer address of the SCSI command |
| 187 | * @sense_bufflen: Length of the sense buffer |
| 188 | * @scsi_status: SCSI status of the command |
| 189 | * @command_type: SCSI, UFS, Query. |
| 190 | * @task_tag: Task tag of the command |
| 191 | * @lun: LUN of the command |
| 192 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
| 193 | * @issue_time_stamp: time stamp for debug purposes |
| 194 | * @compl_time_stamp: time stamp for statistics |
| 195 | * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) |
| 196 | * @data_unit_num: the data unit number for the first block for inline crypto |
| 197 | * @req_abort_skip: skip request abort task flag |
| 198 | * @in_use: indicates that this lrb is still in use |
| 199 | */ |
| 200 | struct ufshcd_lrb { |
| 201 | struct utp_transfer_req_desc *utr_descriptor_ptr; |
| 202 | struct utp_upiu_req *ucd_req_ptr; |
| 203 | struct utp_upiu_rsp *ucd_rsp_ptr; |
| 204 | struct ufshcd_sg_entry *ucd_prdt_ptr; |
| 205 | |
| 206 | dma_addr_t utrd_dma_addr; |
| 207 | dma_addr_t ucd_req_dma_addr; |
| 208 | dma_addr_t ucd_rsp_dma_addr; |
| 209 | dma_addr_t ucd_prdt_dma_addr; |
| 210 | |
| 211 | struct scsi_cmnd *cmd; |
| 212 | u8 *sense_buffer; |
| 213 | unsigned int sense_bufflen; |
| 214 | int scsi_status; |
| 215 | |
| 216 | int command_type; |
| 217 | int task_tag; |
| 218 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
| 219 | bool intr_cmd; |
| 220 | ktime_t issue_time_stamp; |
| 221 | ktime_t compl_time_stamp; |
| 222 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
| 223 | int crypto_key_slot; |
| 224 | u64 data_unit_num; |
| 225 | #endif |
| 226 | |
| 227 | bool req_abort_skip; |
| 228 | bool in_use; |
| 229 | }; |
| 230 | |
| 231 | /** |
| 232 | * struct ufs_query - holds relevant data structures for query request |
| 233 | * @request: request upiu and function |
| 234 | * @descriptor: buffer for sending/receiving descriptor |
| 235 | * @response: response upiu and response |
| 236 | */ |
| 237 | struct ufs_query { |
| 238 | struct ufs_query_req request; |
| 239 | u8 *descriptor; |
| 240 | struct ufs_query_res response; |
| 241 | }; |
| 242 | |
| 243 | /** |
| 244 | * struct ufs_dev_cmd - all assosiated fields with device management commands |
| 245 | * @type: device management command type - Query, NOP OUT |
| 246 | * @lock: lock to allow one command at a time |
| 247 | * @complete: internal commands completion |
| 248 | */ |
| 249 | struct ufs_dev_cmd { |
| 250 | enum dev_cmd_type type; |
| 251 | struct mutex lock; |
| 252 | struct completion *complete; |
| 253 | struct ufs_query query; |
| 254 | }; |
| 255 | |
| 256 | /** |
| 257 | * struct ufs_clk_info - UFS clock related info |
| 258 | * @list: list headed by hba->clk_list_head |
| 259 | * @clk: clock node |
| 260 | * @name: clock name |
| 261 | * @max_freq: maximum frequency supported by the clock |
| 262 | * @min_freq: min frequency that can be used for clock scaling |
| 263 | * @curr_freq: indicates the current frequency that it is set to |
| 264 | * @keep_link_active: indicates that the clk should not be disabled if |
| 265 | link is active |
| 266 | * @enabled: variable to check against multiple enable/disable |
| 267 | */ |
| 268 | struct ufs_clk_info { |
| 269 | struct list_head list; |
| 270 | struct clk *clk; |
| 271 | const char *name; |
| 272 | u32 max_freq; |
| 273 | u32 min_freq; |
| 274 | u32 curr_freq; |
| 275 | bool keep_link_active; |
| 276 | bool enabled; |
| 277 | }; |
| 278 | |
| 279 | enum ufs_notify_change_status { |
| 280 | PRE_CHANGE, |
| 281 | POST_CHANGE, |
| 282 | }; |
| 283 | |
| 284 | struct ufs_pa_layer_attr { |
| 285 | u32 gear_rx; |
| 286 | u32 gear_tx; |
| 287 | u32 lane_rx; |
| 288 | u32 lane_tx; |
| 289 | u32 pwr_rx; |
| 290 | u32 pwr_tx; |
| 291 | u32 hs_rate; |
| 292 | }; |
| 293 | |
| 294 | struct ufs_pwr_mode_info { |
| 295 | bool is_valid; |
| 296 | struct ufs_pa_layer_attr info; |
| 297 | }; |
| 298 | |
| 299 | /** |
| 300 | * struct ufs_hba_variant_ops - variant specific callbacks |
| 301 | * @name: variant name |
| 302 | * @init: called when the driver is initialized |
| 303 | * @exit: called to cleanup everything done in init |
| 304 | * @get_ufs_hci_version: called to get UFS HCI version |
| 305 | * @clk_scale_notify: notifies that clks are scaled up/down |
| 306 | * @setup_clocks: called before touching any of the controller registers |
| 307 | * @hce_enable_notify: called before and after HCE enable bit is set to allow |
| 308 | * variant specific Uni-Pro initialization. |
| 309 | * @link_startup_notify: called before and after Link startup is carried out |
| 310 | * to allow variant specific Uni-Pro initialization. |
| 311 | * @pwr_change_notify: called before and after a power mode change |
| 312 | * is carried out to allow vendor spesific capabilities |
| 313 | * to be set. |
| 314 | * @setup_xfer_req: called before any transfer request is issued |
| 315 | * to set some things |
| 316 | * @setup_task_mgmt: called before any task management request is issued |
| 317 | * to set some things |
| 318 | * @hibern8_notify: called around hibern8 enter/exit |
| 319 | * @apply_dev_quirks: called to apply device specific quirks |
| 320 | * @suspend: called during host controller PM callback |
| 321 | * @resume: called during host controller PM callback |
| 322 | * @dbg_register_dump: used to dump controller debug information |
| 323 | * @phy_initialization: used to initialize phys |
| 324 | * @device_reset: called to issue a reset pulse on the UFS device |
| 325 | * @program_key: program or evict an inline encryption key |
| 326 | * @event_notify: called to notify important events |
| 327 | */ |
| 328 | struct ufs_hba_variant_ops { |
| 329 | const char *name; |
| 330 | int (*init)(struct ufs_hba *); |
| 331 | void (*exit)(struct ufs_hba *); |
| 332 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
| 333 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
| 334 | enum ufs_notify_change_status); |
| 335 | int (*setup_clocks)(struct ufs_hba *, bool, |
| 336 | enum ufs_notify_change_status); |
| 337 | int (*hce_enable_notify)(struct ufs_hba *, |
| 338 | enum ufs_notify_change_status); |
| 339 | int (*link_startup_notify)(struct ufs_hba *, |
| 340 | enum ufs_notify_change_status); |
| 341 | int (*pwr_change_notify)(struct ufs_hba *, |
| 342 | enum ufs_notify_change_status status, |
| 343 | struct ufs_pa_layer_attr *, |
| 344 | struct ufs_pa_layer_attr *); |
| 345 | void (*setup_xfer_req)(struct ufs_hba *, int, bool); |
| 346 | void (*setup_task_mgmt)(struct ufs_hba *, int, u8); |
| 347 | void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, |
| 348 | enum ufs_notify_change_status); |
| 349 | int (*apply_dev_quirks)(struct ufs_hba *hba); |
| 350 | void (*fixup_dev_quirks)(struct ufs_hba *hba); |
| 351 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op); |
| 352 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); |
| 353 | void (*dbg_register_dump)(struct ufs_hba *hba); |
| 354 | int (*phy_initialization)(struct ufs_hba *); |
| 355 | int (*device_reset)(struct ufs_hba *hba); |
| 356 | void (*config_scaling_param)(struct ufs_hba *hba, |
| 357 | struct devfreq_dev_profile *profile, |
| 358 | void *data); |
| 359 | int (*program_key)(struct ufs_hba *hba, |
| 360 | const union ufs_crypto_cfg_entry *cfg, int slot); |
| 361 | void (*event_notify)(struct ufs_hba *hba, |
| 362 | enum ufs_event_type evt, void *data); |
| 363 | }; |
| 364 | |
| 365 | /* clock gating state */ |
| 366 | enum clk_gating_state { |
| 367 | CLKS_OFF, |
| 368 | CLKS_ON, |
| 369 | REQ_CLKS_OFF, |
| 370 | REQ_CLKS_ON, |
| 371 | }; |
| 372 | |
| 373 | /** |
| 374 | * struct ufs_clk_gating - UFS clock gating related info |
| 375 | * @gate_work: worker to turn off clocks after some delay as specified in |
| 376 | * delay_ms |
| 377 | * @ungate_work: worker to turn on clocks that will be used in case of |
| 378 | * interrupt context |
| 379 | * @state: the current clocks state |
| 380 | * @delay_ms: gating delay in ms |
| 381 | * @is_suspended: clk gating is suspended when set to 1 which can be used |
| 382 | * during suspend/resume |
| 383 | * @delay_attr: sysfs attribute to control delay_attr |
| 384 | * @enable_attr: sysfs attribute to enable/disable clock gating |
| 385 | * @is_enabled: Indicates the current status of clock gating |
| 386 | * @is_initialized: Indicates whether clock gating is initialized or not |
| 387 | * @active_reqs: number of requests that are pending and should be waited for |
| 388 | * completion before gating clocks. |
| 389 | */ |
| 390 | struct ufs_clk_gating { |
| 391 | struct delayed_work gate_work; |
| 392 | struct work_struct ungate_work; |
| 393 | enum clk_gating_state state; |
| 394 | unsigned long delay_ms; |
| 395 | bool is_suspended; |
| 396 | struct device_attribute delay_attr; |
| 397 | struct device_attribute enable_attr; |
| 398 | bool is_enabled; |
| 399 | bool is_initialized; |
| 400 | int active_reqs; |
| 401 | struct workqueue_struct *clk_gating_workq; |
| 402 | }; |
| 403 | |
| 404 | struct ufs_saved_pwr_info { |
| 405 | struct ufs_pa_layer_attr info; |
| 406 | bool is_valid; |
| 407 | }; |
| 408 | |
| 409 | /** |
| 410 | * struct ufs_clk_scaling - UFS clock scaling related data |
| 411 | * @active_reqs: number of requests that are pending. If this is zero when |
| 412 | * devfreq ->target() function is called then schedule "suspend_work" to |
| 413 | * suspend devfreq. |
| 414 | * @tot_busy_t: Total busy time in current polling window |
| 415 | * @window_start_t: Start time (in jiffies) of the current polling window |
| 416 | * @busy_start_t: Start time of current busy period |
| 417 | * @enable_attr: sysfs attribute to enable/disable clock scaling |
| 418 | * @saved_pwr_info: UFS power mode may also be changed during scaling and this |
| 419 | * one keeps track of previous power mode. |
| 420 | * @workq: workqueue to schedule devfreq suspend/resume work |
| 421 | * @suspend_work: worker to suspend devfreq |
| 422 | * @resume_work: worker to resume devfreq |
| 423 | * @min_gear: lowest HS gear to scale down to |
| 424 | * @is_enabled: tracks if scaling is currently enabled or not, controlled by |
| 425 | clkscale_enable sysfs node |
| 426 | * @is_allowed: tracks if scaling is currently allowed or not, used to block |
| 427 | clock scaling which is not invoked from devfreq governor |
| 428 | * @is_initialized: Indicates whether clock scaling is initialized or not |
| 429 | * @is_busy_started: tracks if busy period has started or not |
| 430 | * @is_suspended: tracks if devfreq is suspended or not |
| 431 | */ |
| 432 | struct ufs_clk_scaling { |
| 433 | int active_reqs; |
| 434 | unsigned long tot_busy_t; |
| 435 | ktime_t window_start_t; |
| 436 | ktime_t busy_start_t; |
| 437 | struct device_attribute enable_attr; |
| 438 | struct ufs_saved_pwr_info saved_pwr_info; |
| 439 | struct workqueue_struct *workq; |
| 440 | struct work_struct suspend_work; |
| 441 | struct work_struct resume_work; |
| 442 | u32 min_gear; |
| 443 | bool is_enabled; |
| 444 | bool is_allowed; |
| 445 | bool is_initialized; |
| 446 | bool is_busy_started; |
| 447 | bool is_suspended; |
| 448 | }; |
| 449 | |
| 450 | #define UFS_EVENT_HIST_LENGTH 8 |
| 451 | /** |
| 452 | * struct ufs_event_hist - keeps history of errors |
| 453 | * @pos: index to indicate cyclic buffer position |
| 454 | * @reg: cyclic buffer for registers value |
| 455 | * @tstamp: cyclic buffer for time stamp |
| 456 | * @cnt: error counter |
| 457 | */ |
| 458 | struct ufs_event_hist { |
| 459 | int pos; |
| 460 | u32 val[UFS_EVENT_HIST_LENGTH]; |
| 461 | ktime_t tstamp[UFS_EVENT_HIST_LENGTH]; |
| 462 | unsigned long long cnt; |
| 463 | }; |
| 464 | |
| 465 | /** |
| 466 | * struct ufs_stats - keeps usage/err statistics |
| 467 | * @last_intr_status: record the last interrupt status. |
| 468 | * @last_intr_ts: record the last interrupt timestamp. |
| 469 | * @hibern8_exit_cnt: Counter to keep track of number of exits, |
| 470 | * reset this after link-startup. |
| 471 | * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. |
| 472 | * Clear after the first successful command completion. |
| 473 | */ |
| 474 | struct ufs_stats { |
| 475 | u32 last_intr_status; |
| 476 | ktime_t last_intr_ts; |
| 477 | |
| 478 | u32 hibern8_exit_cnt; |
| 479 | ktime_t last_hibern8_exit_tstamp; |
| 480 | struct ufs_event_hist event[UFS_EVT_CNT]; |
| 481 | }; |
| 482 | |
| 483 | enum ufshcd_quirks { |
| 484 | /* Interrupt aggregation support is broken */ |
| 485 | UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, |
| 486 | |
| 487 | /* |
| 488 | * delay before each dme command is required as the unipro |
| 489 | * layer has shown instabilities |
| 490 | */ |
| 491 | UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, |
| 492 | |
| 493 | /* |
| 494 | * If UFS host controller is having issue in processing LCC (Line |
| 495 | * Control Command) coming from device then enable this quirk. |
| 496 | * When this quirk is enabled, host controller driver should disable |
| 497 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE |
| 498 | * attribute of device to 0). |
| 499 | */ |
| 500 | UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, |
| 501 | |
| 502 | /* |
| 503 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the |
| 504 | * inbound Link supports unterminated line in HS mode. Setting this |
| 505 | * attribute to 1 fixes moving to HS gear. |
| 506 | */ |
| 507 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, |
| 508 | |
| 509 | /* |
| 510 | * This quirk needs to be enabled if the host controller only allows |
| 511 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or |
| 512 | * SLOW AUTO). |
| 513 | */ |
| 514 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, |
| 515 | |
| 516 | /* |
| 517 | * This quirk needs to be enabled if the host controller doesn't |
| 518 | * advertise the correct version in UFS_VER register. If this quirk |
| 519 | * is enabled, standard UFS host driver will call the vendor specific |
| 520 | * ops (get_ufs_hci_version) to get the correct version. |
| 521 | */ |
| 522 | UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, |
| 523 | |
| 524 | /* |
| 525 | * Clear handling for transfer/task request list is just opposite. |
| 526 | */ |
| 527 | UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, |
| 528 | |
| 529 | /* |
| 530 | * This quirk needs to be enabled if host controller doesn't allow |
| 531 | * that the interrupt aggregation timer and counter are reset by s/w. |
| 532 | */ |
| 533 | UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, |
| 534 | |
| 535 | /* |
| 536 | * This quirks needs to be enabled if host controller cannot be |
| 537 | * enabled via HCE register. |
| 538 | */ |
| 539 | UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, |
| 540 | |
| 541 | /* |
| 542 | * This quirk needs to be enabled if the host controller regards |
| 543 | * resolution of the values of PRDTO and PRDTL in UTRD as byte. |
| 544 | */ |
| 545 | UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, |
| 546 | |
| 547 | /* |
| 548 | * This quirk needs to be enabled if the host controller reports |
| 549 | * OCS FATAL ERROR with device error through sense data |
| 550 | */ |
| 551 | UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, |
| 552 | |
| 553 | /* |
| 554 | * This quirk needs to be enabled if the host controller has |
| 555 | * auto-hibernate capability but it doesn't work. |
| 556 | */ |
| 557 | UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, |
| 558 | |
| 559 | /* |
| 560 | * This quirk needs to disable manual flush for write booster |
| 561 | */ |
| 562 | UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, |
| 563 | |
| 564 | /* |
| 565 | * This quirk needs to disable unipro timeout values |
| 566 | * before power mode change |
| 567 | */ |
| 568 | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, |
| 569 | |
| 570 | /* |
| 571 | * This quirk allows only sg entries aligned with page size. |
| 572 | */ |
| 573 | UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, |
| 574 | }; |
| 575 | |
| 576 | enum ufshcd_caps { |
| 577 | /* Allow dynamic clk gating */ |
| 578 | UFSHCD_CAP_CLK_GATING = 1 << 0, |
| 579 | |
| 580 | /* Allow hiberb8 with clk gating */ |
| 581 | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, |
| 582 | |
| 583 | /* Allow dynamic clk scaling */ |
| 584 | UFSHCD_CAP_CLK_SCALING = 1 << 2, |
| 585 | |
| 586 | /* Allow auto bkops to enabled during runtime suspend */ |
| 587 | UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, |
| 588 | |
| 589 | /* |
| 590 | * This capability allows host controller driver to use the UFS HCI's |
| 591 | * interrupt aggregation capability. |
| 592 | * CAUTION: Enabling this might reduce overall UFS throughput. |
| 593 | */ |
| 594 | UFSHCD_CAP_INTR_AGGR = 1 << 4, |
| 595 | |
| 596 | /* |
| 597 | * This capability allows the device auto-bkops to be always enabled |
| 598 | * except during suspend (both runtime and suspend). |
| 599 | * Enabling this capability means that device will always be allowed |
| 600 | * to do background operation when it's active but it might degrade |
| 601 | * the performance of ongoing read/write operations. |
| 602 | */ |
| 603 | UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, |
| 604 | |
| 605 | /* |
| 606 | * This capability allows host controller driver to automatically |
| 607 | * enable runtime power management by itself instead of waiting |
| 608 | * for userspace to control the power management. |
| 609 | */ |
| 610 | UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, |
| 611 | |
| 612 | /* |
| 613 | * This capability allows the host controller driver to turn-on |
| 614 | * WriteBooster, if the underlying device supports it and is |
| 615 | * provisioned to be used. This would increase the write performance. |
| 616 | */ |
| 617 | UFSHCD_CAP_WB_EN = 1 << 7, |
| 618 | |
| 619 | /* |
| 620 | * This capability allows the host controller driver to use the |
| 621 | * inline crypto engine, if it is present |
| 622 | */ |
| 623 | UFSHCD_CAP_CRYPTO = 1 << 8, |
| 624 | |
| 625 | /* |
| 626 | * This capability allows the controller regulators to be put into |
| 627 | * lpm mode aggressively during clock gating. |
| 628 | * This would increase power savings. |
| 629 | */ |
| 630 | UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, |
| 631 | |
| 632 | /* |
| 633 | * This capability allows the host controller driver to use DeepSleep, |
| 634 | * if it is supported by the UFS device. The host controller driver must |
| 635 | * support device hardware reset via the hba->device_reset() callback, |
| 636 | * in order to exit DeepSleep state. |
| 637 | */ |
| 638 | UFSHCD_CAP_DEEPSLEEP = 1 << 10, |
| 639 | }; |
| 640 | |
| 641 | struct ufs_hba_variant_params { |
| 642 | struct devfreq_dev_profile devfreq_profile; |
| 643 | struct devfreq_simple_ondemand_data ondemand_data; |
| 644 | u16 hba_enable_delay_us; |
| 645 | u32 wb_flush_threshold; |
| 646 | }; |
| 647 | |
| 648 | /** |
| 649 | * struct ufs_hba - per adapter private structure |
| 650 | * @mmio_base: UFSHCI base register address |
| 651 | * @ucdl_base_addr: UFS Command Descriptor base address |
| 652 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address |
| 653 | * @utmrdl_base_addr: UTP Task Management Descriptor base address |
| 654 | * @ucdl_dma_addr: UFS Command Descriptor DMA address |
| 655 | * @utrdl_dma_addr: UTRDL DMA address |
| 656 | * @utmrdl_dma_addr: UTMRDL DMA address |
| 657 | * @host: Scsi_Host instance of the driver |
| 658 | * @dev: device handle |
| 659 | * @lrb: local reference block |
| 660 | * @cmd_queue: Used to allocate command tags from hba->host->tag_set. |
| 661 | * @outstanding_tasks: Bits representing outstanding task requests |
| 662 | * @outstanding_reqs: Bits representing outstanding transfer requests |
| 663 | * @capabilities: UFS Controller Capabilities |
| 664 | * @nutrs: Transfer Request Queue depth supported by controller |
| 665 | * @nutmrs: Task Management Queue depth supported by controller |
| 666 | * @ufs_version: UFS Version to which controller complies |
| 667 | * @vops: pointer to variant specific operations |
| 668 | * @priv: pointer to variant specific private data |
| 669 | * @irq: Irq number of the controller |
| 670 | * @active_uic_cmd: handle of active UIC command |
| 671 | * @uic_cmd_mutex: mutex for uic command |
| 672 | * @tmf_tag_set: TMF tag set. |
| 673 | * @tmf_queue: Used to allocate TMF tags. |
| 674 | * @pwr_done: completion for power mode change |
| 675 | * @ufshcd_state: UFSHCD states |
| 676 | * @eh_flags: Error handling flags |
| 677 | * @intr_mask: Interrupt Mask Bits |
| 678 | * @ee_ctrl_mask: Exception event control mask |
| 679 | * @is_powered: flag to check if HBA is powered |
| 680 | * @shutting_down: flag to check if shutdown has been invoked |
| 681 | * @host_sem: semaphore used to serialize concurrent contexts |
| 682 | * @eh_wq: Workqueue that eh_work works on |
| 683 | * @eh_work: Worker to handle UFS errors that require s/w attention |
| 684 | * @eeh_work: Worker to handle exception events |
| 685 | * @errors: HBA errors |
| 686 | * @uic_error: UFS interconnect layer error status |
| 687 | * @saved_err: sticky error mask |
| 688 | * @saved_uic_err: sticky UIC error mask |
| 689 | * @force_reset: flag to force eh_work perform a full reset |
| 690 | * @force_pmc: flag to force a power mode change |
| 691 | * @silence_err_logs: flag to silence error logs |
| 692 | * @dev_cmd: ufs device management command information |
| 693 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
| 694 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
| 695 | * @vreg_info: UFS device voltage regulator information |
| 696 | * @clk_list_head: UFS host controller clocks list node head |
| 697 | * @pwr_info: holds current power mode |
| 698 | * @max_pwr_info: keeps the device max valid pwm |
| 699 | * @desc_size: descriptor sizes reported by device |
| 700 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
| 701 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for |
| 702 | * device is known or not. |
| 703 | * @scsi_block_reqs_cnt: reference counting for scsi block requests |
| 704 | * @crypto_capabilities: Content of crypto capabilities register (0x100) |
| 705 | * @crypto_cap_array: Array of crypto capabilities |
| 706 | * @crypto_cfg_register: Start of the crypto cfg array |
| 707 | * @ksm: the keyslot manager tied to this hba |
| 708 | */ |
| 709 | struct ufs_hba { |
| 710 | void __iomem *mmio_base; |
| 711 | |
| 712 | /* Virtual memory reference */ |
| 713 | struct utp_transfer_cmd_desc *ucdl_base_addr; |
| 714 | struct utp_transfer_req_desc *utrdl_base_addr; |
| 715 | struct utp_task_req_desc *utmrdl_base_addr; |
| 716 | |
| 717 | /* DMA memory reference */ |
| 718 | dma_addr_t ucdl_dma_addr; |
| 719 | dma_addr_t utrdl_dma_addr; |
| 720 | dma_addr_t utmrdl_dma_addr; |
| 721 | |
| 722 | struct Scsi_Host *host; |
| 723 | struct device *dev; |
| 724 | struct request_queue *cmd_queue; |
| 725 | /* |
| 726 | * This field is to keep a reference to "scsi_device" corresponding to |
| 727 | * "UFS device" W-LU. |
| 728 | */ |
| 729 | struct scsi_device *sdev_ufs_device; |
| 730 | struct scsi_device *sdev_rpmb; |
| 731 | |
| 732 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
| 733 | enum uic_link_state uic_link_state; |
| 734 | /* Desired UFS power management level during runtime PM */ |
| 735 | enum ufs_pm_level rpm_lvl; |
| 736 | /* Desired UFS power management level during system PM */ |
| 737 | enum ufs_pm_level spm_lvl; |
| 738 | struct device_attribute rpm_lvl_attr; |
| 739 | struct device_attribute spm_lvl_attr; |
| 740 | int pm_op_in_progress; |
| 741 | |
| 742 | /* Auto-Hibernate Idle Timer register value */ |
| 743 | u32 ahit; |
| 744 | |
| 745 | struct ufshcd_lrb *lrb; |
| 746 | |
| 747 | unsigned long outstanding_tasks; |
| 748 | unsigned long outstanding_reqs; |
| 749 | |
| 750 | u32 capabilities; |
| 751 | int nutrs; |
| 752 | int nutmrs; |
| 753 | u32 ufs_version; |
| 754 | const struct ufs_hba_variant_ops *vops; |
| 755 | struct ufs_hba_variant_params *vps; |
| 756 | void *priv; |
| 757 | unsigned int irq; |
| 758 | bool is_irq_enabled; |
| 759 | enum ufs_ref_clk_freq dev_ref_clk_freq; |
| 760 | |
| 761 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
| 762 | |
| 763 | /* Device deviations from standard UFS device spec. */ |
| 764 | unsigned int dev_quirks; |
| 765 | |
| 766 | struct blk_mq_tag_set tmf_tag_set; |
| 767 | struct request_queue *tmf_queue; |
| 768 | |
| 769 | struct uic_command *active_uic_cmd; |
| 770 | struct mutex uic_cmd_mutex; |
| 771 | struct completion *uic_async_done; |
| 772 | |
| 773 | u32 ufshcd_state; |
| 774 | u32 eh_flags; |
| 775 | u32 intr_mask; |
| 776 | u16 ee_ctrl_mask; /* Exception event mask */ |
| 777 | u16 ee_drv_mask; /* Exception event mask for driver */ |
| 778 | u16 ee_usr_mask; /* Exception event mask for user (via debugfs) */ |
| 779 | struct mutex ee_ctrl_mutex; |
| 780 | bool is_powered; |
| 781 | bool shutting_down; |
| 782 | struct semaphore host_sem; |
| 783 | |
| 784 | /* Work Queues */ |
| 785 | struct workqueue_struct *eh_wq; |
| 786 | struct work_struct eh_work; |
| 787 | struct work_struct eeh_work; |
| 788 | |
| 789 | /* HBA Errors */ |
| 790 | u32 errors; |
| 791 | u32 uic_error; |
| 792 | u32 saved_err; |
| 793 | u32 saved_uic_err; |
| 794 | struct ufs_stats ufs_stats; |
| 795 | bool force_reset; |
| 796 | bool force_pmc; |
| 797 | bool silence_err_logs; |
| 798 | |
| 799 | /* Device management request data */ |
| 800 | struct ufs_dev_cmd dev_cmd; |
| 801 | ktime_t last_dme_cmd_tstamp; |
| 802 | |
| 803 | /* Keeps information of the UFS device connected to this host */ |
| 804 | struct ufs_dev_info dev_info; |
| 805 | bool auto_bkops_enabled; |
| 806 | struct ufs_vreg_info vreg_info; |
| 807 | struct list_head clk_list_head; |
| 808 | |
| 809 | bool wlun_dev_clr_ua; |
| 810 | |
| 811 | /* Number of requests aborts */ |
| 812 | int req_abort_count; |
| 813 | |
| 814 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
| 815 | u32 lanes_per_direction; |
| 816 | struct ufs_pa_layer_attr pwr_info; |
| 817 | struct ufs_pwr_mode_info max_pwr_info; |
| 818 | |
| 819 | struct ufs_clk_gating clk_gating; |
| 820 | /* Control to enable/disable host capabilities */ |
| 821 | u32 caps; |
| 822 | |
| 823 | struct devfreq *devfreq; |
| 824 | struct ufs_clk_scaling clk_scaling; |
| 825 | bool is_sys_suspended; |
| 826 | |
| 827 | enum bkops_status urgent_bkops_lvl; |
| 828 | bool is_urgent_bkops_lvl_checked; |
| 829 | |
| 830 | struct rw_semaphore clk_scaling_lock; |
| 831 | unsigned char desc_size[QUERY_DESC_IDN_MAX]; |
| 832 | atomic_t scsi_block_reqs_cnt; |
| 833 | |
| 834 | struct device bsg_dev; |
| 835 | struct request_queue *bsg_queue; |
| 836 | struct delayed_work rpm_dev_flush_recheck_work; |
| 837 | |
| 838 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
| 839 | union ufs_crypto_capabilities crypto_capabilities; |
| 840 | union ufs_crypto_cap_entry *crypto_cap_array; |
| 841 | u32 crypto_cfg_register; |
| 842 | struct blk_keyslot_manager ksm; |
| 843 | #endif |
| 844 | #ifdef CONFIG_DEBUG_FS |
| 845 | struct dentry *debugfs_root; |
| 846 | struct delayed_work debugfs_ee_work; |
| 847 | u32 debugfs_ee_rate_limit_ms; |
| 848 | #endif |
| 849 | }; |
| 850 | |
| 851 | /* Returns true if clocks can be gated. Otherwise false */ |
| 852 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) |
| 853 | { |
| 854 | return hba->caps & UFSHCD_CAP_CLK_GATING; |
| 855 | } |
| 856 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) |
| 857 | { |
| 858 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; |
| 859 | } |
| 860 | static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) |
| 861 | { |
| 862 | return hba->caps & UFSHCD_CAP_CLK_SCALING; |
| 863 | } |
| 864 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
| 865 | { |
| 866 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; |
| 867 | } |
| 868 | static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) |
| 869 | { |
| 870 | return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; |
| 871 | } |
| 872 | |
| 873 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
| 874 | { |
| 875 | /* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/ |
| 876 | #ifndef CONFIG_SCSI_UFS_DWC |
| 877 | if ((hba->caps & UFSHCD_CAP_INTR_AGGR) && |
| 878 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR)) |
| 879 | return true; |
| 880 | else |
| 881 | return false; |
| 882 | #else |
| 883 | return true; |
| 884 | #endif |
| 885 | } |
| 886 | |
| 887 | static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) |
| 888 | { |
| 889 | return !!(ufshcd_is_link_hibern8(hba) && |
| 890 | (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); |
| 891 | } |
| 892 | |
| 893 | static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) |
| 894 | { |
| 895 | return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && |
| 896 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); |
| 897 | } |
| 898 | |
| 899 | static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) |
| 900 | { |
| 901 | return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit) ? true : false; |
| 902 | } |
| 903 | |
| 904 | static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) |
| 905 | { |
| 906 | return hba->caps & UFSHCD_CAP_WB_EN; |
| 907 | } |
| 908 | |
| 909 | static inline bool ufshcd_is_user_access_allowed(struct ufs_hba *hba) |
| 910 | { |
| 911 | return !hba->shutting_down; |
| 912 | } |
| 913 | |
| 914 | #define ufshcd_writel(hba, val, reg) \ |
| 915 | writel((val), (hba)->mmio_base + (reg)) |
| 916 | #define ufshcd_readl(hba, reg) \ |
| 917 | readl((hba)->mmio_base + (reg)) |
| 918 | |
| 919 | /** |
| 920 | * ufshcd_rmwl - read modify write into a register |
| 921 | * @hba - per adapter instance |
| 922 | * @mask - mask to apply on read value |
| 923 | * @val - actual value to write |
| 924 | * @reg - register address |
| 925 | */ |
| 926 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) |
| 927 | { |
| 928 | u32 tmp; |
| 929 | |
| 930 | tmp = ufshcd_readl(hba, reg); |
| 931 | tmp &= ~mask; |
| 932 | tmp |= (val & mask); |
| 933 | ufshcd_writel(hba, tmp, reg); |
| 934 | } |
| 935 | |
| 936 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
| 937 | void ufshcd_dealloc_host(struct ufs_hba *); |
| 938 | int ufshcd_hba_enable(struct ufs_hba *hba); |
| 939 | int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int); |
| 940 | int ufshcd_link_recovery(struct ufs_hba *hba); |
| 941 | int ufshcd_make_hba_operational(struct ufs_hba *hba); |
| 942 | void ufshcd_remove(struct ufs_hba *); |
| 943 | int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); |
| 944 | void ufshcd_delay_us(unsigned long us, unsigned long tolerance); |
| 945 | int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, |
| 946 | u32 val, unsigned long interval_us, |
| 947 | unsigned long timeout_ms); |
| 948 | void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); |
| 949 | void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); |
| 950 | |
| 951 | static inline void check_upiu_size(void) |
| 952 | { |
| 953 | BUILD_BUG_ON(ALIGNED_UPIU_SIZE < |
| 954 | GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); |
| 955 | } |
| 956 | |
| 957 | /** |
| 958 | * ufshcd_set_variant - set variant specific data to the hba |
| 959 | * @hba - per adapter instance |
| 960 | * @variant - pointer to variant specific data |
| 961 | */ |
| 962 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) |
| 963 | { |
| 964 | BUG_ON(!hba); |
| 965 | hba->priv = variant; |
| 966 | } |
| 967 | |
| 968 | /** |
| 969 | * ufshcd_get_variant - get variant specific data from the hba |
| 970 | * @hba - per adapter instance |
| 971 | */ |
| 972 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) |
| 973 | { |
| 974 | BUG_ON(!hba); |
| 975 | return hba->priv; |
| 976 | } |
| 977 | static inline bool ufshcd_keep_autobkops_enabled_except_suspend( |
| 978 | struct ufs_hba *hba) |
| 979 | { |
| 980 | return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND; |
| 981 | } |
| 982 | |
| 983 | static inline u8 ufshcd_wb_get_query_index(struct ufs_hba *hba) |
| 984 | { |
| 985 | if (hba->dev_info.wb_buffer_type == WB_BUF_MODE_LU_DEDICATED) |
| 986 | return hba->dev_info.wb_dedicated_lu; |
| 987 | return 0; |
| 988 | } |
| 989 | |
| 990 | extern int ufshcd_runtime_suspend(struct ufs_hba *hba); |
| 991 | extern int ufshcd_runtime_resume(struct ufs_hba *hba); |
| 992 | extern int ufshcd_runtime_idle(struct ufs_hba *hba); |
| 993 | extern int ufshcd_system_suspend(struct ufs_hba *hba); |
| 994 | extern int ufshcd_system_resume(struct ufs_hba *hba); |
| 995 | extern int ufshcd_shutdown(struct ufs_hba *hba); |
| 996 | extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, |
| 997 | int agreed_gear, |
| 998 | int adapt_val); |
| 999 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
| 1000 | u8 attr_set, u32 mib_val, u8 peer); |
| 1001 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, |
| 1002 | u32 *mib_val, u8 peer); |
| 1003 | extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
| 1004 | struct ufs_pa_layer_attr *desired_pwr_mode); |
| 1005 | |
| 1006 | /* UIC command interfaces for DME primitives */ |
| 1007 | #define DME_LOCAL 0 |
| 1008 | #define DME_PEER 1 |
| 1009 | #define ATTR_SET_NOR 0 /* NORMAL */ |
| 1010 | #define ATTR_SET_ST 1 /* STATIC */ |
| 1011 | |
| 1012 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, |
| 1013 | u32 mib_val) |
| 1014 | { |
| 1015 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, |
| 1016 | mib_val, DME_LOCAL); |
| 1017 | } |
| 1018 | |
| 1019 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, |
| 1020 | u32 mib_val) |
| 1021 | { |
| 1022 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, |
| 1023 | mib_val, DME_LOCAL); |
| 1024 | } |
| 1025 | |
| 1026 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, |
| 1027 | u32 mib_val) |
| 1028 | { |
| 1029 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, |
| 1030 | mib_val, DME_PEER); |
| 1031 | } |
| 1032 | |
| 1033 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, |
| 1034 | u32 mib_val) |
| 1035 | { |
| 1036 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, |
| 1037 | mib_val, DME_PEER); |
| 1038 | } |
| 1039 | |
| 1040 | static inline int ufshcd_dme_get(struct ufs_hba *hba, |
| 1041 | u32 attr_sel, u32 *mib_val) |
| 1042 | { |
| 1043 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); |
| 1044 | } |
| 1045 | |
| 1046 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, |
| 1047 | u32 attr_sel, u32 *mib_val) |
| 1048 | { |
| 1049 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); |
| 1050 | } |
| 1051 | |
| 1052 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
| 1053 | { |
| 1054 | return (pwr_info->pwr_rx == FAST_MODE || |
| 1055 | pwr_info->pwr_rx == FASTAUTO_MODE) && |
| 1056 | (pwr_info->pwr_tx == FAST_MODE || |
| 1057 | pwr_info->pwr_tx == FASTAUTO_MODE); |
| 1058 | } |
| 1059 | |
| 1060 | static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) |
| 1061 | { |
| 1062 | return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); |
| 1063 | } |
| 1064 | |
| 1065 | /* Expose Query-Request API */ |
| 1066 | int ufshcd_query_descriptor_retry(struct ufs_hba *hba, |
| 1067 | enum query_opcode opcode, |
| 1068 | enum desc_idn idn, u8 index, |
| 1069 | u8 selector, |
| 1070 | u8 *desc_buf, int *buf_len); |
| 1071 | int ufshcd_read_desc_param(struct ufs_hba *hba, |
| 1072 | enum desc_idn desc_id, |
| 1073 | int desc_index, |
| 1074 | u8 param_offset, |
| 1075 | u8 *param_read_buf, |
| 1076 | u8 param_size); |
| 1077 | int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, |
| 1078 | enum attr_idn idn, u8 index, u8 selector, u32 *attr_val); |
| 1079 | int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, |
| 1080 | enum flag_idn idn, u8 index, bool *flag_res); |
| 1081 | |
| 1082 | void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); |
| 1083 | void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); |
| 1084 | void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups); |
| 1085 | #define SD_ASCII_STD true |
| 1086 | #define SD_RAW false |
| 1087 | int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, |
| 1088 | u8 **buf, bool ascii); |
| 1089 | |
| 1090 | int ufshcd_hold(struct ufs_hba *hba, bool async); |
| 1091 | void ufshcd_release(struct ufs_hba *hba); |
| 1092 | |
| 1093 | void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, |
| 1094 | int *desc_length); |
| 1095 | |
| 1096 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
| 1097 | |
| 1098 | int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); |
| 1099 | |
| 1100 | int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, |
| 1101 | struct utp_upiu_req *req_upiu, |
| 1102 | struct utp_upiu_req *rsp_upiu, |
| 1103 | int msgcode, |
| 1104 | u8 *desc_buff, int *buff_len, |
| 1105 | enum query_opcode desc_op); |
| 1106 | |
| 1107 | int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable); |
| 1108 | |
| 1109 | /* Wrapper functions for safely calling variant operations */ |
| 1110 | static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) |
| 1111 | { |
| 1112 | if (hba->vops) |
| 1113 | return hba->vops->name; |
| 1114 | return ""; |
| 1115 | } |
| 1116 | |
| 1117 | static inline int ufshcd_vops_init(struct ufs_hba *hba) |
| 1118 | { |
| 1119 | if (hba->vops && hba->vops->init) |
| 1120 | return hba->vops->init(hba); |
| 1121 | |
| 1122 | return 0; |
| 1123 | } |
| 1124 | |
| 1125 | static inline void ufshcd_vops_exit(struct ufs_hba *hba) |
| 1126 | { |
| 1127 | if (hba->vops && hba->vops->exit) |
| 1128 | return hba->vops->exit(hba); |
| 1129 | } |
| 1130 | |
| 1131 | static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) |
| 1132 | { |
| 1133 | if (hba->vops && hba->vops->get_ufs_hci_version) |
| 1134 | return hba->vops->get_ufs_hci_version(hba); |
| 1135 | |
| 1136 | return ufshcd_readl(hba, REG_UFS_VERSION); |
| 1137 | } |
| 1138 | |
| 1139 | static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, |
| 1140 | bool up, enum ufs_notify_change_status status) |
| 1141 | { |
| 1142 | if (hba->vops && hba->vops->clk_scale_notify) |
| 1143 | return hba->vops->clk_scale_notify(hba, up, status); |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
| 1147 | static inline void ufshcd_vops_event_notify(struct ufs_hba *hba, |
| 1148 | enum ufs_event_type evt, |
| 1149 | void *data) |
| 1150 | { |
| 1151 | if (hba->vops && hba->vops->event_notify) |
| 1152 | hba->vops->event_notify(hba, evt, data); |
| 1153 | } |
| 1154 | |
| 1155 | static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on, |
| 1156 | enum ufs_notify_change_status status) |
| 1157 | { |
| 1158 | if (hba->vops && hba->vops->setup_clocks) |
| 1159 | return hba->vops->setup_clocks(hba, on, status); |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba, |
| 1164 | bool status) |
| 1165 | { |
| 1166 | if (hba->vops && hba->vops->hce_enable_notify) |
| 1167 | return hba->vops->hce_enable_notify(hba, status); |
| 1168 | |
| 1169 | return 0; |
| 1170 | } |
| 1171 | static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, |
| 1172 | bool status) |
| 1173 | { |
| 1174 | if (hba->vops && hba->vops->link_startup_notify) |
| 1175 | return hba->vops->link_startup_notify(hba, status); |
| 1176 | |
| 1177 | return 0; |
| 1178 | } |
| 1179 | |
| 1180 | static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) |
| 1181 | { |
| 1182 | if (hba->vops && hba->vops->phy_initialization) |
| 1183 | return hba->vops->phy_initialization(hba); |
| 1184 | |
| 1185 | return 0; |
| 1186 | } |
| 1187 | |
| 1188 | static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba, |
| 1189 | bool status, |
| 1190 | struct ufs_pa_layer_attr *dev_max_params, |
| 1191 | struct ufs_pa_layer_attr *dev_req_params) |
| 1192 | { |
| 1193 | if (hba->vops && hba->vops->pwr_change_notify) |
| 1194 | return hba->vops->pwr_change_notify(hba, status, |
| 1195 | dev_max_params, dev_req_params); |
| 1196 | |
| 1197 | return -ENOTSUPP; |
| 1198 | } |
| 1199 | |
| 1200 | static inline void ufshcd_vops_setup_xfer_req(struct ufs_hba *hba, int tag, |
| 1201 | bool is_scsi_cmd) |
| 1202 | { |
| 1203 | if (hba->vops && hba->vops->setup_xfer_req) |
| 1204 | return hba->vops->setup_xfer_req(hba, tag, is_scsi_cmd); |
| 1205 | } |
| 1206 | |
| 1207 | static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba, |
| 1208 | int tag, u8 tm_function) |
| 1209 | { |
| 1210 | if (hba->vops && hba->vops->setup_task_mgmt) |
| 1211 | return hba->vops->setup_task_mgmt(hba, tag, tm_function); |
| 1212 | } |
| 1213 | |
| 1214 | static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba, |
| 1215 | enum uic_cmd_dme cmd, |
| 1216 | enum ufs_notify_change_status status) |
| 1217 | { |
| 1218 | if (hba->vops && hba->vops->hibern8_notify) |
| 1219 | return hba->vops->hibern8_notify(hba, cmd, status); |
| 1220 | } |
| 1221 | |
| 1222 | static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba) |
| 1223 | { |
| 1224 | if (hba->vops && hba->vops->apply_dev_quirks) |
| 1225 | return hba->vops->apply_dev_quirks(hba); |
| 1226 | return 0; |
| 1227 | } |
| 1228 | |
| 1229 | static inline void ufshcd_vops_fixup_dev_quirks(struct ufs_hba *hba) |
| 1230 | { |
| 1231 | if (hba->vops && hba->vops->fixup_dev_quirks) |
| 1232 | hba->vops->fixup_dev_quirks(hba); |
| 1233 | } |
| 1234 | |
| 1235 | static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op) |
| 1236 | { |
| 1237 | if (hba->vops && hba->vops->suspend) |
| 1238 | return hba->vops->suspend(hba, op); |
| 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
| 1243 | static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op) |
| 1244 | { |
| 1245 | if (hba->vops && hba->vops->resume) |
| 1246 | return hba->vops->resume(hba, op); |
| 1247 | |
| 1248 | return 0; |
| 1249 | } |
| 1250 | |
| 1251 | static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba) |
| 1252 | { |
| 1253 | if (hba->vops && hba->vops->dbg_register_dump) |
| 1254 | hba->vops->dbg_register_dump(hba); |
| 1255 | } |
| 1256 | |
| 1257 | static inline int ufshcd_vops_device_reset(struct ufs_hba *hba) |
| 1258 | { |
| 1259 | if (hba->vops && hba->vops->device_reset) |
| 1260 | return hba->vops->device_reset(hba); |
| 1261 | |
| 1262 | return -EOPNOTSUPP; |
| 1263 | } |
| 1264 | |
| 1265 | static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba, |
| 1266 | struct devfreq_dev_profile |
| 1267 | *profile, void *data) |
| 1268 | { |
| 1269 | if (hba->vops && hba->vops->config_scaling_param) |
| 1270 | hba->vops->config_scaling_param(hba, profile, data); |
| 1271 | } |
| 1272 | |
| 1273 | extern struct ufs_pm_lvl_states ufs_pm_lvl_states[]; |
| 1274 | |
| 1275 | /* |
| 1276 | * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN |
| 1277 | * @scsi_lun: scsi LUN id |
| 1278 | * |
| 1279 | * Returns UPIU LUN id |
| 1280 | */ |
| 1281 | static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun) |
| 1282 | { |
| 1283 | if (scsi_is_wlun(scsi_lun)) |
| 1284 | return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID) |
| 1285 | | UFS_UPIU_WLUN_ID; |
| 1286 | else |
| 1287 | return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID; |
| 1288 | } |
| 1289 | |
| 1290 | int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, |
| 1291 | const char *prefix); |
| 1292 | |
| 1293 | int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); |
| 1294 | int ufshcd_write_ee_control(struct ufs_hba *hba); |
| 1295 | int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask, |
| 1296 | u16 set, u16 clr); |
| 1297 | |
| 1298 | static inline int ufshcd_update_ee_drv_mask(struct ufs_hba *hba, |
| 1299 | u16 set, u16 clr) |
| 1300 | { |
| 1301 | return ufshcd_update_ee_control(hba, &hba->ee_drv_mask, |
| 1302 | &hba->ee_usr_mask, set, clr); |
| 1303 | } |
| 1304 | |
| 1305 | static inline int ufshcd_update_ee_usr_mask(struct ufs_hba *hba, |
| 1306 | u16 set, u16 clr) |
| 1307 | { |
| 1308 | return ufshcd_update_ee_control(hba, &hba->ee_usr_mask, |
| 1309 | &hba->ee_drv_mask, set, clr); |
| 1310 | } |
| 1311 | |
| 1312 | #endif /* End of Header */ |