| 1 | /* |
| 2 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 3 | * redistributing this file, you may do so under either license. |
| 4 | * |
| 5 | * GPL LICENSE SUMMARY |
| 6 | * |
| 7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of version 2 of the GNU General Public License as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 21 | * The full GNU General Public License is included in this distribution |
| 22 | * in the file called LICENSE.GPL. |
| 23 | * |
| 24 | * BSD LICENSE |
| 25 | * |
| 26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
| 27 | * All rights reserved. |
| 28 | * |
| 29 | * Redistribution and use in source and binary forms, with or without |
| 30 | * modification, are permitted provided that the following conditions |
| 31 | * are met: |
| 32 | * |
| 33 | * * Redistributions of source code must retain the above copyright |
| 34 | * notice, this list of conditions and the following disclaimer. |
| 35 | * * Redistributions in binary form must reproduce the above copyright |
| 36 | * notice, this list of conditions and the following disclaimer in |
| 37 | * the documentation and/or other materials provided with the |
| 38 | * distribution. |
| 39 | * * Neither the name of Intel Corporation nor the names of its |
| 40 | * contributors may be used to endorse or promote products derived |
| 41 | * from this software without specific prior written permission. |
| 42 | * |
| 43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 54 | */ |
| 55 | |
| 56 | #include "isci.h" |
| 57 | #include "host.h" |
| 58 | #include "phy.h" |
| 59 | #include "scu_event_codes.h" |
| 60 | #include "probe_roms.h" |
| 61 | |
| 62 | #undef C |
| 63 | #define C(a) (#a) |
| 64 | static const char *phy_state_name(enum sci_phy_states state) |
| 65 | { |
| 66 | static const char * const strings[] = PHY_STATES; |
| 67 | |
| 68 | return strings[state]; |
| 69 | } |
| 70 | #undef C |
| 71 | |
| 72 | /* Maximum arbitration wait time in micro-seconds */ |
| 73 | #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME (700) |
| 74 | |
| 75 | enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy) |
| 76 | { |
| 77 | return iphy->max_negotiated_speed; |
| 78 | } |
| 79 | |
| 80 | static struct device *sciphy_to_dev(struct isci_phy *iphy) |
| 81 | { |
| 82 | struct isci_phy *table = iphy - iphy->phy_index; |
| 83 | struct isci_host *ihost = container_of(table, typeof(*ihost), phys[0]); |
| 84 | |
| 85 | return &ihost->pdev->dev; |
| 86 | } |
| 87 | |
| 88 | static enum sci_status |
| 89 | sci_phy_transport_layer_initialization(struct isci_phy *iphy, |
| 90 | struct scu_transport_layer_registers __iomem *reg) |
| 91 | { |
| 92 | u32 tl_control; |
| 93 | |
| 94 | iphy->transport_layer_registers = reg; |
| 95 | |
| 96 | writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX, |
| 97 | &iphy->transport_layer_registers->stp_rni); |
| 98 | |
| 99 | /* |
| 100 | * Hardware team recommends that we enable the STP prefetch for all |
| 101 | * transports |
| 102 | */ |
| 103 | tl_control = readl(&iphy->transport_layer_registers->control); |
| 104 | tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH); |
| 105 | writel(tl_control, &iphy->transport_layer_registers->control); |
| 106 | |
| 107 | return SCI_SUCCESS; |
| 108 | } |
| 109 | |
| 110 | static enum sci_status |
| 111 | sci_phy_link_layer_initialization(struct isci_phy *iphy, |
| 112 | struct scu_link_layer_registers __iomem *llr) |
| 113 | { |
| 114 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 115 | struct sci_phy_user_params *phy_user; |
| 116 | struct sci_phy_oem_params *phy_oem; |
| 117 | int phy_idx = iphy->phy_index; |
| 118 | struct sci_phy_cap phy_cap; |
| 119 | u32 phy_configuration; |
| 120 | u32 parity_check = 0; |
| 121 | u32 parity_count = 0; |
| 122 | u32 llctl, link_rate; |
| 123 | u32 clksm_value = 0; |
| 124 | u32 sp_timeouts = 0; |
| 125 | |
| 126 | phy_user = &ihost->user_parameters.phys[phy_idx]; |
| 127 | phy_oem = &ihost->oem_parameters.phys[phy_idx]; |
| 128 | iphy->link_layer_registers = llr; |
| 129 | |
| 130 | /* Set our IDENTIFY frame data */ |
| 131 | #define SCI_END_DEVICE 0x01 |
| 132 | |
| 133 | writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) | |
| 134 | SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) | |
| 135 | SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) | |
| 136 | SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) | |
| 137 | SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE), |
| 138 | &llr->transmit_identification); |
| 139 | |
| 140 | /* Write the device SAS Address */ |
| 141 | writel(0xFEDCBA98, &llr->sas_device_name_high); |
| 142 | writel(phy_idx, &llr->sas_device_name_low); |
| 143 | |
| 144 | /* Write the source SAS Address */ |
| 145 | writel(phy_oem->sas_address.high, &llr->source_sas_address_high); |
| 146 | writel(phy_oem->sas_address.low, &llr->source_sas_address_low); |
| 147 | |
| 148 | /* Clear and Set the PHY Identifier */ |
| 149 | writel(0, &llr->identify_frame_phy_id); |
| 150 | writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id); |
| 151 | |
| 152 | /* Change the initial state of the phy configuration register */ |
| 153 | phy_configuration = readl(&llr->phy_configuration); |
| 154 | |
| 155 | /* Hold OOB state machine in reset */ |
| 156 | phy_configuration |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET); |
| 157 | writel(phy_configuration, &llr->phy_configuration); |
| 158 | |
| 159 | /* Configure the SNW capabilities */ |
| 160 | phy_cap.all = 0; |
| 161 | phy_cap.start = 1; |
| 162 | phy_cap.gen3_no_ssc = 1; |
| 163 | phy_cap.gen2_no_ssc = 1; |
| 164 | phy_cap.gen1_no_ssc = 1; |
| 165 | if (ihost->oem_parameters.controller.do_enable_ssc) { |
| 166 | struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe; |
| 167 | struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_idx]; |
| 168 | struct isci_pci_info *pci_info = to_pci_info(ihost->pdev); |
| 169 | bool en_sas = false; |
| 170 | bool en_sata = false; |
| 171 | u32 sas_type = 0; |
| 172 | u32 sata_spread = 0x2; |
| 173 | u32 sas_spread = 0x2; |
| 174 | |
| 175 | phy_cap.gen3_ssc = 1; |
| 176 | phy_cap.gen2_ssc = 1; |
| 177 | phy_cap.gen1_ssc = 1; |
| 178 | |
| 179 | if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1) |
| 180 | en_sas = en_sata = true; |
| 181 | else { |
| 182 | sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level; |
| 183 | sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level; |
| 184 | |
| 185 | if (sata_spread) |
| 186 | en_sata = true; |
| 187 | |
| 188 | if (sas_spread) { |
| 189 | en_sas = true; |
| 190 | sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type; |
| 191 | } |
| 192 | |
| 193 | } |
| 194 | |
| 195 | if (en_sas) { |
| 196 | u32 reg; |
| 197 | |
| 198 | reg = readl(&xcvr->afe_xcvr_control0); |
| 199 | reg |= (0x00100000 | (sas_type << 19)); |
| 200 | writel(reg, &xcvr->afe_xcvr_control0); |
| 201 | |
| 202 | reg = readl(&xcvr->afe_tx_ssc_control); |
| 203 | reg |= sas_spread << 8; |
| 204 | writel(reg, &xcvr->afe_tx_ssc_control); |
| 205 | } |
| 206 | |
| 207 | if (en_sata) { |
| 208 | u32 reg; |
| 209 | |
| 210 | reg = readl(&xcvr->afe_tx_ssc_control); |
| 211 | reg |= sata_spread; |
| 212 | writel(reg, &xcvr->afe_tx_ssc_control); |
| 213 | |
| 214 | reg = readl(&llr->stp_control); |
| 215 | reg |= 1 << 12; |
| 216 | writel(reg, &llr->stp_control); |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | /* The SAS specification indicates that the phy_capabilities that |
| 221 | * are transmitted shall have an even parity. Calculate the parity. |
| 222 | */ |
| 223 | parity_check = phy_cap.all; |
| 224 | while (parity_check != 0) { |
| 225 | if (parity_check & 0x1) |
| 226 | parity_count++; |
| 227 | parity_check >>= 1; |
| 228 | } |
| 229 | |
| 230 | /* If parity indicates there are an odd number of bits set, then |
| 231 | * set the parity bit to 1 in the phy capabilities. |
| 232 | */ |
| 233 | if ((parity_count % 2) != 0) |
| 234 | phy_cap.parity = 1; |
| 235 | |
| 236 | writel(phy_cap.all, &llr->phy_capabilities); |
| 237 | |
| 238 | /* Set the enable spinup period but disable the ability to send |
| 239 | * notify enable spinup |
| 240 | */ |
| 241 | writel(SCU_ENSPINUP_GEN_VAL(COUNT, |
| 242 | phy_user->notify_enable_spin_up_insertion_frequency), |
| 243 | &llr->notify_enable_spinup_control); |
| 244 | |
| 245 | /* Write the ALIGN Insertion Ferequency for connected phy and |
| 246 | * inpendent of connected state |
| 247 | */ |
| 248 | clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED, |
| 249 | phy_user->in_connection_align_insertion_frequency); |
| 250 | |
| 251 | clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL, |
| 252 | phy_user->align_insertion_frequency); |
| 253 | |
| 254 | writel(clksm_value, &llr->clock_skew_management); |
| 255 | |
| 256 | if (is_c0(ihost->pdev) || is_c1(ihost->pdev)) { |
| 257 | writel(0x04210400, &llr->afe_lookup_table_control); |
| 258 | writel(0x020A7C05, &llr->sas_primitive_timeout); |
| 259 | } else |
| 260 | writel(0x02108421, &llr->afe_lookup_table_control); |
| 261 | |
| 262 | llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT, |
| 263 | (u8)ihost->user_parameters.no_outbound_task_timeout); |
| 264 | |
| 265 | switch (phy_user->max_speed_generation) { |
| 266 | case SCIC_SDS_PARM_GEN3_SPEED: |
| 267 | link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3; |
| 268 | break; |
| 269 | case SCIC_SDS_PARM_GEN2_SPEED: |
| 270 | link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2; |
| 271 | break; |
| 272 | default: |
| 273 | link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1; |
| 274 | break; |
| 275 | } |
| 276 | llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate); |
| 277 | writel(llctl, &llr->link_layer_control); |
| 278 | |
| 279 | sp_timeouts = readl(&llr->sas_phy_timeouts); |
| 280 | |
| 281 | /* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */ |
| 282 | sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF); |
| 283 | |
| 284 | /* Set RATE_CHANGE timeout value to 0x3B (59us). This ensures SCU can |
| 285 | * lock with 3Gb drive when SCU max rate is set to 1.5Gb. |
| 286 | */ |
| 287 | sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B); |
| 288 | |
| 289 | writel(sp_timeouts, &llr->sas_phy_timeouts); |
| 290 | |
| 291 | if (is_a2(ihost->pdev)) { |
| 292 | /* Program the max ARB time for the PHY to 700us so we |
| 293 | * inter-operate with the PMC expander which shuts down |
| 294 | * PHYs if the expander PHY generates too many breaks. |
| 295 | * This time value will guarantee that the initiator PHY |
| 296 | * will generate the break. |
| 297 | */ |
| 298 | writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME, |
| 299 | &llr->maximum_arbitration_wait_timer_timeout); |
| 300 | } |
| 301 | |
| 302 | /* Disable link layer hang detection, rely on the OS timeout for |
| 303 | * I/O timeouts. |
| 304 | */ |
| 305 | writel(0, &llr->link_layer_hang_detection_timeout); |
| 306 | |
| 307 | /* We can exit the initial state to the stopped state */ |
| 308 | sci_change_state(&iphy->sm, SCI_PHY_STOPPED); |
| 309 | |
| 310 | return SCI_SUCCESS; |
| 311 | } |
| 312 | |
| 313 | static void phy_sata_timeout(unsigned long data) |
| 314 | { |
| 315 | struct sci_timer *tmr = (struct sci_timer *)data; |
| 316 | struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer); |
| 317 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 318 | unsigned long flags; |
| 319 | |
| 320 | spin_lock_irqsave(&ihost->scic_lock, flags); |
| 321 | |
| 322 | if (tmr->cancel) |
| 323 | goto done; |
| 324 | |
| 325 | dev_dbg(sciphy_to_dev(iphy), |
| 326 | "%s: SCIC SDS Phy 0x%p did not receive signature fis before " |
| 327 | "timeout.\n", |
| 328 | __func__, |
| 329 | iphy); |
| 330 | |
| 331 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 332 | done: |
| 333 | spin_unlock_irqrestore(&ihost->scic_lock, flags); |
| 334 | } |
| 335 | |
| 336 | /** |
| 337 | * This method returns the port currently containing this phy. If the phy is |
| 338 | * currently contained by the dummy port, then the phy is considered to not |
| 339 | * be part of a port. |
| 340 | * @sci_phy: This parameter specifies the phy for which to retrieve the |
| 341 | * containing port. |
| 342 | * |
| 343 | * This method returns a handle to a port that contains the supplied phy. |
| 344 | * NULL This value is returned if the phy is not part of a real |
| 345 | * port (i.e. it's contained in the dummy port). !NULL All other |
| 346 | * values indicate a handle/pointer to the port containing the phy. |
| 347 | */ |
| 348 | struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy) |
| 349 | { |
| 350 | struct isci_port *iport = iphy->owning_port; |
| 351 | |
| 352 | if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT) |
| 353 | return NULL; |
| 354 | |
| 355 | return iphy->owning_port; |
| 356 | } |
| 357 | |
| 358 | /** |
| 359 | * This method will assign a port to the phy object. |
| 360 | * @out]: iphy This parameter specifies the phy for which to assign a port |
| 361 | * object. |
| 362 | * |
| 363 | * |
| 364 | */ |
| 365 | void sci_phy_set_port( |
| 366 | struct isci_phy *iphy, |
| 367 | struct isci_port *iport) |
| 368 | { |
| 369 | iphy->owning_port = iport; |
| 370 | |
| 371 | if (iphy->bcn_received_while_port_unassigned) { |
| 372 | iphy->bcn_received_while_port_unassigned = false; |
| 373 | sci_port_broadcast_change_received(iphy->owning_port, iphy); |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | enum sci_status sci_phy_initialize(struct isci_phy *iphy, |
| 378 | struct scu_transport_layer_registers __iomem *tl, |
| 379 | struct scu_link_layer_registers __iomem *ll) |
| 380 | { |
| 381 | /* Perfrom the initialization of the TL hardware */ |
| 382 | sci_phy_transport_layer_initialization(iphy, tl); |
| 383 | |
| 384 | /* Perofrm the initialization of the PE hardware */ |
| 385 | sci_phy_link_layer_initialization(iphy, ll); |
| 386 | |
| 387 | /* There is nothing that needs to be done in this state just |
| 388 | * transition to the stopped state |
| 389 | */ |
| 390 | sci_change_state(&iphy->sm, SCI_PHY_STOPPED); |
| 391 | |
| 392 | return SCI_SUCCESS; |
| 393 | } |
| 394 | |
| 395 | /** |
| 396 | * This method assigns the direct attached device ID for this phy. |
| 397 | * |
| 398 | * @iphy The phy for which the direct attached device id is to |
| 399 | * be assigned. |
| 400 | * @device_id The direct attached device ID to assign to the phy. |
| 401 | * This will either be the RNi for the device or an invalid RNi if there |
| 402 | * is no current device assigned to the phy. |
| 403 | */ |
| 404 | void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id) |
| 405 | { |
| 406 | u32 tl_control; |
| 407 | |
| 408 | writel(device_id, &iphy->transport_layer_registers->stp_rni); |
| 409 | |
| 410 | /* |
| 411 | * The read should guarantee that the first write gets posted |
| 412 | * before the next write |
| 413 | */ |
| 414 | tl_control = readl(&iphy->transport_layer_registers->control); |
| 415 | tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE); |
| 416 | writel(tl_control, &iphy->transport_layer_registers->control); |
| 417 | } |
| 418 | |
| 419 | static void sci_phy_suspend(struct isci_phy *iphy) |
| 420 | { |
| 421 | u32 scu_sas_pcfg_value; |
| 422 | |
| 423 | scu_sas_pcfg_value = |
| 424 | readl(&iphy->link_layer_registers->phy_configuration); |
| 425 | scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE); |
| 426 | writel(scu_sas_pcfg_value, |
| 427 | &iphy->link_layer_registers->phy_configuration); |
| 428 | |
| 429 | sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX); |
| 430 | } |
| 431 | |
| 432 | void sci_phy_resume(struct isci_phy *iphy) |
| 433 | { |
| 434 | u32 scu_sas_pcfg_value; |
| 435 | |
| 436 | scu_sas_pcfg_value = |
| 437 | readl(&iphy->link_layer_registers->phy_configuration); |
| 438 | scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE); |
| 439 | writel(scu_sas_pcfg_value, |
| 440 | &iphy->link_layer_registers->phy_configuration); |
| 441 | } |
| 442 | |
| 443 | void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas) |
| 444 | { |
| 445 | sas->high = readl(&iphy->link_layer_registers->source_sas_address_high); |
| 446 | sas->low = readl(&iphy->link_layer_registers->source_sas_address_low); |
| 447 | } |
| 448 | |
| 449 | void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas) |
| 450 | { |
| 451 | struct sas_identify_frame *iaf; |
| 452 | |
| 453 | iaf = &iphy->frame_rcvd.iaf; |
| 454 | memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE); |
| 455 | } |
| 456 | |
| 457 | void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto) |
| 458 | { |
| 459 | proto->all = readl(&iphy->link_layer_registers->transmit_identification); |
| 460 | } |
| 461 | |
| 462 | enum sci_status sci_phy_start(struct isci_phy *iphy) |
| 463 | { |
| 464 | enum sci_phy_states state = iphy->sm.current_state_id; |
| 465 | |
| 466 | if (state != SCI_PHY_STOPPED) { |
| 467 | dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", |
| 468 | __func__, phy_state_name(state)); |
| 469 | return SCI_FAILURE_INVALID_STATE; |
| 470 | } |
| 471 | |
| 472 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 473 | return SCI_SUCCESS; |
| 474 | } |
| 475 | |
| 476 | enum sci_status sci_phy_stop(struct isci_phy *iphy) |
| 477 | { |
| 478 | enum sci_phy_states state = iphy->sm.current_state_id; |
| 479 | |
| 480 | switch (state) { |
| 481 | case SCI_PHY_SUB_INITIAL: |
| 482 | case SCI_PHY_SUB_AWAIT_OSSP_EN: |
| 483 | case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: |
| 484 | case SCI_PHY_SUB_AWAIT_SAS_POWER: |
| 485 | case SCI_PHY_SUB_AWAIT_SATA_POWER: |
| 486 | case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: |
| 487 | case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: |
| 488 | case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: |
| 489 | case SCI_PHY_SUB_FINAL: |
| 490 | case SCI_PHY_READY: |
| 491 | break; |
| 492 | default: |
| 493 | dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", |
| 494 | __func__, phy_state_name(state)); |
| 495 | return SCI_FAILURE_INVALID_STATE; |
| 496 | } |
| 497 | |
| 498 | sci_change_state(&iphy->sm, SCI_PHY_STOPPED); |
| 499 | return SCI_SUCCESS; |
| 500 | } |
| 501 | |
| 502 | enum sci_status sci_phy_reset(struct isci_phy *iphy) |
| 503 | { |
| 504 | enum sci_phy_states state = iphy->sm.current_state_id; |
| 505 | |
| 506 | if (state != SCI_PHY_READY) { |
| 507 | dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", |
| 508 | __func__, phy_state_name(state)); |
| 509 | return SCI_FAILURE_INVALID_STATE; |
| 510 | } |
| 511 | |
| 512 | sci_change_state(&iphy->sm, SCI_PHY_RESETTING); |
| 513 | return SCI_SUCCESS; |
| 514 | } |
| 515 | |
| 516 | enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy) |
| 517 | { |
| 518 | enum sci_phy_states state = iphy->sm.current_state_id; |
| 519 | |
| 520 | switch (state) { |
| 521 | case SCI_PHY_SUB_AWAIT_SAS_POWER: { |
| 522 | u32 enable_spinup; |
| 523 | |
| 524 | enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control); |
| 525 | enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE); |
| 526 | writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control); |
| 527 | |
| 528 | /* Change state to the final state this substate machine has run to completion */ |
| 529 | sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL); |
| 530 | |
| 531 | return SCI_SUCCESS; |
| 532 | } |
| 533 | case SCI_PHY_SUB_AWAIT_SATA_POWER: { |
| 534 | u32 scu_sas_pcfg_value; |
| 535 | |
| 536 | /* Release the spinup hold state and reset the OOB state machine */ |
| 537 | scu_sas_pcfg_value = |
| 538 | readl(&iphy->link_layer_registers->phy_configuration); |
| 539 | scu_sas_pcfg_value &= |
| 540 | ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE)); |
| 541 | scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET); |
| 542 | writel(scu_sas_pcfg_value, |
| 543 | &iphy->link_layer_registers->phy_configuration); |
| 544 | |
| 545 | /* Now restart the OOB operation */ |
| 546 | scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET); |
| 547 | scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); |
| 548 | writel(scu_sas_pcfg_value, |
| 549 | &iphy->link_layer_registers->phy_configuration); |
| 550 | |
| 551 | /* Change state to the final state this substate machine has run to completion */ |
| 552 | sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN); |
| 553 | |
| 554 | return SCI_SUCCESS; |
| 555 | } |
| 556 | default: |
| 557 | dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", |
| 558 | __func__, phy_state_name(state)); |
| 559 | return SCI_FAILURE_INVALID_STATE; |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | static void sci_phy_start_sas_link_training(struct isci_phy *iphy) |
| 564 | { |
| 565 | /* continue the link training for the phy as if it were a SAS PHY |
| 566 | * instead of a SATA PHY. This is done because the completion queue had a SAS |
| 567 | * PHY DETECTED event when the state machine was expecting a SATA PHY event. |
| 568 | */ |
| 569 | u32 phy_control; |
| 570 | |
| 571 | phy_control = readl(&iphy->link_layer_registers->phy_configuration); |
| 572 | phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD); |
| 573 | writel(phy_control, |
| 574 | &iphy->link_layer_registers->phy_configuration); |
| 575 | |
| 576 | sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN); |
| 577 | |
| 578 | iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS; |
| 579 | } |
| 580 | |
| 581 | static void sci_phy_start_sata_link_training(struct isci_phy *iphy) |
| 582 | { |
| 583 | /* This method continues the link training for the phy as if it were a SATA PHY |
| 584 | * instead of a SAS PHY. This is done because the completion queue had a SATA |
| 585 | * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none |
| 586 | */ |
| 587 | sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER); |
| 588 | |
| 589 | iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA; |
| 590 | } |
| 591 | |
| 592 | /** |
| 593 | * sci_phy_complete_link_training - perform processing common to |
| 594 | * all protocols upon completion of link training. |
| 595 | * @sci_phy: This parameter specifies the phy object for which link training |
| 596 | * has completed. |
| 597 | * @max_link_rate: This parameter specifies the maximum link rate to be |
| 598 | * associated with this phy. |
| 599 | * @next_state: This parameter specifies the next state for the phy's starting |
| 600 | * sub-state machine. |
| 601 | * |
| 602 | */ |
| 603 | static void sci_phy_complete_link_training(struct isci_phy *iphy, |
| 604 | enum sas_linkrate max_link_rate, |
| 605 | u32 next_state) |
| 606 | { |
| 607 | iphy->max_negotiated_speed = max_link_rate; |
| 608 | |
| 609 | sci_change_state(&iphy->sm, next_state); |
| 610 | } |
| 611 | |
| 612 | enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code) |
| 613 | { |
| 614 | enum sci_phy_states state = iphy->sm.current_state_id; |
| 615 | |
| 616 | switch (state) { |
| 617 | case SCI_PHY_SUB_AWAIT_OSSP_EN: |
| 618 | switch (scu_get_event_code(event_code)) { |
| 619 | case SCU_EVENT_SAS_PHY_DETECTED: |
| 620 | sci_phy_start_sas_link_training(iphy); |
| 621 | iphy->is_in_link_training = true; |
| 622 | break; |
| 623 | case SCU_EVENT_SATA_SPINUP_HOLD: |
| 624 | sci_phy_start_sata_link_training(iphy); |
| 625 | iphy->is_in_link_training = true; |
| 626 | break; |
| 627 | default: |
| 628 | dev_dbg(sciphy_to_dev(iphy), |
| 629 | "%s: PHY starting substate machine received " |
| 630 | "unexpected event_code %x\n", |
| 631 | __func__, |
| 632 | event_code); |
| 633 | return SCI_FAILURE; |
| 634 | } |
| 635 | return SCI_SUCCESS; |
| 636 | case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: |
| 637 | switch (scu_get_event_code(event_code)) { |
| 638 | case SCU_EVENT_SAS_PHY_DETECTED: |
| 639 | /* |
| 640 | * Why is this being reported again by the controller? |
| 641 | * We would re-enter this state so just stay here */ |
| 642 | break; |
| 643 | case SCU_EVENT_SAS_15: |
| 644 | case SCU_EVENT_SAS_15_SSC: |
| 645 | sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS, |
| 646 | SCI_PHY_SUB_AWAIT_IAF_UF); |
| 647 | break; |
| 648 | case SCU_EVENT_SAS_30: |
| 649 | case SCU_EVENT_SAS_30_SSC: |
| 650 | sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS, |
| 651 | SCI_PHY_SUB_AWAIT_IAF_UF); |
| 652 | break; |
| 653 | case SCU_EVENT_SAS_60: |
| 654 | case SCU_EVENT_SAS_60_SSC: |
| 655 | sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS, |
| 656 | SCI_PHY_SUB_AWAIT_IAF_UF); |
| 657 | break; |
| 658 | case SCU_EVENT_SATA_SPINUP_HOLD: |
| 659 | /* |
| 660 | * We were doing SAS PHY link training and received a SATA PHY event |
| 661 | * continue OOB/SN as if this were a SATA PHY */ |
| 662 | sci_phy_start_sata_link_training(iphy); |
| 663 | break; |
| 664 | case SCU_EVENT_LINK_FAILURE: |
| 665 | /* Link failure change state back to the starting state */ |
| 666 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 667 | break; |
| 668 | default: |
| 669 | dev_warn(sciphy_to_dev(iphy), |
| 670 | "%s: PHY starting substate machine received " |
| 671 | "unexpected event_code %x\n", |
| 672 | __func__, event_code); |
| 673 | |
| 674 | return SCI_FAILURE; |
| 675 | break; |
| 676 | } |
| 677 | return SCI_SUCCESS; |
| 678 | case SCI_PHY_SUB_AWAIT_IAF_UF: |
| 679 | switch (scu_get_event_code(event_code)) { |
| 680 | case SCU_EVENT_SAS_PHY_DETECTED: |
| 681 | /* Backup the state machine */ |
| 682 | sci_phy_start_sas_link_training(iphy); |
| 683 | break; |
| 684 | case SCU_EVENT_SATA_SPINUP_HOLD: |
| 685 | /* We were doing SAS PHY link training and received a |
| 686 | * SATA PHY event continue OOB/SN as if this were a |
| 687 | * SATA PHY |
| 688 | */ |
| 689 | sci_phy_start_sata_link_training(iphy); |
| 690 | break; |
| 691 | case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT: |
| 692 | case SCU_EVENT_LINK_FAILURE: |
| 693 | case SCU_EVENT_HARD_RESET_RECEIVED: |
| 694 | /* Start the oob/sn state machine over again */ |
| 695 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 696 | break; |
| 697 | default: |
| 698 | dev_warn(sciphy_to_dev(iphy), |
| 699 | "%s: PHY starting substate machine received " |
| 700 | "unexpected event_code %x\n", |
| 701 | __func__, event_code); |
| 702 | return SCI_FAILURE; |
| 703 | } |
| 704 | return SCI_SUCCESS; |
| 705 | case SCI_PHY_SUB_AWAIT_SAS_POWER: |
| 706 | switch (scu_get_event_code(event_code)) { |
| 707 | case SCU_EVENT_LINK_FAILURE: |
| 708 | /* Link failure change state back to the starting state */ |
| 709 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 710 | break; |
| 711 | default: |
| 712 | dev_warn(sciphy_to_dev(iphy), |
| 713 | "%s: PHY starting substate machine received unexpected " |
| 714 | "event_code %x\n", |
| 715 | __func__, |
| 716 | event_code); |
| 717 | return SCI_FAILURE; |
| 718 | } |
| 719 | return SCI_SUCCESS; |
| 720 | case SCI_PHY_SUB_AWAIT_SATA_POWER: |
| 721 | switch (scu_get_event_code(event_code)) { |
| 722 | case SCU_EVENT_LINK_FAILURE: |
| 723 | /* Link failure change state back to the starting state */ |
| 724 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 725 | break; |
| 726 | case SCU_EVENT_SATA_SPINUP_HOLD: |
| 727 | /* These events are received every 10ms and are |
| 728 | * expected while in this state |
| 729 | */ |
| 730 | break; |
| 731 | |
| 732 | case SCU_EVENT_SAS_PHY_DETECTED: |
| 733 | /* There has been a change in the phy type before OOB/SN for the |
| 734 | * SATA finished start down the SAS link traning path. |
| 735 | */ |
| 736 | sci_phy_start_sas_link_training(iphy); |
| 737 | break; |
| 738 | |
| 739 | default: |
| 740 | dev_warn(sciphy_to_dev(iphy), |
| 741 | "%s: PHY starting substate machine received " |
| 742 | "unexpected event_code %x\n", |
| 743 | __func__, event_code); |
| 744 | |
| 745 | return SCI_FAILURE; |
| 746 | } |
| 747 | return SCI_SUCCESS; |
| 748 | case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: |
| 749 | switch (scu_get_event_code(event_code)) { |
| 750 | case SCU_EVENT_LINK_FAILURE: |
| 751 | /* Link failure change state back to the starting state */ |
| 752 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 753 | break; |
| 754 | case SCU_EVENT_SATA_SPINUP_HOLD: |
| 755 | /* These events might be received since we dont know how many may be in |
| 756 | * the completion queue while waiting for power |
| 757 | */ |
| 758 | break; |
| 759 | case SCU_EVENT_SATA_PHY_DETECTED: |
| 760 | iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA; |
| 761 | |
| 762 | /* We have received the SATA PHY notification change state */ |
| 763 | sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN); |
| 764 | break; |
| 765 | case SCU_EVENT_SAS_PHY_DETECTED: |
| 766 | /* There has been a change in the phy type before OOB/SN for the |
| 767 | * SATA finished start down the SAS link traning path. |
| 768 | */ |
| 769 | sci_phy_start_sas_link_training(iphy); |
| 770 | break; |
| 771 | default: |
| 772 | dev_warn(sciphy_to_dev(iphy), |
| 773 | "%s: PHY starting substate machine received " |
| 774 | "unexpected event_code %x\n", |
| 775 | __func__, |
| 776 | event_code); |
| 777 | |
| 778 | return SCI_FAILURE; |
| 779 | } |
| 780 | return SCI_SUCCESS; |
| 781 | case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: |
| 782 | switch (scu_get_event_code(event_code)) { |
| 783 | case SCU_EVENT_SATA_PHY_DETECTED: |
| 784 | /* |
| 785 | * The hardware reports multiple SATA PHY detected events |
| 786 | * ignore the extras */ |
| 787 | break; |
| 788 | case SCU_EVENT_SATA_15: |
| 789 | case SCU_EVENT_SATA_15_SSC: |
| 790 | sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS, |
| 791 | SCI_PHY_SUB_AWAIT_SIG_FIS_UF); |
| 792 | break; |
| 793 | case SCU_EVENT_SATA_30: |
| 794 | case SCU_EVENT_SATA_30_SSC: |
| 795 | sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS, |
| 796 | SCI_PHY_SUB_AWAIT_SIG_FIS_UF); |
| 797 | break; |
| 798 | case SCU_EVENT_SATA_60: |
| 799 | case SCU_EVENT_SATA_60_SSC: |
| 800 | sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS, |
| 801 | SCI_PHY_SUB_AWAIT_SIG_FIS_UF); |
| 802 | break; |
| 803 | case SCU_EVENT_LINK_FAILURE: |
| 804 | /* Link failure change state back to the starting state */ |
| 805 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 806 | break; |
| 807 | case SCU_EVENT_SAS_PHY_DETECTED: |
| 808 | /* |
| 809 | * There has been a change in the phy type before OOB/SN for the |
| 810 | * SATA finished start down the SAS link traning path. */ |
| 811 | sci_phy_start_sas_link_training(iphy); |
| 812 | break; |
| 813 | default: |
| 814 | dev_warn(sciphy_to_dev(iphy), |
| 815 | "%s: PHY starting substate machine received " |
| 816 | "unexpected event_code %x\n", |
| 817 | __func__, event_code); |
| 818 | |
| 819 | return SCI_FAILURE; |
| 820 | } |
| 821 | |
| 822 | return SCI_SUCCESS; |
| 823 | case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: |
| 824 | switch (scu_get_event_code(event_code)) { |
| 825 | case SCU_EVENT_SATA_PHY_DETECTED: |
| 826 | /* Backup the state machine */ |
| 827 | sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN); |
| 828 | break; |
| 829 | |
| 830 | case SCU_EVENT_LINK_FAILURE: |
| 831 | /* Link failure change state back to the starting state */ |
| 832 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 833 | break; |
| 834 | |
| 835 | default: |
| 836 | dev_warn(sciphy_to_dev(iphy), |
| 837 | "%s: PHY starting substate machine received " |
| 838 | "unexpected event_code %x\n", |
| 839 | __func__, |
| 840 | event_code); |
| 841 | |
| 842 | return SCI_FAILURE; |
| 843 | } |
| 844 | return SCI_SUCCESS; |
| 845 | case SCI_PHY_READY: |
| 846 | switch (scu_get_event_code(event_code)) { |
| 847 | case SCU_EVENT_LINK_FAILURE: |
| 848 | /* Link failure change state back to the starting state */ |
| 849 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 850 | break; |
| 851 | case SCU_EVENT_BROADCAST_CHANGE: |
| 852 | /* Broadcast change received. Notify the port. */ |
| 853 | if (phy_get_non_dummy_port(iphy) != NULL) |
| 854 | sci_port_broadcast_change_received(iphy->owning_port, iphy); |
| 855 | else |
| 856 | iphy->bcn_received_while_port_unassigned = true; |
| 857 | break; |
| 858 | default: |
| 859 | dev_warn(sciphy_to_dev(iphy), |
| 860 | "%sP SCIC PHY 0x%p ready state machine received " |
| 861 | "unexpected event_code %x\n", |
| 862 | __func__, iphy, event_code); |
| 863 | return SCI_FAILURE_INVALID_STATE; |
| 864 | } |
| 865 | return SCI_SUCCESS; |
| 866 | case SCI_PHY_RESETTING: |
| 867 | switch (scu_get_event_code(event_code)) { |
| 868 | case SCU_EVENT_HARD_RESET_TRANSMITTED: |
| 869 | /* Link failure change state back to the starting state */ |
| 870 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 871 | break; |
| 872 | default: |
| 873 | dev_warn(sciphy_to_dev(iphy), |
| 874 | "%s: SCIC PHY 0x%p resetting state machine received " |
| 875 | "unexpected event_code %x\n", |
| 876 | __func__, iphy, event_code); |
| 877 | |
| 878 | return SCI_FAILURE_INVALID_STATE; |
| 879 | break; |
| 880 | } |
| 881 | return SCI_SUCCESS; |
| 882 | default: |
| 883 | dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", |
| 884 | __func__, phy_state_name(state)); |
| 885 | return SCI_FAILURE_INVALID_STATE; |
| 886 | } |
| 887 | } |
| 888 | |
| 889 | enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index) |
| 890 | { |
| 891 | enum sci_phy_states state = iphy->sm.current_state_id; |
| 892 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 893 | enum sci_status result; |
| 894 | unsigned long flags; |
| 895 | |
| 896 | switch (state) { |
| 897 | case SCI_PHY_SUB_AWAIT_IAF_UF: { |
| 898 | u32 *frame_words; |
| 899 | struct sas_identify_frame iaf; |
| 900 | |
| 901 | result = sci_unsolicited_frame_control_get_header(&ihost->uf_control, |
| 902 | frame_index, |
| 903 | (void **)&frame_words); |
| 904 | |
| 905 | if (result != SCI_SUCCESS) |
| 906 | return result; |
| 907 | |
| 908 | sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32)); |
| 909 | if (iaf.frame_type == 0) { |
| 910 | u32 state; |
| 911 | |
| 912 | spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags); |
| 913 | memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf)); |
| 914 | spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags); |
| 915 | if (iaf.smp_tport) { |
| 916 | /* We got the IAF for an expander PHY go to the final |
| 917 | * state since there are no power requirements for |
| 918 | * expander phys. |
| 919 | */ |
| 920 | state = SCI_PHY_SUB_FINAL; |
| 921 | } else { |
| 922 | /* We got the IAF we can now go to the await spinup |
| 923 | * semaphore state |
| 924 | */ |
| 925 | state = SCI_PHY_SUB_AWAIT_SAS_POWER; |
| 926 | } |
| 927 | sci_change_state(&iphy->sm, state); |
| 928 | result = SCI_SUCCESS; |
| 929 | } else |
| 930 | dev_warn(sciphy_to_dev(iphy), |
| 931 | "%s: PHY starting substate machine received " |
| 932 | "unexpected frame id %x\n", |
| 933 | __func__, frame_index); |
| 934 | |
| 935 | sci_controller_release_frame(ihost, frame_index); |
| 936 | return result; |
| 937 | } |
| 938 | case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: { |
| 939 | struct dev_to_host_fis *frame_header; |
| 940 | u32 *fis_frame_data; |
| 941 | |
| 942 | result = sci_unsolicited_frame_control_get_header(&ihost->uf_control, |
| 943 | frame_index, |
| 944 | (void **)&frame_header); |
| 945 | |
| 946 | if (result != SCI_SUCCESS) |
| 947 | return result; |
| 948 | |
| 949 | if ((frame_header->fis_type == FIS_REGD2H) && |
| 950 | !(frame_header->status & ATA_BUSY)) { |
| 951 | sci_unsolicited_frame_control_get_buffer(&ihost->uf_control, |
| 952 | frame_index, |
| 953 | (void **)&fis_frame_data); |
| 954 | |
| 955 | spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags); |
| 956 | sci_controller_copy_sata_response(&iphy->frame_rcvd.fis, |
| 957 | frame_header, |
| 958 | fis_frame_data); |
| 959 | spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags); |
| 960 | |
| 961 | /* got IAF we can now go to the await spinup semaphore state */ |
| 962 | sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL); |
| 963 | |
| 964 | result = SCI_SUCCESS; |
| 965 | } else |
| 966 | dev_warn(sciphy_to_dev(iphy), |
| 967 | "%s: PHY starting substate machine received " |
| 968 | "unexpected frame id %x\n", |
| 969 | __func__, frame_index); |
| 970 | |
| 971 | /* Regardless of the result we are done with this frame with it */ |
| 972 | sci_controller_release_frame(ihost, frame_index); |
| 973 | |
| 974 | return result; |
| 975 | } |
| 976 | default: |
| 977 | dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", |
| 978 | __func__, phy_state_name(state)); |
| 979 | return SCI_FAILURE_INVALID_STATE; |
| 980 | } |
| 981 | |
| 982 | } |
| 983 | |
| 984 | static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm) |
| 985 | { |
| 986 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 987 | |
| 988 | /* This is just an temporary state go off to the starting state */ |
| 989 | sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN); |
| 990 | } |
| 991 | |
| 992 | static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm) |
| 993 | { |
| 994 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 995 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 996 | |
| 997 | sci_controller_power_control_queue_insert(ihost, iphy); |
| 998 | } |
| 999 | |
| 1000 | static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm) |
| 1001 | { |
| 1002 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1003 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 1004 | |
| 1005 | sci_controller_power_control_queue_remove(ihost, iphy); |
| 1006 | } |
| 1007 | |
| 1008 | static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm) |
| 1009 | { |
| 1010 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1011 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 1012 | |
| 1013 | sci_controller_power_control_queue_insert(ihost, iphy); |
| 1014 | } |
| 1015 | |
| 1016 | static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm) |
| 1017 | { |
| 1018 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1019 | struct isci_host *ihost = iphy->owning_port->owning_controller; |
| 1020 | |
| 1021 | sci_controller_power_control_queue_remove(ihost, iphy); |
| 1022 | } |
| 1023 | |
| 1024 | static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm) |
| 1025 | { |
| 1026 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1027 | |
| 1028 | sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT); |
| 1029 | } |
| 1030 | |
| 1031 | static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm) |
| 1032 | { |
| 1033 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1034 | |
| 1035 | sci_del_timer(&iphy->sata_timer); |
| 1036 | } |
| 1037 | |
| 1038 | static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm) |
| 1039 | { |
| 1040 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1041 | |
| 1042 | sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT); |
| 1043 | } |
| 1044 | |
| 1045 | static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm) |
| 1046 | { |
| 1047 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1048 | |
| 1049 | sci_del_timer(&iphy->sata_timer); |
| 1050 | } |
| 1051 | |
| 1052 | static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm) |
| 1053 | { |
| 1054 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1055 | |
| 1056 | if (sci_port_link_detected(iphy->owning_port, iphy)) { |
| 1057 | |
| 1058 | /* |
| 1059 | * Clear the PE suspend condition so we can actually |
| 1060 | * receive SIG FIS |
| 1061 | * The hardware will not respond to the XRDY until the PE |
| 1062 | * suspend condition is cleared. |
| 1063 | */ |
| 1064 | sci_phy_resume(iphy); |
| 1065 | |
| 1066 | sci_mod_timer(&iphy->sata_timer, |
| 1067 | SCIC_SDS_SIGNATURE_FIS_TIMEOUT); |
| 1068 | } else |
| 1069 | iphy->is_in_link_training = false; |
| 1070 | } |
| 1071 | |
| 1072 | static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm) |
| 1073 | { |
| 1074 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1075 | |
| 1076 | sci_del_timer(&iphy->sata_timer); |
| 1077 | } |
| 1078 | |
| 1079 | static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm) |
| 1080 | { |
| 1081 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1082 | |
| 1083 | /* State machine has run to completion so exit out and change |
| 1084 | * the base state machine to the ready state |
| 1085 | */ |
| 1086 | sci_change_state(&iphy->sm, SCI_PHY_READY); |
| 1087 | } |
| 1088 | |
| 1089 | /** |
| 1090 | * |
| 1091 | * @sci_phy: This is the struct isci_phy object to stop. |
| 1092 | * |
| 1093 | * This method will stop the struct isci_phy object. This does not reset the |
| 1094 | * protocol engine it just suspends it and places it in a state where it will |
| 1095 | * not cause the end device to power up. none |
| 1096 | */ |
| 1097 | static void scu_link_layer_stop_protocol_engine( |
| 1098 | struct isci_phy *iphy) |
| 1099 | { |
| 1100 | u32 scu_sas_pcfg_value; |
| 1101 | u32 enable_spinup_value; |
| 1102 | |
| 1103 | /* Suspend the protocol engine and place it in a sata spinup hold state */ |
| 1104 | scu_sas_pcfg_value = |
| 1105 | readl(&iphy->link_layer_registers->phy_configuration); |
| 1106 | scu_sas_pcfg_value |= |
| 1107 | (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) | |
| 1108 | SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) | |
| 1109 | SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD)); |
| 1110 | writel(scu_sas_pcfg_value, |
| 1111 | &iphy->link_layer_registers->phy_configuration); |
| 1112 | |
| 1113 | /* Disable the notify enable spinup primitives */ |
| 1114 | enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control); |
| 1115 | enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE); |
| 1116 | writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control); |
| 1117 | } |
| 1118 | |
| 1119 | static void scu_link_layer_start_oob(struct isci_phy *iphy) |
| 1120 | { |
| 1121 | struct scu_link_layer_registers __iomem *ll = iphy->link_layer_registers; |
| 1122 | u32 val; |
| 1123 | |
| 1124 | /** Reset OOB sequence - start */ |
| 1125 | val = readl(&ll->phy_configuration); |
| 1126 | val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) | |
| 1127 | SCU_SAS_PCFG_GEN_BIT(HARD_RESET)); |
| 1128 | writel(val, &ll->phy_configuration); |
| 1129 | readl(&ll->phy_configuration); /* flush */ |
| 1130 | /** Reset OOB sequence - end */ |
| 1131 | |
| 1132 | /** Start OOB sequence - start */ |
| 1133 | val = readl(&ll->phy_configuration); |
| 1134 | val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); |
| 1135 | writel(val, &ll->phy_configuration); |
| 1136 | readl(&ll->phy_configuration); /* flush */ |
| 1137 | /** Start OOB sequence - end */ |
| 1138 | } |
| 1139 | |
| 1140 | /** |
| 1141 | * |
| 1142 | * |
| 1143 | * This method will transmit a hard reset request on the specified phy. The SCU |
| 1144 | * hardware requires that we reset the OOB state machine and set the hard reset |
| 1145 | * bit in the phy configuration register. We then must start OOB over with the |
| 1146 | * hard reset bit set. |
| 1147 | */ |
| 1148 | static void scu_link_layer_tx_hard_reset( |
| 1149 | struct isci_phy *iphy) |
| 1150 | { |
| 1151 | u32 phy_configuration_value; |
| 1152 | |
| 1153 | /* |
| 1154 | * SAS Phys must wait for the HARD_RESET_TX event notification to transition |
| 1155 | * to the starting state. */ |
| 1156 | phy_configuration_value = |
| 1157 | readl(&iphy->link_layer_registers->phy_configuration); |
| 1158 | phy_configuration_value |= |
| 1159 | (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) | |
| 1160 | SCU_SAS_PCFG_GEN_BIT(OOB_RESET)); |
| 1161 | writel(phy_configuration_value, |
| 1162 | &iphy->link_layer_registers->phy_configuration); |
| 1163 | |
| 1164 | /* Now take the OOB state machine out of reset */ |
| 1165 | phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); |
| 1166 | phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET); |
| 1167 | writel(phy_configuration_value, |
| 1168 | &iphy->link_layer_registers->phy_configuration); |
| 1169 | } |
| 1170 | |
| 1171 | static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm) |
| 1172 | { |
| 1173 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1174 | struct isci_port *iport = iphy->owning_port; |
| 1175 | struct isci_host *ihost = iport->owning_controller; |
| 1176 | |
| 1177 | /* |
| 1178 | * @todo We need to get to the controller to place this PE in a |
| 1179 | * reset state |
| 1180 | */ |
| 1181 | sci_del_timer(&iphy->sata_timer); |
| 1182 | |
| 1183 | scu_link_layer_stop_protocol_engine(iphy); |
| 1184 | |
| 1185 | if (iphy->sm.previous_state_id != SCI_PHY_INITIAL) |
| 1186 | sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy); |
| 1187 | } |
| 1188 | |
| 1189 | static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm) |
| 1190 | { |
| 1191 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1192 | struct isci_port *iport = iphy->owning_port; |
| 1193 | struct isci_host *ihost = iport->owning_controller; |
| 1194 | |
| 1195 | scu_link_layer_stop_protocol_engine(iphy); |
| 1196 | scu_link_layer_start_oob(iphy); |
| 1197 | |
| 1198 | /* We don't know what kind of phy we are going to be just yet */ |
| 1199 | iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN; |
| 1200 | iphy->bcn_received_while_port_unassigned = false; |
| 1201 | |
| 1202 | if (iphy->sm.previous_state_id == SCI_PHY_READY) |
| 1203 | sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy); |
| 1204 | |
| 1205 | sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL); |
| 1206 | } |
| 1207 | |
| 1208 | static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm) |
| 1209 | { |
| 1210 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1211 | struct isci_port *iport = iphy->owning_port; |
| 1212 | struct isci_host *ihost = iport->owning_controller; |
| 1213 | |
| 1214 | sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy); |
| 1215 | } |
| 1216 | |
| 1217 | static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm) |
| 1218 | { |
| 1219 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1220 | |
| 1221 | sci_phy_suspend(iphy); |
| 1222 | } |
| 1223 | |
| 1224 | static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm) |
| 1225 | { |
| 1226 | struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); |
| 1227 | |
| 1228 | /* The phy is being reset, therefore deactivate it from the port. In |
| 1229 | * the resetting state we don't notify the user regarding link up and |
| 1230 | * link down notifications |
| 1231 | */ |
| 1232 | sci_port_deactivate_phy(iphy->owning_port, iphy, false); |
| 1233 | |
| 1234 | if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) { |
| 1235 | scu_link_layer_tx_hard_reset(iphy); |
| 1236 | } else { |
| 1237 | /* The SCU does not need to have a discrete reset state so |
| 1238 | * just go back to the starting state. |
| 1239 | */ |
| 1240 | sci_change_state(&iphy->sm, SCI_PHY_STARTING); |
| 1241 | } |
| 1242 | } |
| 1243 | |
| 1244 | static const struct sci_base_state sci_phy_state_table[] = { |
| 1245 | [SCI_PHY_INITIAL] = { }, |
| 1246 | [SCI_PHY_STOPPED] = { |
| 1247 | .enter_state = sci_phy_stopped_state_enter, |
| 1248 | }, |
| 1249 | [SCI_PHY_STARTING] = { |
| 1250 | .enter_state = sci_phy_starting_state_enter, |
| 1251 | }, |
| 1252 | [SCI_PHY_SUB_INITIAL] = { |
| 1253 | .enter_state = sci_phy_starting_initial_substate_enter, |
| 1254 | }, |
| 1255 | [SCI_PHY_SUB_AWAIT_OSSP_EN] = { }, |
| 1256 | [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { }, |
| 1257 | [SCI_PHY_SUB_AWAIT_IAF_UF] = { }, |
| 1258 | [SCI_PHY_SUB_AWAIT_SAS_POWER] = { |
| 1259 | .enter_state = sci_phy_starting_await_sas_power_substate_enter, |
| 1260 | .exit_state = sci_phy_starting_await_sas_power_substate_exit, |
| 1261 | }, |
| 1262 | [SCI_PHY_SUB_AWAIT_SATA_POWER] = { |
| 1263 | .enter_state = sci_phy_starting_await_sata_power_substate_enter, |
| 1264 | .exit_state = sci_phy_starting_await_sata_power_substate_exit |
| 1265 | }, |
| 1266 | [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = { |
| 1267 | .enter_state = sci_phy_starting_await_sata_phy_substate_enter, |
| 1268 | .exit_state = sci_phy_starting_await_sata_phy_substate_exit |
| 1269 | }, |
| 1270 | [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = { |
| 1271 | .enter_state = sci_phy_starting_await_sata_speed_substate_enter, |
| 1272 | .exit_state = sci_phy_starting_await_sata_speed_substate_exit |
| 1273 | }, |
| 1274 | [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = { |
| 1275 | .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter, |
| 1276 | .exit_state = sci_phy_starting_await_sig_fis_uf_substate_exit |
| 1277 | }, |
| 1278 | [SCI_PHY_SUB_FINAL] = { |
| 1279 | .enter_state = sci_phy_starting_final_substate_enter, |
| 1280 | }, |
| 1281 | [SCI_PHY_READY] = { |
| 1282 | .enter_state = sci_phy_ready_state_enter, |
| 1283 | .exit_state = sci_phy_ready_state_exit, |
| 1284 | }, |
| 1285 | [SCI_PHY_RESETTING] = { |
| 1286 | .enter_state = sci_phy_resetting_state_enter, |
| 1287 | }, |
| 1288 | [SCI_PHY_FINAL] = { }, |
| 1289 | }; |
| 1290 | |
| 1291 | void sci_phy_construct(struct isci_phy *iphy, |
| 1292 | struct isci_port *iport, u8 phy_index) |
| 1293 | { |
| 1294 | sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL); |
| 1295 | |
| 1296 | /* Copy the rest of the input data to our locals */ |
| 1297 | iphy->owning_port = iport; |
| 1298 | iphy->phy_index = phy_index; |
| 1299 | iphy->bcn_received_while_port_unassigned = false; |
| 1300 | iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN; |
| 1301 | iphy->link_layer_registers = NULL; |
| 1302 | iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN; |
| 1303 | |
| 1304 | /* Create the SIGNATURE FIS Timeout timer for this phy */ |
| 1305 | sci_init_timer(&iphy->sata_timer, phy_sata_timeout); |
| 1306 | } |
| 1307 | |
| 1308 | void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index) |
| 1309 | { |
| 1310 | struct sci_oem_params *oem = &ihost->oem_parameters; |
| 1311 | u64 sci_sas_addr; |
| 1312 | __be64 sas_addr; |
| 1313 | |
| 1314 | sci_sas_addr = oem->phys[index].sas_address.high; |
| 1315 | sci_sas_addr <<= 32; |
| 1316 | sci_sas_addr |= oem->phys[index].sas_address.low; |
| 1317 | sas_addr = cpu_to_be64(sci_sas_addr); |
| 1318 | memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr)); |
| 1319 | |
| 1320 | iphy->sas_phy.enabled = 0; |
| 1321 | iphy->sas_phy.id = index; |
| 1322 | iphy->sas_phy.sas_addr = &iphy->sas_addr[0]; |
| 1323 | iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd; |
| 1324 | iphy->sas_phy.ha = &ihost->sas_ha; |
| 1325 | iphy->sas_phy.lldd_phy = iphy; |
| 1326 | iphy->sas_phy.enabled = 1; |
| 1327 | iphy->sas_phy.class = SAS; |
| 1328 | iphy->sas_phy.iproto = SAS_PROTOCOL_ALL; |
| 1329 | iphy->sas_phy.tproto = 0; |
| 1330 | iphy->sas_phy.type = PHY_TYPE_PHYSICAL; |
| 1331 | iphy->sas_phy.role = PHY_ROLE_INITIATOR; |
| 1332 | iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED; |
| 1333 | iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN; |
| 1334 | memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd)); |
| 1335 | } |
| 1336 | |
| 1337 | |
| 1338 | /** |
| 1339 | * isci_phy_control() - This function is one of the SAS Domain Template |
| 1340 | * functions. This is a phy management function. |
| 1341 | * @phy: This parameter specifies the sphy being controlled. |
| 1342 | * @func: This parameter specifies the phy control function being invoked. |
| 1343 | * @buf: This parameter is specific to the phy function being invoked. |
| 1344 | * |
| 1345 | * status, zero indicates success. |
| 1346 | */ |
| 1347 | int isci_phy_control(struct asd_sas_phy *sas_phy, |
| 1348 | enum phy_func func, |
| 1349 | void *buf) |
| 1350 | { |
| 1351 | int ret = 0; |
| 1352 | struct isci_phy *iphy = sas_phy->lldd_phy; |
| 1353 | struct asd_sas_port *port = sas_phy->port; |
| 1354 | struct isci_host *ihost = sas_phy->ha->lldd_ha; |
| 1355 | unsigned long flags; |
| 1356 | |
| 1357 | dev_dbg(&ihost->pdev->dev, |
| 1358 | "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n", |
| 1359 | __func__, sas_phy, func, buf, iphy, port); |
| 1360 | |
| 1361 | switch (func) { |
| 1362 | case PHY_FUNC_DISABLE: |
| 1363 | spin_lock_irqsave(&ihost->scic_lock, flags); |
| 1364 | sci_phy_stop(iphy); |
| 1365 | spin_unlock_irqrestore(&ihost->scic_lock, flags); |
| 1366 | break; |
| 1367 | |
| 1368 | case PHY_FUNC_LINK_RESET: |
| 1369 | spin_lock_irqsave(&ihost->scic_lock, flags); |
| 1370 | sci_phy_stop(iphy); |
| 1371 | sci_phy_start(iphy); |
| 1372 | spin_unlock_irqrestore(&ihost->scic_lock, flags); |
| 1373 | break; |
| 1374 | |
| 1375 | case PHY_FUNC_HARD_RESET: |
| 1376 | if (!port) |
| 1377 | return -ENODEV; |
| 1378 | |
| 1379 | ret = isci_port_perform_hard_reset(ihost, port->lldd_port, iphy); |
| 1380 | |
| 1381 | break; |
| 1382 | case PHY_FUNC_GET_EVENTS: { |
| 1383 | struct scu_link_layer_registers __iomem *r; |
| 1384 | struct sas_phy *phy = sas_phy->phy; |
| 1385 | |
| 1386 | r = iphy->link_layer_registers; |
| 1387 | phy->running_disparity_error_count = readl(&r->running_disparity_error_count); |
| 1388 | phy->loss_of_dword_sync_count = readl(&r->loss_of_sync_error_count); |
| 1389 | phy->phy_reset_problem_count = readl(&r->phy_reset_problem_count); |
| 1390 | phy->invalid_dword_count = readl(&r->invalid_dword_counter); |
| 1391 | break; |
| 1392 | } |
| 1393 | |
| 1394 | default: |
| 1395 | dev_dbg(&ihost->pdev->dev, |
| 1396 | "%s: phy %p; func %d NOT IMPLEMENTED!\n", |
| 1397 | __func__, sas_phy, func); |
| 1398 | ret = -ENOSYS; |
| 1399 | break; |
| 1400 | } |
| 1401 | return ret; |
| 1402 | } |