| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx |
| 4 | * |
| 5 | * Copyright (c) 2000 Nils Faerber |
| 6 | * |
| 7 | * Based on rtc.c by Paul Gortmaker |
| 8 | * |
| 9 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> |
| 10 | * |
| 11 | * Modifications from: |
| 12 | * CIH <cih@coventive.com> |
| 13 | * Nicolas Pitre <nico@fluxnic.net> |
| 14 | * Andrew Christian <andrew.christian@hp.com> |
| 15 | * |
| 16 | * Converted to the RTC subsystem and Driver Model |
| 17 | * by Richard Purdie <rpurdie@rpsys.net> |
| 18 | */ |
| 19 | |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/rtc.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/fs.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/string.h> |
| 29 | #include <linux/of.h> |
| 30 | #include <linux/pm.h> |
| 31 | #include <linux/bitops.h> |
| 32 | #include <linux/io.h> |
| 33 | |
| 34 | #define RTSR_HZE BIT(3) /* HZ interrupt enable */ |
| 35 | #define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */ |
| 36 | #define RTSR_HZ BIT(1) /* HZ rising-edge detected */ |
| 37 | #define RTSR_AL BIT(0) /* RTC alarm detected */ |
| 38 | |
| 39 | #include "rtc-sa1100.h" |
| 40 | |
| 41 | #define RTC_DEF_DIVIDER (32768 - 1) |
| 42 | #define RTC_DEF_TRIM 0 |
| 43 | #define RTC_FREQ 1024 |
| 44 | |
| 45 | |
| 46 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
| 47 | { |
| 48 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
| 49 | struct rtc_device *rtc = info->rtc; |
| 50 | unsigned int rtsr; |
| 51 | unsigned long events = 0; |
| 52 | |
| 53 | spin_lock(&info->lock); |
| 54 | |
| 55 | rtsr = readl_relaxed(info->rtsr); |
| 56 | /* clear interrupt sources */ |
| 57 | writel_relaxed(0, info->rtsr); |
| 58 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
| 59 | * See also the comments in sa1100_rtc_probe(). */ |
| 60 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { |
| 61 | /* This is the original code, before there was the if test |
| 62 | * above. This code does not clear interrupts that were not |
| 63 | * enabled. */ |
| 64 | writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); |
| 65 | } else { |
| 66 | /* For some reason, it is possible to enter this routine |
| 67 | * without interruptions enabled, it has been tested with |
| 68 | * several units (Bug in SA11xx chip?). |
| 69 | * |
| 70 | * This situation leads to an infinite "loop" of interrupt |
| 71 | * routine calling and as a result the processor seems to |
| 72 | * lock on its first call to open(). */ |
| 73 | writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); |
| 74 | } |
| 75 | |
| 76 | /* clear alarm interrupt if it has occurred */ |
| 77 | if (rtsr & RTSR_AL) |
| 78 | rtsr &= ~RTSR_ALE; |
| 79 | writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); |
| 80 | |
| 81 | /* update irq data & counter */ |
| 82 | if (rtsr & RTSR_AL) |
| 83 | events |= RTC_AF | RTC_IRQF; |
| 84 | if (rtsr & RTSR_HZ) |
| 85 | events |= RTC_UF | RTC_IRQF; |
| 86 | |
| 87 | rtc_update_irq(rtc, 1, events); |
| 88 | |
| 89 | spin_unlock(&info->lock); |
| 90 | |
| 91 | return IRQ_HANDLED; |
| 92 | } |
| 93 | |
| 94 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
| 95 | { |
| 96 | u32 rtsr; |
| 97 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 98 | |
| 99 | spin_lock_irq(&info->lock); |
| 100 | rtsr = readl_relaxed(info->rtsr); |
| 101 | if (enabled) |
| 102 | rtsr |= RTSR_ALE; |
| 103 | else |
| 104 | rtsr &= ~RTSR_ALE; |
| 105 | writel_relaxed(rtsr, info->rtsr); |
| 106 | spin_unlock_irq(&info->lock); |
| 107 | return 0; |
| 108 | } |
| 109 | |
| 110 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
| 111 | { |
| 112 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 113 | |
| 114 | rtc_time64_to_tm(readl_relaxed(info->rcnr), tm); |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) |
| 119 | { |
| 120 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 121 | |
| 122 | writel_relaxed(rtc_tm_to_time64(tm), info->rcnr); |
| 123 | |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
| 128 | { |
| 129 | u32 rtsr; |
| 130 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 131 | |
| 132 | rtsr = readl_relaxed(info->rtsr); |
| 133 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
| 134 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
| 139 | { |
| 140 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 141 | |
| 142 | spin_lock_irq(&info->lock); |
| 143 | writel_relaxed(readl_relaxed(info->rtsr) & |
| 144 | (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr); |
| 145 | writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar); |
| 146 | if (alrm->enabled) |
| 147 | writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); |
| 148 | else |
| 149 | writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); |
| 150 | spin_unlock_irq(&info->lock); |
| 151 | |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) |
| 156 | { |
| 157 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 158 | |
| 159 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr)); |
| 160 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr)); |
| 161 | |
| 162 | return 0; |
| 163 | } |
| 164 | |
| 165 | static const struct rtc_class_ops sa1100_rtc_ops = { |
| 166 | .read_time = sa1100_rtc_read_time, |
| 167 | .set_time = sa1100_rtc_set_time, |
| 168 | .read_alarm = sa1100_rtc_read_alarm, |
| 169 | .set_alarm = sa1100_rtc_set_alarm, |
| 170 | .proc = sa1100_rtc_proc, |
| 171 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
| 172 | }; |
| 173 | |
| 174 | int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info) |
| 175 | { |
| 176 | int ret; |
| 177 | |
| 178 | spin_lock_init(&info->lock); |
| 179 | |
| 180 | info->clk = devm_clk_get(&pdev->dev, NULL); |
| 181 | if (IS_ERR(info->clk)) { |
| 182 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); |
| 183 | return PTR_ERR(info->clk); |
| 184 | } |
| 185 | |
| 186 | ret = clk_prepare_enable(info->clk); |
| 187 | if (ret) |
| 188 | return ret; |
| 189 | /* |
| 190 | * According to the manual we should be able to let RTTR be zero |
| 191 | * and then a default diviser for a 32.768KHz clock is used. |
| 192 | * Apparently this doesn't work, at least for my SA1110 rev 5. |
| 193 | * If the clock divider is uninitialized then reset it to the |
| 194 | * default value to get the 1Hz clock. |
| 195 | */ |
| 196 | if (readl_relaxed(info->rttr) == 0) { |
| 197 | writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr); |
| 198 | dev_warn(&pdev->dev, "warning: " |
| 199 | "initializing default clock divider/trim value\n"); |
| 200 | /* The current RTC value probably doesn't make sense either */ |
| 201 | writel_relaxed(0, info->rcnr); |
| 202 | } |
| 203 | |
| 204 | info->rtc->ops = &sa1100_rtc_ops; |
| 205 | info->rtc->max_user_freq = RTC_FREQ; |
| 206 | info->rtc->range_max = U32_MAX; |
| 207 | |
| 208 | ret = rtc_register_device(info->rtc); |
| 209 | if (ret) { |
| 210 | clk_disable_unprepare(info->clk); |
| 211 | return ret; |
| 212 | } |
| 213 | |
| 214 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
| 215 | * See also the comments in sa1100_rtc_interrupt(). |
| 216 | * |
| 217 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an |
| 218 | * interrupt pending, even though interrupts were never enabled. |
| 219 | * In this case, this bit it must be reset before enabling |
| 220 | * interruptions to avoid a nonexistent interrupt to occur. |
| 221 | * |
| 222 | * In principle, the same problem would apply to bit 0, although it has |
| 223 | * never been observed to happen. |
| 224 | * |
| 225 | * This issue is addressed both here and in sa1100_rtc_interrupt(). |
| 226 | * If the issue is not addressed here, in the times when the processor |
| 227 | * wakes up with the bit set there will be one spurious interrupt. |
| 228 | * |
| 229 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the |
| 230 | * safe side, once the condition that lead to this strange |
| 231 | * initialization is unknown and could in principle happen during |
| 232 | * normal processing. |
| 233 | * |
| 234 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to |
| 235 | * the corresponding bits in RTSR. */ |
| 236 | writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); |
| 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | EXPORT_SYMBOL_GPL(sa1100_rtc_init); |
| 241 | |
| 242 | static int sa1100_rtc_probe(struct platform_device *pdev) |
| 243 | { |
| 244 | struct sa1100_rtc *info; |
| 245 | void __iomem *base; |
| 246 | int irq_1hz, irq_alarm; |
| 247 | int ret; |
| 248 | |
| 249 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); |
| 250 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); |
| 251 | if (irq_1hz < 0 || irq_alarm < 0) |
| 252 | return -ENODEV; |
| 253 | |
| 254 | info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL); |
| 255 | if (!info) |
| 256 | return -ENOMEM; |
| 257 | info->irq_1hz = irq_1hz; |
| 258 | info->irq_alarm = irq_alarm; |
| 259 | |
| 260 | info->rtc = devm_rtc_allocate_device(&pdev->dev); |
| 261 | if (IS_ERR(info->rtc)) |
| 262 | return PTR_ERR(info->rtc); |
| 263 | |
| 264 | ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0, |
| 265 | "rtc 1Hz", &pdev->dev); |
| 266 | if (ret) { |
| 267 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz); |
| 268 | return ret; |
| 269 | } |
| 270 | ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0, |
| 271 | "rtc Alrm", &pdev->dev); |
| 272 | if (ret) { |
| 273 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm); |
| 274 | return ret; |
| 275 | } |
| 276 | |
| 277 | base = devm_platform_ioremap_resource(pdev, 0); |
| 278 | if (IS_ERR(base)) |
| 279 | return PTR_ERR(base); |
| 280 | |
| 281 | if (IS_ENABLED(CONFIG_ARCH_SA1100) || |
| 282 | of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) { |
| 283 | info->rcnr = base + 0x04; |
| 284 | info->rtsr = base + 0x10; |
| 285 | info->rtar = base + 0x00; |
| 286 | info->rttr = base + 0x08; |
| 287 | } else { |
| 288 | info->rcnr = base + 0x0; |
| 289 | info->rtsr = base + 0x8; |
| 290 | info->rtar = base + 0x4; |
| 291 | info->rttr = base + 0xc; |
| 292 | } |
| 293 | |
| 294 | platform_set_drvdata(pdev, info); |
| 295 | device_init_wakeup(&pdev->dev, 1); |
| 296 | |
| 297 | return sa1100_rtc_init(pdev, info); |
| 298 | } |
| 299 | |
| 300 | static int sa1100_rtc_remove(struct platform_device *pdev) |
| 301 | { |
| 302 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
| 303 | |
| 304 | if (info) { |
| 305 | spin_lock_irq(&info->lock); |
| 306 | writel_relaxed(0, info->rtsr); |
| 307 | spin_unlock_irq(&info->lock); |
| 308 | clk_disable_unprepare(info->clk); |
| 309 | } |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | #ifdef CONFIG_PM_SLEEP |
| 315 | static int sa1100_rtc_suspend(struct device *dev) |
| 316 | { |
| 317 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 318 | if (device_may_wakeup(dev)) |
| 319 | enable_irq_wake(info->irq_alarm); |
| 320 | return 0; |
| 321 | } |
| 322 | |
| 323 | static int sa1100_rtc_resume(struct device *dev) |
| 324 | { |
| 325 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
| 326 | if (device_may_wakeup(dev)) |
| 327 | disable_irq_wake(info->irq_alarm); |
| 328 | return 0; |
| 329 | } |
| 330 | #endif |
| 331 | |
| 332 | static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend, |
| 333 | sa1100_rtc_resume); |
| 334 | |
| 335 | #ifdef CONFIG_OF |
| 336 | static const struct of_device_id sa1100_rtc_dt_ids[] = { |
| 337 | { .compatible = "mrvl,sa1100-rtc", }, |
| 338 | { .compatible = "mrvl,mmp-rtc", }, |
| 339 | {} |
| 340 | }; |
| 341 | MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids); |
| 342 | #endif |
| 343 | |
| 344 | static struct platform_driver sa1100_rtc_driver = { |
| 345 | .probe = sa1100_rtc_probe, |
| 346 | .remove = sa1100_rtc_remove, |
| 347 | .driver = { |
| 348 | .name = "sa1100-rtc", |
| 349 | .pm = &sa1100_rtc_pm_ops, |
| 350 | .of_match_table = of_match_ptr(sa1100_rtc_dt_ids), |
| 351 | }, |
| 352 | }; |
| 353 | |
| 354 | module_platform_driver(sa1100_rtc_driver); |
| 355 | |
| 356 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); |
| 357 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); |
| 358 | MODULE_LICENSE("GPL"); |
| 359 | MODULE_ALIAS("platform:sa1100-rtc"); |