| 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // |
| 3 | // RTC driver for Maxim MAX77686 and MAX77802 |
| 4 | // |
| 5 | // Copyright (C) 2012 Samsung Electronics Co.Ltd |
| 6 | // |
| 7 | // based on rtc-max8997.c |
| 8 | |
| 9 | #include <linux/i2c.h> |
| 10 | #include <linux/slab.h> |
| 11 | #include <linux/rtc.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/mutex.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/mfd/max77686-private.h> |
| 17 | #include <linux/irqdomain.h> |
| 18 | #include <linux/regmap.h> |
| 19 | |
| 20 | #define MAX77686_I2C_ADDR_RTC (0x0C >> 1) |
| 21 | #define MAX77620_I2C_ADDR_RTC 0x68 |
| 22 | #define MAX77714_I2C_ADDR_RTC 0x48 |
| 23 | #define MAX77686_INVALID_I2C_ADDR (-1) |
| 24 | |
| 25 | /* Define non existing register */ |
| 26 | #define MAX77686_INVALID_REG (-1) |
| 27 | |
| 28 | /* RTC Control Register */ |
| 29 | #define BCD_EN_SHIFT 0 |
| 30 | #define BCD_EN_MASK BIT(BCD_EN_SHIFT) |
| 31 | #define MODEL24_SHIFT 1 |
| 32 | #define MODEL24_MASK BIT(MODEL24_SHIFT) |
| 33 | /* RTC Update Register1 */ |
| 34 | #define RTC_UDR_SHIFT 0 |
| 35 | #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT) |
| 36 | #define RTC_RBUDR_SHIFT 4 |
| 37 | #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT) |
| 38 | /* RTC Alarm Enable */ |
| 39 | #define ALARM_ENABLE_SHIFT 7 |
| 40 | #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT) |
| 41 | |
| 42 | #define REG_RTC_NONE 0xdeadbeef |
| 43 | |
| 44 | /* |
| 45 | * MAX77802 has separate register (RTCAE1) for alarm enable instead |
| 46 | * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE} |
| 47 | * as in done in MAX77686. |
| 48 | */ |
| 49 | #define MAX77802_ALARM_ENABLE_VALUE 0x77 |
| 50 | |
| 51 | enum { |
| 52 | RTC_SEC = 0, |
| 53 | RTC_MIN, |
| 54 | RTC_HOUR, |
| 55 | RTC_WEEKDAY, |
| 56 | RTC_MONTH, |
| 57 | RTC_YEAR, |
| 58 | RTC_MONTHDAY, |
| 59 | RTC_NR_TIME |
| 60 | }; |
| 61 | |
| 62 | /** |
| 63 | * struct max77686_rtc_driver_data - model-specific configuration |
| 64 | * @delay: Minimum usecs needed for a RTC update |
| 65 | * @mask: Mask used to read RTC registers value |
| 66 | * @map: Registers offset to I2C addresses map |
| 67 | * @alarm_enable_reg: Has a separate alarm enable register? |
| 68 | * @rtc_i2c_addr: I2C address for RTC block |
| 69 | * @rtc_irq_from_platform: RTC interrupt via platform resource |
| 70 | * @alarm_pending_status_reg: Pending alarm status register |
| 71 | * @rtc_irq_chip: RTC IRQ CHIP for regmap |
| 72 | * @regmap_config: regmap configuration for the chip |
| 73 | */ |
| 74 | struct max77686_rtc_driver_data { |
| 75 | unsigned long delay; |
| 76 | u8 mask; |
| 77 | const unsigned int *map; |
| 78 | bool alarm_enable_reg; |
| 79 | int rtc_i2c_addr; |
| 80 | bool rtc_irq_from_platform; |
| 81 | int alarm_pending_status_reg; |
| 82 | const struct regmap_irq_chip *rtc_irq_chip; |
| 83 | const struct regmap_config *regmap_config; |
| 84 | }; |
| 85 | |
| 86 | struct max77686_rtc_info { |
| 87 | struct device *dev; |
| 88 | struct i2c_client *rtc; |
| 89 | struct rtc_device *rtc_dev; |
| 90 | struct mutex lock; |
| 91 | |
| 92 | struct regmap *regmap; |
| 93 | struct regmap *rtc_regmap; |
| 94 | |
| 95 | const struct max77686_rtc_driver_data *drv_data; |
| 96 | struct regmap_irq_chip_data *rtc_irq_data; |
| 97 | |
| 98 | int rtc_irq; |
| 99 | int virq; |
| 100 | }; |
| 101 | |
| 102 | enum MAX77686_RTC_OP { |
| 103 | MAX77686_RTC_WRITE, |
| 104 | MAX77686_RTC_READ, |
| 105 | }; |
| 106 | |
| 107 | /* These are not registers but just offsets that are mapped to addresses */ |
| 108 | enum max77686_rtc_reg_offset { |
| 109 | REG_RTC_CONTROLM = 0, |
| 110 | REG_RTC_CONTROL, |
| 111 | REG_RTC_UPDATE0, |
| 112 | REG_WTSR_SMPL_CNTL, |
| 113 | REG_RTC_SEC, |
| 114 | REG_RTC_MIN, |
| 115 | REG_RTC_HOUR, |
| 116 | REG_RTC_WEEKDAY, |
| 117 | REG_RTC_MONTH, |
| 118 | REG_RTC_YEAR, |
| 119 | REG_RTC_MONTHDAY, |
| 120 | REG_ALARM1_SEC, |
| 121 | REG_ALARM1_MIN, |
| 122 | REG_ALARM1_HOUR, |
| 123 | REG_ALARM1_WEEKDAY, |
| 124 | REG_ALARM1_MONTH, |
| 125 | REG_ALARM1_YEAR, |
| 126 | REG_ALARM1_DATE, |
| 127 | REG_ALARM2_SEC, |
| 128 | REG_ALARM2_MIN, |
| 129 | REG_ALARM2_HOUR, |
| 130 | REG_ALARM2_WEEKDAY, |
| 131 | REG_ALARM2_MONTH, |
| 132 | REG_ALARM2_YEAR, |
| 133 | REG_ALARM2_DATE, |
| 134 | REG_RTC_AE1, |
| 135 | REG_RTC_END, |
| 136 | }; |
| 137 | |
| 138 | /* Maps RTC registers offset to the MAX77686 register addresses */ |
| 139 | static const unsigned int max77686_map[REG_RTC_END] = { |
| 140 | [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM, |
| 141 | [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL, |
| 142 | [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0, |
| 143 | [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL, |
| 144 | [REG_RTC_SEC] = MAX77686_RTC_SEC, |
| 145 | [REG_RTC_MIN] = MAX77686_RTC_MIN, |
| 146 | [REG_RTC_HOUR] = MAX77686_RTC_HOUR, |
| 147 | [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY, |
| 148 | [REG_RTC_MONTH] = MAX77686_RTC_MONTH, |
| 149 | [REG_RTC_YEAR] = MAX77686_RTC_YEAR, |
| 150 | [REG_RTC_MONTHDAY] = MAX77686_RTC_MONTHDAY, |
| 151 | [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC, |
| 152 | [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN, |
| 153 | [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR, |
| 154 | [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY, |
| 155 | [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH, |
| 156 | [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR, |
| 157 | [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE, |
| 158 | [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC, |
| 159 | [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN, |
| 160 | [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR, |
| 161 | [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY, |
| 162 | [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH, |
| 163 | [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR, |
| 164 | [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE, |
| 165 | [REG_RTC_AE1] = REG_RTC_NONE, |
| 166 | }; |
| 167 | |
| 168 | static const struct regmap_irq max77686_rtc_irqs[] = { |
| 169 | /* RTC interrupts */ |
| 170 | REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK), |
| 171 | REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK), |
| 172 | REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK), |
| 173 | REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK), |
| 174 | REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK), |
| 175 | REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK), |
| 176 | }; |
| 177 | |
| 178 | static const struct regmap_irq_chip max77686_rtc_irq_chip = { |
| 179 | .name = "max77686-rtc", |
| 180 | .status_base = MAX77686_RTC_INT, |
| 181 | .mask_base = MAX77686_RTC_INTM, |
| 182 | .num_regs = 1, |
| 183 | .irqs = max77686_rtc_irqs, |
| 184 | .num_irqs = ARRAY_SIZE(max77686_rtc_irqs), |
| 185 | }; |
| 186 | |
| 187 | static const struct regmap_config max77686_rtc_regmap_config = { |
| 188 | .reg_bits = 8, |
| 189 | .val_bits = 8, |
| 190 | }; |
| 191 | |
| 192 | static const struct max77686_rtc_driver_data max77686_drv_data = { |
| 193 | .delay = 16000, |
| 194 | .mask = 0x7f, |
| 195 | .map = max77686_map, |
| 196 | .alarm_enable_reg = false, |
| 197 | .rtc_irq_from_platform = false, |
| 198 | .alarm_pending_status_reg = MAX77686_REG_STATUS2, |
| 199 | .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC, |
| 200 | .rtc_irq_chip = &max77686_rtc_irq_chip, |
| 201 | .regmap_config = &max77686_rtc_regmap_config, |
| 202 | }; |
| 203 | |
| 204 | static const struct regmap_irq_chip max77714_rtc_irq_chip = { |
| 205 | .name = "max77714-rtc", |
| 206 | .status_base = MAX77686_RTC_INT, |
| 207 | .mask_base = MAX77686_RTC_INTM, |
| 208 | .num_regs = 1, |
| 209 | .irqs = max77686_rtc_irqs, |
| 210 | .num_irqs = ARRAY_SIZE(max77686_rtc_irqs) - 1, /* no WTSR on 77714 */ |
| 211 | }; |
| 212 | |
| 213 | static const struct max77686_rtc_driver_data max77714_drv_data = { |
| 214 | .delay = 16000, |
| 215 | .mask = 0x7f, |
| 216 | .map = max77686_map, |
| 217 | .alarm_enable_reg = false, |
| 218 | .rtc_irq_from_platform = false, |
| 219 | /* On MAX77714 RTCA1 is BIT 1 of RTCINT (0x00). Not supported by this driver. */ |
| 220 | .alarm_pending_status_reg = MAX77686_INVALID_REG, |
| 221 | .rtc_i2c_addr = MAX77714_I2C_ADDR_RTC, |
| 222 | .rtc_irq_chip = &max77714_rtc_irq_chip, |
| 223 | .regmap_config = &max77686_rtc_regmap_config, |
| 224 | }; |
| 225 | |
| 226 | static const struct regmap_config max77620_rtc_regmap_config = { |
| 227 | .reg_bits = 8, |
| 228 | .val_bits = 8, |
| 229 | .use_single_write = true, |
| 230 | }; |
| 231 | |
| 232 | static const struct max77686_rtc_driver_data max77620_drv_data = { |
| 233 | .delay = 16000, |
| 234 | .mask = 0x7f, |
| 235 | .map = max77686_map, |
| 236 | .alarm_enable_reg = false, |
| 237 | .rtc_irq_from_platform = true, |
| 238 | .alarm_pending_status_reg = MAX77686_INVALID_REG, |
| 239 | .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC, |
| 240 | .rtc_irq_chip = &max77686_rtc_irq_chip, |
| 241 | .regmap_config = &max77620_rtc_regmap_config, |
| 242 | }; |
| 243 | |
| 244 | static const unsigned int max77802_map[REG_RTC_END] = { |
| 245 | [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM, |
| 246 | [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL, |
| 247 | [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0, |
| 248 | [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL, |
| 249 | [REG_RTC_SEC] = MAX77802_RTC_SEC, |
| 250 | [REG_RTC_MIN] = MAX77802_RTC_MIN, |
| 251 | [REG_RTC_HOUR] = MAX77802_RTC_HOUR, |
| 252 | [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY, |
| 253 | [REG_RTC_MONTH] = MAX77802_RTC_MONTH, |
| 254 | [REG_RTC_YEAR] = MAX77802_RTC_YEAR, |
| 255 | [REG_RTC_MONTHDAY] = MAX77802_RTC_MONTHDAY, |
| 256 | [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC, |
| 257 | [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN, |
| 258 | [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR, |
| 259 | [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY, |
| 260 | [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH, |
| 261 | [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR, |
| 262 | [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE, |
| 263 | [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC, |
| 264 | [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN, |
| 265 | [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR, |
| 266 | [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY, |
| 267 | [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH, |
| 268 | [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR, |
| 269 | [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE, |
| 270 | [REG_RTC_AE1] = MAX77802_RTC_AE1, |
| 271 | }; |
| 272 | |
| 273 | static const struct regmap_irq_chip max77802_rtc_irq_chip = { |
| 274 | .name = "max77802-rtc", |
| 275 | .status_base = MAX77802_RTC_INT, |
| 276 | .mask_base = MAX77802_RTC_INTM, |
| 277 | .num_regs = 1, |
| 278 | .irqs = max77686_rtc_irqs, /* same masks as 77686 */ |
| 279 | .num_irqs = ARRAY_SIZE(max77686_rtc_irqs), |
| 280 | }; |
| 281 | |
| 282 | static const struct max77686_rtc_driver_data max77802_drv_data = { |
| 283 | .delay = 200, |
| 284 | .mask = 0xff, |
| 285 | .map = max77802_map, |
| 286 | .alarm_enable_reg = true, |
| 287 | .rtc_irq_from_platform = false, |
| 288 | .alarm_pending_status_reg = MAX77686_REG_STATUS2, |
| 289 | .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR, |
| 290 | .rtc_irq_chip = &max77802_rtc_irq_chip, |
| 291 | }; |
| 292 | |
| 293 | static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm, |
| 294 | struct max77686_rtc_info *info) |
| 295 | { |
| 296 | u8 mask = info->drv_data->mask; |
| 297 | |
| 298 | tm->tm_sec = data[RTC_SEC] & mask; |
| 299 | tm->tm_min = data[RTC_MIN] & mask; |
| 300 | tm->tm_hour = data[RTC_HOUR] & 0x1f; |
| 301 | |
| 302 | /* Only a single bit is set in data[], so fls() would be equivalent */ |
| 303 | tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1; |
| 304 | tm->tm_mday = data[RTC_MONTHDAY] & 0x1f; |
| 305 | tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; |
| 306 | tm->tm_year = data[RTC_YEAR] & mask; |
| 307 | tm->tm_yday = 0; |
| 308 | tm->tm_isdst = 0; |
| 309 | |
| 310 | /* |
| 311 | * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the |
| 312 | * year values are just 0..99 so add 100 to support up to 2099. |
| 313 | */ |
| 314 | if (!info->drv_data->alarm_enable_reg) |
| 315 | tm->tm_year += 100; |
| 316 | } |
| 317 | |
| 318 | static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data, |
| 319 | struct max77686_rtc_info *info) |
| 320 | { |
| 321 | data[RTC_SEC] = tm->tm_sec; |
| 322 | data[RTC_MIN] = tm->tm_min; |
| 323 | data[RTC_HOUR] = tm->tm_hour; |
| 324 | data[RTC_WEEKDAY] = 1 << tm->tm_wday; |
| 325 | data[RTC_MONTHDAY] = tm->tm_mday; |
| 326 | data[RTC_MONTH] = tm->tm_mon + 1; |
| 327 | |
| 328 | if (info->drv_data->alarm_enable_reg) { |
| 329 | data[RTC_YEAR] = tm->tm_year; |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0; |
| 334 | |
| 335 | if (tm->tm_year < 100) { |
| 336 | dev_err(info->dev, "RTC cannot handle the year %d.\n", |
| 337 | 1900 + tm->tm_year); |
| 338 | return -EINVAL; |
| 339 | } |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | static int max77686_rtc_update(struct max77686_rtc_info *info, |
| 345 | enum MAX77686_RTC_OP op) |
| 346 | { |
| 347 | int ret; |
| 348 | unsigned int data; |
| 349 | unsigned long delay = info->drv_data->delay; |
| 350 | |
| 351 | if (op == MAX77686_RTC_WRITE) |
| 352 | data = 1 << RTC_UDR_SHIFT; |
| 353 | else |
| 354 | data = 1 << RTC_RBUDR_SHIFT; |
| 355 | |
| 356 | ret = regmap_update_bits(info->rtc_regmap, |
| 357 | info->drv_data->map[REG_RTC_UPDATE0], |
| 358 | data, data); |
| 359 | if (ret < 0) |
| 360 | dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n", |
| 361 | ret, data); |
| 362 | else { |
| 363 | /* Minimum delay required before RTC update. */ |
| 364 | usleep_range(delay, delay * 2); |
| 365 | } |
| 366 | |
| 367 | return ret; |
| 368 | } |
| 369 | |
| 370 | static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm) |
| 371 | { |
| 372 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 373 | u8 data[RTC_NR_TIME]; |
| 374 | int ret; |
| 375 | |
| 376 | mutex_lock(&info->lock); |
| 377 | |
| 378 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); |
| 379 | if (ret < 0) |
| 380 | goto out; |
| 381 | |
| 382 | ret = regmap_bulk_read(info->rtc_regmap, |
| 383 | info->drv_data->map[REG_RTC_SEC], |
| 384 | data, ARRAY_SIZE(data)); |
| 385 | if (ret < 0) { |
| 386 | dev_err(info->dev, "Fail to read time reg(%d)\n", ret); |
| 387 | goto out; |
| 388 | } |
| 389 | |
| 390 | max77686_rtc_data_to_tm(data, tm, info); |
| 391 | |
| 392 | out: |
| 393 | mutex_unlock(&info->lock); |
| 394 | return ret; |
| 395 | } |
| 396 | |
| 397 | static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm) |
| 398 | { |
| 399 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 400 | u8 data[RTC_NR_TIME]; |
| 401 | int ret; |
| 402 | |
| 403 | ret = max77686_rtc_tm_to_data(tm, data, info); |
| 404 | if (ret < 0) |
| 405 | return ret; |
| 406 | |
| 407 | mutex_lock(&info->lock); |
| 408 | |
| 409 | ret = regmap_bulk_write(info->rtc_regmap, |
| 410 | info->drv_data->map[REG_RTC_SEC], |
| 411 | data, ARRAY_SIZE(data)); |
| 412 | if (ret < 0) { |
| 413 | dev_err(info->dev, "Fail to write time reg(%d)\n", ret); |
| 414 | goto out; |
| 415 | } |
| 416 | |
| 417 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); |
| 418 | |
| 419 | out: |
| 420 | mutex_unlock(&info->lock); |
| 421 | return ret; |
| 422 | } |
| 423 | |
| 424 | static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
| 425 | { |
| 426 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 427 | u8 data[RTC_NR_TIME]; |
| 428 | unsigned int val; |
| 429 | const unsigned int *map = info->drv_data->map; |
| 430 | int i, ret; |
| 431 | |
| 432 | mutex_lock(&info->lock); |
| 433 | |
| 434 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); |
| 435 | if (ret < 0) |
| 436 | goto out; |
| 437 | |
| 438 | ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC], |
| 439 | data, ARRAY_SIZE(data)); |
| 440 | if (ret < 0) { |
| 441 | dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret); |
| 442 | goto out; |
| 443 | } |
| 444 | |
| 445 | max77686_rtc_data_to_tm(data, &alrm->time, info); |
| 446 | |
| 447 | alrm->enabled = 0; |
| 448 | |
| 449 | if (info->drv_data->alarm_enable_reg) { |
| 450 | if (map[REG_RTC_AE1] == REG_RTC_NONE) { |
| 451 | ret = -EINVAL; |
| 452 | dev_err(info->dev, |
| 453 | "alarm enable register not set(%d)\n", ret); |
| 454 | goto out; |
| 455 | } |
| 456 | |
| 457 | ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val); |
| 458 | if (ret < 0) { |
| 459 | dev_err(info->dev, |
| 460 | "fail to read alarm enable(%d)\n", ret); |
| 461 | goto out; |
| 462 | } |
| 463 | |
| 464 | if (val) |
| 465 | alrm->enabled = 1; |
| 466 | } else { |
| 467 | for (i = 0; i < ARRAY_SIZE(data); i++) { |
| 468 | if (data[i] & ALARM_ENABLE_MASK) { |
| 469 | alrm->enabled = 1; |
| 470 | break; |
| 471 | } |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | alrm->pending = 0; |
| 476 | |
| 477 | if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG) |
| 478 | goto out; |
| 479 | |
| 480 | ret = regmap_read(info->regmap, |
| 481 | info->drv_data->alarm_pending_status_reg, &val); |
| 482 | if (ret < 0) { |
| 483 | dev_err(info->dev, |
| 484 | "Fail to read alarm pending status reg(%d)\n", ret); |
| 485 | goto out; |
| 486 | } |
| 487 | |
| 488 | if (val & (1 << 4)) /* RTCA1 */ |
| 489 | alrm->pending = 1; |
| 490 | |
| 491 | out: |
| 492 | mutex_unlock(&info->lock); |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info) |
| 497 | { |
| 498 | u8 data[RTC_NR_TIME]; |
| 499 | int ret, i; |
| 500 | struct rtc_time tm; |
| 501 | const unsigned int *map = info->drv_data->map; |
| 502 | |
| 503 | if (!mutex_is_locked(&info->lock)) |
| 504 | dev_warn(info->dev, "%s: should have mutex locked\n", __func__); |
| 505 | |
| 506 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); |
| 507 | if (ret < 0) |
| 508 | goto out; |
| 509 | |
| 510 | if (info->drv_data->alarm_enable_reg) { |
| 511 | if (map[REG_RTC_AE1] == REG_RTC_NONE) { |
| 512 | ret = -EINVAL; |
| 513 | dev_err(info->dev, |
| 514 | "alarm enable register not set(%d)\n", ret); |
| 515 | goto out; |
| 516 | } |
| 517 | |
| 518 | ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0); |
| 519 | } else { |
| 520 | ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC], |
| 521 | data, ARRAY_SIZE(data)); |
| 522 | if (ret < 0) { |
| 523 | dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret); |
| 524 | goto out; |
| 525 | } |
| 526 | |
| 527 | max77686_rtc_data_to_tm(data, &tm, info); |
| 528 | |
| 529 | for (i = 0; i < ARRAY_SIZE(data); i++) |
| 530 | data[i] &= ~ALARM_ENABLE_MASK; |
| 531 | |
| 532 | ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC], |
| 533 | data, ARRAY_SIZE(data)); |
| 534 | } |
| 535 | |
| 536 | if (ret < 0) { |
| 537 | dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret); |
| 538 | goto out; |
| 539 | } |
| 540 | |
| 541 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); |
| 542 | out: |
| 543 | return ret; |
| 544 | } |
| 545 | |
| 546 | static int max77686_rtc_start_alarm(struct max77686_rtc_info *info) |
| 547 | { |
| 548 | u8 data[RTC_NR_TIME]; |
| 549 | int ret; |
| 550 | struct rtc_time tm; |
| 551 | const unsigned int *map = info->drv_data->map; |
| 552 | |
| 553 | if (!mutex_is_locked(&info->lock)) |
| 554 | dev_warn(info->dev, "%s: should have mutex locked\n", __func__); |
| 555 | |
| 556 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); |
| 557 | if (ret < 0) |
| 558 | goto out; |
| 559 | |
| 560 | if (info->drv_data->alarm_enable_reg) { |
| 561 | ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], |
| 562 | MAX77802_ALARM_ENABLE_VALUE); |
| 563 | } else { |
| 564 | ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC], |
| 565 | data, ARRAY_SIZE(data)); |
| 566 | if (ret < 0) { |
| 567 | dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret); |
| 568 | goto out; |
| 569 | } |
| 570 | |
| 571 | max77686_rtc_data_to_tm(data, &tm, info); |
| 572 | |
| 573 | data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT); |
| 574 | data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT); |
| 575 | data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT); |
| 576 | data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK; |
| 577 | if (data[RTC_MONTH] & 0xf) |
| 578 | data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT); |
| 579 | if (data[RTC_YEAR] & info->drv_data->mask) |
| 580 | data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT); |
| 581 | if (data[RTC_MONTHDAY] & 0x1f) |
| 582 | data[RTC_MONTHDAY] |= (1 << ALARM_ENABLE_SHIFT); |
| 583 | |
| 584 | ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC], |
| 585 | data, ARRAY_SIZE(data)); |
| 586 | } |
| 587 | |
| 588 | if (ret < 0) { |
| 589 | dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret); |
| 590 | goto out; |
| 591 | } |
| 592 | |
| 593 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); |
| 594 | out: |
| 595 | return ret; |
| 596 | } |
| 597 | |
| 598 | static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
| 599 | { |
| 600 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 601 | u8 data[RTC_NR_TIME]; |
| 602 | int ret; |
| 603 | |
| 604 | ret = max77686_rtc_tm_to_data(&alrm->time, data, info); |
| 605 | if (ret < 0) |
| 606 | return ret; |
| 607 | |
| 608 | mutex_lock(&info->lock); |
| 609 | |
| 610 | ret = max77686_rtc_stop_alarm(info); |
| 611 | if (ret < 0) |
| 612 | goto out; |
| 613 | |
| 614 | ret = regmap_bulk_write(info->rtc_regmap, |
| 615 | info->drv_data->map[REG_ALARM1_SEC], |
| 616 | data, ARRAY_SIZE(data)); |
| 617 | |
| 618 | if (ret < 0) { |
| 619 | dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret); |
| 620 | goto out; |
| 621 | } |
| 622 | |
| 623 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); |
| 624 | if (ret < 0) |
| 625 | goto out; |
| 626 | |
| 627 | if (alrm->enabled) |
| 628 | ret = max77686_rtc_start_alarm(info); |
| 629 | out: |
| 630 | mutex_unlock(&info->lock); |
| 631 | return ret; |
| 632 | } |
| 633 | |
| 634 | static int max77686_rtc_alarm_irq_enable(struct device *dev, |
| 635 | unsigned int enabled) |
| 636 | { |
| 637 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 638 | int ret; |
| 639 | |
| 640 | mutex_lock(&info->lock); |
| 641 | if (enabled) |
| 642 | ret = max77686_rtc_start_alarm(info); |
| 643 | else |
| 644 | ret = max77686_rtc_stop_alarm(info); |
| 645 | mutex_unlock(&info->lock); |
| 646 | |
| 647 | return ret; |
| 648 | } |
| 649 | |
| 650 | static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data) |
| 651 | { |
| 652 | struct max77686_rtc_info *info = data; |
| 653 | |
| 654 | dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq); |
| 655 | |
| 656 | rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); |
| 657 | |
| 658 | return IRQ_HANDLED; |
| 659 | } |
| 660 | |
| 661 | static const struct rtc_class_ops max77686_rtc_ops = { |
| 662 | .read_time = max77686_rtc_read_time, |
| 663 | .set_time = max77686_rtc_set_time, |
| 664 | .read_alarm = max77686_rtc_read_alarm, |
| 665 | .set_alarm = max77686_rtc_set_alarm, |
| 666 | .alarm_irq_enable = max77686_rtc_alarm_irq_enable, |
| 667 | }; |
| 668 | |
| 669 | static int max77686_rtc_init_reg(struct max77686_rtc_info *info) |
| 670 | { |
| 671 | u8 data[2]; |
| 672 | int ret; |
| 673 | |
| 674 | /* Set RTC control register : Binary mode, 24hour mdoe */ |
| 675 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
| 676 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
| 677 | |
| 678 | ret = regmap_bulk_write(info->rtc_regmap, |
| 679 | info->drv_data->map[REG_RTC_CONTROLM], |
| 680 | data, ARRAY_SIZE(data)); |
| 681 | if (ret < 0) { |
| 682 | dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret); |
| 683 | return ret; |
| 684 | } |
| 685 | |
| 686 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); |
| 687 | return ret; |
| 688 | } |
| 689 | |
| 690 | static int max77686_init_rtc_regmap(struct max77686_rtc_info *info) |
| 691 | { |
| 692 | struct device *parent = info->dev->parent; |
| 693 | struct i2c_client *parent_i2c = to_i2c_client(parent); |
| 694 | int ret; |
| 695 | |
| 696 | if (info->drv_data->rtc_irq_from_platform) { |
| 697 | struct platform_device *pdev = to_platform_device(info->dev); |
| 698 | |
| 699 | info->rtc_irq = platform_get_irq(pdev, 0); |
| 700 | if (info->rtc_irq < 0) |
| 701 | return info->rtc_irq; |
| 702 | } else { |
| 703 | info->rtc_irq = parent_i2c->irq; |
| 704 | } |
| 705 | |
| 706 | info->regmap = dev_get_regmap(parent, NULL); |
| 707 | if (!info->regmap) { |
| 708 | dev_err(info->dev, "Failed to get rtc regmap\n"); |
| 709 | return -ENODEV; |
| 710 | } |
| 711 | |
| 712 | if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) { |
| 713 | info->rtc_regmap = info->regmap; |
| 714 | goto add_rtc_irq; |
| 715 | } |
| 716 | |
| 717 | info->rtc = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter, |
| 718 | info->drv_data->rtc_i2c_addr); |
| 719 | if (IS_ERR(info->rtc)) { |
| 720 | dev_err(info->dev, "Failed to allocate I2C device for RTC\n"); |
| 721 | return PTR_ERR(info->rtc); |
| 722 | } |
| 723 | |
| 724 | info->rtc_regmap = devm_regmap_init_i2c(info->rtc, |
| 725 | info->drv_data->regmap_config); |
| 726 | if (IS_ERR(info->rtc_regmap)) { |
| 727 | ret = PTR_ERR(info->rtc_regmap); |
| 728 | dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret); |
| 729 | return ret; |
| 730 | } |
| 731 | |
| 732 | add_rtc_irq: |
| 733 | ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq, |
| 734 | IRQF_ONESHOT | IRQF_SHARED, |
| 735 | 0, info->drv_data->rtc_irq_chip, |
| 736 | &info->rtc_irq_data); |
| 737 | if (ret < 0) { |
| 738 | dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret); |
| 739 | return ret; |
| 740 | } |
| 741 | |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | static int max77686_rtc_probe(struct platform_device *pdev) |
| 746 | { |
| 747 | struct max77686_rtc_info *info; |
| 748 | const struct platform_device_id *id = platform_get_device_id(pdev); |
| 749 | int ret; |
| 750 | |
| 751 | info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info), |
| 752 | GFP_KERNEL); |
| 753 | if (!info) |
| 754 | return -ENOMEM; |
| 755 | |
| 756 | mutex_init(&info->lock); |
| 757 | info->dev = &pdev->dev; |
| 758 | info->drv_data = (const struct max77686_rtc_driver_data *) |
| 759 | id->driver_data; |
| 760 | |
| 761 | ret = max77686_init_rtc_regmap(info); |
| 762 | if (ret < 0) |
| 763 | return ret; |
| 764 | |
| 765 | platform_set_drvdata(pdev, info); |
| 766 | |
| 767 | ret = max77686_rtc_init_reg(info); |
| 768 | if (ret < 0) { |
| 769 | dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret); |
| 770 | goto err_rtc; |
| 771 | } |
| 772 | |
| 773 | device_init_wakeup(&pdev->dev, 1); |
| 774 | |
| 775 | info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name, |
| 776 | &max77686_rtc_ops, THIS_MODULE); |
| 777 | |
| 778 | if (IS_ERR(info->rtc_dev)) { |
| 779 | ret = PTR_ERR(info->rtc_dev); |
| 780 | dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); |
| 781 | if (ret == 0) |
| 782 | ret = -EINVAL; |
| 783 | goto err_rtc; |
| 784 | } |
| 785 | |
| 786 | info->virq = regmap_irq_get_virq(info->rtc_irq_data, |
| 787 | MAX77686_RTCIRQ_RTCA1); |
| 788 | if (info->virq <= 0) { |
| 789 | ret = -ENXIO; |
| 790 | goto err_rtc; |
| 791 | } |
| 792 | |
| 793 | ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0, |
| 794 | "rtc-alarm1", info); |
| 795 | if (ret < 0) { |
| 796 | dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", |
| 797 | info->virq, ret); |
| 798 | goto err_rtc; |
| 799 | } |
| 800 | |
| 801 | return 0; |
| 802 | |
| 803 | err_rtc: |
| 804 | regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data); |
| 805 | |
| 806 | return ret; |
| 807 | } |
| 808 | |
| 809 | static int max77686_rtc_remove(struct platform_device *pdev) |
| 810 | { |
| 811 | struct max77686_rtc_info *info = platform_get_drvdata(pdev); |
| 812 | |
| 813 | free_irq(info->virq, info); |
| 814 | regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data); |
| 815 | |
| 816 | return 0; |
| 817 | } |
| 818 | |
| 819 | #ifdef CONFIG_PM_SLEEP |
| 820 | static int max77686_rtc_suspend(struct device *dev) |
| 821 | { |
| 822 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 823 | int ret = 0; |
| 824 | |
| 825 | if (device_may_wakeup(dev)) { |
| 826 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 827 | |
| 828 | ret = enable_irq_wake(info->virq); |
| 829 | } |
| 830 | |
| 831 | /* |
| 832 | * If the main IRQ (not virtual) is the parent IRQ, then it must be |
| 833 | * disabled during suspend because if it happens while suspended it |
| 834 | * will be handled before resuming I2C. |
| 835 | * |
| 836 | * Since Main IRQ is shared, all its users should disable it to be sure |
| 837 | * it won't fire while one of them is still suspended. |
| 838 | */ |
| 839 | if (!info->drv_data->rtc_irq_from_platform) |
| 840 | disable_irq(info->rtc_irq); |
| 841 | |
| 842 | return ret; |
| 843 | } |
| 844 | |
| 845 | static int max77686_rtc_resume(struct device *dev) |
| 846 | { |
| 847 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 848 | |
| 849 | if (!info->drv_data->rtc_irq_from_platform) |
| 850 | enable_irq(info->rtc_irq); |
| 851 | |
| 852 | if (device_may_wakeup(dev)) { |
| 853 | struct max77686_rtc_info *info = dev_get_drvdata(dev); |
| 854 | |
| 855 | return disable_irq_wake(info->virq); |
| 856 | } |
| 857 | |
| 858 | return 0; |
| 859 | } |
| 860 | #endif |
| 861 | |
| 862 | static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops, |
| 863 | max77686_rtc_suspend, max77686_rtc_resume); |
| 864 | |
| 865 | static const struct platform_device_id rtc_id[] = { |
| 866 | { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, }, |
| 867 | { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, }, |
| 868 | { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, }, |
| 869 | { "max77714-rtc", .driver_data = (kernel_ulong_t)&max77714_drv_data, }, |
| 870 | {}, |
| 871 | }; |
| 872 | MODULE_DEVICE_TABLE(platform, rtc_id); |
| 873 | |
| 874 | static struct platform_driver max77686_rtc_driver = { |
| 875 | .driver = { |
| 876 | .name = "max77686-rtc", |
| 877 | .pm = &max77686_rtc_pm_ops, |
| 878 | }, |
| 879 | .probe = max77686_rtc_probe, |
| 880 | .remove = max77686_rtc_remove, |
| 881 | .id_table = rtc_id, |
| 882 | }; |
| 883 | |
| 884 | module_platform_driver(max77686_rtc_driver); |
| 885 | |
| 886 | MODULE_DESCRIPTION("Maxim MAX77686 RTC driver"); |
| 887 | MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>"); |
| 888 | MODULE_LICENSE("GPL"); |