| 1 | /* |
| 2 | * AXP20x regulators driver. |
| 3 | * |
| 4 | * Copyright (C) 2013 Carlo Caione <carlo@caione.org> |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General |
| 7 | * Public License. See the file "COPYING" in the main directory of this |
| 8 | * archive for more details. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/bitops.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/mfd/axp20x.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/regmap.h> |
| 25 | #include <linux/regulator/driver.h> |
| 26 | #include <linux/regulator/machine.h> |
| 27 | #include <linux/regulator/of_regulator.h> |
| 28 | |
| 29 | #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0) |
| 30 | #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0) |
| 31 | |
| 32 | #define AXP20X_IO_ENABLED 0x03 |
| 33 | #define AXP20X_IO_DISABLED 0x07 |
| 34 | |
| 35 | #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2) |
| 36 | #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1) |
| 37 | |
| 38 | #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0) |
| 39 | |
| 40 | #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2) |
| 41 | |
| 42 | #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0) |
| 43 | #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0) |
| 44 | #define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4) |
| 45 | #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0) |
| 46 | #define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0) |
| 47 | #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4) |
| 48 | |
| 49 | #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0) |
| 50 | #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1) |
| 51 | #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2) |
| 52 | #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3) |
| 53 | #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4) |
| 54 | #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6) |
| 55 | |
| 56 | #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0) |
| 57 | #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \ |
| 58 | ((x) << 0) |
| 59 | #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1) |
| 60 | #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \ |
| 61 | ((x) << 1) |
| 62 | #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2) |
| 63 | #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2) |
| 64 | #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3) |
| 65 | #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3) |
| 66 | |
| 67 | #define AXP20X_LDO4_V_OUT_1250mV_START 0x0 |
| 68 | #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0 |
| 69 | #define AXP20X_LDO4_V_OUT_1250mV_END \ |
| 70 | (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS) |
| 71 | #define AXP20X_LDO4_V_OUT_1300mV_START 0x1 |
| 72 | #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7 |
| 73 | #define AXP20X_LDO4_V_OUT_1300mV_END \ |
| 74 | (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS) |
| 75 | #define AXP20X_LDO4_V_OUT_2500mV_START 0x9 |
| 76 | #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0 |
| 77 | #define AXP20X_LDO4_V_OUT_2500mV_END \ |
| 78 | (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS) |
| 79 | #define AXP20X_LDO4_V_OUT_2700mV_START 0xa |
| 80 | #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1 |
| 81 | #define AXP20X_LDO4_V_OUT_2700mV_END \ |
| 82 | (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS) |
| 83 | #define AXP20X_LDO4_V_OUT_3000mV_START 0xc |
| 84 | #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3 |
| 85 | #define AXP20X_LDO4_V_OUT_3000mV_END \ |
| 86 | (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS) |
| 87 | #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16 |
| 88 | |
| 89 | #define AXP22X_IO_ENABLED 0x03 |
| 90 | #define AXP22X_IO_DISABLED 0x04 |
| 91 | |
| 92 | #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x) |
| 93 | |
| 94 | #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) |
| 95 | |
| 96 | #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0) |
| 97 | #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0) |
| 98 | #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0) |
| 99 | #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0) |
| 100 | #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0) |
| 101 | #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0) |
| 102 | #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0) |
| 103 | #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0) |
| 104 | #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0) |
| 105 | #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0) |
| 106 | #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0) |
| 107 | #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0) |
| 108 | #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0) |
| 109 | #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0) |
| 110 | #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0) |
| 111 | #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0) |
| 112 | #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0) |
| 113 | #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0) |
| 114 | |
| 115 | #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0) |
| 116 | #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1) |
| 117 | #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2) |
| 118 | #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3) |
| 119 | #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4) |
| 120 | #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5) |
| 121 | #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6) |
| 122 | #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7) |
| 123 | |
| 124 | #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6) |
| 125 | #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7) |
| 126 | |
| 127 | #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0) |
| 128 | #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1) |
| 129 | #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2) |
| 130 | #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3) |
| 131 | #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4) |
| 132 | #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5) |
| 133 | #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6) |
| 134 | #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7) |
| 135 | |
| 136 | #define AXP313A_DCDC1_NUM_VOLTAGES 107 |
| 137 | #define AXP313A_DCDC23_NUM_VOLTAGES 88 |
| 138 | #define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0) |
| 139 | #define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0) |
| 140 | |
| 141 | #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) |
| 142 | #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) |
| 143 | #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) |
| 144 | #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3) |
| 145 | #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4) |
| 146 | #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5) |
| 147 | |
| 148 | #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2) |
| 149 | #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3) |
| 150 | |
| 151 | #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0) |
| 152 | #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0) |
| 153 | #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0) |
| 154 | #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0) |
| 155 | #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0) |
| 156 | #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0) |
| 157 | |
| 158 | #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0) |
| 159 | #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0) |
| 160 | |
| 161 | #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6) |
| 162 | #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5) |
| 163 | |
| 164 | #define AXP803_DCDC234_500mV_START 0x00 |
| 165 | #define AXP803_DCDC234_500mV_STEPS 70 |
| 166 | #define AXP803_DCDC234_500mV_END \ |
| 167 | (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS) |
| 168 | #define AXP803_DCDC234_1220mV_START 0x47 |
| 169 | #define AXP803_DCDC234_1220mV_STEPS 4 |
| 170 | #define AXP803_DCDC234_1220mV_END \ |
| 171 | (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS) |
| 172 | #define AXP803_DCDC234_NUM_VOLTAGES 76 |
| 173 | |
| 174 | #define AXP803_DCDC5_800mV_START 0x00 |
| 175 | #define AXP803_DCDC5_800mV_STEPS 32 |
| 176 | #define AXP803_DCDC5_800mV_END \ |
| 177 | (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS) |
| 178 | #define AXP803_DCDC5_1140mV_START 0x21 |
| 179 | #define AXP803_DCDC5_1140mV_STEPS 35 |
| 180 | #define AXP803_DCDC5_1140mV_END \ |
| 181 | (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS) |
| 182 | #define AXP803_DCDC5_NUM_VOLTAGES 69 |
| 183 | |
| 184 | #define AXP803_DCDC6_600mV_START 0x00 |
| 185 | #define AXP803_DCDC6_600mV_STEPS 50 |
| 186 | #define AXP803_DCDC6_600mV_END \ |
| 187 | (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS) |
| 188 | #define AXP803_DCDC6_1120mV_START 0x33 |
| 189 | #define AXP803_DCDC6_1120mV_STEPS 20 |
| 190 | #define AXP803_DCDC6_1120mV_END \ |
| 191 | (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) |
| 192 | #define AXP803_DCDC6_NUM_VOLTAGES 72 |
| 193 | |
| 194 | #define AXP803_DLDO2_700mV_START 0x00 |
| 195 | #define AXP803_DLDO2_700mV_STEPS 26 |
| 196 | #define AXP803_DLDO2_700mV_END \ |
| 197 | (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS) |
| 198 | #define AXP803_DLDO2_3400mV_START 0x1b |
| 199 | #define AXP803_DLDO2_3400mV_STEPS 4 |
| 200 | #define AXP803_DLDO2_3400mV_END \ |
| 201 | (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS) |
| 202 | #define AXP803_DLDO2_NUM_VOLTAGES 32 |
| 203 | |
| 204 | #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0) |
| 205 | #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0) |
| 206 | #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0) |
| 207 | #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0) |
| 208 | #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0) |
| 209 | #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0) |
| 210 | #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0) |
| 211 | #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0) |
| 212 | #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0) |
| 213 | #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0) |
| 214 | #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0) |
| 215 | #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0) |
| 216 | #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0) |
| 217 | #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0) |
| 218 | #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0) |
| 219 | |
| 220 | #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0) |
| 221 | #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1) |
| 222 | #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2) |
| 223 | #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3) |
| 224 | #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4) |
| 225 | #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5) |
| 226 | #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6) |
| 227 | #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7) |
| 228 | #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0) |
| 229 | #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1) |
| 230 | #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2) |
| 231 | #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3) |
| 232 | #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4) |
| 233 | #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5) |
| 234 | #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6) |
| 235 | #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7) |
| 236 | |
| 237 | #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40 |
| 238 | #define AXP806_DCDCABC_POLYPHASE_TRI 0x80 |
| 239 | #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6) |
| 240 | |
| 241 | #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5) |
| 242 | |
| 243 | #define AXP806_DCDCA_600mV_START 0x00 |
| 244 | #define AXP806_DCDCA_600mV_STEPS 50 |
| 245 | #define AXP806_DCDCA_600mV_END \ |
| 246 | (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS) |
| 247 | #define AXP806_DCDCA_1120mV_START 0x33 |
| 248 | #define AXP806_DCDCA_1120mV_STEPS 20 |
| 249 | #define AXP806_DCDCA_1120mV_END \ |
| 250 | (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS) |
| 251 | #define AXP806_DCDCA_NUM_VOLTAGES 72 |
| 252 | |
| 253 | #define AXP806_DCDCD_600mV_START 0x00 |
| 254 | #define AXP806_DCDCD_600mV_STEPS 45 |
| 255 | #define AXP806_DCDCD_600mV_END \ |
| 256 | (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS) |
| 257 | #define AXP806_DCDCD_1600mV_START 0x2e |
| 258 | #define AXP806_DCDCD_1600mV_STEPS 17 |
| 259 | #define AXP806_DCDCD_1600mV_END \ |
| 260 | (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS) |
| 261 | #define AXP806_DCDCD_NUM_VOLTAGES 64 |
| 262 | |
| 263 | #define AXP809_DCDC4_600mV_START 0x00 |
| 264 | #define AXP809_DCDC4_600mV_STEPS 47 |
| 265 | #define AXP809_DCDC4_600mV_END \ |
| 266 | (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS) |
| 267 | #define AXP809_DCDC4_1800mV_START 0x30 |
| 268 | #define AXP809_DCDC4_1800mV_STEPS 8 |
| 269 | #define AXP809_DCDC4_1800mV_END \ |
| 270 | (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS) |
| 271 | #define AXP809_DCDC4_NUM_VOLTAGES 57 |
| 272 | |
| 273 | #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0) |
| 274 | |
| 275 | #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6) |
| 276 | |
| 277 | #define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0) |
| 278 | #define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0) |
| 279 | #define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0) |
| 280 | #define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0) |
| 281 | #define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0) |
| 282 | #define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0) |
| 283 | #define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0) |
| 284 | #define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0) |
| 285 | #define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0) |
| 286 | #define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0) |
| 287 | #define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0) |
| 288 | #define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0) |
| 289 | #define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0) |
| 290 | #define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0) |
| 291 | #define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0) |
| 292 | #define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0) |
| 293 | #define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0) |
| 294 | #define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0) |
| 295 | #define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0) |
| 296 | #define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0) |
| 297 | #define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0) |
| 298 | |
| 299 | #define AXP15060_PWR_OUT_DCDC1_MASK BIT_MASK(0) |
| 300 | #define AXP15060_PWR_OUT_DCDC2_MASK BIT_MASK(1) |
| 301 | #define AXP15060_PWR_OUT_DCDC3_MASK BIT_MASK(2) |
| 302 | #define AXP15060_PWR_OUT_DCDC4_MASK BIT_MASK(3) |
| 303 | #define AXP15060_PWR_OUT_DCDC5_MASK BIT_MASK(4) |
| 304 | #define AXP15060_PWR_OUT_DCDC6_MASK BIT_MASK(5) |
| 305 | #define AXP15060_PWR_OUT_ALDO1_MASK BIT_MASK(0) |
| 306 | #define AXP15060_PWR_OUT_ALDO2_MASK BIT_MASK(1) |
| 307 | #define AXP15060_PWR_OUT_ALDO3_MASK BIT_MASK(2) |
| 308 | #define AXP15060_PWR_OUT_ALDO4_MASK BIT_MASK(3) |
| 309 | #define AXP15060_PWR_OUT_ALDO5_MASK BIT_MASK(4) |
| 310 | #define AXP15060_PWR_OUT_BLDO1_MASK BIT_MASK(5) |
| 311 | #define AXP15060_PWR_OUT_BLDO2_MASK BIT_MASK(6) |
| 312 | #define AXP15060_PWR_OUT_BLDO3_MASK BIT_MASK(7) |
| 313 | #define AXP15060_PWR_OUT_BLDO4_MASK BIT_MASK(0) |
| 314 | #define AXP15060_PWR_OUT_BLDO5_MASK BIT_MASK(1) |
| 315 | #define AXP15060_PWR_OUT_CLDO1_MASK BIT_MASK(2) |
| 316 | #define AXP15060_PWR_OUT_CLDO2_MASK BIT_MASK(3) |
| 317 | #define AXP15060_PWR_OUT_CLDO3_MASK BIT_MASK(4) |
| 318 | #define AXP15060_PWR_OUT_CLDO4_MASK BIT_MASK(5) |
| 319 | #define AXP15060_PWR_OUT_CPUSLDO_MASK BIT_MASK(6) |
| 320 | #define AXP15060_PWR_OUT_SW_MASK BIT_MASK(7) |
| 321 | |
| 322 | #define AXP15060_DCDC23_POLYPHASE_DUAL_MASK BIT_MASK(6) |
| 323 | #define AXP15060_DCDC46_POLYPHASE_DUAL_MASK BIT_MASK(7) |
| 324 | |
| 325 | #define AXP15060_DCDC234_500mV_START 0x00 |
| 326 | #define AXP15060_DCDC234_500mV_STEPS 70 |
| 327 | #define AXP15060_DCDC234_500mV_END \ |
| 328 | (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS) |
| 329 | #define AXP15060_DCDC234_1220mV_START 0x47 |
| 330 | #define AXP15060_DCDC234_1220mV_STEPS 16 |
| 331 | #define AXP15060_DCDC234_1220mV_END \ |
| 332 | (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS) |
| 333 | #define AXP15060_DCDC234_NUM_VOLTAGES 88 |
| 334 | |
| 335 | #define AXP15060_DCDC5_800mV_START 0x00 |
| 336 | #define AXP15060_DCDC5_800mV_STEPS 32 |
| 337 | #define AXP15060_DCDC5_800mV_END \ |
| 338 | (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS) |
| 339 | #define AXP15060_DCDC5_1140mV_START 0x21 |
| 340 | #define AXP15060_DCDC5_1140mV_STEPS 35 |
| 341 | #define AXP15060_DCDC5_1140mV_END \ |
| 342 | (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS) |
| 343 | #define AXP15060_DCDC5_NUM_VOLTAGES 69 |
| 344 | |
| 345 | #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 346 | _vmask, _ereg, _emask, _enable_val, _disable_val) \ |
| 347 | [_family##_##_id] = { \ |
| 348 | .name = (_match), \ |
| 349 | .supply_name = (_supply), \ |
| 350 | .of_match = of_match_ptr(_match), \ |
| 351 | .regulators_node = of_match_ptr("regulators"), \ |
| 352 | .type = REGULATOR_VOLTAGE, \ |
| 353 | .id = _family##_##_id, \ |
| 354 | .n_voltages = (((_max) - (_min)) / (_step) + 1), \ |
| 355 | .owner = THIS_MODULE, \ |
| 356 | .min_uV = (_min) * 1000, \ |
| 357 | .uV_step = (_step) * 1000, \ |
| 358 | .vsel_reg = (_vreg), \ |
| 359 | .vsel_mask = (_vmask), \ |
| 360 | .enable_reg = (_ereg), \ |
| 361 | .enable_mask = (_emask), \ |
| 362 | .enable_val = (_enable_val), \ |
| 363 | .disable_val = (_disable_val), \ |
| 364 | .ops = &axp20x_ops, \ |
| 365 | } |
| 366 | |
| 367 | #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 368 | _vmask, _ereg, _emask) \ |
| 369 | [_family##_##_id] = { \ |
| 370 | .name = (_match), \ |
| 371 | .supply_name = (_supply), \ |
| 372 | .of_match = of_match_ptr(_match), \ |
| 373 | .regulators_node = of_match_ptr("regulators"), \ |
| 374 | .type = REGULATOR_VOLTAGE, \ |
| 375 | .id = _family##_##_id, \ |
| 376 | .n_voltages = (((_max) - (_min)) / (_step) + 1), \ |
| 377 | .owner = THIS_MODULE, \ |
| 378 | .min_uV = (_min) * 1000, \ |
| 379 | .uV_step = (_step) * 1000, \ |
| 380 | .vsel_reg = (_vreg), \ |
| 381 | .vsel_mask = (_vmask), \ |
| 382 | .enable_reg = (_ereg), \ |
| 383 | .enable_mask = (_emask), \ |
| 384 | .ops = &axp20x_ops, \ |
| 385 | } |
| 386 | |
| 387 | #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ |
| 388 | [_family##_##_id] = { \ |
| 389 | .name = (_match), \ |
| 390 | .supply_name = (_supply), \ |
| 391 | .of_match = of_match_ptr(_match), \ |
| 392 | .regulators_node = of_match_ptr("regulators"), \ |
| 393 | .type = REGULATOR_VOLTAGE, \ |
| 394 | .id = _family##_##_id, \ |
| 395 | .owner = THIS_MODULE, \ |
| 396 | .enable_reg = (_ereg), \ |
| 397 | .enable_mask = (_emask), \ |
| 398 | .ops = &axp20x_ops_sw, \ |
| 399 | } |
| 400 | |
| 401 | #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ |
| 402 | [_family##_##_id] = { \ |
| 403 | .name = (_match), \ |
| 404 | .supply_name = (_supply), \ |
| 405 | .of_match = of_match_ptr(_match), \ |
| 406 | .regulators_node = of_match_ptr("regulators"), \ |
| 407 | .type = REGULATOR_VOLTAGE, \ |
| 408 | .id = _family##_##_id, \ |
| 409 | .n_voltages = 1, \ |
| 410 | .owner = THIS_MODULE, \ |
| 411 | .min_uV = (_volt) * 1000, \ |
| 412 | .ops = &axp20x_ops_fixed \ |
| 413 | } |
| 414 | |
| 415 | #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ |
| 416 | _vreg, _vmask, _ereg, _emask) \ |
| 417 | [_family##_##_id] = { \ |
| 418 | .name = (_match), \ |
| 419 | .supply_name = (_supply), \ |
| 420 | .of_match = of_match_ptr(_match), \ |
| 421 | .regulators_node = of_match_ptr("regulators"), \ |
| 422 | .type = REGULATOR_VOLTAGE, \ |
| 423 | .id = _family##_##_id, \ |
| 424 | .n_voltages = (_n_voltages), \ |
| 425 | .owner = THIS_MODULE, \ |
| 426 | .vsel_reg = (_vreg), \ |
| 427 | .vsel_mask = (_vmask), \ |
| 428 | .enable_reg = (_ereg), \ |
| 429 | .enable_mask = (_emask), \ |
| 430 | .linear_ranges = (_ranges), \ |
| 431 | .n_linear_ranges = ARRAY_SIZE(_ranges), \ |
| 432 | .ops = &axp20x_ops_range, \ |
| 433 | } |
| 434 | |
| 435 | static const int axp209_dcdc2_ldo3_slew_rates[] = { |
| 436 | 1600, |
| 437 | 800, |
| 438 | }; |
| 439 | |
| 440 | static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) |
| 441 | { |
| 442 | struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); |
| 443 | int id = rdev_get_id(rdev); |
| 444 | u8 reg, mask, enable, cfg = 0xff; |
| 445 | const int *slew_rates; |
| 446 | int rate_count = 0; |
| 447 | |
| 448 | switch (axp20x->variant) { |
| 449 | case AXP209_ID: |
| 450 | if (id == AXP20X_DCDC2) { |
| 451 | slew_rates = axp209_dcdc2_ldo3_slew_rates; |
| 452 | rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); |
| 453 | reg = AXP20X_DCDC2_LDO3_V_RAMP; |
| 454 | mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | |
| 455 | AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; |
| 456 | enable = (ramp > 0) ? |
| 457 | AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0; |
| 458 | break; |
| 459 | } |
| 460 | |
| 461 | if (id == AXP20X_LDO3) { |
| 462 | slew_rates = axp209_dcdc2_ldo3_slew_rates; |
| 463 | rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); |
| 464 | reg = AXP20X_DCDC2_LDO3_V_RAMP; |
| 465 | mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | |
| 466 | AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; |
| 467 | enable = (ramp > 0) ? |
| 468 | AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0; |
| 469 | break; |
| 470 | } |
| 471 | |
| 472 | if (rate_count > 0) |
| 473 | break; |
| 474 | |
| 475 | fallthrough; |
| 476 | default: |
| 477 | /* Not supported for this regulator */ |
| 478 | return -ENOTSUPP; |
| 479 | } |
| 480 | |
| 481 | if (ramp == 0) { |
| 482 | cfg = enable; |
| 483 | } else { |
| 484 | int i; |
| 485 | |
| 486 | for (i = 0; i < rate_count; i++) { |
| 487 | if (ramp > slew_rates[i]) |
| 488 | break; |
| 489 | |
| 490 | if (id == AXP20X_DCDC2) |
| 491 | cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i); |
| 492 | else |
| 493 | cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i); |
| 494 | } |
| 495 | |
| 496 | if (cfg == 0xff) { |
| 497 | dev_err(axp20x->dev, "unsupported ramp value %d", ramp); |
| 498 | return -EINVAL; |
| 499 | } |
| 500 | |
| 501 | cfg |= enable; |
| 502 | } |
| 503 | |
| 504 | return regmap_update_bits(axp20x->regmap, reg, mask, cfg); |
| 505 | } |
| 506 | |
| 507 | static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) |
| 508 | { |
| 509 | struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); |
| 510 | int id = rdev_get_id(rdev); |
| 511 | |
| 512 | switch (axp20x->variant) { |
| 513 | case AXP209_ID: |
| 514 | if ((id == AXP20X_LDO3) && |
| 515 | rdev->constraints && rdev->constraints->soft_start) { |
| 516 | int v_out; |
| 517 | int ret; |
| 518 | |
| 519 | /* |
| 520 | * On some boards, the LDO3 can be overloaded when |
| 521 | * turning on, causing the entire PMIC to shutdown |
| 522 | * without warning. Turning it on at the minimal voltage |
| 523 | * and then setting the voltage to the requested value |
| 524 | * works reliably. |
| 525 | */ |
| 526 | if (regulator_is_enabled_regmap(rdev)) |
| 527 | break; |
| 528 | |
| 529 | v_out = regulator_get_voltage_sel_regmap(rdev); |
| 530 | if (v_out < 0) |
| 531 | return v_out; |
| 532 | |
| 533 | if (v_out == 0) |
| 534 | break; |
| 535 | |
| 536 | ret = regulator_set_voltage_sel_regmap(rdev, 0x00); |
| 537 | /* |
| 538 | * A small pause is needed between |
| 539 | * setting the voltage and enabling the LDO to give the |
| 540 | * internal state machine time to process the request. |
| 541 | */ |
| 542 | usleep_range(1000, 5000); |
| 543 | ret |= regulator_enable_regmap(rdev); |
| 544 | ret |= regulator_set_voltage_sel_regmap(rdev, v_out); |
| 545 | |
| 546 | return ret; |
| 547 | } |
| 548 | break; |
| 549 | default: |
| 550 | /* No quirks */ |
| 551 | break; |
| 552 | } |
| 553 | |
| 554 | return regulator_enable_regmap(rdev); |
| 555 | }; |
| 556 | |
| 557 | static const struct regulator_ops axp20x_ops_fixed = { |
| 558 | .list_voltage = regulator_list_voltage_linear, |
| 559 | }; |
| 560 | |
| 561 | static const struct regulator_ops axp20x_ops_range = { |
| 562 | .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| 563 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
| 564 | .list_voltage = regulator_list_voltage_linear_range, |
| 565 | .enable = regulator_enable_regmap, |
| 566 | .disable = regulator_disable_regmap, |
| 567 | .is_enabled = regulator_is_enabled_regmap, |
| 568 | }; |
| 569 | |
| 570 | static const struct regulator_ops axp20x_ops = { |
| 571 | .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| 572 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
| 573 | .list_voltage = regulator_list_voltage_linear, |
| 574 | .enable = axp20x_regulator_enable_regmap, |
| 575 | .disable = regulator_disable_regmap, |
| 576 | .is_enabled = regulator_is_enabled_regmap, |
| 577 | .set_ramp_delay = axp20x_set_ramp_delay, |
| 578 | }; |
| 579 | |
| 580 | static const struct regulator_ops axp20x_ops_sw = { |
| 581 | .enable = regulator_enable_regmap, |
| 582 | .disable = regulator_disable_regmap, |
| 583 | .is_enabled = regulator_is_enabled_regmap, |
| 584 | }; |
| 585 | |
| 586 | static const struct linear_range axp20x_ldo4_ranges[] = { |
| 587 | REGULATOR_LINEAR_RANGE(1250000, |
| 588 | AXP20X_LDO4_V_OUT_1250mV_START, |
| 589 | AXP20X_LDO4_V_OUT_1250mV_END, |
| 590 | 0), |
| 591 | REGULATOR_LINEAR_RANGE(1300000, |
| 592 | AXP20X_LDO4_V_OUT_1300mV_START, |
| 593 | AXP20X_LDO4_V_OUT_1300mV_END, |
| 594 | 100000), |
| 595 | REGULATOR_LINEAR_RANGE(2500000, |
| 596 | AXP20X_LDO4_V_OUT_2500mV_START, |
| 597 | AXP20X_LDO4_V_OUT_2500mV_END, |
| 598 | 0), |
| 599 | REGULATOR_LINEAR_RANGE(2700000, |
| 600 | AXP20X_LDO4_V_OUT_2700mV_START, |
| 601 | AXP20X_LDO4_V_OUT_2700mV_END, |
| 602 | 100000), |
| 603 | REGULATOR_LINEAR_RANGE(3000000, |
| 604 | AXP20X_LDO4_V_OUT_3000mV_START, |
| 605 | AXP20X_LDO4_V_OUT_3000mV_END, |
| 606 | 100000), |
| 607 | }; |
| 608 | |
| 609 | static const struct regulator_desc axp20x_regulators[] = { |
| 610 | AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, |
| 611 | AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK, |
| 612 | AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK), |
| 613 | AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, |
| 614 | AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK, |
| 615 | AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK), |
| 616 | AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), |
| 617 | AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, |
| 618 | AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK, |
| 619 | AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK), |
| 620 | AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, |
| 621 | AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK, |
| 622 | AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK), |
| 623 | AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", |
| 624 | axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES, |
| 625 | AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK, |
| 626 | AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK), |
| 627 | AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, |
| 628 | AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK, |
| 629 | AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, |
| 630 | AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), |
| 631 | }; |
| 632 | |
| 633 | static const struct regulator_desc axp22x_regulators[] = { |
| 634 | AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, |
| 635 | AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, |
| 636 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), |
| 637 | AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, |
| 638 | AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, |
| 639 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), |
| 640 | AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, |
| 641 | AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, |
| 642 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), |
| 643 | AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, |
| 644 | AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, |
| 645 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), |
| 646 | AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, |
| 647 | AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, |
| 648 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), |
| 649 | /* secondary switchable output of DCDC1 */ |
| 650 | AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, |
| 651 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), |
| 652 | /* LDO regulator internally chained to DCDC5 */ |
| 653 | AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, |
| 654 | AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, |
| 655 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), |
| 656 | AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 657 | AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, |
| 658 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), |
| 659 | AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, |
| 660 | AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, |
| 661 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), |
| 662 | AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 663 | AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, |
| 664 | AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK), |
| 665 | AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, |
| 666 | AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, |
| 667 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), |
| 668 | AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, |
| 669 | AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, |
| 670 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), |
| 671 | AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, |
| 672 | AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, |
| 673 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), |
| 674 | AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, |
| 675 | AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, |
| 676 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), |
| 677 | AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, |
| 678 | AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, |
| 679 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), |
| 680 | AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, |
| 681 | AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, |
| 682 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), |
| 683 | AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, |
| 684 | AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, |
| 685 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), |
| 686 | /* Note the datasheet only guarantees reliable operation up to |
| 687 | * 3.3V, this needs to be enforced via dts provided constraints */ |
| 688 | AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, |
| 689 | AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, |
| 690 | AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, |
| 691 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 692 | /* Note the datasheet only guarantees reliable operation up to |
| 693 | * 3.3V, this needs to be enforced via dts provided constraints */ |
| 694 | AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, |
| 695 | AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, |
| 696 | AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, |
| 697 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 698 | AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), |
| 699 | }; |
| 700 | |
| 701 | static const struct regulator_desc axp22x_drivevbus_regulator = { |
| 702 | .name = "drivevbus", |
| 703 | .supply_name = "drivevbus", |
| 704 | .of_match = of_match_ptr("drivevbus"), |
| 705 | .regulators_node = of_match_ptr("regulators"), |
| 706 | .type = REGULATOR_VOLTAGE, |
| 707 | .owner = THIS_MODULE, |
| 708 | .enable_reg = AXP20X_VBUS_IPSOUT_MGMT, |
| 709 | .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK, |
| 710 | .ops = &axp20x_ops_sw, |
| 711 | }; |
| 712 | |
| 713 | static const struct linear_range axp313a_dcdc1_ranges[] = { |
| 714 | REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), |
| 715 | REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), |
| 716 | REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000), |
| 717 | }; |
| 718 | |
| 719 | static const struct linear_range axp313a_dcdc2_ranges[] = { |
| 720 | REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), |
| 721 | REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), |
| 722 | }; |
| 723 | |
| 724 | /* |
| 725 | * This is deviating from the datasheet. The values here are taken from the |
| 726 | * BSP driver and have been confirmed by measurements. |
| 727 | */ |
| 728 | static const struct linear_range axp313a_dcdc3_ranges[] = { |
| 729 | REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), |
| 730 | REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000), |
| 731 | }; |
| 732 | |
| 733 | static const struct regulator_desc axp313a_regulators[] = { |
| 734 | AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1", |
| 735 | axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES, |
| 736 | AXP313A_DCDC1_CONRTOL, AXP313A_DCDC_V_OUT_MASK, |
| 737 | AXP313A_OUTPUT_CONTROL, BIT(0)), |
| 738 | AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2", |
| 739 | axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES, |
| 740 | AXP313A_DCDC2_CONRTOL, AXP313A_DCDC_V_OUT_MASK, |
| 741 | AXP313A_OUTPUT_CONTROL, BIT(1)), |
| 742 | AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3", |
| 743 | axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES, |
| 744 | AXP313A_DCDC3_CONRTOL, AXP313A_DCDC_V_OUT_MASK, |
| 745 | AXP313A_OUTPUT_CONTROL, BIT(2)), |
| 746 | AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100, |
| 747 | AXP313A_ALDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, |
| 748 | AXP313A_OUTPUT_CONTROL, BIT(3)), |
| 749 | AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100, |
| 750 | AXP313A_DLDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, |
| 751 | AXP313A_OUTPUT_CONTROL, BIT(4)), |
| 752 | AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800), |
| 753 | }; |
| 754 | |
| 755 | /* DCDC ranges shared with AXP813 */ |
| 756 | static const struct linear_range axp803_dcdc234_ranges[] = { |
| 757 | REGULATOR_LINEAR_RANGE(500000, |
| 758 | AXP803_DCDC234_500mV_START, |
| 759 | AXP803_DCDC234_500mV_END, |
| 760 | 10000), |
| 761 | REGULATOR_LINEAR_RANGE(1220000, |
| 762 | AXP803_DCDC234_1220mV_START, |
| 763 | AXP803_DCDC234_1220mV_END, |
| 764 | 20000), |
| 765 | }; |
| 766 | |
| 767 | static const struct linear_range axp803_dcdc5_ranges[] = { |
| 768 | REGULATOR_LINEAR_RANGE(800000, |
| 769 | AXP803_DCDC5_800mV_START, |
| 770 | AXP803_DCDC5_800mV_END, |
| 771 | 10000), |
| 772 | REGULATOR_LINEAR_RANGE(1140000, |
| 773 | AXP803_DCDC5_1140mV_START, |
| 774 | AXP803_DCDC5_1140mV_END, |
| 775 | 20000), |
| 776 | }; |
| 777 | |
| 778 | static const struct linear_range axp803_dcdc6_ranges[] = { |
| 779 | REGULATOR_LINEAR_RANGE(600000, |
| 780 | AXP803_DCDC6_600mV_START, |
| 781 | AXP803_DCDC6_600mV_END, |
| 782 | 10000), |
| 783 | REGULATOR_LINEAR_RANGE(1120000, |
| 784 | AXP803_DCDC6_1120mV_START, |
| 785 | AXP803_DCDC6_1120mV_END, |
| 786 | 20000), |
| 787 | }; |
| 788 | |
| 789 | /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */ |
| 790 | static const struct linear_range axp803_dldo2_ranges[] = { |
| 791 | REGULATOR_LINEAR_RANGE(700000, |
| 792 | AXP803_DLDO2_700mV_START, |
| 793 | AXP803_DLDO2_700mV_END, |
| 794 | 100000), |
| 795 | REGULATOR_LINEAR_RANGE(3400000, |
| 796 | AXP803_DLDO2_3400mV_START, |
| 797 | AXP803_DLDO2_3400mV_END, |
| 798 | 200000), |
| 799 | }; |
| 800 | |
| 801 | static const struct regulator_desc axp803_regulators[] = { |
| 802 | AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, |
| 803 | AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, |
| 804 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), |
| 805 | AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", |
| 806 | axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, |
| 807 | AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, |
| 808 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), |
| 809 | AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", |
| 810 | axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, |
| 811 | AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, |
| 812 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), |
| 813 | AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", |
| 814 | axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, |
| 815 | AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, |
| 816 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), |
| 817 | AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", |
| 818 | axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, |
| 819 | AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, |
| 820 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), |
| 821 | AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", |
| 822 | axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, |
| 823 | AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, |
| 824 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), |
| 825 | /* secondary switchable output of DCDC1 */ |
| 826 | AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, |
| 827 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), |
| 828 | AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 829 | AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, |
| 830 | AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), |
| 831 | AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, |
| 832 | AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, |
| 833 | AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), |
| 834 | AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 835 | AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, |
| 836 | AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), |
| 837 | AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100, |
| 838 | AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, |
| 839 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), |
| 840 | AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", |
| 841 | axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, |
| 842 | AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, |
| 843 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), |
| 844 | AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, |
| 845 | AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, |
| 846 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), |
| 847 | AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100, |
| 848 | AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, |
| 849 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), |
| 850 | AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50, |
| 851 | AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, |
| 852 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), |
| 853 | AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50, |
| 854 | AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, |
| 855 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), |
| 856 | AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, |
| 857 | AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, |
| 858 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), |
| 859 | AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, |
| 860 | AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, |
| 861 | AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), |
| 862 | AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50, |
| 863 | AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, |
| 864 | AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), |
| 865 | AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, |
| 866 | AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, |
| 867 | AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, |
| 868 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 869 | AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, |
| 870 | AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, |
| 871 | AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, |
| 872 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 873 | AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000), |
| 874 | }; |
| 875 | |
| 876 | static const struct linear_range axp806_dcdca_ranges[] = { |
| 877 | REGULATOR_LINEAR_RANGE(600000, |
| 878 | AXP806_DCDCA_600mV_START, |
| 879 | AXP806_DCDCA_600mV_END, |
| 880 | 10000), |
| 881 | REGULATOR_LINEAR_RANGE(1120000, |
| 882 | AXP806_DCDCA_1120mV_START, |
| 883 | AXP806_DCDCA_1120mV_END, |
| 884 | 20000), |
| 885 | }; |
| 886 | |
| 887 | static const struct linear_range axp806_dcdcd_ranges[] = { |
| 888 | REGULATOR_LINEAR_RANGE(600000, |
| 889 | AXP806_DCDCD_600mV_START, |
| 890 | AXP806_DCDCD_600mV_END, |
| 891 | 20000), |
| 892 | REGULATOR_LINEAR_RANGE(1600000, |
| 893 | AXP806_DCDCD_1600mV_START, |
| 894 | AXP806_DCDCD_1600mV_END, |
| 895 | 100000), |
| 896 | }; |
| 897 | |
| 898 | static const struct regulator_desc axp806_regulators[] = { |
| 899 | AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", |
| 900 | axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, |
| 901 | AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, |
| 902 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), |
| 903 | AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, |
| 904 | AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK, |
| 905 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), |
| 906 | AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", |
| 907 | axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, |
| 908 | AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK, |
| 909 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK), |
| 910 | AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", |
| 911 | axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES, |
| 912 | AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK, |
| 913 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK), |
| 914 | AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100, |
| 915 | AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK, |
| 916 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK), |
| 917 | AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 918 | AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK, |
| 919 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK), |
| 920 | AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100, |
| 921 | AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK, |
| 922 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK), |
| 923 | AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 924 | AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK, |
| 925 | AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK), |
| 926 | AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100, |
| 927 | AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, |
| 928 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), |
| 929 | AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, |
| 930 | AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK, |
| 931 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), |
| 932 | AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, |
| 933 | AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, |
| 934 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK), |
| 935 | AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100, |
| 936 | AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK, |
| 937 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK), |
| 938 | AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100, |
| 939 | AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK, |
| 940 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK), |
| 941 | AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", |
| 942 | axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, |
| 943 | AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK, |
| 944 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK), |
| 945 | AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100, |
| 946 | AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK, |
| 947 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK), |
| 948 | AXP_DESC_SW(AXP806, SW, "sw", "swin", |
| 949 | AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK), |
| 950 | }; |
| 951 | |
| 952 | static const struct linear_range axp809_dcdc4_ranges[] = { |
| 953 | REGULATOR_LINEAR_RANGE(600000, |
| 954 | AXP809_DCDC4_600mV_START, |
| 955 | AXP809_DCDC4_600mV_END, |
| 956 | 20000), |
| 957 | REGULATOR_LINEAR_RANGE(1800000, |
| 958 | AXP809_DCDC4_1800mV_START, |
| 959 | AXP809_DCDC4_1800mV_END, |
| 960 | 100000), |
| 961 | }; |
| 962 | |
| 963 | static const struct regulator_desc axp809_regulators[] = { |
| 964 | AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, |
| 965 | AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, |
| 966 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), |
| 967 | AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20, |
| 968 | AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, |
| 969 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), |
| 970 | AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20, |
| 971 | AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, |
| 972 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), |
| 973 | AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", |
| 974 | axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES, |
| 975 | AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, |
| 976 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), |
| 977 | AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, |
| 978 | AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, |
| 979 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), |
| 980 | /* secondary switchable output of DCDC1 */ |
| 981 | AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, |
| 982 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), |
| 983 | /* LDO regulator internally chained to DCDC5 */ |
| 984 | AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, |
| 985 | AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, |
| 986 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), |
| 987 | AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 988 | AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, |
| 989 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), |
| 990 | AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100, |
| 991 | AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, |
| 992 | AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), |
| 993 | AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 994 | AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, |
| 995 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK), |
| 996 | AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", |
| 997 | axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, |
| 998 | AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, |
| 999 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), |
| 1000 | AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, |
| 1001 | AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, |
| 1002 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), |
| 1003 | AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100, |
| 1004 | AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, |
| 1005 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), |
| 1006 | AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100, |
| 1007 | AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, |
| 1008 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), |
| 1009 | AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, |
| 1010 | AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, |
| 1011 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), |
| 1012 | /* |
| 1013 | * Note the datasheet only guarantees reliable operation up to |
| 1014 | * 3.3V, this needs to be enforced via dts provided constraints |
| 1015 | */ |
| 1016 | AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, |
| 1017 | AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, |
| 1018 | AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, |
| 1019 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 1020 | /* |
| 1021 | * Note the datasheet only guarantees reliable operation up to |
| 1022 | * 3.3V, this needs to be enforced via dts provided constraints |
| 1023 | */ |
| 1024 | AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, |
| 1025 | AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, |
| 1026 | AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, |
| 1027 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 1028 | AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), |
| 1029 | AXP_DESC_SW(AXP809, SW, "sw", "swin", |
| 1030 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK), |
| 1031 | }; |
| 1032 | |
| 1033 | static const struct regulator_desc axp813_regulators[] = { |
| 1034 | AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, |
| 1035 | AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, |
| 1036 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), |
| 1037 | AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2", |
| 1038 | axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, |
| 1039 | AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, |
| 1040 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), |
| 1041 | AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3", |
| 1042 | axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, |
| 1043 | AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, |
| 1044 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), |
| 1045 | AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4", |
| 1046 | axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, |
| 1047 | AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, |
| 1048 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), |
| 1049 | AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5", |
| 1050 | axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, |
| 1051 | AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, |
| 1052 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), |
| 1053 | AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6", |
| 1054 | axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, |
| 1055 | AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, |
| 1056 | AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), |
| 1057 | AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7", |
| 1058 | axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, |
| 1059 | AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK, |
| 1060 | AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK), |
| 1061 | AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 1062 | AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, |
| 1063 | AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), |
| 1064 | AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, |
| 1065 | AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, |
| 1066 | AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), |
| 1067 | AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 1068 | AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, |
| 1069 | AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), |
| 1070 | AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100, |
| 1071 | AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, |
| 1072 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), |
| 1073 | AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", |
| 1074 | axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, |
| 1075 | AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, |
| 1076 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), |
| 1077 | AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, |
| 1078 | AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, |
| 1079 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), |
| 1080 | AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100, |
| 1081 | AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, |
| 1082 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), |
| 1083 | AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50, |
| 1084 | AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, |
| 1085 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), |
| 1086 | AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50, |
| 1087 | AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, |
| 1088 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), |
| 1089 | AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, |
| 1090 | AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, |
| 1091 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), |
| 1092 | /* to do / check ... */ |
| 1093 | AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, |
| 1094 | AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, |
| 1095 | AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), |
| 1096 | AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50, |
| 1097 | AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, |
| 1098 | AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), |
| 1099 | /* |
| 1100 | * TODO: FLDO3 = {DCDC5, FLDOIN} / 2 |
| 1101 | * |
| 1102 | * This means FLDO3 effectively switches supplies at runtime, |
| 1103 | * something the regulator subsystem does not support. |
| 1104 | */ |
| 1105 | AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800), |
| 1106 | AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, |
| 1107 | AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, |
| 1108 | AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, |
| 1109 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 1110 | AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, |
| 1111 | AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, |
| 1112 | AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, |
| 1113 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 1114 | AXP_DESC_SW(AXP813, SW, "sw", "swin", |
| 1115 | AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), |
| 1116 | }; |
| 1117 | |
| 1118 | static const struct linear_range axp15060_dcdc234_ranges[] = { |
| 1119 | REGULATOR_LINEAR_RANGE(500000, |
| 1120 | AXP15060_DCDC234_500mV_START, |
| 1121 | AXP15060_DCDC234_500mV_END, |
| 1122 | 10000), |
| 1123 | REGULATOR_LINEAR_RANGE(1220000, |
| 1124 | AXP15060_DCDC234_1220mV_START, |
| 1125 | AXP15060_DCDC234_1220mV_END, |
| 1126 | 20000), |
| 1127 | }; |
| 1128 | |
| 1129 | static const struct linear_range axp15060_dcdc5_ranges[] = { |
| 1130 | REGULATOR_LINEAR_RANGE(800000, |
| 1131 | AXP15060_DCDC5_800mV_START, |
| 1132 | AXP15060_DCDC5_800mV_END, |
| 1133 | 10000), |
| 1134 | REGULATOR_LINEAR_RANGE(1140000, |
| 1135 | AXP15060_DCDC5_1140mV_START, |
| 1136 | AXP15060_DCDC5_1140mV_END, |
| 1137 | 20000), |
| 1138 | }; |
| 1139 | |
| 1140 | static const struct regulator_desc axp15060_regulators[] = { |
| 1141 | AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100, |
| 1142 | AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK, |
| 1143 | AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK), |
| 1144 | AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2", |
| 1145 | axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, |
| 1146 | AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK, |
| 1147 | AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK), |
| 1148 | AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3", |
| 1149 | axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, |
| 1150 | AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK, |
| 1151 | AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK), |
| 1152 | AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4", |
| 1153 | axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, |
| 1154 | AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK, |
| 1155 | AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK), |
| 1156 | AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5", |
| 1157 | axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES, |
| 1158 | AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK, |
| 1159 | AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK), |
| 1160 | AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100, |
| 1161 | AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK, |
| 1162 | AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK), |
| 1163 | AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 1164 | AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK, |
| 1165 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK), |
| 1166 | AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100, |
| 1167 | AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK, |
| 1168 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK), |
| 1169 | AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 1170 | AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK, |
| 1171 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK), |
| 1172 | AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100, |
| 1173 | AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK, |
| 1174 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK), |
| 1175 | AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100, |
| 1176 | AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK, |
| 1177 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK), |
| 1178 | AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100, |
| 1179 | AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK, |
| 1180 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK), |
| 1181 | AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100, |
| 1182 | AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK, |
| 1183 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK), |
| 1184 | AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100, |
| 1185 | AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK, |
| 1186 | AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK), |
| 1187 | AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100, |
| 1188 | AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK, |
| 1189 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK), |
| 1190 | AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100, |
| 1191 | AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK, |
| 1192 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK), |
| 1193 | AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100, |
| 1194 | AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK, |
| 1195 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK), |
| 1196 | AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100, |
| 1197 | AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK, |
| 1198 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK), |
| 1199 | AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100, |
| 1200 | AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK, |
| 1201 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK), |
| 1202 | AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100, |
| 1203 | AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK, |
| 1204 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK), |
| 1205 | /* Supply comes from DCDC5 */ |
| 1206 | AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50, |
| 1207 | AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK, |
| 1208 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK), |
| 1209 | /* Supply comes from DCDC1 */ |
| 1210 | AXP_DESC_SW(AXP15060, SW, "sw", NULL, |
| 1211 | AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK), |
| 1212 | /* Supply comes from ALDO1 */ |
| 1213 | AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800), |
| 1214 | }; |
| 1215 | |
| 1216 | static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) |
| 1217 | { |
| 1218 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); |
| 1219 | unsigned int reg = AXP20X_DCDC_FREQ; |
| 1220 | u32 min, max, def, step; |
| 1221 | |
| 1222 | switch (axp20x->variant) { |
| 1223 | case AXP202_ID: |
| 1224 | case AXP209_ID: |
| 1225 | min = 750; |
| 1226 | max = 1875; |
| 1227 | def = 1500; |
| 1228 | step = 75; |
| 1229 | break; |
| 1230 | case AXP803_ID: |
| 1231 | case AXP813_ID: |
| 1232 | /* |
| 1233 | * AXP803/AXP813 DCDC work frequency setting has the same |
| 1234 | * range and step as AXP22X, but at a different register. |
| 1235 | * (See include/linux/mfd/axp20x.h) |
| 1236 | */ |
| 1237 | reg = AXP803_DCDC_FREQ_CTRL; |
| 1238 | fallthrough; /* to the check below */ |
| 1239 | case AXP806_ID: |
| 1240 | /* |
| 1241 | * AXP806 also have DCDC work frequency setting register at a |
| 1242 | * different position. |
| 1243 | */ |
| 1244 | if (axp20x->variant == AXP806_ID) |
| 1245 | reg = AXP806_DCDC_FREQ_CTRL; |
| 1246 | fallthrough; |
| 1247 | case AXP221_ID: |
| 1248 | case AXP223_ID: |
| 1249 | case AXP809_ID: |
| 1250 | min = 1800; |
| 1251 | max = 4050; |
| 1252 | def = 3000; |
| 1253 | step = 150; |
| 1254 | break; |
| 1255 | case AXP313A_ID: |
| 1256 | case AXP15060_ID: |
| 1257 | /* The DCDC PWM frequency seems to be fixed to 3 MHz. */ |
| 1258 | if (dcdcfreq != 0) { |
| 1259 | dev_err(&pdev->dev, |
| 1260 | "DCDC frequency on this PMIC is fixed to 3 MHz.\n"); |
| 1261 | return -EINVAL; |
| 1262 | } |
| 1263 | |
| 1264 | return 0; |
| 1265 | default: |
| 1266 | dev_err(&pdev->dev, |
| 1267 | "Setting DCDC frequency for unsupported AXP variant\n"); |
| 1268 | return -EINVAL; |
| 1269 | } |
| 1270 | |
| 1271 | if (dcdcfreq == 0) |
| 1272 | dcdcfreq = def; |
| 1273 | |
| 1274 | if (dcdcfreq < min) { |
| 1275 | dcdcfreq = min; |
| 1276 | dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", |
| 1277 | min); |
| 1278 | } |
| 1279 | |
| 1280 | if (dcdcfreq > max) { |
| 1281 | dcdcfreq = max; |
| 1282 | dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", |
| 1283 | max); |
| 1284 | } |
| 1285 | |
| 1286 | dcdcfreq = (dcdcfreq - min) / step; |
| 1287 | |
| 1288 | return regmap_update_bits(axp20x->regmap, reg, |
| 1289 | AXP20X_FREQ_DCDC_MASK, dcdcfreq); |
| 1290 | } |
| 1291 | |
| 1292 | static int axp20x_regulator_parse_dt(struct platform_device *pdev) |
| 1293 | { |
| 1294 | struct device_node *np, *regulators; |
| 1295 | int ret = 0; |
| 1296 | u32 dcdcfreq = 0; |
| 1297 | |
| 1298 | np = of_node_get(pdev->dev.parent->of_node); |
| 1299 | if (!np) |
| 1300 | return 0; |
| 1301 | |
| 1302 | regulators = of_get_child_by_name(np, "regulators"); |
| 1303 | if (!regulators) { |
| 1304 | dev_warn(&pdev->dev, "regulators node not found\n"); |
| 1305 | } else { |
| 1306 | of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); |
| 1307 | ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); |
| 1308 | if (ret < 0) { |
| 1309 | dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); |
| 1310 | } |
| 1311 | of_node_put(regulators); |
| 1312 | } |
| 1313 | |
| 1314 | of_node_put(np); |
| 1315 | return ret; |
| 1316 | } |
| 1317 | |
| 1318 | static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) |
| 1319 | { |
| 1320 | struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); |
| 1321 | unsigned int reg = AXP20X_DCDC_MODE; |
| 1322 | unsigned int mask; |
| 1323 | |
| 1324 | switch (axp20x->variant) { |
| 1325 | case AXP202_ID: |
| 1326 | case AXP209_ID: |
| 1327 | if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) |
| 1328 | return -EINVAL; |
| 1329 | |
| 1330 | mask = AXP20X_WORKMODE_DCDC2_MASK; |
| 1331 | if (id == AXP20X_DCDC3) |
| 1332 | mask = AXP20X_WORKMODE_DCDC3_MASK; |
| 1333 | |
| 1334 | workmode <<= ffs(mask) - 1; |
| 1335 | break; |
| 1336 | |
| 1337 | case AXP806_ID: |
| 1338 | /* |
| 1339 | * AXP806 DCDC regulator IDs have the same range as AXP22X. |
| 1340 | * (See include/linux/mfd/axp20x.h) |
| 1341 | */ |
| 1342 | reg = AXP806_DCDC_MODE_CTRL2; |
| 1343 | fallthrough; /* to the check below */ |
| 1344 | case AXP221_ID: |
| 1345 | case AXP223_ID: |
| 1346 | case AXP809_ID: |
| 1347 | if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) |
| 1348 | return -EINVAL; |
| 1349 | |
| 1350 | mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); |
| 1351 | workmode <<= id - AXP22X_DCDC1; |
| 1352 | break; |
| 1353 | |
| 1354 | case AXP803_ID: |
| 1355 | if (id < AXP803_DCDC1 || id > AXP803_DCDC6) |
| 1356 | return -EINVAL; |
| 1357 | |
| 1358 | mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); |
| 1359 | workmode <<= id - AXP803_DCDC1; |
| 1360 | break; |
| 1361 | |
| 1362 | case AXP813_ID: |
| 1363 | if (id < AXP813_DCDC1 || id > AXP813_DCDC7) |
| 1364 | return -EINVAL; |
| 1365 | |
| 1366 | mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1); |
| 1367 | workmode <<= id - AXP813_DCDC1; |
| 1368 | break; |
| 1369 | |
| 1370 | case AXP15060_ID: |
| 1371 | reg = AXP15060_DCDC_MODE_CTRL2; |
| 1372 | if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6) |
| 1373 | return -EINVAL; |
| 1374 | |
| 1375 | mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1); |
| 1376 | workmode <<= id - AXP15060_DCDC1; |
| 1377 | break; |
| 1378 | |
| 1379 | default: |
| 1380 | /* should not happen */ |
| 1381 | WARN_ON(1); |
| 1382 | return -EINVAL; |
| 1383 | } |
| 1384 | |
| 1385 | return regmap_update_bits(rdev->regmap, reg, mask, workmode); |
| 1386 | } |
| 1387 | |
| 1388 | /* |
| 1389 | * This function checks whether a regulator is part of a poly-phase |
| 1390 | * output setup based on the registers settings. Returns true if it is. |
| 1391 | */ |
| 1392 | static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id) |
| 1393 | { |
| 1394 | u32 reg = 0; |
| 1395 | |
| 1396 | /* |
| 1397 | * Currently in our supported AXP variants, only AXP803, AXP806, |
| 1398 | * AXP813 and AXP15060 have polyphase regulators. |
| 1399 | */ |
| 1400 | switch (axp20x->variant) { |
| 1401 | case AXP803_ID: |
| 1402 | case AXP813_ID: |
| 1403 | regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); |
| 1404 | |
| 1405 | switch (id) { |
| 1406 | case AXP803_DCDC3: |
| 1407 | return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); |
| 1408 | case AXP803_DCDC6: |
| 1409 | return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); |
| 1410 | } |
| 1411 | break; |
| 1412 | |
| 1413 | case AXP806_ID: |
| 1414 | regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); |
| 1415 | |
| 1416 | switch (id) { |
| 1417 | case AXP806_DCDCB: |
| 1418 | return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) == |
| 1419 | AXP806_DCDCAB_POLYPHASE_DUAL) || |
| 1420 | ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == |
| 1421 | AXP806_DCDCABC_POLYPHASE_TRI)); |
| 1422 | case AXP806_DCDCC: |
| 1423 | return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == |
| 1424 | AXP806_DCDCABC_POLYPHASE_TRI); |
| 1425 | case AXP806_DCDCE: |
| 1426 | return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); |
| 1427 | } |
| 1428 | break; |
| 1429 | |
| 1430 | case AXP15060_ID: |
| 1431 | regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, ®); |
| 1432 | |
| 1433 | switch (id) { |
| 1434 | case AXP15060_DCDC3: |
| 1435 | return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK); |
| 1436 | case AXP15060_DCDC6: |
| 1437 | return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK); |
| 1438 | } |
| 1439 | break; |
| 1440 | |
| 1441 | default: |
| 1442 | return false; |
| 1443 | } |
| 1444 | |
| 1445 | return false; |
| 1446 | } |
| 1447 | |
| 1448 | static int axp20x_regulator_probe(struct platform_device *pdev) |
| 1449 | { |
| 1450 | struct regulator_dev *rdev; |
| 1451 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); |
| 1452 | const struct regulator_desc *regulators; |
| 1453 | struct regulator_config config = { |
| 1454 | .dev = pdev->dev.parent, |
| 1455 | .regmap = axp20x->regmap, |
| 1456 | .driver_data = axp20x, |
| 1457 | }; |
| 1458 | int ret, i, nregulators; |
| 1459 | u32 workmode; |
| 1460 | const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name; |
| 1461 | const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name; |
| 1462 | const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name; |
| 1463 | bool drivevbus = false; |
| 1464 | |
| 1465 | switch (axp20x->variant) { |
| 1466 | case AXP202_ID: |
| 1467 | case AXP209_ID: |
| 1468 | regulators = axp20x_regulators; |
| 1469 | nregulators = AXP20X_REG_ID_MAX; |
| 1470 | break; |
| 1471 | case AXP221_ID: |
| 1472 | case AXP223_ID: |
| 1473 | regulators = axp22x_regulators; |
| 1474 | nregulators = AXP22X_REG_ID_MAX; |
| 1475 | drivevbus = of_property_read_bool(pdev->dev.parent->of_node, |
| 1476 | "x-powers,drive-vbus-en"); |
| 1477 | break; |
| 1478 | case AXP313A_ID: |
| 1479 | regulators = axp313a_regulators; |
| 1480 | nregulators = AXP313A_REG_ID_MAX; |
| 1481 | break; |
| 1482 | case AXP803_ID: |
| 1483 | regulators = axp803_regulators; |
| 1484 | nregulators = AXP803_REG_ID_MAX; |
| 1485 | drivevbus = of_property_read_bool(pdev->dev.parent->of_node, |
| 1486 | "x-powers,drive-vbus-en"); |
| 1487 | break; |
| 1488 | case AXP806_ID: |
| 1489 | regulators = axp806_regulators; |
| 1490 | nregulators = AXP806_REG_ID_MAX; |
| 1491 | break; |
| 1492 | case AXP809_ID: |
| 1493 | regulators = axp809_regulators; |
| 1494 | nregulators = AXP809_REG_ID_MAX; |
| 1495 | break; |
| 1496 | case AXP813_ID: |
| 1497 | regulators = axp813_regulators; |
| 1498 | nregulators = AXP813_REG_ID_MAX; |
| 1499 | drivevbus = of_property_read_bool(pdev->dev.parent->of_node, |
| 1500 | "x-powers,drive-vbus-en"); |
| 1501 | break; |
| 1502 | case AXP15060_ID: |
| 1503 | regulators = axp15060_regulators; |
| 1504 | nregulators = AXP15060_REG_ID_MAX; |
| 1505 | break; |
| 1506 | default: |
| 1507 | dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n", |
| 1508 | axp20x->variant); |
| 1509 | return -EINVAL; |
| 1510 | } |
| 1511 | |
| 1512 | /* This only sets the dcdc freq. Ignore any errors */ |
| 1513 | axp20x_regulator_parse_dt(pdev); |
| 1514 | |
| 1515 | for (i = 0; i < nregulators; i++) { |
| 1516 | const struct regulator_desc *desc = ®ulators[i]; |
| 1517 | struct regulator_desc *new_desc; |
| 1518 | |
| 1519 | /* |
| 1520 | * If this regulator is a slave in a poly-phase setup, |
| 1521 | * skip it, as its controls are bound to the master |
| 1522 | * regulator and won't work. |
| 1523 | */ |
| 1524 | if (axp20x_is_polyphase_slave(axp20x, i)) |
| 1525 | continue; |
| 1526 | |
| 1527 | /* Support for AXP813's FLDO3 is not implemented */ |
| 1528 | if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3) |
| 1529 | continue; |
| 1530 | |
| 1531 | /* |
| 1532 | * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are |
| 1533 | * connected internally, so we have to handle their supply |
| 1534 | * names separately. |
| 1535 | * |
| 1536 | * We always register the regulators in proper sequence, |
| 1537 | * so the supply names are correctly read. See the last |
| 1538 | * part of this loop to see where we save the DT defined |
| 1539 | * name. |
| 1540 | */ |
| 1541 | if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || |
| 1542 | (regulators == axp803_regulators && i == AXP803_DC1SW) || |
| 1543 | (regulators == axp809_regulators && i == AXP809_DC1SW) || |
| 1544 | (regulators == axp15060_regulators && i == AXP15060_SW)) { |
| 1545 | new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), |
| 1546 | GFP_KERNEL); |
| 1547 | if (!new_desc) |
| 1548 | return -ENOMEM; |
| 1549 | |
| 1550 | *new_desc = regulators[i]; |
| 1551 | new_desc->supply_name = dcdc1_name; |
| 1552 | desc = new_desc; |
| 1553 | } |
| 1554 | |
| 1555 | if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) || |
| 1556 | (regulators == axp809_regulators && i == AXP809_DC5LDO) || |
| 1557 | (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) { |
| 1558 | new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), |
| 1559 | GFP_KERNEL); |
| 1560 | if (!new_desc) |
| 1561 | return -ENOMEM; |
| 1562 | |
| 1563 | *new_desc = regulators[i]; |
| 1564 | new_desc->supply_name = dcdc5_name; |
| 1565 | desc = new_desc; |
| 1566 | } |
| 1567 | |
| 1568 | |
| 1569 | if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) { |
| 1570 | new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), |
| 1571 | GFP_KERNEL); |
| 1572 | if (!new_desc) |
| 1573 | return -ENOMEM; |
| 1574 | |
| 1575 | *new_desc = regulators[i]; |
| 1576 | new_desc->supply_name = aldo1_name; |
| 1577 | desc = new_desc; |
| 1578 | } |
| 1579 | |
| 1580 | rdev = devm_regulator_register(&pdev->dev, desc, &config); |
| 1581 | if (IS_ERR(rdev)) { |
| 1582 | dev_err(&pdev->dev, "Failed to register %s\n", |
| 1583 | regulators[i].name); |
| 1584 | |
| 1585 | return PTR_ERR(rdev); |
| 1586 | } |
| 1587 | |
| 1588 | ret = of_property_read_u32(rdev->dev.of_node, |
| 1589 | "x-powers,dcdc-workmode", |
| 1590 | &workmode); |
| 1591 | if (!ret) { |
| 1592 | if (axp20x_set_dcdc_workmode(rdev, i, workmode)) |
| 1593 | dev_err(&pdev->dev, "Failed to set workmode on %s\n", |
| 1594 | rdev->desc->name); |
| 1595 | } |
| 1596 | |
| 1597 | /* |
| 1598 | * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later. |
| 1599 | */ |
| 1600 | if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) || |
| 1601 | (regulators == axp809_regulators && i == AXP809_DCDC1) || |
| 1602 | (regulators == axp15060_regulators && i == AXP15060_DCDC1)) |
| 1603 | of_property_read_string(rdev->dev.of_node, |
| 1604 | "regulator-name", |
| 1605 | &dcdc1_name); |
| 1606 | |
| 1607 | if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) || |
| 1608 | (regulators == axp809_regulators && i == AXP809_DCDC5) || |
| 1609 | (regulators == axp15060_regulators && i == AXP15060_DCDC5)) |
| 1610 | of_property_read_string(rdev->dev.of_node, |
| 1611 | "regulator-name", |
| 1612 | &dcdc5_name); |
| 1613 | |
| 1614 | if (regulators == axp15060_regulators && i == AXP15060_ALDO1) |
| 1615 | of_property_read_string(rdev->dev.of_node, |
| 1616 | "regulator-name", |
| 1617 | &aldo1_name); |
| 1618 | } |
| 1619 | |
| 1620 | if (drivevbus) { |
| 1621 | /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */ |
| 1622 | regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP, |
| 1623 | AXP22X_MISC_N_VBUSEN_FUNC, 0); |
| 1624 | rdev = devm_regulator_register(&pdev->dev, |
| 1625 | &axp22x_drivevbus_regulator, |
| 1626 | &config); |
| 1627 | if (IS_ERR(rdev)) { |
| 1628 | dev_err(&pdev->dev, "Failed to register drivevbus\n"); |
| 1629 | return PTR_ERR(rdev); |
| 1630 | } |
| 1631 | } |
| 1632 | |
| 1633 | return 0; |
| 1634 | } |
| 1635 | |
| 1636 | static struct platform_driver axp20x_regulator_driver = { |
| 1637 | .probe = axp20x_regulator_probe, |
| 1638 | .driver = { |
| 1639 | .name = "axp20x-regulator", |
| 1640 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
| 1641 | }, |
| 1642 | }; |
| 1643 | |
| 1644 | module_platform_driver(axp20x_regulator_driver); |
| 1645 | |
| 1646 | MODULE_LICENSE("GPL v2"); |
| 1647 | MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); |
| 1648 | MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); |
| 1649 | MODULE_ALIAS("platform:axp20x-regulator"); |