| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2016 |
| 4 | * |
| 5 | * Author: Gerald Baeza <gerald.baeza@st.com> |
| 6 | * |
| 7 | * Inspired by timer-stm32.c from Maxime Coquelin |
| 8 | * pwm-atmel.c from Bo Shen |
| 9 | */ |
| 10 | |
| 11 | #include <linux/bitfield.h> |
| 12 | #include <linux/mfd/stm32-timers.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/pinctrl/consumer.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/pwm.h> |
| 18 | |
| 19 | #define CCMR_CHANNEL_SHIFT 8 |
| 20 | #define CCMR_CHANNEL_MASK 0xFF |
| 21 | #define MAX_BREAKINPUT 2 |
| 22 | |
| 23 | struct stm32_breakinput { |
| 24 | u32 index; |
| 25 | u32 level; |
| 26 | u32 filter; |
| 27 | }; |
| 28 | |
| 29 | struct stm32_pwm { |
| 30 | struct mutex lock; /* protect pwm config/enable */ |
| 31 | struct clk *clk; |
| 32 | struct regmap *regmap; |
| 33 | u32 max_arr; |
| 34 | bool have_complementary_output; |
| 35 | struct stm32_breakinput breakinputs[MAX_BREAKINPUT]; |
| 36 | unsigned int num_breakinputs; |
| 37 | u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ |
| 38 | }; |
| 39 | |
| 40 | static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) |
| 41 | { |
| 42 | return pwmchip_get_drvdata(chip); |
| 43 | } |
| 44 | |
| 45 | static u32 active_channels(struct stm32_pwm *dev) |
| 46 | { |
| 47 | u32 ccer; |
| 48 | |
| 49 | regmap_read(dev->regmap, TIM_CCER, &ccer); |
| 50 | |
| 51 | return ccer & TIM_CCER_CCXE; |
| 52 | } |
| 53 | |
| 54 | #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) |
| 55 | #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) |
| 56 | #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) |
| 57 | #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) |
| 58 | |
| 59 | /* |
| 60 | * Capture using PWM input mode: |
| 61 | * ___ ___ |
| 62 | * TI[1, 2, 3 or 4]: ........._| |________| |
| 63 | * ^0 ^1 ^2 |
| 64 | * . . . |
| 65 | * . . XXXXX |
| 66 | * . . XXXXX | |
| 67 | * . XXXXX . | |
| 68 | * XXXXX . . | |
| 69 | * COUNTER: ______XXXXX . . . |_XXX |
| 70 | * start^ . . . ^stop |
| 71 | * . . . . |
| 72 | * v v . v |
| 73 | * v |
| 74 | * CCR1/CCR3: tx..........t0...........t2 |
| 75 | * CCR2/CCR4: tx..............t1......... |
| 76 | * |
| 77 | * DMA burst transfer: | | |
| 78 | * v v |
| 79 | * DMA buffer: { t0, tx } { t2, t1 } |
| 80 | * DMA done: ^ |
| 81 | * |
| 82 | * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 |
| 83 | * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) |
| 84 | * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 |
| 85 | * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 |
| 86 | * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) |
| 87 | * |
| 88 | * DMA done, compute: |
| 89 | * - Period = t2 - t0 |
| 90 | * - Duty cycle = t1 - t0 |
| 91 | */ |
| 92 | static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
| 93 | unsigned long tmo_ms, u32 *raw_prd, |
| 94 | u32 *raw_dty) |
| 95 | { |
| 96 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 97 | struct device *parent = pwmchip_parent(chip)->parent; |
| 98 | enum stm32_timers_dmas dma_id; |
| 99 | u32 ccen, ccr; |
| 100 | int ret; |
| 101 | |
| 102 | /* Ensure registers have been updated, enable counter and capture */ |
| 103 | regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); |
| 104 | regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); |
| 105 | |
| 106 | /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ |
| 107 | dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; |
| 108 | ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; |
| 109 | ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; |
| 110 | regmap_set_bits(priv->regmap, TIM_CCER, ccen); |
| 111 | |
| 112 | /* |
| 113 | * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both |
| 114 | * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. |
| 115 | * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } |
| 116 | * or { CCR3, CCR4 }, { CCR3, CCR4 } |
| 117 | */ |
| 118 | ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, |
| 119 | 2, tmo_ms); |
| 120 | if (ret) |
| 121 | goto stop; |
| 122 | |
| 123 | /* Period: t2 - t0 (take care of counter overflow) */ |
| 124 | if (priv->capture[0] <= priv->capture[2]) |
| 125 | *raw_prd = priv->capture[2] - priv->capture[0]; |
| 126 | else |
| 127 | *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; |
| 128 | |
| 129 | /* Duty cycle capture requires at least two capture units */ |
| 130 | if (pwm->chip->npwm < 2) |
| 131 | *raw_dty = 0; |
| 132 | else if (priv->capture[0] <= priv->capture[3]) |
| 133 | *raw_dty = priv->capture[3] - priv->capture[0]; |
| 134 | else |
| 135 | *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; |
| 136 | |
| 137 | if (*raw_dty > *raw_prd) { |
| 138 | /* |
| 139 | * Race beetween PWM input and DMA: it may happen |
| 140 | * falling edge triggers new capture on TI2/4 before DMA |
| 141 | * had a chance to read CCR2/4. It means capture[1] |
| 142 | * contains period + duty_cycle. So, subtract period. |
| 143 | */ |
| 144 | *raw_dty -= *raw_prd; |
| 145 | } |
| 146 | |
| 147 | stop: |
| 148 | regmap_clear_bits(priv->regmap, TIM_CCER, ccen); |
| 149 | regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); |
| 150 | |
| 151 | return ret; |
| 152 | } |
| 153 | |
| 154 | static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
| 155 | struct pwm_capture *result, unsigned long tmo_ms) |
| 156 | { |
| 157 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 158 | unsigned long long prd, div, dty; |
| 159 | unsigned long rate; |
| 160 | unsigned int psc = 0, icpsc, scale; |
| 161 | u32 raw_prd = 0, raw_dty = 0; |
| 162 | int ret = 0; |
| 163 | |
| 164 | mutex_lock(&priv->lock); |
| 165 | |
| 166 | if (active_channels(priv)) { |
| 167 | ret = -EBUSY; |
| 168 | goto unlock; |
| 169 | } |
| 170 | |
| 171 | ret = clk_enable(priv->clk); |
| 172 | if (ret) { |
| 173 | dev_err(pwmchip_parent(chip), "failed to enable counter clock\n"); |
| 174 | goto unlock; |
| 175 | } |
| 176 | |
| 177 | rate = clk_get_rate(priv->clk); |
| 178 | if (!rate) { |
| 179 | ret = -EINVAL; |
| 180 | goto clk_dis; |
| 181 | } |
| 182 | |
| 183 | /* prescaler: fit timeout window provided by upper layer */ |
| 184 | div = (unsigned long long)rate * (unsigned long long)tmo_ms; |
| 185 | do_div(div, MSEC_PER_SEC); |
| 186 | prd = div; |
| 187 | while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { |
| 188 | psc++; |
| 189 | div = prd; |
| 190 | do_div(div, psc + 1); |
| 191 | } |
| 192 | regmap_write(priv->regmap, TIM_ARR, priv->max_arr); |
| 193 | regmap_write(priv->regmap, TIM_PSC, psc); |
| 194 | |
| 195 | /* Reset input selector to its default input and disable slave mode */ |
| 196 | regmap_write(priv->regmap, TIM_TISEL, 0x0); |
| 197 | regmap_write(priv->regmap, TIM_SMCR, 0x0); |
| 198 | |
| 199 | /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ |
| 200 | regmap_update_bits(priv->regmap, |
| 201 | pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, |
| 202 | TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? |
| 203 | TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : |
| 204 | TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); |
| 205 | |
| 206 | /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ |
| 207 | regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? |
| 208 | TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? |
| 209 | TIM_CCER_CC2P : TIM_CCER_CC4P); |
| 210 | |
| 211 | ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty); |
| 212 | if (ret) |
| 213 | goto stop; |
| 214 | |
| 215 | /* |
| 216 | * Got a capture. Try to improve accuracy at high rates: |
| 217 | * - decrease counter clock prescaler, scale up to max rate. |
| 218 | * - use input prescaler, capture once every /2 /4 or /8 edges. |
| 219 | */ |
| 220 | if (raw_prd) { |
| 221 | u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ |
| 222 | |
| 223 | scale = max_arr / min(max_arr, raw_prd); |
| 224 | } else { |
| 225 | scale = priv->max_arr; /* bellow resolution, use max scale */ |
| 226 | } |
| 227 | |
| 228 | if (psc && scale > 1) { |
| 229 | /* 2nd measure with new scale */ |
| 230 | psc /= scale; |
| 231 | regmap_write(priv->regmap, TIM_PSC, psc); |
| 232 | ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, |
| 233 | &raw_dty); |
| 234 | if (ret) |
| 235 | goto stop; |
| 236 | } |
| 237 | |
| 238 | /* Compute intermediate period not to exceed timeout at low rates */ |
| 239 | prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; |
| 240 | do_div(prd, rate); |
| 241 | |
| 242 | for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { |
| 243 | /* input prescaler: also keep arbitrary margin */ |
| 244 | if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) |
| 245 | break; |
| 246 | if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) |
| 247 | break; |
| 248 | } |
| 249 | |
| 250 | if (!icpsc) |
| 251 | goto done; |
| 252 | |
| 253 | /* Last chance to improve period accuracy, using input prescaler */ |
| 254 | regmap_update_bits(priv->regmap, |
| 255 | pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, |
| 256 | TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, |
| 257 | FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | |
| 258 | FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); |
| 259 | |
| 260 | ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty); |
| 261 | if (ret) |
| 262 | goto stop; |
| 263 | |
| 264 | if (raw_dty >= (raw_prd >> icpsc)) { |
| 265 | /* |
| 266 | * We may fall here using input prescaler, when input |
| 267 | * capture starts on high side (before falling edge). |
| 268 | * Example with icpsc to capture on each 4 events: |
| 269 | * |
| 270 | * start 1st capture 2nd capture |
| 271 | * v v v |
| 272 | * ___ _____ _____ _____ _____ ____ |
| 273 | * TI1..4 |__| |__| |__| |__| |__| |
| 274 | * v v . . . . . v v |
| 275 | * icpsc1/3: . 0 . 1 . 2 . 3 . 0 |
| 276 | * icpsc2/4: 0 1 2 3 0 |
| 277 | * v v v v |
| 278 | * CCR1/3 ......t0..............................t2 |
| 279 | * CCR2/4 ..t1..............................t1'... |
| 280 | * . . . |
| 281 | * Capture0: .<----------------------------->. |
| 282 | * Capture1: .<-------------------------->. . |
| 283 | * . . . |
| 284 | * Period: .<------> . . |
| 285 | * Low side: .<>. |
| 286 | * |
| 287 | * Result: |
| 288 | * - Period = Capture0 / icpsc |
| 289 | * - Duty = Period - Low side = Period - (Capture0 - Capture1) |
| 290 | */ |
| 291 | raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); |
| 292 | } |
| 293 | |
| 294 | done: |
| 295 | prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; |
| 296 | result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); |
| 297 | dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; |
| 298 | result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); |
| 299 | stop: |
| 300 | regmap_write(priv->regmap, TIM_CCER, 0); |
| 301 | regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); |
| 302 | regmap_write(priv->regmap, TIM_PSC, 0); |
| 303 | clk_dis: |
| 304 | clk_disable(priv->clk); |
| 305 | unlock: |
| 306 | mutex_unlock(&priv->lock); |
| 307 | |
| 308 | return ret; |
| 309 | } |
| 310 | |
| 311 | static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch, |
| 312 | u64 duty_ns, u64 period_ns) |
| 313 | { |
| 314 | unsigned long long prd, dty; |
| 315 | unsigned long long prescaler; |
| 316 | u32 ccmr, mask, shift; |
| 317 | |
| 318 | /* |
| 319 | * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so |
| 320 | * the calculations here won't overflow. |
| 321 | * First we need to find the minimal value for prescaler such that |
| 322 | * |
| 323 | * period_ns * clkrate |
| 324 | * ------------------------------ |
| 325 | * NSEC_PER_SEC * (prescaler + 1) |
| 326 | * |
| 327 | * isn't bigger than max_arr. |
| 328 | */ |
| 329 | |
| 330 | prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk), |
| 331 | (u64)NSEC_PER_SEC * priv->max_arr); |
| 332 | if (prescaler > 0) |
| 333 | prescaler -= 1; |
| 334 | |
| 335 | if (prescaler > MAX_TIM_PSC) |
| 336 | return -EINVAL; |
| 337 | |
| 338 | prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk), |
| 339 | (u64)NSEC_PER_SEC * (prescaler + 1)); |
| 340 | |
| 341 | /* |
| 342 | * All channels share the same prescaler and counter so when two |
| 343 | * channels are active at the same time we can't change them |
| 344 | */ |
| 345 | if (active_channels(priv) & ~(1 << ch * 4)) { |
| 346 | u32 psc, arr; |
| 347 | |
| 348 | regmap_read(priv->regmap, TIM_PSC, &psc); |
| 349 | regmap_read(priv->regmap, TIM_ARR, &arr); |
| 350 | |
| 351 | if ((psc != prescaler) || (arr != prd - 1)) |
| 352 | return -EBUSY; |
| 353 | } |
| 354 | |
| 355 | regmap_write(priv->regmap, TIM_PSC, prescaler); |
| 356 | regmap_write(priv->regmap, TIM_ARR, prd - 1); |
| 357 | regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); |
| 358 | |
| 359 | /* Calculate the duty cycles */ |
| 360 | dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk), |
| 361 | (u64)NSEC_PER_SEC * (prescaler + 1)); |
| 362 | |
| 363 | regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty); |
| 364 | |
| 365 | /* Configure output mode */ |
| 366 | shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; |
| 367 | ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; |
| 368 | mask = CCMR_CHANNEL_MASK << shift; |
| 369 | |
| 370 | if (ch < 2) |
| 371 | regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); |
| 372 | else |
| 373 | regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); |
| 374 | |
| 375 | regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch, |
| 381 | enum pwm_polarity polarity) |
| 382 | { |
| 383 | u32 mask; |
| 384 | |
| 385 | mask = TIM_CCER_CC1P << (ch * 4); |
| 386 | if (priv->have_complementary_output) |
| 387 | mask |= TIM_CCER_CC1NP << (ch * 4); |
| 388 | |
| 389 | regmap_update_bits(priv->regmap, TIM_CCER, mask, |
| 390 | polarity == PWM_POLARITY_NORMAL ? 0 : mask); |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) |
| 396 | { |
| 397 | u32 mask; |
| 398 | int ret; |
| 399 | |
| 400 | ret = clk_enable(priv->clk); |
| 401 | if (ret) |
| 402 | return ret; |
| 403 | |
| 404 | /* Enable channel */ |
| 405 | mask = TIM_CCER_CC1E << (ch * 4); |
| 406 | if (priv->have_complementary_output) |
| 407 | mask |= TIM_CCER_CC1NE << (ch * 4); |
| 408 | |
| 409 | regmap_set_bits(priv->regmap, TIM_CCER, mask); |
| 410 | |
| 411 | /* Make sure that registers are updated */ |
| 412 | regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); |
| 413 | |
| 414 | /* Enable controller */ |
| 415 | regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); |
| 416 | |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch) |
| 421 | { |
| 422 | u32 mask; |
| 423 | |
| 424 | /* Disable channel */ |
| 425 | mask = TIM_CCER_CC1E << (ch * 4); |
| 426 | if (priv->have_complementary_output) |
| 427 | mask |= TIM_CCER_CC1NE << (ch * 4); |
| 428 | |
| 429 | regmap_clear_bits(priv->regmap, TIM_CCER, mask); |
| 430 | |
| 431 | /* When all channels are disabled, we can disable the controller */ |
| 432 | if (!active_channels(priv)) |
| 433 | regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); |
| 434 | |
| 435 | clk_disable(priv->clk); |
| 436 | } |
| 437 | |
| 438 | static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
| 439 | const struct pwm_state *state) |
| 440 | { |
| 441 | bool enabled; |
| 442 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 443 | int ret; |
| 444 | |
| 445 | enabled = pwm->state.enabled; |
| 446 | |
| 447 | if (enabled && !state->enabled) { |
| 448 | stm32_pwm_disable(priv, pwm->hwpwm); |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | if (state->polarity != pwm->state.polarity) |
| 453 | stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); |
| 454 | |
| 455 | ret = stm32_pwm_config(priv, pwm->hwpwm, |
| 456 | state->duty_cycle, state->period); |
| 457 | if (ret) |
| 458 | return ret; |
| 459 | |
| 460 | if (!enabled && state->enabled) |
| 461 | ret = stm32_pwm_enable(priv, pwm->hwpwm); |
| 462 | |
| 463 | return ret; |
| 464 | } |
| 465 | |
| 466 | static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, |
| 467 | const struct pwm_state *state) |
| 468 | { |
| 469 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 470 | int ret; |
| 471 | |
| 472 | /* protect common prescaler for all active channels */ |
| 473 | mutex_lock(&priv->lock); |
| 474 | ret = stm32_pwm_apply(chip, pwm, state); |
| 475 | mutex_unlock(&priv->lock); |
| 476 | |
| 477 | return ret; |
| 478 | } |
| 479 | |
| 480 | static int stm32_pwm_get_state(struct pwm_chip *chip, |
| 481 | struct pwm_device *pwm, struct pwm_state *state) |
| 482 | { |
| 483 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 484 | int ch = pwm->hwpwm; |
| 485 | unsigned long rate; |
| 486 | u32 ccer, psc, arr, ccr; |
| 487 | u64 dty, prd; |
| 488 | int ret; |
| 489 | |
| 490 | mutex_lock(&priv->lock); |
| 491 | |
| 492 | ret = regmap_read(priv->regmap, TIM_CCER, &ccer); |
| 493 | if (ret) |
| 494 | goto out; |
| 495 | |
| 496 | state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4)); |
| 497 | state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ? |
| 498 | PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; |
| 499 | ret = regmap_read(priv->regmap, TIM_PSC, &psc); |
| 500 | if (ret) |
| 501 | goto out; |
| 502 | ret = regmap_read(priv->regmap, TIM_ARR, &arr); |
| 503 | if (ret) |
| 504 | goto out; |
| 505 | ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr); |
| 506 | if (ret) |
| 507 | goto out; |
| 508 | |
| 509 | rate = clk_get_rate(priv->clk); |
| 510 | |
| 511 | prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1); |
| 512 | state->period = DIV_ROUND_UP_ULL(prd, rate); |
| 513 | dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr; |
| 514 | state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); |
| 515 | |
| 516 | out: |
| 517 | mutex_unlock(&priv->lock); |
| 518 | return ret; |
| 519 | } |
| 520 | |
| 521 | static const struct pwm_ops stm32pwm_ops = { |
| 522 | .apply = stm32_pwm_apply_locked, |
| 523 | .get_state = stm32_pwm_get_state, |
| 524 | .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, |
| 525 | }; |
| 526 | |
| 527 | static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, |
| 528 | const struct stm32_breakinput *bi) |
| 529 | { |
| 530 | u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); |
| 531 | u32 bke = TIM_BDTR_BKE(bi->index); |
| 532 | u32 bkp = TIM_BDTR_BKP(bi->index); |
| 533 | u32 bkf = TIM_BDTR_BKF(bi->index); |
| 534 | u32 mask = bkf | bkp | bke; |
| 535 | u32 bdtr; |
| 536 | |
| 537 | bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; |
| 538 | |
| 539 | if (bi->level) |
| 540 | bdtr |= bkp; |
| 541 | |
| 542 | regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); |
| 543 | |
| 544 | regmap_read(priv->regmap, TIM_BDTR, &bdtr); |
| 545 | |
| 546 | return (bdtr & bke) ? 0 : -EINVAL; |
| 547 | } |
| 548 | |
| 549 | static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv) |
| 550 | { |
| 551 | unsigned int i; |
| 552 | int ret; |
| 553 | |
| 554 | for (i = 0; i < priv->num_breakinputs; i++) { |
| 555 | ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); |
| 556 | if (ret < 0) |
| 557 | return ret; |
| 558 | } |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | |
| 563 | static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv, |
| 564 | struct device_node *np) |
| 565 | { |
| 566 | int nb, ret, array_size; |
| 567 | unsigned int i; |
| 568 | |
| 569 | nb = of_property_count_elems_of_size(np, "st,breakinput", |
| 570 | sizeof(struct stm32_breakinput)); |
| 571 | |
| 572 | /* |
| 573 | * Because "st,breakinput" parameter is optional do not make probe |
| 574 | * failed if it doesn't exist. |
| 575 | */ |
| 576 | if (nb <= 0) |
| 577 | return 0; |
| 578 | |
| 579 | if (nb > MAX_BREAKINPUT) |
| 580 | return -EINVAL; |
| 581 | |
| 582 | priv->num_breakinputs = nb; |
| 583 | array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); |
| 584 | ret = of_property_read_u32_array(np, "st,breakinput", |
| 585 | (u32 *)priv->breakinputs, array_size); |
| 586 | if (ret) |
| 587 | return ret; |
| 588 | |
| 589 | for (i = 0; i < priv->num_breakinputs; i++) { |
| 590 | if (priv->breakinputs[i].index > 1 || |
| 591 | priv->breakinputs[i].level > 1 || |
| 592 | priv->breakinputs[i].filter > 15) |
| 593 | return -EINVAL; |
| 594 | } |
| 595 | |
| 596 | return stm32_pwm_apply_breakinputs(priv); |
| 597 | } |
| 598 | |
| 599 | static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) |
| 600 | { |
| 601 | u32 ccer; |
| 602 | |
| 603 | /* |
| 604 | * If complementary bit doesn't exist writing 1 will have no |
| 605 | * effect so we can detect it. |
| 606 | */ |
| 607 | regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); |
| 608 | regmap_read(priv->regmap, TIM_CCER, &ccer); |
| 609 | regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); |
| 610 | |
| 611 | priv->have_complementary_output = (ccer != 0); |
| 612 | } |
| 613 | |
| 614 | static unsigned int stm32_pwm_detect_channels(struct regmap *regmap, |
| 615 | unsigned int *num_enabled) |
| 616 | { |
| 617 | u32 ccer, ccer_backup; |
| 618 | |
| 619 | /* |
| 620 | * If channels enable bits don't exist writing 1 will have no |
| 621 | * effect so we can detect and count them. |
| 622 | */ |
| 623 | regmap_read(regmap, TIM_CCER, &ccer_backup); |
| 624 | regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE); |
| 625 | regmap_read(regmap, TIM_CCER, &ccer); |
| 626 | regmap_write(regmap, TIM_CCER, ccer_backup); |
| 627 | |
| 628 | *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE); |
| 629 | |
| 630 | return hweight32(ccer & TIM_CCER_CCXE); |
| 631 | } |
| 632 | |
| 633 | static int stm32_pwm_probe(struct platform_device *pdev) |
| 634 | { |
| 635 | struct device *dev = &pdev->dev; |
| 636 | struct device_node *np = dev->of_node; |
| 637 | struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); |
| 638 | struct pwm_chip *chip; |
| 639 | struct stm32_pwm *priv; |
| 640 | unsigned int npwm, num_enabled; |
| 641 | unsigned int i; |
| 642 | int ret; |
| 643 | |
| 644 | npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled); |
| 645 | |
| 646 | chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv)); |
| 647 | if (IS_ERR(chip)) |
| 648 | return PTR_ERR(chip); |
| 649 | priv = to_stm32_pwm_dev(chip); |
| 650 | |
| 651 | mutex_init(&priv->lock); |
| 652 | priv->regmap = ddata->regmap; |
| 653 | priv->clk = ddata->clk; |
| 654 | priv->max_arr = ddata->max_arr; |
| 655 | |
| 656 | if (!priv->regmap || !priv->clk) |
| 657 | return dev_err_probe(dev, -EINVAL, "Failed to get %s\n", |
| 658 | priv->regmap ? "clk" : "regmap"); |
| 659 | |
| 660 | ret = stm32_pwm_probe_breakinputs(priv, np); |
| 661 | if (ret) |
| 662 | return dev_err_probe(dev, ret, |
| 663 | "Failed to configure breakinputs\n"); |
| 664 | |
| 665 | stm32_pwm_detect_complementary(priv); |
| 666 | |
| 667 | ret = devm_clk_rate_exclusive_get(dev, priv->clk); |
| 668 | if (ret) |
| 669 | return dev_err_probe(dev, ret, "Failed to lock clock\n"); |
| 670 | |
| 671 | /* |
| 672 | * With the clk running with not more than 1 GHz the calculations in |
| 673 | * .apply() won't overflow. |
| 674 | */ |
| 675 | if (clk_get_rate(priv->clk) > 1000000000) |
| 676 | return dev_err_probe(dev, -EINVAL, "Failed to lock clock\n"); |
| 677 | |
| 678 | chip->ops = &stm32pwm_ops; |
| 679 | |
| 680 | /* Initialize clock refcount to number of enabled PWM channels. */ |
| 681 | for (i = 0; i < num_enabled; i++) |
| 682 | clk_enable(priv->clk); |
| 683 | |
| 684 | ret = devm_pwmchip_add(dev, chip); |
| 685 | if (ret < 0) |
| 686 | return dev_err_probe(dev, ret, |
| 687 | "Failed to register pwmchip\n"); |
| 688 | |
| 689 | platform_set_drvdata(pdev, chip); |
| 690 | |
| 691 | return 0; |
| 692 | } |
| 693 | |
| 694 | static int stm32_pwm_suspend(struct device *dev) |
| 695 | { |
| 696 | struct pwm_chip *chip = dev_get_drvdata(dev); |
| 697 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 698 | unsigned int i; |
| 699 | u32 ccer, mask; |
| 700 | |
| 701 | /* Look for active channels */ |
| 702 | ccer = active_channels(priv); |
| 703 | |
| 704 | for (i = 0; i < chip->npwm; i++) { |
| 705 | mask = TIM_CCER_CC1E << (i * 4); |
| 706 | if (ccer & mask) { |
| 707 | dev_err(dev, "PWM %u still in use by consumer %s\n", |
| 708 | i, chip->pwms[i].label); |
| 709 | return -EBUSY; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | return pinctrl_pm_select_sleep_state(dev); |
| 714 | } |
| 715 | |
| 716 | static int stm32_pwm_resume(struct device *dev) |
| 717 | { |
| 718 | struct pwm_chip *chip = dev_get_drvdata(dev); |
| 719 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
| 720 | int ret; |
| 721 | |
| 722 | ret = pinctrl_pm_select_default_state(dev); |
| 723 | if (ret) |
| 724 | return ret; |
| 725 | |
| 726 | /* restore breakinput registers that may have been lost in low power */ |
| 727 | return stm32_pwm_apply_breakinputs(priv); |
| 728 | } |
| 729 | |
| 730 | static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); |
| 731 | |
| 732 | static const struct of_device_id stm32_pwm_of_match[] = { |
| 733 | { .compatible = "st,stm32-pwm", }, |
| 734 | { /* end node */ }, |
| 735 | }; |
| 736 | MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); |
| 737 | |
| 738 | static struct platform_driver stm32_pwm_driver = { |
| 739 | .probe = stm32_pwm_probe, |
| 740 | .driver = { |
| 741 | .name = "stm32-pwm", |
| 742 | .of_match_table = stm32_pwm_of_match, |
| 743 | .pm = pm_ptr(&stm32_pwm_pm_ops), |
| 744 | }, |
| 745 | }; |
| 746 | module_platform_driver(stm32_pwm_driver); |
| 747 | |
| 748 | MODULE_ALIAS("platform:stm32-pwm"); |
| 749 | MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); |
| 750 | MODULE_LICENSE("GPL v2"); |