| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * AXP20x pinctrl and GPIO driver |
| 4 | * |
| 5 | * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> |
| 6 | * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com> |
| 7 | */ |
| 8 | |
| 9 | #include <linux/bitops.h> |
| 10 | #include <linux/device.h> |
| 11 | #include <linux/gpio/driver.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/mfd/axp20x.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/regmap.h> |
| 20 | #include <linux/slab.h> |
| 21 | |
| 22 | #include <linux/pinctrl/consumer.h> |
| 23 | #include <linux/pinctrl/pinconf-generic.h> |
| 24 | #include <linux/pinctrl/pinctrl.h> |
| 25 | #include <linux/pinctrl/pinmux.h> |
| 26 | |
| 27 | #define AXP20X_GPIO_FUNCTIONS 0x7 |
| 28 | #define AXP20X_GPIO_FUNCTION_OUT_LOW 0 |
| 29 | #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1 |
| 30 | #define AXP20X_GPIO_FUNCTION_INPUT 2 |
| 31 | |
| 32 | #define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1) |
| 33 | #define AXP20X_GPIO3_FUNCTION_OUT_LOW 0 |
| 34 | #define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2 |
| 35 | #define AXP20X_GPIO3_FUNCTION_INPUT 4 |
| 36 | |
| 37 | #define AXP20X_FUNC_GPIO_OUT 0 |
| 38 | #define AXP20X_FUNC_GPIO_IN 1 |
| 39 | #define AXP20X_FUNC_LDO 2 |
| 40 | #define AXP20X_FUNC_ADC 3 |
| 41 | #define AXP20X_FUNCS_NB 4 |
| 42 | |
| 43 | #define AXP20X_MUX_GPIO_OUT 0 |
| 44 | #define AXP20X_MUX_GPIO_IN BIT(1) |
| 45 | #define AXP20X_MUX_ADC BIT(2) |
| 46 | |
| 47 | #define AXP813_MUX_ADC (BIT(2) | BIT(0)) |
| 48 | |
| 49 | struct axp20x_pctrl_desc { |
| 50 | const struct pinctrl_pin_desc *pins; |
| 51 | unsigned int npins; |
| 52 | /* Stores the pins supporting LDO function. Bit offset is pin number. */ |
| 53 | u8 ldo_mask; |
| 54 | /* Stores the pins supporting ADC function. Bit offset is pin number. */ |
| 55 | u8 adc_mask; |
| 56 | u8 gpio_status_offset; |
| 57 | u8 adc_mux; |
| 58 | }; |
| 59 | |
| 60 | struct axp20x_pinctrl_function { |
| 61 | const char *name; |
| 62 | unsigned int muxval; |
| 63 | const char **groups; |
| 64 | unsigned int ngroups; |
| 65 | }; |
| 66 | |
| 67 | struct axp20x_pctl { |
| 68 | struct gpio_chip chip; |
| 69 | struct regmap *regmap; |
| 70 | struct pinctrl_dev *pctl_dev; |
| 71 | struct device *dev; |
| 72 | const struct axp20x_pctrl_desc *desc; |
| 73 | struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB]; |
| 74 | }; |
| 75 | |
| 76 | static const struct pinctrl_pin_desc axp209_pins[] = { |
| 77 | PINCTRL_PIN(0, "GPIO0"), |
| 78 | PINCTRL_PIN(1, "GPIO1"), |
| 79 | PINCTRL_PIN(2, "GPIO2"), |
| 80 | PINCTRL_PIN(3, "GPIO3"), |
| 81 | }; |
| 82 | |
| 83 | static const struct pinctrl_pin_desc axp22x_pins[] = { |
| 84 | PINCTRL_PIN(0, "GPIO0"), |
| 85 | PINCTRL_PIN(1, "GPIO1"), |
| 86 | }; |
| 87 | |
| 88 | static const struct axp20x_pctrl_desc axp20x_data = { |
| 89 | .pins = axp209_pins, |
| 90 | .npins = ARRAY_SIZE(axp209_pins), |
| 91 | .ldo_mask = BIT(0) | BIT(1), |
| 92 | .adc_mask = BIT(0) | BIT(1), |
| 93 | .gpio_status_offset = 4, |
| 94 | .adc_mux = AXP20X_MUX_ADC, |
| 95 | }; |
| 96 | |
| 97 | static const struct axp20x_pctrl_desc axp22x_data = { |
| 98 | .pins = axp22x_pins, |
| 99 | .npins = ARRAY_SIZE(axp22x_pins), |
| 100 | .ldo_mask = BIT(0) | BIT(1), |
| 101 | .gpio_status_offset = 0, |
| 102 | }; |
| 103 | |
| 104 | static const struct axp20x_pctrl_desc axp813_data = { |
| 105 | .pins = axp22x_pins, |
| 106 | .npins = ARRAY_SIZE(axp22x_pins), |
| 107 | .ldo_mask = BIT(0) | BIT(1), |
| 108 | .adc_mask = BIT(0), |
| 109 | .gpio_status_offset = 0, |
| 110 | .adc_mux = AXP813_MUX_ADC, |
| 111 | }; |
| 112 | |
| 113 | static int axp20x_gpio_get_reg(unsigned int offset) |
| 114 | { |
| 115 | switch (offset) { |
| 116 | case 0: |
| 117 | return AXP20X_GPIO0_CTRL; |
| 118 | case 1: |
| 119 | return AXP20X_GPIO1_CTRL; |
| 120 | case 2: |
| 121 | return AXP20X_GPIO2_CTRL; |
| 122 | } |
| 123 | |
| 124 | return -EINVAL; |
| 125 | } |
| 126 | |
| 127 | static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset) |
| 128 | { |
| 129 | return pinctrl_gpio_direction_input(chip->base + offset); |
| 130 | } |
| 131 | |
| 132 | static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset) |
| 133 | { |
| 134 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
| 135 | unsigned int val; |
| 136 | int ret; |
| 137 | |
| 138 | /* AXP209 has GPIO3 status sharing the settings register */ |
| 139 | if (offset == 3) { |
| 140 | ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); |
| 141 | if (ret) |
| 142 | return ret; |
| 143 | return !!(val & BIT(0)); |
| 144 | } |
| 145 | |
| 146 | ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); |
| 147 | if (ret) |
| 148 | return ret; |
| 149 | |
| 150 | return !!(val & BIT(offset + pctl->desc->gpio_status_offset)); |
| 151 | } |
| 152 | |
| 153 | static int axp20x_gpio_get_direction(struct gpio_chip *chip, |
| 154 | unsigned int offset) |
| 155 | { |
| 156 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
| 157 | unsigned int val; |
| 158 | int reg, ret; |
| 159 | |
| 160 | /* AXP209 GPIO3 settings have a different layout */ |
| 161 | if (offset == 3) { |
| 162 | ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); |
| 163 | if (ret) |
| 164 | return ret; |
| 165 | if (val & AXP20X_GPIO3_FUNCTION_INPUT) |
| 166 | return GPIO_LINE_DIRECTION_IN; |
| 167 | |
| 168 | return GPIO_LINE_DIRECTION_OUT; |
| 169 | } |
| 170 | |
| 171 | reg = axp20x_gpio_get_reg(offset); |
| 172 | if (reg < 0) |
| 173 | return reg; |
| 174 | |
| 175 | ret = regmap_read(pctl->regmap, reg, &val); |
| 176 | if (ret) |
| 177 | return ret; |
| 178 | |
| 179 | /* |
| 180 | * This shouldn't really happen if the pin is in use already, |
| 181 | * or if it's not in use yet, it doesn't matter since we're |
| 182 | * going to change the value soon anyway. Default to output. |
| 183 | */ |
| 184 | if ((val & AXP20X_GPIO_FUNCTIONS) > 2) |
| 185 | return GPIO_LINE_DIRECTION_OUT; |
| 186 | |
| 187 | /* |
| 188 | * The GPIO directions are the three lowest values. |
| 189 | * 2 is input, 0 and 1 are output |
| 190 | */ |
| 191 | if (val & 2) |
| 192 | return GPIO_LINE_DIRECTION_IN; |
| 193 | |
| 194 | return GPIO_LINE_DIRECTION_OUT; |
| 195 | } |
| 196 | |
| 197 | static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset, |
| 198 | int value) |
| 199 | { |
| 200 | chip->set(chip, offset, value); |
| 201 | |
| 202 | return 0; |
| 203 | } |
| 204 | |
| 205 | static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset, |
| 206 | int value) |
| 207 | { |
| 208 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
| 209 | int reg; |
| 210 | |
| 211 | /* AXP209 has GPIO3 status sharing the settings register */ |
| 212 | if (offset == 3) { |
| 213 | regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, |
| 214 | AXP20X_GPIO3_FUNCTIONS, |
| 215 | value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH : |
| 216 | AXP20X_GPIO3_FUNCTION_OUT_LOW); |
| 217 | return; |
| 218 | } |
| 219 | |
| 220 | reg = axp20x_gpio_get_reg(offset); |
| 221 | if (reg < 0) |
| 222 | return; |
| 223 | |
| 224 | regmap_update_bits(pctl->regmap, reg, |
| 225 | AXP20X_GPIO_FUNCTIONS, |
| 226 | value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : |
| 227 | AXP20X_GPIO_FUNCTION_OUT_LOW); |
| 228 | } |
| 229 | |
| 230 | static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, |
| 231 | u8 config) |
| 232 | { |
| 233 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 234 | int reg; |
| 235 | |
| 236 | /* AXP209 GPIO3 settings have a different layout */ |
| 237 | if (offset == 3) { |
| 238 | return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, |
| 239 | AXP20X_GPIO3_FUNCTIONS, |
| 240 | config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW : |
| 241 | AXP20X_GPIO3_FUNCTION_INPUT); |
| 242 | } |
| 243 | |
| 244 | reg = axp20x_gpio_get_reg(offset); |
| 245 | if (reg < 0) |
| 246 | return reg; |
| 247 | |
| 248 | return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, |
| 249 | config); |
| 250 | } |
| 251 | |
| 252 | static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev) |
| 253 | { |
| 254 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 255 | |
| 256 | return ARRAY_SIZE(pctl->funcs); |
| 257 | } |
| 258 | |
| 259 | static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev, |
| 260 | unsigned int selector) |
| 261 | { |
| 262 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 263 | |
| 264 | return pctl->funcs[selector].name; |
| 265 | } |
| 266 | |
| 267 | static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, |
| 268 | unsigned int selector, |
| 269 | const char * const **groups, |
| 270 | unsigned int *num_groups) |
| 271 | { |
| 272 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 273 | |
| 274 | *groups = pctl->funcs[selector].groups; |
| 275 | *num_groups = pctl->funcs[selector].ngroups; |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev, |
| 281 | unsigned int function, unsigned int group) |
| 282 | { |
| 283 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 284 | unsigned int mask; |
| 285 | |
| 286 | /* Every pin supports GPIO_OUT and GPIO_IN functions */ |
| 287 | if (function <= AXP20X_FUNC_GPIO_IN) |
| 288 | return axp20x_pmx_set(pctldev, group, |
| 289 | pctl->funcs[function].muxval); |
| 290 | |
| 291 | if (function == AXP20X_FUNC_LDO) |
| 292 | mask = pctl->desc->ldo_mask; |
| 293 | else |
| 294 | mask = pctl->desc->adc_mask; |
| 295 | |
| 296 | if (!(BIT(group) & mask)) |
| 297 | return -EINVAL; |
| 298 | |
| 299 | /* |
| 300 | * We let the regulator framework handle the LDO muxing as muxing bits |
| 301 | * are basically also regulators on/off bits. It's better not to enforce |
| 302 | * any state of the regulator when selecting LDO mux so that we don't |
| 303 | * interfere with the regulator driver. |
| 304 | */ |
| 305 | if (function == AXP20X_FUNC_LDO) |
| 306 | return 0; |
| 307 | |
| 308 | return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval); |
| 309 | } |
| 310 | |
| 311 | static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 312 | struct pinctrl_gpio_range *range, |
| 313 | unsigned int offset, bool input) |
| 314 | { |
| 315 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 316 | |
| 317 | if (input) |
| 318 | return axp20x_pmx_set(pctldev, offset, |
| 319 | pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval); |
| 320 | |
| 321 | return axp20x_pmx_set(pctldev, offset, |
| 322 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval); |
| 323 | } |
| 324 | |
| 325 | static const struct pinmux_ops axp20x_pmx_ops = { |
| 326 | .get_functions_count = axp20x_pmx_func_cnt, |
| 327 | .get_function_name = axp20x_pmx_func_name, |
| 328 | .get_function_groups = axp20x_pmx_func_groups, |
| 329 | .set_mux = axp20x_pmx_set_mux, |
| 330 | .gpio_set_direction = axp20x_pmx_gpio_set_direction, |
| 331 | .strict = true, |
| 332 | }; |
| 333 | |
| 334 | static int axp20x_groups_cnt(struct pinctrl_dev *pctldev) |
| 335 | { |
| 336 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 337 | |
| 338 | return pctl->desc->npins; |
| 339 | } |
| 340 | |
| 341 | static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, |
| 342 | const unsigned int **pins, unsigned int *num_pins) |
| 343 | { |
| 344 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 345 | |
| 346 | *pins = (unsigned int *)&pctl->desc->pins[selector]; |
| 347 | *num_pins = 1; |
| 348 | |
| 349 | return 0; |
| 350 | } |
| 351 | |
| 352 | static const char *axp20x_group_name(struct pinctrl_dev *pctldev, |
| 353 | unsigned int selector) |
| 354 | { |
| 355 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 356 | |
| 357 | return pctl->desc->pins[selector].name; |
| 358 | } |
| 359 | |
| 360 | static const struct pinctrl_ops axp20x_pctrl_ops = { |
| 361 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
| 362 | .dt_free_map = pinconf_generic_dt_free_map, |
| 363 | .get_groups_count = axp20x_groups_cnt, |
| 364 | .get_group_name = axp20x_group_name, |
| 365 | .get_group_pins = axp20x_group_pins, |
| 366 | }; |
| 367 | |
| 368 | static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask, |
| 369 | unsigned int mask_len, |
| 370 | struct axp20x_pinctrl_function *func, |
| 371 | const struct pinctrl_pin_desc *pins) |
| 372 | { |
| 373 | unsigned long int mask_cpy = mask; |
| 374 | const char **group; |
| 375 | unsigned int ngroups = hweight8(mask); |
| 376 | int bit; |
| 377 | |
| 378 | func->ngroups = ngroups; |
| 379 | if (func->ngroups > 0) { |
| 380 | func->groups = devm_kcalloc(dev, |
| 381 | ngroups, sizeof(const char *), |
| 382 | GFP_KERNEL); |
| 383 | if (!func->groups) |
| 384 | return -ENOMEM; |
| 385 | group = func->groups; |
| 386 | for_each_set_bit(bit, &mask_cpy, mask_len) { |
| 387 | *group = pins[bit].name; |
| 388 | group++; |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | static int axp20x_build_funcs_groups(struct platform_device *pdev) |
| 396 | { |
| 397 | struct axp20x_pctl *pctl = platform_get_drvdata(pdev); |
| 398 | int i, ret, pin, npins = pctl->desc->npins; |
| 399 | |
| 400 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out"; |
| 401 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT; |
| 402 | pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in"; |
| 403 | pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN; |
| 404 | pctl->funcs[AXP20X_FUNC_LDO].name = "ldo"; |
| 405 | /* |
| 406 | * Muxval for LDO is useless as we won't use it. |
| 407 | * See comment in axp20x_pmx_set_mux. |
| 408 | */ |
| 409 | pctl->funcs[AXP20X_FUNC_ADC].name = "adc"; |
| 410 | pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux; |
| 411 | |
| 412 | /* Every pin supports GPIO_OUT and GPIO_IN functions */ |
| 413 | for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) { |
| 414 | pctl->funcs[i].ngroups = npins; |
| 415 | pctl->funcs[i].groups = devm_kcalloc(&pdev->dev, |
| 416 | npins, sizeof(char *), |
| 417 | GFP_KERNEL); |
| 418 | if (!pctl->funcs[i].groups) |
| 419 | return -ENOMEM; |
| 420 | for (pin = 0; pin < npins; pin++) |
| 421 | pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name; |
| 422 | } |
| 423 | |
| 424 | ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask, |
| 425 | npins, &pctl->funcs[AXP20X_FUNC_LDO], |
| 426 | pctl->desc->pins); |
| 427 | if (ret) |
| 428 | return ret; |
| 429 | |
| 430 | ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask, |
| 431 | npins, &pctl->funcs[AXP20X_FUNC_ADC], |
| 432 | pctl->desc->pins); |
| 433 | if (ret) |
| 434 | return ret; |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | static const struct of_device_id axp20x_pctl_match[] = { |
| 440 | { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, }, |
| 441 | { .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, }, |
| 442 | { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, }, |
| 443 | { } |
| 444 | }; |
| 445 | MODULE_DEVICE_TABLE(of, axp20x_pctl_match); |
| 446 | |
| 447 | static int axp20x_pctl_probe(struct platform_device *pdev) |
| 448 | { |
| 449 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); |
| 450 | struct axp20x_pctl *pctl; |
| 451 | struct device *dev = &pdev->dev; |
| 452 | struct pinctrl_desc *pctrl_desc; |
| 453 | int ret; |
| 454 | |
| 455 | if (!of_device_is_available(pdev->dev.of_node)) |
| 456 | return -ENODEV; |
| 457 | |
| 458 | if (!axp20x) { |
| 459 | dev_err(&pdev->dev, "Parent drvdata not set\n"); |
| 460 | return -EINVAL; |
| 461 | } |
| 462 | |
| 463 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
| 464 | if (!pctl) |
| 465 | return -ENOMEM; |
| 466 | |
| 467 | pctl->chip.base = -1; |
| 468 | pctl->chip.can_sleep = true; |
| 469 | pctl->chip.request = gpiochip_generic_request; |
| 470 | pctl->chip.free = gpiochip_generic_free; |
| 471 | pctl->chip.parent = &pdev->dev; |
| 472 | pctl->chip.label = dev_name(&pdev->dev); |
| 473 | pctl->chip.owner = THIS_MODULE; |
| 474 | pctl->chip.get = axp20x_gpio_get; |
| 475 | pctl->chip.get_direction = axp20x_gpio_get_direction; |
| 476 | pctl->chip.set = axp20x_gpio_set; |
| 477 | pctl->chip.direction_input = axp20x_gpio_input; |
| 478 | pctl->chip.direction_output = axp20x_gpio_output; |
| 479 | |
| 480 | pctl->desc = of_device_get_match_data(dev); |
| 481 | |
| 482 | pctl->chip.ngpio = pctl->desc->npins; |
| 483 | |
| 484 | pctl->regmap = axp20x->regmap; |
| 485 | pctl->dev = &pdev->dev; |
| 486 | |
| 487 | platform_set_drvdata(pdev, pctl); |
| 488 | |
| 489 | ret = axp20x_build_funcs_groups(pdev); |
| 490 | if (ret) { |
| 491 | dev_err(&pdev->dev, "failed to build groups\n"); |
| 492 | return ret; |
| 493 | } |
| 494 | |
| 495 | pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL); |
| 496 | if (!pctrl_desc) |
| 497 | return -ENOMEM; |
| 498 | |
| 499 | pctrl_desc->name = dev_name(&pdev->dev); |
| 500 | pctrl_desc->owner = THIS_MODULE; |
| 501 | pctrl_desc->pins = pctl->desc->pins; |
| 502 | pctrl_desc->npins = pctl->desc->npins; |
| 503 | pctrl_desc->pctlops = &axp20x_pctrl_ops; |
| 504 | pctrl_desc->pmxops = &axp20x_pmx_ops; |
| 505 | |
| 506 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); |
| 507 | if (IS_ERR(pctl->pctl_dev)) { |
| 508 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
| 509 | return PTR_ERR(pctl->pctl_dev); |
| 510 | } |
| 511 | |
| 512 | ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl); |
| 513 | if (ret) { |
| 514 | dev_err(&pdev->dev, "Failed to register GPIO chip\n"); |
| 515 | return ret; |
| 516 | } |
| 517 | |
| 518 | ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev), |
| 519 | pctl->desc->pins->number, |
| 520 | pctl->desc->pins->number, |
| 521 | pctl->desc->npins); |
| 522 | if (ret) { |
| 523 | dev_err(&pdev->dev, "failed to add pin range\n"); |
| 524 | return ret; |
| 525 | } |
| 526 | |
| 527 | dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n"); |
| 528 | |
| 529 | return 0; |
| 530 | } |
| 531 | |
| 532 | static struct platform_driver axp20x_pctl_driver = { |
| 533 | .probe = axp20x_pctl_probe, |
| 534 | .driver = { |
| 535 | .name = "axp20x-gpio", |
| 536 | .of_match_table = axp20x_pctl_match, |
| 537 | }, |
| 538 | }; |
| 539 | |
| 540 | module_platform_driver(axp20x_pctl_driver); |
| 541 | |
| 542 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |
| 543 | MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>"); |
| 544 | MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver"); |
| 545 | MODULE_LICENSE("GPL"); |