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Merge tag 'perf-tools-fixes-for-v6.17-2025-09-16' of git://git.kernel.org/pub/scm...
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-at91-pio4.c
... / ...
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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for the Atmel PIO4 controller
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9#include <dt-bindings/pinctrl/at91.h>
10
11#include <linux/clk.h>
12#include <linux/gpio/driver.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/seq_file.h>
19#include <linux/slab.h>
20
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25
26#include "core.h"
27#include "pinconf.h"
28#include "pinctrl-utils.h"
29
30/*
31 * Warning:
32 * In order to not introduce confusion between Atmel PIO groups and pinctrl
33 * framework groups, Atmel PIO groups will be called banks, line is kept to
34 * designed the pin id into this bank.
35 */
36
37#define ATMEL_PIO_MSKR 0x0000
38#define ATMEL_PIO_CFGR 0x0004
39#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
40#define ATMEL_PIO_DIR_MASK BIT(8)
41#define ATMEL_PIO_PUEN_MASK BIT(9)
42#define ATMEL_PIO_PDEN_MASK BIT(10)
43#define ATMEL_PIO_SR_MASK BIT(11)
44#define ATMEL_PIO_IFEN_MASK BIT(12)
45#define ATMEL_PIO_IFSCEN_MASK BIT(13)
46#define ATMEL_PIO_OPD_MASK BIT(14)
47#define ATMEL_PIO_SCHMITT_MASK BIT(15)
48#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
49#define ATMEL_PIO_DRVSTR_OFFSET 16
50#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
51#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
52#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
53#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
54#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
55#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
56#define ATMEL_PIO_PDSR 0x0008
57#define ATMEL_PIO_LOCKSR 0x000C
58#define ATMEL_PIO_SODR 0x0010
59#define ATMEL_PIO_CODR 0x0014
60#define ATMEL_PIO_ODSR 0x0018
61#define ATMEL_PIO_IER 0x0020
62#define ATMEL_PIO_IDR 0x0024
63#define ATMEL_PIO_IMR 0x0028
64#define ATMEL_PIO_ISR 0x002C
65#define ATMEL_PIO_IOFR 0x003C
66
67#define ATMEL_PIO_NPINS_PER_BANK 32
68#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
69#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
70#define ATMEL_PIO_BANK_OFFSET 0x40
71
72#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
73#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
74#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
75
76/* Custom pinconf parameters */
77#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
78
79/**
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
81 * @nbanks: number of PIO banks
82 * @last_bank_count: number of lines in the last bank (can be less than
83 * the rest of the banks).
84 * @slew_rate_support: slew rate support
85 */
86struct atmel_pioctrl_data {
87 unsigned int nbanks;
88 unsigned int last_bank_count;
89 unsigned int slew_rate_support;
90};
91
92struct atmel_group {
93 const char *name;
94 u32 pin;
95};
96
97struct atmel_pin {
98 unsigned int pin_id;
99 unsigned int mux;
100 unsigned int ioset;
101 unsigned int bank;
102 unsigned int line;
103 const char *device;
104};
105
106/**
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
108 * @reg_base: base address of the controller.
109 * @clk: clock of the controller.
110 * @nbanks: number of PIO groups, it can vary depending on the SoC.
111 * @pinctrl_dev: pinctrl device registered.
112 * @groups: groups table to provide group name and pin in the group to pinctrl.
113 * @group_names: group names table to provide all the group/pin names to
114 * pinctrl or gpio.
115 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
116 * fields are set at probe time. Other ones are set when parsing dt
117 * pinctrl.
118 * @npins: number of pins.
119 * @gpio_chip: gpio chip registered.
120 * @irq_domain: irq domain for the gpio controller.
121 * @irqs: table containing the hw irq number of the bank. The index of the
122 * table is the bank id.
123 * @pm_wakeup_sources: bitmap of wakeup sources (lines)
124 * @pm_suspend_backup: backup/restore register values on suspend/resume
125 * @dev: device entry for the Atmel PIO controller.
126 * @node: node of the Atmel PIO controller.
127 * @slew_rate_support: slew rate support
128 */
129struct atmel_pioctrl {
130 void __iomem *reg_base;
131 struct clk *clk;
132 unsigned int nbanks;
133 struct pinctrl_dev *pinctrl_dev;
134 struct atmel_group *groups;
135 const char * const *group_names;
136 struct atmel_pin **pins;
137 unsigned int npins;
138 struct gpio_chip *gpio_chip;
139 struct irq_domain *irq_domain;
140 int *irqs;
141 unsigned int *pm_wakeup_sources;
142 struct {
143 u32 imr;
144 u32 odsr;
145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
146 } *pm_suspend_backup;
147 struct device *dev;
148 struct device_node *node;
149 unsigned int slew_rate_support;
150};
151
152static const char * const atmel_functions[] = {
153 "GPIO", "A", "B", "C", "D", "E", "F", "G"
154};
155
156static const struct pinconf_generic_params atmel_custom_bindings[] = {
157 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
158};
159
160/* --- GPIO --- */
161static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
162 unsigned int bank, unsigned int reg)
163{
164 return readl_relaxed(atmel_pioctrl->reg_base
165 + ATMEL_PIO_BANK_OFFSET * bank + reg);
166}
167
168static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
169 unsigned int bank, unsigned int reg,
170 unsigned int val)
171{
172 writel_relaxed(val, atmel_pioctrl->reg_base
173 + ATMEL_PIO_BANK_OFFSET * bank + reg);
174}
175
176static void atmel_gpio_irq_ack(struct irq_data *d)
177{
178 /*
179 * Nothing to do, interrupt is cleared when reading the status
180 * register.
181 */
182}
183
184static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
185{
186 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
187 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
188 unsigned int reg;
189
190 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
191 BIT(pin->line));
192 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
193 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
194
195 switch (type) {
196 case IRQ_TYPE_EDGE_RISING:
197 irq_set_handler_locked(d, handle_edge_irq);
198 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
199 break;
200 case IRQ_TYPE_EDGE_FALLING:
201 irq_set_handler_locked(d, handle_edge_irq);
202 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
203 break;
204 case IRQ_TYPE_EDGE_BOTH:
205 irq_set_handler_locked(d, handle_edge_irq);
206 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
207 break;
208 case IRQ_TYPE_LEVEL_LOW:
209 irq_set_handler_locked(d, handle_level_irq);
210 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
211 break;
212 case IRQ_TYPE_LEVEL_HIGH:
213 irq_set_handler_locked(d, handle_level_irq);
214 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
215 break;
216 case IRQ_TYPE_NONE:
217 default:
218 return -EINVAL;
219 }
220
221 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
222
223 return 0;
224}
225
226static void atmel_gpio_irq_mask(struct irq_data *d)
227{
228 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
229 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
230
231 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
232 BIT(pin->line));
233}
234
235static void atmel_gpio_irq_unmask(struct irq_data *d)
236{
237 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
238 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
239
240 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
241 BIT(pin->line));
242}
243
244static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
245{
246 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
247 int bank = ATMEL_PIO_BANK(d->hwirq);
248 int line = ATMEL_PIO_LINE(d->hwirq);
249
250 /* The gpio controller has one interrupt line per bank. */
251 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
252
253 if (on)
254 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
255 else
256 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
257
258 return 0;
259}
260
261static struct irq_chip atmel_gpio_irq_chip = {
262 .name = "GPIO",
263 .irq_ack = atmel_gpio_irq_ack,
264 .irq_mask = atmel_gpio_irq_mask,
265 .irq_unmask = atmel_gpio_irq_unmask,
266 .irq_set_type = atmel_gpio_irq_set_type,
267 .irq_set_wake = pm_sleep_ptr(atmel_gpio_irq_set_wake),
268};
269
270static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
271{
272 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
273
274 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
275}
276
277static void atmel_gpio_irq_handler(struct irq_desc *desc)
278{
279 unsigned int irq = irq_desc_get_irq(desc);
280 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
281 struct irq_chip *chip = irq_desc_get_chip(desc);
282 unsigned long isr;
283 int n, bank = -1;
284
285 /* Find from which bank is the irq received. */
286 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
287 if (atmel_pioctrl->irqs[n] == irq) {
288 bank = n;
289 break;
290 }
291 }
292
293 if (bank < 0) {
294 dev_err(atmel_pioctrl->dev,
295 "no bank associated to irq %u\n", irq);
296 return;
297 }
298
299 chained_irq_enter(chip, desc);
300
301 for (;;) {
302 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
303 ATMEL_PIO_ISR);
304 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
305 ATMEL_PIO_IMR);
306 if (!isr)
307 break;
308
309 for_each_set_bit(n, &isr, BITS_PER_LONG)
310 generic_handle_irq(atmel_gpio_to_irq(
311 atmel_pioctrl->gpio_chip,
312 bank * ATMEL_PIO_NPINS_PER_BANK + n));
313 }
314
315 chained_irq_exit(chip, desc);
316}
317
318static int atmel_gpio_direction_input(struct gpio_chip *chip,
319 unsigned int offset)
320{
321 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
322 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
323 unsigned int reg;
324
325 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
326 BIT(pin->line));
327 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
328 reg &= ~ATMEL_PIO_DIR_MASK;
329 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
330
331 return 0;
332}
333
334static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
335{
336 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
337 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
338 unsigned int reg;
339
340 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
341
342 return !!(reg & BIT(pin->line));
343}
344
345static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
346 unsigned long *bits)
347{
348 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
349 unsigned int bank;
350
351 bitmap_zero(bits, atmel_pioctrl->npins);
352
353 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
354 unsigned int word = bank;
355 unsigned int offset = 0;
356 unsigned int reg;
357
358#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
359 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
360 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
361#endif
362 if (!mask[word])
363 continue;
364
365 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
366 bits[word] |= mask[word] & (reg << offset);
367 }
368
369 return 0;
370}
371
372static int atmel_gpio_direction_output(struct gpio_chip *chip,
373 unsigned int offset,
374 int value)
375{
376 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
377 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
378 unsigned int reg;
379
380 atmel_gpio_write(atmel_pioctrl, pin->bank,
381 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
382 BIT(pin->line));
383
384 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
385 BIT(pin->line));
386 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
387 reg |= ATMEL_PIO_DIR_MASK;
388 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
389
390 return 0;
391}
392
393static int atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
394{
395 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
396 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
397
398 atmel_gpio_write(atmel_pioctrl, pin->bank,
399 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
400 BIT(pin->line));
401
402 return 0;
403}
404
405static int atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
406 unsigned long *bits)
407{
408 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
409 unsigned int bank;
410
411 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
412 unsigned int bitmask;
413 unsigned int word = bank;
414
415/*
416 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
417 * two 32bit words to handle the whole bitmask
418 */
419#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
420 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
421#endif
422 if (!mask[word])
423 continue;
424
425 bitmask = mask[word] & bits[word];
426 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
427
428 bitmask = mask[word] & ~bits[word];
429 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
430
431#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
432 mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
433 bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
434#endif
435 }
436
437 return 0;
438}
439
440static struct gpio_chip atmel_gpio_chip = {
441 .direction_input = atmel_gpio_direction_input,
442 .get = atmel_gpio_get,
443 .get_multiple = atmel_gpio_get_multiple,
444 .direction_output = atmel_gpio_direction_output,
445 .set = atmel_gpio_set,
446 .set_multiple = atmel_gpio_set_multiple,
447 .to_irq = atmel_gpio_to_irq,
448 .base = 0,
449};
450
451/* --- PINCTRL --- */
452static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
453 unsigned int pin_id)
454{
455 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
456 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
457 unsigned int line = atmel_pioctrl->pins[pin_id]->line;
458 void __iomem *addr = atmel_pioctrl->reg_base
459 + bank * ATMEL_PIO_BANK_OFFSET;
460
461 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
462 /* Have to set MSKR first, to access the right pin CFGR. */
463 wmb();
464
465 return readl_relaxed(addr + ATMEL_PIO_CFGR);
466}
467
468static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
469 unsigned int pin_id, u32 conf)
470{
471 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
472 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
473 unsigned int line = atmel_pioctrl->pins[pin_id]->line;
474 void __iomem *addr = atmel_pioctrl->reg_base
475 + bank * ATMEL_PIO_BANK_OFFSET;
476
477 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
478 /* Have to set MSKR first, to access the right pin CFGR. */
479 wmb();
480 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
481}
482
483static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
484{
485 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
486
487 return atmel_pioctrl->npins;
488}
489
490static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
491 unsigned int selector)
492{
493 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
494
495 return atmel_pioctrl->groups[selector].name;
496}
497
498static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
499 unsigned int selector,
500 const unsigned int **pins,
501 unsigned int *num_pins)
502{
503 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
504
505 *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
506 *num_pins = 1;
507
508 return 0;
509}
510
511static struct atmel_group *
512atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
513{
514 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
515 int i;
516
517 for (i = 0; i < atmel_pioctrl->npins; i++) {
518 struct atmel_group *grp = atmel_pioctrl->groups + i;
519
520 if (grp->pin == pin)
521 return grp;
522 }
523
524 return NULL;
525}
526
527static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
528 struct device_node *np,
529 u32 pinfunc, const char **grp_name,
530 const char **func_name)
531{
532 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
533 unsigned int pin_id, func_id;
534 struct atmel_group *grp;
535
536 pin_id = ATMEL_GET_PIN_NO(pinfunc);
537 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
538
539 if (func_id >= ARRAY_SIZE(atmel_functions))
540 return -EINVAL;
541
542 *func_name = atmel_functions[func_id];
543
544 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
545 if (!grp)
546 return -EINVAL;
547 *grp_name = grp->name;
548
549 atmel_pioctrl->pins[pin_id]->mux = func_id;
550 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
551 /* Want the device name not the group one. */
552 if (np->parent == atmel_pioctrl->node)
553 atmel_pioctrl->pins[pin_id]->device = np->name;
554 else
555 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
556
557 return 0;
558}
559
560static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
561 struct device_node *np,
562 struct pinctrl_map **map,
563 unsigned int *reserved_maps,
564 unsigned int *num_maps)
565{
566 unsigned int num_pins, num_configs, reserve;
567 unsigned long *configs;
568 struct property *pins;
569 u32 pinfunc;
570 int ret, i;
571
572 pins = of_find_property(np, "pinmux", NULL);
573 if (!pins)
574 return -EINVAL;
575
576 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
577 &num_configs);
578 if (ret < 0) {
579 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
580 np);
581 return ret;
582 }
583
584 num_pins = pins->length / sizeof(u32);
585 if (!num_pins) {
586 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
587 ret = -EINVAL;
588 goto exit;
589 }
590
591 /*
592 * Reserve maps, at least there is a mux map and an optional conf
593 * map for each pin.
594 */
595 reserve = 1;
596 if (num_configs)
597 reserve++;
598 reserve *= num_pins;
599 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
600 reserve);
601 if (ret < 0)
602 goto exit;
603
604 for (i = 0; i < num_pins; i++) {
605 const char *group, *func;
606
607 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
608 if (ret)
609 goto exit;
610
611 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
612 &func);
613 if (ret)
614 goto exit;
615
616 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
617 group, func);
618 if (ret)
619 goto exit;
620
621 if (num_configs) {
622 ret = pinctrl_utils_add_map_configs(pctldev, map,
623 reserved_maps, num_maps, group,
624 configs, num_configs,
625 PIN_MAP_TYPE_CONFIGS_GROUP);
626 if (ret < 0)
627 goto exit;
628 }
629 }
630
631exit:
632 kfree(configs);
633 return ret;
634}
635
636static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
637 struct device_node *np_config,
638 struct pinctrl_map **map,
639 unsigned int *num_maps)
640{
641 unsigned int reserved_maps;
642 int ret;
643
644 *map = NULL;
645 *num_maps = 0;
646 reserved_maps = 0;
647
648 /*
649 * If all the pins of a device have the same configuration (or no one),
650 * it is useless to add a subnode, so directly parse node referenced by
651 * phandle.
652 */
653 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
654 &reserved_maps, num_maps);
655 if (ret) {
656 for_each_child_of_node_scoped(np_config, np) {
657 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
658 &reserved_maps, num_maps);
659 if (ret < 0)
660 break;
661 }
662 }
663
664 if (ret < 0) {
665 pinctrl_utils_free_map(pctldev, *map, *num_maps);
666 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
667 np_config);
668 }
669
670 return ret;
671}
672
673static const struct pinctrl_ops atmel_pctlops = {
674 .get_groups_count = atmel_pctl_get_groups_count,
675 .get_group_name = atmel_pctl_get_group_name,
676 .get_group_pins = atmel_pctl_get_group_pins,
677 .dt_node_to_map = atmel_pctl_dt_node_to_map,
678 .dt_free_map = pinctrl_utils_free_map,
679};
680
681static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
682{
683 return ARRAY_SIZE(atmel_functions);
684}
685
686static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
687 unsigned int selector)
688{
689 return atmel_functions[selector];
690}
691
692static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
693 unsigned int selector,
694 const char * const **groups,
695 unsigned * const num_groups)
696{
697 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
698
699 *groups = atmel_pioctrl->group_names;
700 *num_groups = atmel_pioctrl->npins;
701
702 return 0;
703}
704
705static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
706 unsigned int function,
707 unsigned int group)
708{
709 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
710 unsigned int pin;
711 u32 conf;
712
713 dev_dbg(pctldev->dev, "enable function %s group %s\n",
714 atmel_functions[function], atmel_pioctrl->groups[group].name);
715
716 pin = atmel_pioctrl->groups[group].pin;
717 conf = atmel_pin_config_read(pctldev, pin);
718 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
719 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
720 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
721 atmel_pin_config_write(pctldev, pin, conf);
722
723 return 0;
724}
725
726static const struct pinmux_ops atmel_pmxops = {
727 .get_functions_count = atmel_pmx_get_functions_count,
728 .get_function_name = atmel_pmx_get_function_name,
729 .get_function_groups = atmel_pmx_get_function_groups,
730 .set_mux = atmel_pmx_set_mux,
731};
732
733static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
734 unsigned int group,
735 unsigned long *config)
736{
737 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
738 unsigned int param = pinconf_to_config_param(*config), arg = 0;
739 struct atmel_group *grp = atmel_pioctrl->groups + group;
740 unsigned int pin_id = grp->pin;
741 u32 res;
742
743 res = atmel_pin_config_read(pctldev, pin_id);
744
745 switch (param) {
746 case PIN_CONFIG_BIAS_PULL_UP:
747 if (!(res & ATMEL_PIO_PUEN_MASK))
748 return -EINVAL;
749 arg = 1;
750 break;
751 case PIN_CONFIG_BIAS_PULL_DOWN:
752 if ((res & ATMEL_PIO_PUEN_MASK) ||
753 (!(res & ATMEL_PIO_PDEN_MASK)))
754 return -EINVAL;
755 arg = 1;
756 break;
757 case PIN_CONFIG_BIAS_DISABLE:
758 if ((res & ATMEL_PIO_PUEN_MASK) ||
759 ((res & ATMEL_PIO_PDEN_MASK)))
760 return -EINVAL;
761 arg = 1;
762 break;
763 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
764 if (!(res & ATMEL_PIO_OPD_MASK))
765 return -EINVAL;
766 arg = 1;
767 break;
768 case PIN_CONFIG_DRIVE_PUSH_PULL:
769 if (res & ATMEL_PIO_OPD_MASK)
770 return -EINVAL;
771 arg = 1;
772 break;
773 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
774 if (!(res & ATMEL_PIO_SCHMITT_MASK))
775 return -EINVAL;
776 arg = 1;
777 break;
778 case PIN_CONFIG_SLEW_RATE:
779 if (!atmel_pioctrl->slew_rate_support)
780 return -EOPNOTSUPP;
781 if (!(res & ATMEL_PIO_SR_MASK))
782 return -EINVAL;
783 arg = 1;
784 break;
785 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
786 if (!(res & ATMEL_PIO_DRVSTR_MASK))
787 return -EINVAL;
788 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
789 break;
790 case PIN_CONFIG_PERSIST_STATE:
791 return -ENOTSUPP;
792 default:
793 return -ENOTSUPP;
794 }
795
796 *config = pinconf_to_config_packed(param, arg);
797 return 0;
798}
799
800static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
801 unsigned int group,
802 unsigned long *configs,
803 unsigned int num_configs)
804{
805 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
806 struct atmel_group *grp = atmel_pioctrl->groups + group;
807 unsigned int bank, pin, pin_id = grp->pin;
808 u32 mask, conf = 0;
809 int i;
810
811 conf = atmel_pin_config_read(pctldev, pin_id);
812
813 /* Keep slew rate enabled by default. */
814 if (atmel_pioctrl->slew_rate_support)
815 conf |= ATMEL_PIO_SR_MASK;
816
817 for (i = 0; i < num_configs; i++) {
818 unsigned int param = pinconf_to_config_param(configs[i]);
819 unsigned int arg = pinconf_to_config_argument(configs[i]);
820
821 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
822 __func__, pin_id, configs[i]);
823
824 switch (param) {
825 case PIN_CONFIG_BIAS_DISABLE:
826 conf &= (~ATMEL_PIO_PUEN_MASK);
827 conf &= (~ATMEL_PIO_PDEN_MASK);
828 break;
829 case PIN_CONFIG_BIAS_PULL_UP:
830 conf |= ATMEL_PIO_PUEN_MASK;
831 conf &= (~ATMEL_PIO_PDEN_MASK);
832 break;
833 case PIN_CONFIG_BIAS_PULL_DOWN:
834 conf |= ATMEL_PIO_PDEN_MASK;
835 conf &= (~ATMEL_PIO_PUEN_MASK);
836 break;
837 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
838 conf |= ATMEL_PIO_OPD_MASK;
839 break;
840 case PIN_CONFIG_DRIVE_PUSH_PULL:
841 conf &= ~ATMEL_PIO_OPD_MASK;
842 break;
843 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
844 if (arg == 0)
845 conf |= ATMEL_PIO_SCHMITT_MASK;
846 else
847 conf &= (~ATMEL_PIO_SCHMITT_MASK);
848 break;
849 case PIN_CONFIG_INPUT_DEBOUNCE:
850 if (arg == 0) {
851 conf &= (~ATMEL_PIO_IFEN_MASK);
852 conf &= (~ATMEL_PIO_IFSCEN_MASK);
853 } else {
854 /*
855 * We don't care about the debounce value for several reasons:
856 * - can't have different debounce periods inside a same group,
857 * - the register to configure this period is a secure register.
858 * The debouncing filter can filter a pulse with a duration of less
859 * than 1/2 slow clock period.
860 */
861 conf |= ATMEL_PIO_IFEN_MASK;
862 conf |= ATMEL_PIO_IFSCEN_MASK;
863 }
864 break;
865 case PIN_CONFIG_OUTPUT:
866 conf |= ATMEL_PIO_DIR_MASK;
867 bank = ATMEL_PIO_BANK(pin_id);
868 pin = ATMEL_PIO_LINE(pin_id);
869 mask = 1 << pin;
870
871 if (arg == 0) {
872 writel_relaxed(mask, atmel_pioctrl->reg_base +
873 bank * ATMEL_PIO_BANK_OFFSET +
874 ATMEL_PIO_CODR);
875 } else {
876 writel_relaxed(mask, atmel_pioctrl->reg_base +
877 bank * ATMEL_PIO_BANK_OFFSET +
878 ATMEL_PIO_SODR);
879 }
880 break;
881 case PIN_CONFIG_SLEW_RATE:
882 if (!atmel_pioctrl->slew_rate_support)
883 break;
884 /* And remove it if explicitly requested. */
885 if (arg == 0)
886 conf &= ~ATMEL_PIO_SR_MASK;
887 break;
888 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
889 switch (arg) {
890 case ATMEL_PIO_DRVSTR_LO:
891 case ATMEL_PIO_DRVSTR_ME:
892 case ATMEL_PIO_DRVSTR_HI:
893 conf &= (~ATMEL_PIO_DRVSTR_MASK);
894 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
895 break;
896 default:
897 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
898 }
899 break;
900 case PIN_CONFIG_PERSIST_STATE:
901 return -ENOTSUPP;
902 default:
903 dev_warn(pctldev->dev,
904 "unsupported configuration parameter: %u\n",
905 param);
906 continue;
907 }
908 }
909
910 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
911 atmel_pin_config_write(pctldev, pin_id, conf);
912
913 return 0;
914}
915
916static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev,
917 unsigned pin,
918 unsigned long *configs,
919 unsigned num_configs)
920{
921 struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);
922
923 return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs);
924}
925
926static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev,
927 unsigned pin,
928 unsigned long *configs)
929{
930 struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);
931
932 return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs);
933}
934
935static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
936 struct seq_file *s,
937 unsigned int pin_id)
938{
939 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
940 u32 conf;
941
942 if (!atmel_pioctrl->pins[pin_id]->device)
943 return;
944
945 seq_printf(s, " (%s, ioset %u) ",
946 atmel_pioctrl->pins[pin_id]->device,
947 atmel_pioctrl->pins[pin_id]->ioset);
948
949 conf = atmel_pin_config_read(pctldev, pin_id);
950 if (conf & ATMEL_PIO_PUEN_MASK)
951 seq_printf(s, "%s ", "pull-up");
952 if (conf & ATMEL_PIO_PDEN_MASK)
953 seq_printf(s, "%s ", "pull-down");
954 if (conf & ATMEL_PIO_IFEN_MASK)
955 seq_printf(s, "%s ", "debounce");
956 if (conf & ATMEL_PIO_OPD_MASK)
957 seq_printf(s, "%s ", "open-drain");
958 else
959 seq_printf(s, "%s ", "push-pull");
960 if (conf & ATMEL_PIO_SCHMITT_MASK)
961 seq_printf(s, "%s ", "schmitt");
962 if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
963 seq_printf(s, "%s ", "slew-rate");
964 if (conf & ATMEL_PIO_DRVSTR_MASK) {
965 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
966 case ATMEL_PIO_DRVSTR_ME:
967 seq_printf(s, "%s ", "medium-drive");
968 break;
969 case ATMEL_PIO_DRVSTR_HI:
970 seq_printf(s, "%s ", "high-drive");
971 break;
972 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
973 default:
974 seq_printf(s, "%s ", "low-drive");
975 }
976 }
977}
978
979static const struct pinconf_ops atmel_confops = {
980 .pin_config_group_get = atmel_conf_pin_config_group_get,
981 .pin_config_group_set = atmel_conf_pin_config_group_set,
982 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
983 .pin_config_set = atmel_conf_pin_config_set,
984 .pin_config_get = atmel_conf_pin_config_get,
985};
986
987static struct pinctrl_desc atmel_pinctrl_desc = {
988 .name = "atmel_pinctrl",
989 .confops = &atmel_confops,
990 .pctlops = &atmel_pctlops,
991 .pmxops = &atmel_pmxops,
992};
993
994static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
995{
996 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
997 int i, j;
998
999 /*
1000 * For each bank, save IMR to restore it later and disable all GPIO
1001 * interrupts excepting the ones marked as wakeup sources.
1002 */
1003 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1004 atmel_pioctrl->pm_suspend_backup[i].imr =
1005 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
1006 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
1007 ~atmel_pioctrl->pm_wakeup_sources[i]);
1008 atmel_pioctrl->pm_suspend_backup[i].odsr =
1009 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
1010 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
1011 atmel_gpio_write(atmel_pioctrl, i,
1012 ATMEL_PIO_MSKR, BIT(j));
1013 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
1014 atmel_gpio_read(atmel_pioctrl, i,
1015 ATMEL_PIO_CFGR);
1016 }
1017 }
1018
1019 return 0;
1020}
1021
1022static int __maybe_unused atmel_pctrl_resume(struct device *dev)
1023{
1024 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
1025 int i, j;
1026
1027 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1028 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
1029 atmel_pioctrl->pm_suspend_backup[i].imr);
1030 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
1031 atmel_pioctrl->pm_suspend_backup[i].odsr);
1032 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
1033 atmel_gpio_write(atmel_pioctrl, i,
1034 ATMEL_PIO_MSKR, BIT(j));
1035 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
1036 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
1037 }
1038 }
1039
1040 return 0;
1041}
1042
1043static const struct dev_pm_ops atmel_pctrl_pm_ops = {
1044 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
1045};
1046
1047/*
1048 * The number of banks can be different from a SoC to another one.
1049 * We can have up to 16 banks.
1050 */
1051static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
1052 .nbanks = 4,
1053 .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
1054};
1055
1056static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
1057 .nbanks = 5,
1058 .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
1059 .slew_rate_support = 1,
1060};
1061
1062static const struct of_device_id atmel_pctrl_of_match[] = {
1063 {
1064 .compatible = "atmel,sama5d2-pinctrl",
1065 .data = &atmel_sama5d2_pioctrl_data,
1066 }, {
1067 .compatible = "microchip,sama7g5-pinctrl",
1068 .data = &microchip_sama7g5_pioctrl_data,
1069 }, {
1070 /* sentinel */
1071 }
1072};
1073
1074/*
1075 * This lock class allows to tell lockdep that parent IRQ and children IRQ do
1076 * not share the same class so it does not raise false positive
1077 */
1078static struct lock_class_key atmel_lock_key;
1079static struct lock_class_key atmel_request_key;
1080
1081static int atmel_pinctrl_probe(struct platform_device *pdev)
1082{
1083 struct device *dev = &pdev->dev;
1084 struct pinctrl_pin_desc *pin_desc;
1085 const char **group_names;
1086 int i, ret;
1087 struct atmel_pioctrl *atmel_pioctrl;
1088 const struct atmel_pioctrl_data *atmel_pioctrl_data;
1089
1090 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
1091 if (!atmel_pioctrl)
1092 return -ENOMEM;
1093 atmel_pioctrl->dev = dev;
1094 atmel_pioctrl->node = dev->of_node;
1095 platform_set_drvdata(pdev, atmel_pioctrl);
1096
1097 atmel_pioctrl_data = device_get_match_data(dev);
1098 if (!atmel_pioctrl_data)
1099 return dev_err_probe(dev, -ENODEV, "Invalid device data\n");
1100
1101 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
1102 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
1103 /* if last bank has limited number of pins, adjust accordingly */
1104 if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
1105 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
1106 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
1107 }
1108 atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
1109
1110 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1111 if (IS_ERR(atmel_pioctrl->reg_base))
1112 return PTR_ERR(atmel_pioctrl->reg_base);
1113
1114 atmel_pioctrl->clk = devm_clk_get_enabled(dev, NULL);
1115 if (IS_ERR(atmel_pioctrl->clk))
1116 return dev_err_probe(dev, PTR_ERR(atmel_pioctrl->clk), "failed to get clock\n");
1117
1118 atmel_pioctrl->pins = devm_kcalloc(dev,
1119 atmel_pioctrl->npins,
1120 sizeof(*atmel_pioctrl->pins),
1121 GFP_KERNEL);
1122 if (!atmel_pioctrl->pins)
1123 return -ENOMEM;
1124
1125 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
1126 GFP_KERNEL);
1127 if (!pin_desc)
1128 return -ENOMEM;
1129 atmel_pinctrl_desc.pins = pin_desc;
1130 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
1131 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
1132 atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
1133
1134 /* One pin is one group since a pin can achieve all functions. */
1135 group_names = devm_kcalloc(dev,
1136 atmel_pioctrl->npins, sizeof(*group_names),
1137 GFP_KERNEL);
1138 if (!group_names)
1139 return -ENOMEM;
1140 atmel_pioctrl->group_names = group_names;
1141
1142 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1143 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1144 GFP_KERNEL);
1145 if (!atmel_pioctrl->groups)
1146 return -ENOMEM;
1147 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1148 struct atmel_group *group = atmel_pioctrl->groups + i;
1149 unsigned int bank = ATMEL_PIO_BANK(i);
1150 unsigned int line = ATMEL_PIO_LINE(i);
1151
1152 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1153 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1154 if (!atmel_pioctrl->pins[i])
1155 return -ENOMEM;
1156
1157 atmel_pioctrl->pins[i]->pin_id = i;
1158 atmel_pioctrl->pins[i]->bank = bank;
1159 atmel_pioctrl->pins[i]->line = line;
1160
1161 pin_desc[i].number = i;
1162 /* Pin naming convention: P(bank_name)(bank_pin_number). */
1163 pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%u",
1164 bank + 'A', line);
1165 if (!pin_desc[i].name)
1166 return -ENOMEM;
1167
1168 group->name = group_names[i] = pin_desc[i].name;
1169 group->pin = pin_desc[i].number;
1170
1171 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1172 }
1173
1174 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1175 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1176 atmel_pioctrl->gpio_chip->label = dev_name(dev);
1177 atmel_pioctrl->gpio_chip->parent = dev;
1178 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1179 atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config;
1180
1181 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1182 atmel_pioctrl->nbanks,
1183 sizeof(*atmel_pioctrl->pm_wakeup_sources),
1184 GFP_KERNEL);
1185 if (!atmel_pioctrl->pm_wakeup_sources)
1186 return -ENOMEM;
1187
1188 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1189 atmel_pioctrl->nbanks,
1190 sizeof(*atmel_pioctrl->pm_suspend_backup),
1191 GFP_KERNEL);
1192 if (!atmel_pioctrl->pm_suspend_backup)
1193 return -ENOMEM;
1194
1195 atmel_pioctrl->irqs = devm_kcalloc(dev,
1196 atmel_pioctrl->nbanks,
1197 sizeof(*atmel_pioctrl->irqs),
1198 GFP_KERNEL);
1199 if (!atmel_pioctrl->irqs)
1200 return -ENOMEM;
1201
1202 /* There is one controller but each bank has its own irq line. */
1203 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1204 ret = platform_get_irq(pdev, i);
1205 if (ret < 0) {
1206 dev_dbg(dev, "missing irq resource for group %c\n",
1207 'A' + i);
1208 return ret;
1209 }
1210 atmel_pioctrl->irqs[i] = ret;
1211 irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
1212 dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
1213 }
1214
1215 atmel_pioctrl->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
1216 atmel_pioctrl->gpio_chip->ngpio,
1217 &irq_domain_simple_ops, NULL);
1218 if (!atmel_pioctrl->irq_domain)
1219 return dev_err_probe(dev, -ENODEV, "can't add the irq domain\n");
1220
1221 for (i = 0; i < atmel_pioctrl->npins; i++) {
1222 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1223
1224 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1225 handle_simple_irq);
1226 irq_set_chip_data(irq, atmel_pioctrl);
1227 irq_set_lockdep_class(irq, &atmel_lock_key, &atmel_request_key);
1228 dev_dbg(dev,
1229 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1230 i, irq);
1231 }
1232
1233 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1234 &atmel_pinctrl_desc,
1235 atmel_pioctrl);
1236 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1237 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1238 dev_err(dev, "pinctrl registration failed\n");
1239 goto irq_domain_remove_error;
1240 }
1241
1242 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1243 if (ret) {
1244 dev_err(dev, "failed to add gpiochip\n");
1245 goto irq_domain_remove_error;
1246 }
1247
1248 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1249 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1250 if (ret) {
1251 dev_err(dev, "failed to add gpio pin range\n");
1252 goto gpiochip_add_pin_range_error;
1253 }
1254
1255 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1256
1257 return 0;
1258
1259gpiochip_add_pin_range_error:
1260 gpiochip_remove(atmel_pioctrl->gpio_chip);
1261
1262irq_domain_remove_error:
1263 irq_domain_remove(atmel_pioctrl->irq_domain);
1264
1265 return ret;
1266}
1267
1268static struct platform_driver atmel_pinctrl_driver = {
1269 .driver = {
1270 .name = "pinctrl-at91-pio4",
1271 .of_match_table = atmel_pctrl_of_match,
1272 .pm = &atmel_pctrl_pm_ops,
1273 .suppress_bind_attrs = true,
1274 },
1275 .probe = atmel_pinctrl_probe,
1276};
1277builtin_platform_driver(atmel_pinctrl_driver);
Linux 6.x block layer and io_uring tree(s)