| 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2013 |
| 3 | * |
| 4 | * Author: Patrice Chotard <patrice.chotard@st.com> |
| 5 | * License terms: GNU General Public License (GPL) version 2 |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/types.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_device.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/gpio.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/bitops.h> |
| 24 | #include <linux/mfd/abx500.h> |
| 25 | #include <linux/mfd/abx500/ab8500.h> |
| 26 | #include <linux/mfd/abx500/ab8500-gpio.h> |
| 27 | #include <linux/pinctrl/pinctrl.h> |
| 28 | #include <linux/pinctrl/consumer.h> |
| 29 | #include <linux/pinctrl/pinmux.h> |
| 30 | #include <linux/pinctrl/pinconf.h> |
| 31 | #include <linux/pinctrl/pinconf-generic.h> |
| 32 | |
| 33 | #include "pinctrl-abx500.h" |
| 34 | |
| 35 | /* |
| 36 | * The AB9540 and AB8540 GPIO support are extended versions |
| 37 | * of the AB8500 GPIO support. |
| 38 | * The AB9540 supports an additional (7th) register so that |
| 39 | * more GPIO may be configured and used. |
| 40 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have |
| 41 | * internal pull-up and pull-down capabilities. |
| 42 | */ |
| 43 | |
| 44 | /* |
| 45 | * GPIO registers offset |
| 46 | * Bank: 0x10 |
| 47 | */ |
| 48 | #define AB8500_GPIO_SEL1_REG 0x00 |
| 49 | #define AB8500_GPIO_SEL2_REG 0x01 |
| 50 | #define AB8500_GPIO_SEL3_REG 0x02 |
| 51 | #define AB8500_GPIO_SEL4_REG 0x03 |
| 52 | #define AB8500_GPIO_SEL5_REG 0x04 |
| 53 | #define AB8500_GPIO_SEL6_REG 0x05 |
| 54 | #define AB9540_GPIO_SEL7_REG 0x06 |
| 55 | |
| 56 | #define AB8500_GPIO_DIR1_REG 0x10 |
| 57 | #define AB8500_GPIO_DIR2_REG 0x11 |
| 58 | #define AB8500_GPIO_DIR3_REG 0x12 |
| 59 | #define AB8500_GPIO_DIR4_REG 0x13 |
| 60 | #define AB8500_GPIO_DIR5_REG 0x14 |
| 61 | #define AB8500_GPIO_DIR6_REG 0x15 |
| 62 | #define AB9540_GPIO_DIR7_REG 0x16 |
| 63 | |
| 64 | #define AB8500_GPIO_OUT1_REG 0x20 |
| 65 | #define AB8500_GPIO_OUT2_REG 0x21 |
| 66 | #define AB8500_GPIO_OUT3_REG 0x22 |
| 67 | #define AB8500_GPIO_OUT4_REG 0x23 |
| 68 | #define AB8500_GPIO_OUT5_REG 0x24 |
| 69 | #define AB8500_GPIO_OUT6_REG 0x25 |
| 70 | #define AB9540_GPIO_OUT7_REG 0x26 |
| 71 | |
| 72 | #define AB8500_GPIO_PUD1_REG 0x30 |
| 73 | #define AB8500_GPIO_PUD2_REG 0x31 |
| 74 | #define AB8500_GPIO_PUD3_REG 0x32 |
| 75 | #define AB8500_GPIO_PUD4_REG 0x33 |
| 76 | #define AB8500_GPIO_PUD5_REG 0x34 |
| 77 | #define AB8500_GPIO_PUD6_REG 0x35 |
| 78 | #define AB9540_GPIO_PUD7_REG 0x36 |
| 79 | |
| 80 | #define AB8500_GPIO_IN1_REG 0x40 |
| 81 | #define AB8500_GPIO_IN2_REG 0x41 |
| 82 | #define AB8500_GPIO_IN3_REG 0x42 |
| 83 | #define AB8500_GPIO_IN4_REG 0x43 |
| 84 | #define AB8500_GPIO_IN5_REG 0x44 |
| 85 | #define AB8500_GPIO_IN6_REG 0x45 |
| 86 | #define AB9540_GPIO_IN7_REG 0x46 |
| 87 | #define AB8540_GPIO_VINSEL_REG 0x47 |
| 88 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 |
| 89 | #define AB8500_GPIO_ALTFUN_REG 0x50 |
| 90 | #define AB8500_NUM_VIR_GPIO_IRQ 16 |
| 91 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 |
| 92 | #define AB8540_GPIO_VINSEL_MASK 0x03 |
| 93 | #define AB8540_GPIOX_VBAT_START 51 |
| 94 | #define AB8540_GPIOX_VBAT_END 54 |
| 95 | |
| 96 | enum abx500_gpio_action { |
| 97 | NONE, |
| 98 | STARTUP, |
| 99 | SHUTDOWN, |
| 100 | MASK, |
| 101 | UNMASK |
| 102 | }; |
| 103 | |
| 104 | struct abx500_pinctrl { |
| 105 | struct device *dev; |
| 106 | struct pinctrl_dev *pctldev; |
| 107 | struct abx500_pinctrl_soc_data *soc; |
| 108 | struct gpio_chip chip; |
| 109 | struct ab8500 *parent; |
| 110 | struct mutex lock; |
| 111 | u32 irq_base; |
| 112 | enum abx500_gpio_action irq_action; |
| 113 | u16 rising; |
| 114 | u16 falling; |
| 115 | struct abx500_gpio_irq_cluster *irq_cluster; |
| 116 | int irq_cluster_size; |
| 117 | int irq_gpio_rising_offset; |
| 118 | int irq_gpio_falling_offset; |
| 119 | int irq_gpio_factor; |
| 120 | }; |
| 121 | |
| 122 | /** |
| 123 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl |
| 124 | * @chip: Member of the structure abx500_pinctrl |
| 125 | */ |
| 126 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) |
| 127 | { |
| 128 | return container_of(chip, struct abx500_pinctrl, chip); |
| 129 | } |
| 130 | |
| 131 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, |
| 132 | unsigned offset, bool *bit) |
| 133 | { |
| 134 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 135 | u8 pos = offset % 8; |
| 136 | u8 val; |
| 137 | int ret; |
| 138 | |
| 139 | reg += offset / 8; |
| 140 | ret = abx500_get_register_interruptible(pct->dev, |
| 141 | AB8500_MISC, reg, &val); |
| 142 | |
| 143 | *bit = !!(val & BIT(pos)); |
| 144 | |
| 145 | if (ret < 0) |
| 146 | dev_err(pct->dev, |
| 147 | "%s read reg =%x, offset=%x failed\n", |
| 148 | __func__, reg, offset); |
| 149 | |
| 150 | return ret; |
| 151 | } |
| 152 | |
| 153 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, |
| 154 | unsigned offset, int val) |
| 155 | { |
| 156 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 157 | u8 pos = offset % 8; |
| 158 | int ret; |
| 159 | |
| 160 | reg += offset / 8; |
| 161 | ret = abx500_mask_and_set_register_interruptible(pct->dev, |
| 162 | AB8500_MISC, reg, BIT(pos), val << pos); |
| 163 | if (ret < 0) |
| 164 | dev_err(pct->dev, "%s write failed\n", __func__); |
| 165 | |
| 166 | return ret; |
| 167 | } |
| 168 | |
| 169 | /** |
| 170 | * abx500_gpio_get() - Get the particular GPIO value |
| 171 | * @chip: Gpio device |
| 172 | * @offset: GPIO number to read |
| 173 | */ |
| 174 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 175 | { |
| 176 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 177 | bool bit; |
| 178 | int ret; |
| 179 | |
| 180 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, |
| 181 | offset, &bit); |
| 182 | if (ret < 0) { |
| 183 | dev_err(pct->dev, "%s failed\n", __func__); |
| 184 | return ret; |
| 185 | } |
| 186 | |
| 187 | return bit; |
| 188 | } |
| 189 | |
| 190 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
| 191 | { |
| 192 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 193 | int ret; |
| 194 | |
| 195 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); |
| 196 | if (ret < 0) |
| 197 | dev_err(pct->dev, "%s write failed\n", __func__); |
| 198 | } |
| 199 | |
| 200 | static int abx500_config_pull_updown(struct abx500_pinctrl *pct, |
| 201 | int offset, enum abx500_gpio_pull_updown val) |
| 202 | { |
| 203 | u8 pos; |
| 204 | int ret; |
| 205 | struct pullud *pullud; |
| 206 | |
| 207 | if (!pct->soc->pullud) { |
| 208 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", |
| 209 | __func__); |
| 210 | ret = -EPERM; |
| 211 | goto out; |
| 212 | } |
| 213 | |
| 214 | pullud = pct->soc->pullud; |
| 215 | |
| 216 | if ((offset < pullud->first_pin) |
| 217 | || (offset > pullud->last_pin)) { |
| 218 | ret = -EINVAL; |
| 219 | goto out; |
| 220 | } |
| 221 | |
| 222 | pos = offset << 1; |
| 223 | |
| 224 | ret = abx500_mask_and_set_register_interruptible(pct->dev, |
| 225 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, |
| 226 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); |
| 227 | |
| 228 | out: |
| 229 | if (ret < 0) |
| 230 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); |
| 231 | |
| 232 | return ret; |
| 233 | } |
| 234 | |
| 235 | static int abx500_gpio_direction_output(struct gpio_chip *chip, |
| 236 | unsigned offset, |
| 237 | int val) |
| 238 | { |
| 239 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 240 | struct pullud *pullud = pct->soc->pullud; |
| 241 | unsigned gpio; |
| 242 | int ret; |
| 243 | |
| 244 | /* set direction as output */ |
| 245 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); |
| 246 | if (ret < 0) |
| 247 | return ret; |
| 248 | |
| 249 | /* disable pull down */ |
| 250 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); |
| 251 | if (ret < 0) |
| 252 | return ret; |
| 253 | |
| 254 | /* if supported, disable both pull down and pull up */ |
| 255 | gpio = offset + 1; |
| 256 | if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { |
| 257 | ret = abx500_config_pull_updown(pct, |
| 258 | gpio, |
| 259 | ABX500_GPIO_PULL_NONE); |
| 260 | if (ret < 0) |
| 261 | return ret; |
| 262 | } |
| 263 | |
| 264 | /* set the output as 1 or 0 */ |
| 265 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); |
| 266 | } |
| 267 | |
| 268 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 269 | { |
| 270 | /* set the register as input */ |
| 271 | return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); |
| 272 | } |
| 273 | |
| 274 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 275 | { |
| 276 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 277 | /* The AB8500 GPIO numbers are off by one */ |
| 278 | int gpio = offset + 1; |
| 279 | int base = pct->irq_base; |
| 280 | int i; |
| 281 | |
| 282 | for (i = 0; i < pct->irq_cluster_size; i++) { |
| 283 | struct abx500_gpio_irq_cluster *cluster = |
| 284 | &pct->irq_cluster[i]; |
| 285 | |
| 286 | if (gpio >= cluster->start && gpio <= cluster->end) |
| 287 | return base + gpio - cluster->start; |
| 288 | |
| 289 | /* Advance by the number of gpios in this cluster */ |
| 290 | base += cluster->end + cluster->offset - cluster->start + 1; |
| 291 | } |
| 292 | |
| 293 | return -EINVAL; |
| 294 | } |
| 295 | |
| 296 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, |
| 297 | unsigned gpio, int alt_setting) |
| 298 | { |
| 299 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 300 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; |
| 301 | int ret; |
| 302 | int val; |
| 303 | unsigned offset; |
| 304 | |
| 305 | const char *modes[] = { |
| 306 | [ABX500_DEFAULT] = "default", |
| 307 | [ABX500_ALT_A] = "altA", |
| 308 | [ABX500_ALT_B] = "altB", |
| 309 | [ABX500_ALT_C] = "altC", |
| 310 | }; |
| 311 | |
| 312 | /* sanity check */ |
| 313 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || |
| 314 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || |
| 315 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { |
| 316 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, |
| 317 | modes[alt_setting]); |
| 318 | return -EINVAL; |
| 319 | } |
| 320 | |
| 321 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
| 322 | offset = gpio - 1; |
| 323 | |
| 324 | switch (alt_setting) { |
| 325 | case ABX500_DEFAULT: |
| 326 | /* |
| 327 | * for ABx5xx family, default mode is always selected by |
| 328 | * writing 0 to GPIOSELx register, except for pins which |
| 329 | * support at least ALT_B mode, default mode is selected |
| 330 | * by writing 1 to GPIOSELx register |
| 331 | */ |
| 332 | val = 0; |
| 333 | if (af.alt_bit1 != UNUSED) |
| 334 | val++; |
| 335 | |
| 336 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, |
| 337 | offset, val); |
| 338 | break; |
| 339 | |
| 340 | case ABX500_ALT_A: |
| 341 | /* |
| 342 | * for ABx5xx family, alt_a mode is always selected by |
| 343 | * writing 1 to GPIOSELx register, except for pins which |
| 344 | * support at least ALT_B mode, alt_a mode is selected |
| 345 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC |
| 346 | * register |
| 347 | */ |
| 348 | if (af.alt_bit1 != UNUSED) { |
| 349 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, |
| 350 | offset, 0); |
| 351 | ret = abx500_gpio_set_bits(chip, |
| 352 | AB8500_GPIO_ALTFUN_REG, |
| 353 | af.alt_bit1, |
| 354 | !!(af.alta_val && BIT(0))); |
| 355 | if (af.alt_bit2 != UNUSED) |
| 356 | ret = abx500_gpio_set_bits(chip, |
| 357 | AB8500_GPIO_ALTFUN_REG, |
| 358 | af.alt_bit2, |
| 359 | !!(af.alta_val && BIT(1))); |
| 360 | } else |
| 361 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, |
| 362 | offset, 1); |
| 363 | break; |
| 364 | |
| 365 | case ABX500_ALT_B: |
| 366 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, |
| 367 | offset, 0); |
| 368 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
| 369 | af.alt_bit1, !!(af.altb_val && BIT(0))); |
| 370 | if (af.alt_bit2 != UNUSED) |
| 371 | ret = abx500_gpio_set_bits(chip, |
| 372 | AB8500_GPIO_ALTFUN_REG, |
| 373 | af.alt_bit2, |
| 374 | !!(af.altb_val && BIT(1))); |
| 375 | break; |
| 376 | |
| 377 | case ABX500_ALT_C: |
| 378 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, |
| 379 | offset, 0); |
| 380 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
| 381 | af.alt_bit2, !!(af.altc_val && BIT(0))); |
| 382 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
| 383 | af.alt_bit2, !!(af.altc_val && BIT(1))); |
| 384 | break; |
| 385 | |
| 386 | default: |
| 387 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); |
| 388 | |
| 389 | return -EINVAL; |
| 390 | } |
| 391 | |
| 392 | return ret; |
| 393 | } |
| 394 | |
| 395 | static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, |
| 396 | unsigned gpio) |
| 397 | { |
| 398 | u8 mode; |
| 399 | bool bit_mode; |
| 400 | bool alt_bit1; |
| 401 | bool alt_bit2; |
| 402 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 403 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; |
| 404 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
| 405 | unsigned offset = gpio - 1; |
| 406 | |
| 407 | /* |
| 408 | * if gpiosel_bit is set to unused, |
| 409 | * it means no GPIO or special case |
| 410 | */ |
| 411 | if (af.gpiosel_bit == UNUSED) |
| 412 | return ABX500_DEFAULT; |
| 413 | |
| 414 | /* read GpioSelx register */ |
| 415 | abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), |
| 416 | af.gpiosel_bit, &bit_mode); |
| 417 | mode = bit_mode; |
| 418 | |
| 419 | /* sanity check */ |
| 420 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || |
| 421 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { |
| 422 | dev_err(pct->dev, |
| 423 | "alt_bitX value not in correct range (-1 to 7)\n"); |
| 424 | return -EINVAL; |
| 425 | } |
| 426 | |
| 427 | /* if alt_bit2 is used, alt_bit1 must be used too */ |
| 428 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { |
| 429 | dev_err(pct->dev, |
| 430 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); |
| 431 | return -EINVAL; |
| 432 | } |
| 433 | |
| 434 | /* check if pin use AlternateFunction register */ |
| 435 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED)) |
| 436 | return mode; |
| 437 | /* |
| 438 | * if pin GPIOSEL bit is set and pin supports alternate function, |
| 439 | * it means DEFAULT mode |
| 440 | */ |
| 441 | if (mode) |
| 442 | return ABX500_DEFAULT; |
| 443 | |
| 444 | /* |
| 445 | * pin use the AlternatFunction register |
| 446 | * read alt_bit1 value |
| 447 | */ |
| 448 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, |
| 449 | af.alt_bit1, &alt_bit1); |
| 450 | |
| 451 | if (af.alt_bit2 != UNUSED) |
| 452 | /* read alt_bit2 value */ |
| 453 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, |
| 454 | &alt_bit2); |
| 455 | else |
| 456 | alt_bit2 = 0; |
| 457 | |
| 458 | mode = (alt_bit2 << 1) + alt_bit1; |
| 459 | if (mode == af.alta_val) |
| 460 | return ABX500_ALT_A; |
| 461 | else if (mode == af.altb_val) |
| 462 | return ABX500_ALT_B; |
| 463 | else |
| 464 | return ABX500_ALT_C; |
| 465 | } |
| 466 | |
| 467 | #ifdef CONFIG_DEBUG_FS |
| 468 | |
| 469 | #include <linux/seq_file.h> |
| 470 | |
| 471 | static void abx500_gpio_dbg_show_one(struct seq_file *s, |
| 472 | struct pinctrl_dev *pctldev, |
| 473 | struct gpio_chip *chip, |
| 474 | unsigned offset, unsigned gpio) |
| 475 | { |
| 476 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 477 | const char *label = gpiochip_is_requested(chip, offset - 1); |
| 478 | u8 gpio_offset = offset - 1; |
| 479 | int mode = -1; |
| 480 | bool is_out; |
| 481 | bool pull; |
| 482 | |
| 483 | const char *modes[] = { |
| 484 | [ABX500_DEFAULT] = "default", |
| 485 | [ABX500_ALT_A] = "altA", |
| 486 | [ABX500_ALT_B] = "altB", |
| 487 | [ABX500_ALT_C] = "altC", |
| 488 | }; |
| 489 | |
| 490 | abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); |
| 491 | abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull); |
| 492 | |
| 493 | if (pctldev) |
| 494 | mode = abx500_get_mode(pctldev, chip, offset); |
| 495 | |
| 496 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s", |
| 497 | gpio, label ?: "(none)", |
| 498 | is_out ? "out" : "in ", |
| 499 | is_out ? |
| 500 | (chip->get |
| 501 | ? (chip->get(chip, offset) ? "hi" : "lo") |
| 502 | : "? ") |
| 503 | : (pull ? "pull up" : "pull down"), |
| 504 | (mode < 0) ? "unknown" : modes[mode]); |
| 505 | |
| 506 | if (label && !is_out) { |
| 507 | int irq = gpio_to_irq(gpio); |
| 508 | struct irq_desc *desc = irq_to_desc(irq); |
| 509 | |
| 510 | if (irq >= 0 && desc->action) { |
| 511 | char *trigger; |
| 512 | int irq_offset = irq - pct->irq_base; |
| 513 | |
| 514 | if (pct->rising & BIT(irq_offset)) |
| 515 | trigger = "edge-rising"; |
| 516 | else if (pct->falling & BIT(irq_offset)) |
| 517 | trigger = "edge-falling"; |
| 518 | else |
| 519 | trigger = "edge-undefined"; |
| 520 | |
| 521 | seq_printf(s, " irq-%d %s", irq, trigger); |
| 522 | } |
| 523 | } |
| 524 | } |
| 525 | |
| 526 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
| 527 | { |
| 528 | unsigned i; |
| 529 | unsigned gpio = chip->base; |
| 530 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 531 | struct pinctrl_dev *pctldev = pct->pctldev; |
| 532 | |
| 533 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
| 534 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ |
| 535 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); |
| 536 | seq_printf(s, "\n"); |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | #else |
| 541 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, |
| 542 | struct pinctrl_dev *pctldev, |
| 543 | struct gpio_chip *chip, |
| 544 | unsigned offset, unsigned gpio) |
| 545 | { |
| 546 | } |
| 547 | #define abx500_gpio_dbg_show NULL |
| 548 | #endif |
| 549 | |
| 550 | int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 551 | { |
| 552 | int gpio = chip->base + offset; |
| 553 | |
| 554 | return pinctrl_request_gpio(gpio); |
| 555 | } |
| 556 | |
| 557 | void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 558 | { |
| 559 | int gpio = chip->base + offset; |
| 560 | |
| 561 | pinctrl_free_gpio(gpio); |
| 562 | } |
| 563 | |
| 564 | static struct gpio_chip abx500gpio_chip = { |
| 565 | .label = "abx500-gpio", |
| 566 | .owner = THIS_MODULE, |
| 567 | .request = abx500_gpio_request, |
| 568 | .free = abx500_gpio_free, |
| 569 | .direction_input = abx500_gpio_direction_input, |
| 570 | .get = abx500_gpio_get, |
| 571 | .direction_output = abx500_gpio_direction_output, |
| 572 | .set = abx500_gpio_set, |
| 573 | .to_irq = abx500_gpio_to_irq, |
| 574 | .dbg_show = abx500_gpio_dbg_show, |
| 575 | }; |
| 576 | |
| 577 | static unsigned int irq_to_rising(unsigned int irq) |
| 578 | { |
| 579 | struct abx500_pinctrl *pct = irq_get_chip_data(irq); |
| 580 | int offset = irq - pct->irq_base; |
| 581 | int new_irq; |
| 582 | |
| 583 | new_irq = offset * pct->irq_gpio_factor |
| 584 | + pct->irq_gpio_rising_offset |
| 585 | + pct->parent->irq_base; |
| 586 | |
| 587 | return new_irq; |
| 588 | } |
| 589 | |
| 590 | static unsigned int irq_to_falling(unsigned int irq) |
| 591 | { |
| 592 | struct abx500_pinctrl *pct = irq_get_chip_data(irq); |
| 593 | int offset = irq - pct->irq_base; |
| 594 | int new_irq; |
| 595 | |
| 596 | new_irq = offset * pct->irq_gpio_factor |
| 597 | + pct->irq_gpio_falling_offset |
| 598 | + pct->parent->irq_base; |
| 599 | return new_irq; |
| 600 | |
| 601 | } |
| 602 | |
| 603 | static unsigned int rising_to_irq(unsigned int irq, void *dev) |
| 604 | { |
| 605 | struct abx500_pinctrl *pct = dev; |
| 606 | int offset, new_irq; |
| 607 | |
| 608 | offset = irq - pct->irq_gpio_rising_offset |
| 609 | - pct->parent->irq_base; |
| 610 | new_irq = (offset / pct->irq_gpio_factor) |
| 611 | + pct->irq_base; |
| 612 | |
| 613 | return new_irq; |
| 614 | } |
| 615 | |
| 616 | static unsigned int falling_to_irq(unsigned int irq, void *dev) |
| 617 | { |
| 618 | struct abx500_pinctrl *pct = dev; |
| 619 | int offset, new_irq; |
| 620 | |
| 621 | offset = irq - pct->irq_gpio_falling_offset |
| 622 | - pct->parent->irq_base; |
| 623 | new_irq = (offset / pct->irq_gpio_factor) |
| 624 | + pct->irq_base; |
| 625 | |
| 626 | return new_irq; |
| 627 | } |
| 628 | |
| 629 | /* |
| 630 | * IRQ handler |
| 631 | */ |
| 632 | |
| 633 | static irqreturn_t handle_rising(int irq, void *dev) |
| 634 | { |
| 635 | |
| 636 | handle_nested_irq(rising_to_irq(irq , dev)); |
| 637 | return IRQ_HANDLED; |
| 638 | } |
| 639 | |
| 640 | static irqreturn_t handle_falling(int irq, void *dev) |
| 641 | { |
| 642 | |
| 643 | handle_nested_irq(falling_to_irq(irq, dev)); |
| 644 | return IRQ_HANDLED; |
| 645 | } |
| 646 | |
| 647 | static void abx500_gpio_irq_lock(struct irq_data *data) |
| 648 | { |
| 649 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 650 | mutex_lock(&pct->lock); |
| 651 | } |
| 652 | |
| 653 | static void abx500_gpio_irq_sync_unlock(struct irq_data *data) |
| 654 | { |
| 655 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 656 | unsigned int irq = data->irq; |
| 657 | int offset = irq - pct->irq_base; |
| 658 | bool rising = pct->rising & BIT(offset); |
| 659 | bool falling = pct->falling & BIT(offset); |
| 660 | int ret; |
| 661 | |
| 662 | switch (pct->irq_action) { |
| 663 | case STARTUP: |
| 664 | if (rising) |
| 665 | ret = request_threaded_irq(irq_to_rising(irq), |
| 666 | NULL, handle_rising, |
| 667 | IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, |
| 668 | "abx500-gpio-r", pct); |
| 669 | if (falling) |
| 670 | ret = request_threaded_irq(irq_to_falling(irq), |
| 671 | NULL, handle_falling, |
| 672 | IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND, |
| 673 | "abx500-gpio-f", pct); |
| 674 | break; |
| 675 | case SHUTDOWN: |
| 676 | if (rising) |
| 677 | free_irq(irq_to_rising(irq), pct); |
| 678 | if (falling) |
| 679 | free_irq(irq_to_falling(irq), pct); |
| 680 | break; |
| 681 | case MASK: |
| 682 | if (rising) |
| 683 | disable_irq(irq_to_rising(irq)); |
| 684 | if (falling) |
| 685 | disable_irq(irq_to_falling(irq)); |
| 686 | break; |
| 687 | case UNMASK: |
| 688 | if (rising) |
| 689 | enable_irq(irq_to_rising(irq)); |
| 690 | if (falling) |
| 691 | enable_irq(irq_to_falling(irq)); |
| 692 | break; |
| 693 | case NONE: |
| 694 | break; |
| 695 | } |
| 696 | pct->irq_action = NONE; |
| 697 | pct->rising &= ~(BIT(offset)); |
| 698 | pct->falling &= ~(BIT(offset)); |
| 699 | mutex_unlock(&pct->lock); |
| 700 | } |
| 701 | |
| 702 | |
| 703 | static void abx500_gpio_irq_mask(struct irq_data *data) |
| 704 | { |
| 705 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 706 | pct->irq_action = MASK; |
| 707 | } |
| 708 | |
| 709 | static void abx500_gpio_irq_unmask(struct irq_data *data) |
| 710 | { |
| 711 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 712 | pct->irq_action = UNMASK; |
| 713 | } |
| 714 | |
| 715 | static int abx500_gpio_irq_set_type(struct irq_data *data, unsigned int type) |
| 716 | { |
| 717 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 718 | unsigned int irq = data->irq; |
| 719 | int offset = irq - pct->irq_base; |
| 720 | |
| 721 | if (type == IRQ_TYPE_EDGE_BOTH) { |
| 722 | pct->rising = BIT(offset); |
| 723 | pct->falling = BIT(offset); |
| 724 | } else if (type == IRQ_TYPE_EDGE_RISING) { |
| 725 | pct->rising = BIT(offset); |
| 726 | } else { |
| 727 | pct->falling = BIT(offset); |
| 728 | } |
| 729 | return 0; |
| 730 | } |
| 731 | |
| 732 | static unsigned int abx500_gpio_irq_startup(struct irq_data *data) |
| 733 | { |
| 734 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 735 | pct->irq_action = STARTUP; |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | static void abx500_gpio_irq_shutdown(struct irq_data *data) |
| 740 | { |
| 741 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); |
| 742 | pct->irq_action = SHUTDOWN; |
| 743 | } |
| 744 | |
| 745 | static struct irq_chip abx500_gpio_irq_chip = { |
| 746 | .name = "abx500-gpio", |
| 747 | .irq_startup = abx500_gpio_irq_startup, |
| 748 | .irq_shutdown = abx500_gpio_irq_shutdown, |
| 749 | .irq_bus_lock = abx500_gpio_irq_lock, |
| 750 | .irq_bus_sync_unlock = abx500_gpio_irq_sync_unlock, |
| 751 | .irq_mask = abx500_gpio_irq_mask, |
| 752 | .irq_unmask = abx500_gpio_irq_unmask, |
| 753 | .irq_set_type = abx500_gpio_irq_set_type, |
| 754 | }; |
| 755 | |
| 756 | static int abx500_gpio_irq_init(struct abx500_pinctrl *pct) |
| 757 | { |
| 758 | u32 base = pct->irq_base; |
| 759 | int irq; |
| 760 | |
| 761 | for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) { |
| 762 | irq_set_chip_data(irq, pct); |
| 763 | irq_set_chip_and_handler(irq, &abx500_gpio_irq_chip, |
| 764 | handle_simple_irq); |
| 765 | irq_set_nested_thread(irq, 1); |
| 766 | #ifdef CONFIG_ARM |
| 767 | set_irq_flags(irq, IRQF_VALID); |
| 768 | #else |
| 769 | irq_set_noprobe(irq); |
| 770 | #endif |
| 771 | } |
| 772 | |
| 773 | return 0; |
| 774 | } |
| 775 | |
| 776 | static void abx500_gpio_irq_remove(struct abx500_pinctrl *pct) |
| 777 | { |
| 778 | int base = pct->irq_base; |
| 779 | int irq; |
| 780 | |
| 781 | for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) { |
| 782 | #ifdef CONFIG_ARM |
| 783 | set_irq_flags(irq, 0); |
| 784 | #endif |
| 785 | irq_set_chip_and_handler(irq, NULL, NULL); |
| 786 | irq_set_chip_data(irq, NULL); |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
| 791 | { |
| 792 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 793 | |
| 794 | return pct->soc->nfunctions; |
| 795 | } |
| 796 | |
| 797 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, |
| 798 | unsigned function) |
| 799 | { |
| 800 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 801 | |
| 802 | return pct->soc->functions[function].name; |
| 803 | } |
| 804 | |
| 805 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, |
| 806 | unsigned function, |
| 807 | const char * const **groups, |
| 808 | unsigned * const num_groups) |
| 809 | { |
| 810 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 811 | |
| 812 | *groups = pct->soc->functions[function].groups; |
| 813 | *num_groups = pct->soc->functions[function].ngroups; |
| 814 | |
| 815 | return 0; |
| 816 | } |
| 817 | |
| 818 | static void abx500_disable_lazy_irq(struct gpio_chip *chip, unsigned gpio) |
| 819 | { |
| 820 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); |
| 821 | int irq; |
| 822 | int offset; |
| 823 | bool rising; |
| 824 | bool falling; |
| 825 | |
| 826 | /* |
| 827 | * check if gpio has interrupt capability and convert |
| 828 | * gpio number to irq |
| 829 | * On ABx5xx, there is no GPIO0, GPIO1 is the |
| 830 | * first one, so adjust gpio number |
| 831 | */ |
| 832 | gpio--; |
| 833 | irq = gpio_to_irq(gpio + chip->base); |
| 834 | if (irq < 0) |
| 835 | return; |
| 836 | |
| 837 | offset = irq - pct->irq_base; |
| 838 | rising = pct->rising & BIT(offset); |
| 839 | falling = pct->falling & BIT(offset); |
| 840 | |
| 841 | /* nothing to do ?*/ |
| 842 | if (!rising && !falling) |
| 843 | return; |
| 844 | |
| 845 | if (rising) { |
| 846 | disable_irq(irq_to_rising(irq)); |
| 847 | free_irq(irq_to_rising(irq), pct); |
| 848 | } |
| 849 | if (falling) { |
| 850 | disable_irq(irq_to_falling(irq)); |
| 851 | free_irq(irq_to_falling(irq), pct); |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, |
| 856 | unsigned group) |
| 857 | { |
| 858 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 859 | struct gpio_chip *chip = &pct->chip; |
| 860 | const struct abx500_pingroup *g; |
| 861 | int i; |
| 862 | int ret = 0; |
| 863 | |
| 864 | g = &pct->soc->groups[group]; |
| 865 | if (g->altsetting < 0) |
| 866 | return -EINVAL; |
| 867 | |
| 868 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); |
| 869 | |
| 870 | for (i = 0; i < g->npins; i++) { |
| 871 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", |
| 872 | g->pins[i], g->altsetting); |
| 873 | |
| 874 | abx500_disable_lazy_irq(chip, g->pins[i]); |
| 875 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); |
| 876 | } |
| 877 | |
| 878 | return ret; |
| 879 | } |
| 880 | |
| 881 | static void abx500_pmx_disable(struct pinctrl_dev *pctldev, |
| 882 | unsigned function, unsigned group) |
| 883 | { |
| 884 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 885 | const struct abx500_pingroup *g; |
| 886 | |
| 887 | g = &pct->soc->groups[group]; |
| 888 | if (g->altsetting < 0) |
| 889 | return; |
| 890 | |
| 891 | /* FIXME: poke out the mux, set the pin to some default state? */ |
| 892 | dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); |
| 893 | } |
| 894 | |
| 895 | int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, |
| 896 | struct pinctrl_gpio_range *range, |
| 897 | unsigned offset) |
| 898 | { |
| 899 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 900 | const struct abx500_pinrange *p; |
| 901 | int ret; |
| 902 | int i; |
| 903 | |
| 904 | /* |
| 905 | * Different ranges have different ways to enable GPIO function on a |
| 906 | * pin, so refer back to our local range type, where we handily define |
| 907 | * what altfunc enables GPIO for a certain pin. |
| 908 | */ |
| 909 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { |
| 910 | p = &pct->soc->gpio_ranges[i]; |
| 911 | if ((offset >= p->offset) && |
| 912 | (offset < (p->offset + p->npins))) |
| 913 | break; |
| 914 | } |
| 915 | |
| 916 | if (i == pct->soc->gpio_num_ranges) { |
| 917 | dev_err(pct->dev, "%s failed to locate range\n", __func__); |
| 918 | return -ENODEV; |
| 919 | } |
| 920 | |
| 921 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", |
| 922 | p->altfunc, offset); |
| 923 | |
| 924 | ret = abx500_set_mode(pct->pctldev, &pct->chip, |
| 925 | offset, p->altfunc); |
| 926 | if (ret < 0) { |
| 927 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); |
| 928 | return ret; |
| 929 | } |
| 930 | |
| 931 | return ret; |
| 932 | } |
| 933 | |
| 934 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, |
| 935 | struct pinctrl_gpio_range *range, |
| 936 | unsigned offset) |
| 937 | { |
| 938 | } |
| 939 | |
| 940 | static struct pinmux_ops abx500_pinmux_ops = { |
| 941 | .get_functions_count = abx500_pmx_get_funcs_cnt, |
| 942 | .get_function_name = abx500_pmx_get_func_name, |
| 943 | .get_function_groups = abx500_pmx_get_func_groups, |
| 944 | .enable = abx500_pmx_enable, |
| 945 | .disable = abx500_pmx_disable, |
| 946 | .gpio_request_enable = abx500_gpio_request_enable, |
| 947 | .gpio_disable_free = abx500_gpio_disable_free, |
| 948 | }; |
| 949 | |
| 950 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) |
| 951 | { |
| 952 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 953 | |
| 954 | return pct->soc->ngroups; |
| 955 | } |
| 956 | |
| 957 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, |
| 958 | unsigned selector) |
| 959 | { |
| 960 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 961 | |
| 962 | return pct->soc->groups[selector].name; |
| 963 | } |
| 964 | |
| 965 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, |
| 966 | unsigned selector, |
| 967 | const unsigned **pins, |
| 968 | unsigned *num_pins) |
| 969 | { |
| 970 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 971 | |
| 972 | *pins = pct->soc->groups[selector].pins; |
| 973 | *num_pins = pct->soc->groups[selector].npins; |
| 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, |
| 979 | struct seq_file *s, unsigned offset) |
| 980 | { |
| 981 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 982 | struct gpio_chip *chip = &pct->chip; |
| 983 | |
| 984 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, |
| 985 | chip->base + offset - 1); |
| 986 | } |
| 987 | |
| 988 | static struct pinctrl_ops abx500_pinctrl_ops = { |
| 989 | .get_groups_count = abx500_get_groups_cnt, |
| 990 | .get_group_name = abx500_get_group_name, |
| 991 | .get_group_pins = abx500_get_group_pins, |
| 992 | .pin_dbg_show = abx500_pin_dbg_show, |
| 993 | }; |
| 994 | |
| 995 | int abx500_pin_config_get(struct pinctrl_dev *pctldev, |
| 996 | unsigned pin, |
| 997 | unsigned long *config) |
| 998 | { |
| 999 | return -ENOSYS; |
| 1000 | } |
| 1001 | |
| 1002 | int abx500_pin_config_set(struct pinctrl_dev *pctldev, |
| 1003 | unsigned pin, |
| 1004 | unsigned long config) |
| 1005 | { |
| 1006 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
| 1007 | struct pullud *pullud = pct->soc->pullud; |
| 1008 | struct gpio_chip *chip = &pct->chip; |
| 1009 | unsigned offset; |
| 1010 | int ret; |
| 1011 | enum pin_config_param param = pinconf_to_config_param(config); |
| 1012 | enum pin_config_param argument = pinconf_to_config_argument(config); |
| 1013 | |
| 1014 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", |
| 1015 | pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", |
| 1016 | (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : |
| 1017 | (argument ? "pull up" : "pull down")); |
| 1018 | |
| 1019 | /* on ABx500, there is no GPIO0, so adjust the offset */ |
| 1020 | offset = pin - 1; |
| 1021 | |
| 1022 | switch (param) { |
| 1023 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 1024 | /* |
| 1025 | * if argument = 1 set the pull down |
| 1026 | * else clear the pull down |
| 1027 | */ |
| 1028 | ret = abx500_gpio_direction_input(chip, offset); |
| 1029 | /* |
| 1030 | * Some chips only support pull down, while some actually |
| 1031 | * support both pull up and pull down. Such chips have |
| 1032 | * a "pullud" range specified for the pins that support |
| 1033 | * both features. If the pin is not within that range, we |
| 1034 | * fall back to the old bit set that only support pull down. |
| 1035 | */ |
| 1036 | if (pullud && |
| 1037 | pin >= pullud->first_pin && |
| 1038 | pin <= pullud->last_pin) |
| 1039 | ret = abx500_config_pull_updown(pct, |
| 1040 | pin, |
| 1041 | argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); |
| 1042 | else |
| 1043 | /* Chip only supports pull down */ |
| 1044 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, |
| 1045 | offset, argument ? 0 : 1); |
| 1046 | break; |
| 1047 | |
| 1048 | case PIN_CONFIG_OUTPUT: |
| 1049 | ret = abx500_gpio_direction_output(chip, offset, argument); |
| 1050 | |
| 1051 | break; |
| 1052 | |
| 1053 | default: |
| 1054 | dev_err(chip->dev, "illegal configuration requested\n"); |
| 1055 | |
| 1056 | return -EINVAL; |
| 1057 | } |
| 1058 | |
| 1059 | return ret; |
| 1060 | } |
| 1061 | |
| 1062 | static struct pinconf_ops abx500_pinconf_ops = { |
| 1063 | .pin_config_get = abx500_pin_config_get, |
| 1064 | .pin_config_set = abx500_pin_config_set, |
| 1065 | }; |
| 1066 | |
| 1067 | static struct pinctrl_desc abx500_pinctrl_desc = { |
| 1068 | .name = "pinctrl-abx500", |
| 1069 | .pctlops = &abx500_pinctrl_ops, |
| 1070 | .pmxops = &abx500_pinmux_ops, |
| 1071 | .confops = &abx500_pinconf_ops, |
| 1072 | .owner = THIS_MODULE, |
| 1073 | }; |
| 1074 | |
| 1075 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) |
| 1076 | { |
| 1077 | unsigned int lowest = 0; |
| 1078 | unsigned int highest = 0; |
| 1079 | unsigned int npins = 0; |
| 1080 | int i; |
| 1081 | |
| 1082 | /* |
| 1083 | * Compute number of GPIOs from the last SoC gpio range descriptors |
| 1084 | * These ranges may include "holes" but the GPIO number space shall |
| 1085 | * still be homogeneous, so we need to detect and account for any |
| 1086 | * such holes so that these are included in the number of GPIO pins. |
| 1087 | */ |
| 1088 | for (i = 0; i < soc->gpio_num_ranges; i++) { |
| 1089 | unsigned gstart; |
| 1090 | unsigned gend; |
| 1091 | const struct abx500_pinrange *p; |
| 1092 | |
| 1093 | p = &soc->gpio_ranges[i]; |
| 1094 | gstart = p->offset; |
| 1095 | gend = p->offset + p->npins - 1; |
| 1096 | |
| 1097 | if (i == 0) { |
| 1098 | /* First iteration, set start values */ |
| 1099 | lowest = gstart; |
| 1100 | highest = gend; |
| 1101 | } else { |
| 1102 | if (gstart < lowest) |
| 1103 | lowest = gstart; |
| 1104 | if (gend > highest) |
| 1105 | highest = gend; |
| 1106 | } |
| 1107 | } |
| 1108 | /* this gives the absolute number of pins */ |
| 1109 | npins = highest - lowest + 1; |
| 1110 | return npins; |
| 1111 | } |
| 1112 | |
| 1113 | static const struct of_device_id abx500_gpio_match[] = { |
| 1114 | { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, |
| 1115 | { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, |
| 1116 | { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, |
| 1117 | { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, |
| 1118 | }; |
| 1119 | |
| 1120 | static int abx500_gpio_probe(struct platform_device *pdev) |
| 1121 | { |
| 1122 | struct ab8500_platform_data *abx500_pdata = |
| 1123 | dev_get_platdata(pdev->dev.parent); |
| 1124 | struct abx500_gpio_platform_data *pdata = NULL; |
| 1125 | struct device_node *np = pdev->dev.of_node; |
| 1126 | struct abx500_pinctrl *pct; |
| 1127 | const struct platform_device_id *platid = platform_get_device_id(pdev); |
| 1128 | unsigned int id = -1; |
| 1129 | int ret, err; |
| 1130 | int i; |
| 1131 | |
| 1132 | if (abx500_pdata) |
| 1133 | pdata = abx500_pdata->gpio; |
| 1134 | if (!pdata) { |
| 1135 | if (np) { |
| 1136 | const struct of_device_id *match; |
| 1137 | |
| 1138 | match = of_match_device(abx500_gpio_match, &pdev->dev); |
| 1139 | if (!match) |
| 1140 | return -ENODEV; |
| 1141 | id = (unsigned long)match->data; |
| 1142 | } else { |
| 1143 | dev_err(&pdev->dev, "gpio dt and platform data missing\n"); |
| 1144 | return -ENODEV; |
| 1145 | } |
| 1146 | } |
| 1147 | |
| 1148 | if (platid) |
| 1149 | id = platid->driver_data; |
| 1150 | |
| 1151 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), |
| 1152 | GFP_KERNEL); |
| 1153 | if (pct == NULL) { |
| 1154 | dev_err(&pdev->dev, |
| 1155 | "failed to allocate memory for pct\n"); |
| 1156 | return -ENOMEM; |
| 1157 | } |
| 1158 | |
| 1159 | pct->dev = &pdev->dev; |
| 1160 | pct->parent = dev_get_drvdata(pdev->dev.parent); |
| 1161 | pct->chip = abx500gpio_chip; |
| 1162 | pct->chip.dev = &pdev->dev; |
| 1163 | pct->chip.base = pdata->gpio_base; |
| 1164 | pct->irq_base = pdata->irq_base; |
| 1165 | pct->chip.base = (np) ? -1 : pdata->gpio_base; |
| 1166 | |
| 1167 | /* initialize the lock */ |
| 1168 | mutex_init(&pct->lock); |
| 1169 | |
| 1170 | /* Poke in other ASIC variants here */ |
| 1171 | switch (id) { |
| 1172 | case PINCTRL_AB8500: |
| 1173 | abx500_pinctrl_ab8500_init(&pct->soc); |
| 1174 | break; |
| 1175 | case PINCTRL_AB8540: |
| 1176 | abx500_pinctrl_ab8540_init(&pct->soc); |
| 1177 | break; |
| 1178 | case PINCTRL_AB9540: |
| 1179 | abx500_pinctrl_ab9540_init(&pct->soc); |
| 1180 | break; |
| 1181 | case PINCTRL_AB8505: |
| 1182 | abx500_pinctrl_ab8505_init(&pct->soc); |
| 1183 | break; |
| 1184 | default: |
| 1185 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", |
| 1186 | (int) platid->driver_data); |
| 1187 | mutex_destroy(&pct->lock); |
| 1188 | return -EINVAL; |
| 1189 | } |
| 1190 | |
| 1191 | if (!pct->soc) { |
| 1192 | dev_err(&pdev->dev, "Invalid SOC data\n"); |
| 1193 | mutex_destroy(&pct->lock); |
| 1194 | return -EINVAL; |
| 1195 | } |
| 1196 | |
| 1197 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); |
| 1198 | pct->irq_cluster = pct->soc->gpio_irq_cluster; |
| 1199 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; |
| 1200 | pct->irq_gpio_rising_offset = pct->soc->irq_gpio_rising_offset; |
| 1201 | pct->irq_gpio_falling_offset = pct->soc->irq_gpio_falling_offset; |
| 1202 | pct->irq_gpio_factor = pct->soc->irq_gpio_factor; |
| 1203 | |
| 1204 | ret = abx500_gpio_irq_init(pct); |
| 1205 | if (ret) |
| 1206 | goto out_free; |
| 1207 | ret = gpiochip_add(&pct->chip); |
| 1208 | if (ret) { |
| 1209 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
| 1210 | mutex_destroy(&pct->lock); |
| 1211 | goto out_rem_irq; |
| 1212 | } |
| 1213 | dev_info(&pdev->dev, "added gpiochip\n"); |
| 1214 | |
| 1215 | abx500_pinctrl_desc.pins = pct->soc->pins; |
| 1216 | abx500_pinctrl_desc.npins = pct->soc->npins; |
| 1217 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); |
| 1218 | if (!pct->pctldev) { |
| 1219 | dev_err(&pdev->dev, |
| 1220 | "could not register abx500 pinctrl driver\n"); |
| 1221 | ret = -EINVAL; |
| 1222 | goto out_rem_chip; |
| 1223 | } |
| 1224 | dev_info(&pdev->dev, "registered pin controller\n"); |
| 1225 | |
| 1226 | /* We will handle a range of GPIO pins */ |
| 1227 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { |
| 1228 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; |
| 1229 | |
| 1230 | ret = gpiochip_add_pin_range(&pct->chip, |
| 1231 | dev_name(&pdev->dev), |
| 1232 | p->offset - 1, p->offset, p->npins); |
| 1233 | if (ret < 0) |
| 1234 | goto out_rem_chip; |
| 1235 | } |
| 1236 | |
| 1237 | platform_set_drvdata(pdev, pct); |
| 1238 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); |
| 1239 | |
| 1240 | return 0; |
| 1241 | |
| 1242 | out_rem_chip: |
| 1243 | err = gpiochip_remove(&pct->chip); |
| 1244 | if (err) |
| 1245 | dev_info(&pdev->dev, "failed to remove gpiochip\n"); |
| 1246 | out_rem_irq: |
| 1247 | abx500_gpio_irq_remove(pct); |
| 1248 | out_free: |
| 1249 | mutex_destroy(&pct->lock); |
| 1250 | return ret; |
| 1251 | } |
| 1252 | |
| 1253 | /** |
| 1254 | * abx500_gpio_remove() - remove Ab8500-gpio driver |
| 1255 | * @pdev: Platform device registered |
| 1256 | */ |
| 1257 | static int abx500_gpio_remove(struct platform_device *pdev) |
| 1258 | { |
| 1259 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); |
| 1260 | int ret; |
| 1261 | |
| 1262 | ret = gpiochip_remove(&pct->chip); |
| 1263 | if (ret < 0) { |
| 1264 | dev_err(pct->dev, "unable to remove gpiochip: %d\n", |
| 1265 | ret); |
| 1266 | return ret; |
| 1267 | } |
| 1268 | |
| 1269 | mutex_destroy(&pct->lock); |
| 1270 | |
| 1271 | return 0; |
| 1272 | } |
| 1273 | |
| 1274 | static const struct platform_device_id abx500_pinctrl_id[] = { |
| 1275 | { "pinctrl-ab8500", PINCTRL_AB8500 }, |
| 1276 | { "pinctrl-ab8540", PINCTRL_AB8540 }, |
| 1277 | { "pinctrl-ab9540", PINCTRL_AB9540 }, |
| 1278 | { "pinctrl-ab8505", PINCTRL_AB8505 }, |
| 1279 | { }, |
| 1280 | }; |
| 1281 | |
| 1282 | static struct platform_driver abx500_gpio_driver = { |
| 1283 | .driver = { |
| 1284 | .name = "abx500-gpio", |
| 1285 | .owner = THIS_MODULE, |
| 1286 | .of_match_table = abx500_gpio_match, |
| 1287 | }, |
| 1288 | .probe = abx500_gpio_probe, |
| 1289 | .remove = abx500_gpio_remove, |
| 1290 | .id_table = abx500_pinctrl_id, |
| 1291 | }; |
| 1292 | |
| 1293 | static int __init abx500_gpio_init(void) |
| 1294 | { |
| 1295 | return platform_driver_register(&abx500_gpio_driver); |
| 1296 | } |
| 1297 | core_initcall(abx500_gpio_init); |
| 1298 | |
| 1299 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); |
| 1300 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); |
| 1301 | MODULE_ALIAS("platform:abx500-gpio"); |
| 1302 | MODULE_LICENSE("GPL v2"); |