| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. |
| 4 | * |
| 5 | * Copyright (C) 2018-2020 Xilinx Inc. |
| 6 | * |
| 7 | * Author: Anurag Kumar Vulisha <anuragku@xilinx.com> |
| 8 | * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com> |
| 9 | * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 10 | * |
| 11 | * This driver is tested for USB, SATA and Display Port currently. |
| 12 | * Other controllers PCIe and SGMII should also work but that is |
| 13 | * experimental as of now. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/phy/phy.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/slab.h> |
| 25 | |
| 26 | #include <dt-bindings/phy/phy.h> |
| 27 | |
| 28 | /* |
| 29 | * Lane Registers |
| 30 | */ |
| 31 | |
| 32 | /* TX De-emphasis parameters */ |
| 33 | #define L0_TX_ANA_TM_18 0x0048 |
| 34 | #define L0_TX_ANA_TM_118 0x01d8 |
| 35 | #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0) |
| 36 | |
| 37 | /* DN Resistor calibration code parameters */ |
| 38 | #define L0_TXPMA_ST_3 0x0b0c |
| 39 | #define L0_DN_CALIB_CODE 0x3f |
| 40 | |
| 41 | /* PMA control parameters */ |
| 42 | #define L0_TXPMD_TM_45 0x0cb4 |
| 43 | #define L0_TXPMD_TM_48 0x0cc0 |
| 44 | #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0) |
| 45 | #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) |
| 46 | #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) |
| 47 | #define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) |
| 48 | #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) |
| 49 | #define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) |
| 50 | |
| 51 | /* PCS control parameters */ |
| 52 | #define L0_TM_DIG_6 0x106c |
| 53 | #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f |
| 54 | #define L0_TX_DIG_61 0x00f4 |
| 55 | #define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f |
| 56 | |
| 57 | /* PLL Test Mode register parameters */ |
| 58 | #define L0_TM_PLL_DIG_37 0x2094 |
| 59 | #define L0_TM_COARSE_CODE_LIMIT 0x10 |
| 60 | |
| 61 | /* PLL SSC step size offsets */ |
| 62 | #define L0_PLL_SS_STEPS_0_LSB 0x2368 |
| 63 | #define L0_PLL_SS_STEPS_1_MSB 0x236c |
| 64 | #define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 |
| 65 | #define L0_PLL_SS_STEP_SIZE_1 0x2374 |
| 66 | #define L0_PLL_SS_STEP_SIZE_2 0x2378 |
| 67 | #define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c |
| 68 | #define L0_PLL_STATUS_READ_1 0x23e4 |
| 69 | |
| 70 | /* SSC step size parameters */ |
| 71 | #define STEP_SIZE_0_MASK 0xff |
| 72 | #define STEP_SIZE_1_MASK 0xff |
| 73 | #define STEP_SIZE_2_MASK 0xff |
| 74 | #define STEP_SIZE_3_MASK 0x3 |
| 75 | #define STEP_SIZE_SHIFT 8 |
| 76 | #define FORCE_STEP_SIZE 0x10 |
| 77 | #define FORCE_STEPS 0x20 |
| 78 | #define STEPS_0_MASK 0xff |
| 79 | #define STEPS_1_MASK 0x07 |
| 80 | |
| 81 | /* Reference clock selection parameters */ |
| 82 | #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) |
| 83 | #define L0_REF_CLK_SEL_MASK 0x8f |
| 84 | |
| 85 | /* Calibration digital logic parameters */ |
| 86 | #define L3_TM_CALIB_DIG19 0xec4c |
| 87 | #define L3_CALIB_DONE_STATUS 0xef14 |
| 88 | #define L3_TM_CALIB_DIG18 0xec48 |
| 89 | #define L3_TM_CALIB_DIG19_NSW 0x07 |
| 90 | #define L3_TM_CALIB_DIG18_NSW 0xe0 |
| 91 | #define L3_TM_OVERRIDE_NSW_CODE 0x20 |
| 92 | #define L3_CALIB_DONE 0x02 |
| 93 | #define L3_NSW_SHIFT 5 |
| 94 | #define L3_NSW_PIPE_SHIFT 4 |
| 95 | #define L3_NSW_CALIB_SHIFT 3 |
| 96 | |
| 97 | #define PHY_REG_OFFSET 0x4000 |
| 98 | |
| 99 | /* |
| 100 | * Global Registers |
| 101 | */ |
| 102 | |
| 103 | /* Refclk selection parameters */ |
| 104 | #define PLL_REF_SEL(n) (0x10000 + (n) * 4) |
| 105 | #define PLL_FREQ_MASK 0x1f |
| 106 | #define PLL_STATUS_LOCKED 0x10 |
| 107 | |
| 108 | /* Inter Connect Matrix parameters */ |
| 109 | #define ICM_CFG0 0x10010 |
| 110 | #define ICM_CFG1 0x10014 |
| 111 | #define ICM_CFG0_L0_MASK 0x07 |
| 112 | #define ICM_CFG0_L1_MASK 0x70 |
| 113 | #define ICM_CFG1_L2_MASK 0x07 |
| 114 | #define ICM_CFG2_L3_MASK 0x70 |
| 115 | #define ICM_CFG_SHIFT 4 |
| 116 | |
| 117 | /* Inter Connect Matrix allowed protocols */ |
| 118 | #define ICM_PROTOCOL_PD 0x0 |
| 119 | #define ICM_PROTOCOL_PCIE 0x1 |
| 120 | #define ICM_PROTOCOL_SATA 0x2 |
| 121 | #define ICM_PROTOCOL_USB 0x3 |
| 122 | #define ICM_PROTOCOL_DP 0x4 |
| 123 | #define ICM_PROTOCOL_SGMII 0x5 |
| 124 | |
| 125 | /* Test Mode common reset control parameters */ |
| 126 | #define TM_CMN_RST 0x10018 |
| 127 | #define TM_CMN_RST_EN 0x1 |
| 128 | #define TM_CMN_RST_SET 0x2 |
| 129 | #define TM_CMN_RST_MASK 0x3 |
| 130 | |
| 131 | /* Bus width parameters */ |
| 132 | #define TX_PROT_BUS_WIDTH 0x10040 |
| 133 | #define RX_PROT_BUS_WIDTH 0x10044 |
| 134 | #define PROT_BUS_WIDTH_10 0x0 |
| 135 | #define PROT_BUS_WIDTH_20 0x1 |
| 136 | #define PROT_BUS_WIDTH_40 0x2 |
| 137 | #define PROT_BUS_WIDTH_SHIFT 2 |
| 138 | |
| 139 | /* Number of GT lanes */ |
| 140 | #define NUM_LANES 4 |
| 141 | |
| 142 | /* SIOU SATA control register */ |
| 143 | #define SATA_CONTROL_OFFSET 0x0100 |
| 144 | |
| 145 | /* Total number of controllers */ |
| 146 | #define CONTROLLERS_PER_LANE 5 |
| 147 | |
| 148 | /* Protocol Type parameters */ |
| 149 | #define XPSGTR_TYPE_USB0 0 /* USB controller 0 */ |
| 150 | #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */ |
| 151 | #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */ |
| 152 | #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */ |
| 153 | #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */ |
| 154 | #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */ |
| 155 | #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */ |
| 156 | #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */ |
| 157 | #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */ |
| 158 | #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */ |
| 159 | #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */ |
| 160 | #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */ |
| 161 | #define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */ |
| 162 | #define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */ |
| 163 | |
| 164 | /* Timeout values */ |
| 165 | #define TIMEOUT_US 1000 |
| 166 | |
| 167 | struct xpsgtr_dev; |
| 168 | |
| 169 | /** |
| 170 | * struct xpsgtr_ssc - structure to hold SSC settings for a lane |
| 171 | * @refclk_rate: PLL reference clock frequency |
| 172 | * @pll_ref_clk: value to be written to register for corresponding ref clk rate |
| 173 | * @steps: number of steps of SSC (Spread Spectrum Clock) |
| 174 | * @step_size: step size of each step |
| 175 | */ |
| 176 | struct xpsgtr_ssc { |
| 177 | u32 refclk_rate; |
| 178 | u8 pll_ref_clk; |
| 179 | u32 steps; |
| 180 | u32 step_size; |
| 181 | }; |
| 182 | |
| 183 | /** |
| 184 | * struct xpsgtr_phy - representation of a lane |
| 185 | * @phy: pointer to the kernel PHY device |
| 186 | * @type: controller which uses this lane |
| 187 | * @lane: lane number |
| 188 | * @protocol: protocol in which the lane operates |
| 189 | * @skip_phy_init: skip phy_init() if true |
| 190 | * @dev: pointer to the xpsgtr_dev instance |
| 191 | * @refclk: reference clock index |
| 192 | */ |
| 193 | struct xpsgtr_phy { |
| 194 | struct phy *phy; |
| 195 | u8 type; |
| 196 | u8 lane; |
| 197 | u8 protocol; |
| 198 | bool skip_phy_init; |
| 199 | struct xpsgtr_dev *dev; |
| 200 | unsigned int refclk; |
| 201 | }; |
| 202 | |
| 203 | /** |
| 204 | * struct xpsgtr_dev - representation of a ZynMP GT device |
| 205 | * @dev: pointer to device |
| 206 | * @serdes: serdes base address |
| 207 | * @siou: siou base address |
| 208 | * @gtr_mutex: mutex for locking |
| 209 | * @phys: PHY lanes |
| 210 | * @refclk_sscs: spread spectrum settings for the reference clocks |
| 211 | * @clk: reference clocks |
| 212 | * @tx_term_fix: fix for GT issue |
| 213 | * @saved_icm_cfg0: stored value of ICM CFG0 register |
| 214 | * @saved_icm_cfg1: stored value of ICM CFG1 register |
| 215 | */ |
| 216 | struct xpsgtr_dev { |
| 217 | struct device *dev; |
| 218 | void __iomem *serdes; |
| 219 | void __iomem *siou; |
| 220 | struct mutex gtr_mutex; /* mutex for locking */ |
| 221 | struct xpsgtr_phy phys[NUM_LANES]; |
| 222 | const struct xpsgtr_ssc *refclk_sscs[NUM_LANES]; |
| 223 | struct clk *clk[NUM_LANES]; |
| 224 | bool tx_term_fix; |
| 225 | unsigned int saved_icm_cfg0; |
| 226 | unsigned int saved_icm_cfg1; |
| 227 | }; |
| 228 | |
| 229 | /* |
| 230 | * Configuration Data |
| 231 | */ |
| 232 | |
| 233 | /* lookup table to hold all settings needed for a ref clock frequency */ |
| 234 | static const struct xpsgtr_ssc ssc_lookup[] = { |
| 235 | { 19200000, 0x05, 608, 264020 }, |
| 236 | { 20000000, 0x06, 634, 243454 }, |
| 237 | { 24000000, 0x07, 760, 168973 }, |
| 238 | { 26000000, 0x08, 824, 143860 }, |
| 239 | { 27000000, 0x09, 856, 86551 }, |
| 240 | { 38400000, 0x0a, 1218, 65896 }, |
| 241 | { 40000000, 0x0b, 634, 243454 }, |
| 242 | { 52000000, 0x0c, 824, 143860 }, |
| 243 | { 100000000, 0x0d, 1058, 87533 }, |
| 244 | { 108000000, 0x0e, 856, 86551 }, |
| 245 | { 125000000, 0x0f, 992, 119497 }, |
| 246 | { 135000000, 0x10, 1070, 55393 }, |
| 247 | { 150000000, 0x11, 792, 187091 } |
| 248 | }; |
| 249 | |
| 250 | /* |
| 251 | * I/O Accessors |
| 252 | */ |
| 253 | |
| 254 | static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg) |
| 255 | { |
| 256 | return readl(gtr_dev->serdes + reg); |
| 257 | } |
| 258 | |
| 259 | static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value) |
| 260 | { |
| 261 | writel(value, gtr_dev->serdes + reg); |
| 262 | } |
| 263 | |
| 264 | static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg, |
| 265 | u32 clr, u32 set) |
| 266 | { |
| 267 | u32 value = xpsgtr_read(gtr_dev, reg); |
| 268 | |
| 269 | value &= ~clr; |
| 270 | value |= set; |
| 271 | xpsgtr_write(gtr_dev, reg, value); |
| 272 | } |
| 273 | |
| 274 | static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg) |
| 275 | { |
| 276 | void __iomem *addr = gtr_phy->dev->serdes |
| 277 | + gtr_phy->lane * PHY_REG_OFFSET + reg; |
| 278 | |
| 279 | return readl(addr); |
| 280 | } |
| 281 | |
| 282 | static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy, |
| 283 | u32 reg, u32 value) |
| 284 | { |
| 285 | void __iomem *addr = gtr_phy->dev->serdes |
| 286 | + gtr_phy->lane * PHY_REG_OFFSET + reg; |
| 287 | |
| 288 | writel(value, addr); |
| 289 | } |
| 290 | |
| 291 | static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy, |
| 292 | u32 reg, u32 clr, u32 set) |
| 293 | { |
| 294 | void __iomem *addr = gtr_phy->dev->serdes |
| 295 | + gtr_phy->lane * PHY_REG_OFFSET + reg; |
| 296 | |
| 297 | writel((readl(addr) & ~clr) | set, addr); |
| 298 | } |
| 299 | |
| 300 | /* |
| 301 | * Hardware Configuration |
| 302 | */ |
| 303 | |
| 304 | /* Wait for the PLL to lock (with a timeout). */ |
| 305 | static int xpsgtr_wait_pll_lock(struct phy *phy) |
| 306 | { |
| 307 | struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
| 308 | struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 309 | unsigned int timeout = TIMEOUT_US; |
| 310 | int ret; |
| 311 | |
| 312 | dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); |
| 313 | |
| 314 | while (1) { |
| 315 | u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1); |
| 316 | |
| 317 | if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) { |
| 318 | ret = 0; |
| 319 | break; |
| 320 | } |
| 321 | |
| 322 | if (--timeout == 0) { |
| 323 | ret = -ETIMEDOUT; |
| 324 | break; |
| 325 | } |
| 326 | |
| 327 | udelay(1); |
| 328 | } |
| 329 | |
| 330 | if (ret == -ETIMEDOUT) |
| 331 | dev_err(gtr_dev->dev, |
| 332 | "lane %u (type %u, protocol %u): PLL lock timeout\n", |
| 333 | gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); |
| 334 | |
| 335 | return ret; |
| 336 | } |
| 337 | |
| 338 | /* Configure PLL and spread-sprectrum clock. */ |
| 339 | static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy) |
| 340 | { |
| 341 | const struct xpsgtr_ssc *ssc; |
| 342 | u32 step_size; |
| 343 | |
| 344 | ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; |
| 345 | step_size = ssc->step_size; |
| 346 | |
| 347 | xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), |
| 348 | PLL_FREQ_MASK, ssc->pll_ref_clk); |
| 349 | |
| 350 | /* Enable lane clock sharing, if required */ |
| 351 | if (gtr_phy->refclk != gtr_phy->lane) { |
| 352 | /* Lane3 Ref Clock Selection Register */ |
| 353 | xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), |
| 354 | L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); |
| 355 | } |
| 356 | |
| 357 | /* SSC step size [7:0] */ |
| 358 | xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB, |
| 359 | STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK); |
| 360 | |
| 361 | /* SSC step size [15:8] */ |
| 362 | step_size >>= STEP_SIZE_SHIFT; |
| 363 | xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1, |
| 364 | STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK); |
| 365 | |
| 366 | /* SSC step size [23:16] */ |
| 367 | step_size >>= STEP_SIZE_SHIFT; |
| 368 | xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2, |
| 369 | STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK); |
| 370 | |
| 371 | /* SSC steps [7:0] */ |
| 372 | xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB, |
| 373 | STEPS_0_MASK, ssc->steps & STEPS_0_MASK); |
| 374 | |
| 375 | /* SSC steps [10:8] */ |
| 376 | xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB, |
| 377 | STEPS_1_MASK, |
| 378 | (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); |
| 379 | |
| 380 | /* SSC step size [24:25] */ |
| 381 | step_size >>= STEP_SIZE_SHIFT; |
| 382 | xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB, |
| 383 | STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) | |
| 384 | FORCE_STEP_SIZE | FORCE_STEPS); |
| 385 | } |
| 386 | |
| 387 | /* Configure the lane protocol. */ |
| 388 | static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy) |
| 389 | { |
| 390 | struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 391 | u8 protocol = gtr_phy->protocol; |
| 392 | |
| 393 | switch (gtr_phy->lane) { |
| 394 | case 0: |
| 395 | xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol); |
| 396 | break; |
| 397 | case 1: |
| 398 | xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK, |
| 399 | protocol << ICM_CFG_SHIFT); |
| 400 | break; |
| 401 | case 2: |
| 402 | xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol); |
| 403 | break; |
| 404 | case 3: |
| 405 | xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK, |
| 406 | protocol << ICM_CFG_SHIFT); |
| 407 | break; |
| 408 | default: |
| 409 | /* We already checked 0 <= lane <= 3 */ |
| 410 | break; |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | /* Bypass (de)scrambler and 8b/10b decoder and encoder. */ |
| 415 | static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy) |
| 416 | { |
| 417 | xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER); |
| 418 | xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER); |
| 419 | } |
| 420 | |
| 421 | /* DP-specific initialization. */ |
| 422 | static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy) |
| 423 | { |
| 424 | xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45, |
| 425 | L0_TXPMD_TM_45_OVER_DP_MAIN | |
| 426 | L0_TXPMD_TM_45_ENABLE_DP_MAIN | |
| 427 | L0_TXPMD_TM_45_OVER_DP_POST1 | |
| 428 | L0_TXPMD_TM_45_OVER_DP_POST2 | |
| 429 | L0_TXPMD_TM_45_ENABLE_DP_POST2); |
| 430 | xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118, |
| 431 | L0_TX_ANA_TM_118_FORCE_17_0); |
| 432 | } |
| 433 | |
| 434 | /* SATA-specific initialization. */ |
| 435 | static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy) |
| 436 | { |
| 437 | struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 438 | |
| 439 | xpsgtr_bypass_scrambler_8b10b(gtr_phy); |
| 440 | |
| 441 | writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); |
| 442 | } |
| 443 | |
| 444 | /* SGMII-specific initialization. */ |
| 445 | static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) |
| 446 | { |
| 447 | struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 448 | |
| 449 | /* Set SGMII protocol TX and RX bus width to 10 bits. */ |
| 450 | xpsgtr_write(gtr_dev, TX_PROT_BUS_WIDTH, |
| 451 | PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT)); |
| 452 | xpsgtr_write(gtr_dev, RX_PROT_BUS_WIDTH, |
| 453 | PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT)); |
| 454 | |
| 455 | xpsgtr_bypass_scrambler_8b10b(gtr_phy); |
| 456 | } |
| 457 | |
| 458 | /* Configure TX de-emphasis and margining for DP. */ |
| 459 | static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, |
| 460 | unsigned int voltage) |
| 461 | { |
| 462 | static const u8 voltage_swing[4][4] = { |
| 463 | { 0x2a, 0x27, 0x24, 0x20 }, |
| 464 | { 0x27, 0x23, 0x20, 0xff }, |
| 465 | { 0x24, 0x20, 0xff, 0xff }, |
| 466 | { 0xff, 0xff, 0xff, 0xff } |
| 467 | }; |
| 468 | static const u8 pre_emphasis[4][4] = { |
| 469 | { 0x02, 0x02, 0x02, 0x02 }, |
| 470 | { 0x01, 0x01, 0x01, 0xff }, |
| 471 | { 0x00, 0x00, 0xff, 0xff }, |
| 472 | { 0xff, 0xff, 0xff, 0xff } |
| 473 | }; |
| 474 | |
| 475 | xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]); |
| 476 | xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]); |
| 477 | } |
| 478 | |
| 479 | /* |
| 480 | * PHY Operations |
| 481 | */ |
| 482 | |
| 483 | static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy) |
| 484 | { |
| 485 | /* |
| 486 | * As USB may save the snapshot of the states during hibernation, doing |
| 487 | * phy_init() will put the USB controller into reset, resulting in the |
| 488 | * losing of the saved snapshot. So try to avoid phy_init() for USB |
| 489 | * except when gtr_phy->skip_phy_init is false (this happens when FPD is |
| 490 | * shutdown during suspend or when gt lane is changed from current one) |
| 491 | */ |
| 492 | if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) |
| 493 | return false; |
| 494 | else |
| 495 | return true; |
| 496 | } |
| 497 | |
| 498 | /* |
| 499 | * There is a functional issue in the GT. The TX termination resistance can be |
| 500 | * out of spec due to a issue in the calibration logic. This is the workaround |
| 501 | * to fix it, required for XCZU9EG silicon. |
| 502 | */ |
| 503 | static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy) |
| 504 | { |
| 505 | struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 506 | u32 timeout = TIMEOUT_US; |
| 507 | u32 nsw; |
| 508 | |
| 509 | /* Enabling Test Mode control for CMN Rest */ |
| 510 | xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); |
| 511 | |
| 512 | /* Set Test Mode reset */ |
| 513 | xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN); |
| 514 | |
| 515 | xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00); |
| 516 | xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE); |
| 517 | |
| 518 | /* |
| 519 | * As a part of work around sequence for PMOS calibration fix, |
| 520 | * we need to configure any lane ICM_CFG to valid protocol. This |
| 521 | * will deassert the CMN_Resetn signal. |
| 522 | */ |
| 523 | xpsgtr_lane_set_protocol(gtr_phy); |
| 524 | |
| 525 | /* Clear Test Mode reset */ |
| 526 | xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); |
| 527 | |
| 528 | dev_dbg(gtr_dev->dev, "calibrating...\n"); |
| 529 | |
| 530 | do { |
| 531 | u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS); |
| 532 | |
| 533 | if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE) |
| 534 | break; |
| 535 | |
| 536 | if (!--timeout) { |
| 537 | dev_err(gtr_dev->dev, "calibration time out\n"); |
| 538 | return -ETIMEDOUT; |
| 539 | } |
| 540 | |
| 541 | udelay(1); |
| 542 | } while (timeout > 0); |
| 543 | |
| 544 | dev_dbg(gtr_dev->dev, "calibration done\n"); |
| 545 | |
| 546 | /* Reading NMOS Register Code */ |
| 547 | nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE; |
| 548 | |
| 549 | /* Set Test Mode reset */ |
| 550 | xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN); |
| 551 | |
| 552 | /* Writing NMOS register values back [5:3] */ |
| 553 | xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT); |
| 554 | |
| 555 | /* Writing NMOS register value [2:0] */ |
| 556 | xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, |
| 557 | ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) | |
| 558 | (1 << L3_NSW_PIPE_SHIFT)); |
| 559 | |
| 560 | /* Clear Test Mode reset */ |
| 561 | xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); |
| 562 | |
| 563 | return 0; |
| 564 | } |
| 565 | |
| 566 | static int xpsgtr_phy_init(struct phy *phy) |
| 567 | { |
| 568 | struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
| 569 | struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 570 | int ret = 0; |
| 571 | |
| 572 | mutex_lock(>r_dev->gtr_mutex); |
| 573 | |
| 574 | /* Skip initialization if not required. */ |
| 575 | if (!xpsgtr_phy_init_required(gtr_phy)) |
| 576 | goto out; |
| 577 | |
| 578 | if (gtr_dev->tx_term_fix) { |
| 579 | ret = xpsgtr_phy_tx_term_fix(gtr_phy); |
| 580 | if (ret < 0) |
| 581 | goto out; |
| 582 | |
| 583 | gtr_dev->tx_term_fix = false; |
| 584 | } |
| 585 | |
| 586 | /* Enable coarse code saturation limiting logic. */ |
| 587 | xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT); |
| 588 | |
| 589 | /* |
| 590 | * Configure the PLL, the lane protocol, and perform protocol-specific |
| 591 | * initialization. |
| 592 | */ |
| 593 | xpsgtr_configure_pll(gtr_phy); |
| 594 | xpsgtr_lane_set_protocol(gtr_phy); |
| 595 | |
| 596 | switch (gtr_phy->protocol) { |
| 597 | case ICM_PROTOCOL_DP: |
| 598 | xpsgtr_phy_init_dp(gtr_phy); |
| 599 | break; |
| 600 | |
| 601 | case ICM_PROTOCOL_SATA: |
| 602 | xpsgtr_phy_init_sata(gtr_phy); |
| 603 | break; |
| 604 | |
| 605 | case ICM_PROTOCOL_SGMII: |
| 606 | xpsgtr_phy_init_sgmii(gtr_phy); |
| 607 | break; |
| 608 | } |
| 609 | |
| 610 | out: |
| 611 | mutex_unlock(>r_dev->gtr_mutex); |
| 612 | return ret; |
| 613 | } |
| 614 | |
| 615 | static int xpsgtr_phy_exit(struct phy *phy) |
| 616 | { |
| 617 | struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
| 618 | |
| 619 | gtr_phy->skip_phy_init = false; |
| 620 | |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | static int xpsgtr_phy_power_on(struct phy *phy) |
| 625 | { |
| 626 | struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
| 627 | int ret = 0; |
| 628 | |
| 629 | /* |
| 630 | * Wait for the PLL to lock. For DP, only wait on DP0 to avoid |
| 631 | * cumulating waits for both lanes. The user is expected to initialize |
| 632 | * lane 0 last. |
| 633 | */ |
| 634 | if (gtr_phy->protocol != ICM_PROTOCOL_DP || |
| 635 | gtr_phy->type == XPSGTR_TYPE_DP_0) |
| 636 | ret = xpsgtr_wait_pll_lock(phy); |
| 637 | |
| 638 | return ret; |
| 639 | } |
| 640 | |
| 641 | static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts) |
| 642 | { |
| 643 | struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
| 644 | |
| 645 | if (gtr_phy->protocol != ICM_PROTOCOL_DP) |
| 646 | return 0; |
| 647 | |
| 648 | xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); |
| 649 | |
| 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | static const struct phy_ops xpsgtr_phyops = { |
| 654 | .init = xpsgtr_phy_init, |
| 655 | .exit = xpsgtr_phy_exit, |
| 656 | .power_on = xpsgtr_phy_power_on, |
| 657 | .configure = xpsgtr_phy_configure, |
| 658 | .owner = THIS_MODULE, |
| 659 | }; |
| 660 | |
| 661 | /* |
| 662 | * OF Xlate Support |
| 663 | */ |
| 664 | |
| 665 | /* Set the lane type and protocol based on the PHY type and instance number. */ |
| 666 | static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type, |
| 667 | unsigned int phy_instance) |
| 668 | { |
| 669 | unsigned int num_phy_types; |
| 670 | const int *phy_types; |
| 671 | |
| 672 | switch (phy_type) { |
| 673 | case PHY_TYPE_SATA: { |
| 674 | static const int types[] = { |
| 675 | XPSGTR_TYPE_SATA_0, |
| 676 | XPSGTR_TYPE_SATA_1, |
| 677 | }; |
| 678 | |
| 679 | phy_types = types; |
| 680 | num_phy_types = ARRAY_SIZE(types); |
| 681 | gtr_phy->protocol = ICM_PROTOCOL_SATA; |
| 682 | break; |
| 683 | } |
| 684 | case PHY_TYPE_USB3: { |
| 685 | static const int types[] = { |
| 686 | XPSGTR_TYPE_USB0, |
| 687 | XPSGTR_TYPE_USB1, |
| 688 | }; |
| 689 | |
| 690 | phy_types = types; |
| 691 | num_phy_types = ARRAY_SIZE(types); |
| 692 | gtr_phy->protocol = ICM_PROTOCOL_USB; |
| 693 | break; |
| 694 | } |
| 695 | case PHY_TYPE_DP: { |
| 696 | static const int types[] = { |
| 697 | XPSGTR_TYPE_DP_0, |
| 698 | XPSGTR_TYPE_DP_1, |
| 699 | }; |
| 700 | |
| 701 | phy_types = types; |
| 702 | num_phy_types = ARRAY_SIZE(types); |
| 703 | gtr_phy->protocol = ICM_PROTOCOL_DP; |
| 704 | break; |
| 705 | } |
| 706 | case PHY_TYPE_PCIE: { |
| 707 | static const int types[] = { |
| 708 | XPSGTR_TYPE_PCIE_0, |
| 709 | XPSGTR_TYPE_PCIE_1, |
| 710 | XPSGTR_TYPE_PCIE_2, |
| 711 | XPSGTR_TYPE_PCIE_3, |
| 712 | }; |
| 713 | |
| 714 | phy_types = types; |
| 715 | num_phy_types = ARRAY_SIZE(types); |
| 716 | gtr_phy->protocol = ICM_PROTOCOL_PCIE; |
| 717 | break; |
| 718 | } |
| 719 | case PHY_TYPE_SGMII: { |
| 720 | static const int types[] = { |
| 721 | XPSGTR_TYPE_SGMII0, |
| 722 | XPSGTR_TYPE_SGMII1, |
| 723 | XPSGTR_TYPE_SGMII2, |
| 724 | XPSGTR_TYPE_SGMII3, |
| 725 | }; |
| 726 | |
| 727 | phy_types = types; |
| 728 | num_phy_types = ARRAY_SIZE(types); |
| 729 | gtr_phy->protocol = ICM_PROTOCOL_SGMII; |
| 730 | break; |
| 731 | } |
| 732 | default: |
| 733 | return -EINVAL; |
| 734 | } |
| 735 | |
| 736 | if (phy_instance >= num_phy_types) |
| 737 | return -EINVAL; |
| 738 | |
| 739 | gtr_phy->type = phy_types[phy_instance]; |
| 740 | return 0; |
| 741 | } |
| 742 | |
| 743 | /* |
| 744 | * Valid combinations of controllers and lanes (Interconnect Matrix). |
| 745 | */ |
| 746 | static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = { |
| 747 | { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, |
| 748 | XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 }, |
| 749 | { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0, |
| 750 | XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 }, |
| 751 | { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, |
| 752 | XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 }, |
| 753 | { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1, |
| 754 | XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 } |
| 755 | }; |
| 756 | |
| 757 | /* Translate OF phandle and args to PHY instance. */ |
| 758 | static struct phy *xpsgtr_xlate(struct device *dev, |
| 759 | struct of_phandle_args *args) |
| 760 | { |
| 761 | struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); |
| 762 | struct xpsgtr_phy *gtr_phy; |
| 763 | unsigned int phy_instance; |
| 764 | unsigned int phy_lane; |
| 765 | unsigned int phy_type; |
| 766 | unsigned int refclk; |
| 767 | unsigned int i; |
| 768 | int ret; |
| 769 | |
| 770 | if (args->args_count != 4) { |
| 771 | dev_err(dev, "Invalid number of cells in 'phy' property\n"); |
| 772 | return ERR_PTR(-EINVAL); |
| 773 | } |
| 774 | |
| 775 | /* |
| 776 | * Get the PHY parameters from the OF arguments and derive the lane |
| 777 | * type. |
| 778 | */ |
| 779 | phy_lane = args->args[0]; |
| 780 | if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { |
| 781 | dev_err(dev, "Invalid lane number %u\n", phy_lane); |
| 782 | return ERR_PTR(-ENODEV); |
| 783 | } |
| 784 | |
| 785 | gtr_phy = >r_dev->phys[phy_lane]; |
| 786 | phy_type = args->args[1]; |
| 787 | phy_instance = args->args[2]; |
| 788 | |
| 789 | ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance); |
| 790 | if (ret < 0) { |
| 791 | dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); |
| 792 | return ERR_PTR(ret); |
| 793 | } |
| 794 | |
| 795 | refclk = args->args[3]; |
| 796 | if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || |
| 797 | !gtr_dev->refclk_sscs[refclk]) { |
| 798 | dev_err(dev, "Invalid reference clock number %u\n", refclk); |
| 799 | return ERR_PTR(-EINVAL); |
| 800 | } |
| 801 | |
| 802 | gtr_phy->refclk = refclk; |
| 803 | |
| 804 | /* |
| 805 | * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type |
| 806 | * is allowed to operate on the lane. |
| 807 | */ |
| 808 | for (i = 0; i < CONTROLLERS_PER_LANE; i++) { |
| 809 | if (icm_matrix[phy_lane][i] == gtr_phy->type) |
| 810 | return gtr_phy->phy; |
| 811 | } |
| 812 | |
| 813 | return ERR_PTR(-EINVAL); |
| 814 | } |
| 815 | |
| 816 | /* |
| 817 | * Power Management |
| 818 | */ |
| 819 | |
| 820 | static int __maybe_unused xpsgtr_suspend(struct device *dev) |
| 821 | { |
| 822 | struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); |
| 823 | unsigned int i; |
| 824 | |
| 825 | /* Save the snapshot ICM_CFG registers. */ |
| 826 | gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); |
| 827 | gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); |
| 828 | |
| 829 | for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) |
| 830 | clk_disable_unprepare(gtr_dev->clk[i]); |
| 831 | |
| 832 | return 0; |
| 833 | } |
| 834 | |
| 835 | static int __maybe_unused xpsgtr_resume(struct device *dev) |
| 836 | { |
| 837 | struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); |
| 838 | unsigned int icm_cfg0, icm_cfg1; |
| 839 | unsigned int i; |
| 840 | bool skip_phy_init; |
| 841 | int err; |
| 842 | |
| 843 | for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) { |
| 844 | err = clk_prepare_enable(gtr_dev->clk[i]); |
| 845 | if (err) |
| 846 | goto err_clk_put; |
| 847 | } |
| 848 | |
| 849 | icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); |
| 850 | icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); |
| 851 | |
| 852 | /* Return if no GT lanes got configured before suspend. */ |
| 853 | if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) |
| 854 | return 0; |
| 855 | |
| 856 | /* Check if the ICM configurations changed after suspend. */ |
| 857 | if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && |
| 858 | icm_cfg1 == gtr_dev->saved_icm_cfg1) |
| 859 | skip_phy_init = true; |
| 860 | else |
| 861 | skip_phy_init = false; |
| 862 | |
| 863 | /* Update the skip_phy_init for all gtr_phy instances. */ |
| 864 | for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) |
| 865 | gtr_dev->phys[i].skip_phy_init = skip_phy_init; |
| 866 | |
| 867 | return 0; |
| 868 | |
| 869 | err_clk_put: |
| 870 | while (i--) |
| 871 | clk_disable_unprepare(gtr_dev->clk[i]); |
| 872 | |
| 873 | return err; |
| 874 | } |
| 875 | |
| 876 | static const struct dev_pm_ops xpsgtr_pm_ops = { |
| 877 | SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume) |
| 878 | }; |
| 879 | |
| 880 | /* |
| 881 | * Probe & Platform Driver |
| 882 | */ |
| 883 | |
| 884 | static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev) |
| 885 | { |
| 886 | unsigned int refclk; |
| 887 | int ret; |
| 888 | |
| 889 | for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { |
| 890 | unsigned long rate; |
| 891 | unsigned int i; |
| 892 | struct clk *clk; |
| 893 | char name[8]; |
| 894 | |
| 895 | snprintf(name, sizeof(name), "ref%u", refclk); |
| 896 | clk = devm_clk_get_optional(gtr_dev->dev, name); |
| 897 | if (IS_ERR(clk)) { |
| 898 | ret = dev_err_probe(gtr_dev->dev, PTR_ERR(clk), |
| 899 | "Failed to get reference clock %u\n", |
| 900 | refclk); |
| 901 | goto err_clk_put; |
| 902 | } |
| 903 | |
| 904 | if (!clk) |
| 905 | continue; |
| 906 | |
| 907 | ret = clk_prepare_enable(clk); |
| 908 | if (ret) |
| 909 | goto err_clk_put; |
| 910 | |
| 911 | gtr_dev->clk[refclk] = clk; |
| 912 | |
| 913 | /* |
| 914 | * Get the spread spectrum (SSC) settings for the reference |
| 915 | * clock rate. |
| 916 | */ |
| 917 | rate = clk_get_rate(clk); |
| 918 | |
| 919 | for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) { |
| 920 | if (rate == ssc_lookup[i].refclk_rate) { |
| 921 | gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; |
| 922 | break; |
| 923 | } |
| 924 | } |
| 925 | |
| 926 | if (i == ARRAY_SIZE(ssc_lookup)) { |
| 927 | dev_err(gtr_dev->dev, |
| 928 | "Invalid rate %lu for reference clock %u\n", |
| 929 | rate, refclk); |
| 930 | ret = -EINVAL; |
| 931 | goto err_clk_put; |
| 932 | } |
| 933 | } |
| 934 | |
| 935 | return 0; |
| 936 | |
| 937 | err_clk_put: |
| 938 | while (refclk--) |
| 939 | clk_disable_unprepare(gtr_dev->clk[refclk]); |
| 940 | |
| 941 | return ret; |
| 942 | } |
| 943 | |
| 944 | static int xpsgtr_probe(struct platform_device *pdev) |
| 945 | { |
| 946 | struct device_node *np = pdev->dev.of_node; |
| 947 | struct xpsgtr_dev *gtr_dev; |
| 948 | struct phy_provider *provider; |
| 949 | unsigned int port; |
| 950 | unsigned int i; |
| 951 | int ret; |
| 952 | |
| 953 | gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); |
| 954 | if (!gtr_dev) |
| 955 | return -ENOMEM; |
| 956 | |
| 957 | gtr_dev->dev = &pdev->dev; |
| 958 | platform_set_drvdata(pdev, gtr_dev); |
| 959 | |
| 960 | mutex_init(>r_dev->gtr_mutex); |
| 961 | |
| 962 | if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) |
| 963 | gtr_dev->tx_term_fix = |
| 964 | of_property_read_bool(np, "xlnx,tx-termination-fix"); |
| 965 | |
| 966 | /* Acquire resources. */ |
| 967 | gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); |
| 968 | if (IS_ERR(gtr_dev->serdes)) |
| 969 | return PTR_ERR(gtr_dev->serdes); |
| 970 | |
| 971 | gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); |
| 972 | if (IS_ERR(gtr_dev->siou)) |
| 973 | return PTR_ERR(gtr_dev->siou); |
| 974 | |
| 975 | ret = xpsgtr_get_ref_clocks(gtr_dev); |
| 976 | if (ret) |
| 977 | return ret; |
| 978 | |
| 979 | /* Create PHYs. */ |
| 980 | for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { |
| 981 | struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; |
| 982 | struct phy *phy; |
| 983 | |
| 984 | gtr_phy->lane = port; |
| 985 | gtr_phy->dev = gtr_dev; |
| 986 | |
| 987 | phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); |
| 988 | if (IS_ERR(phy)) { |
| 989 | dev_err(&pdev->dev, "failed to create PHY\n"); |
| 990 | ret = PTR_ERR(phy); |
| 991 | goto err_clk_put; |
| 992 | } |
| 993 | |
| 994 | gtr_phy->phy = phy; |
| 995 | phy_set_drvdata(phy, gtr_phy); |
| 996 | } |
| 997 | |
| 998 | /* Register the PHY provider. */ |
| 999 | provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); |
| 1000 | if (IS_ERR(provider)) { |
| 1001 | dev_err(&pdev->dev, "registering provider failed\n"); |
| 1002 | ret = PTR_ERR(provider); |
| 1003 | goto err_clk_put; |
| 1004 | } |
| 1005 | return 0; |
| 1006 | |
| 1007 | err_clk_put: |
| 1008 | for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) |
| 1009 | clk_disable_unprepare(gtr_dev->clk[i]); |
| 1010 | |
| 1011 | return ret; |
| 1012 | } |
| 1013 | |
| 1014 | static const struct of_device_id xpsgtr_of_match[] = { |
| 1015 | { .compatible = "xlnx,zynqmp-psgtr", }, |
| 1016 | { .compatible = "xlnx,zynqmp-psgtr-v1.1", }, |
| 1017 | {}, |
| 1018 | }; |
| 1019 | MODULE_DEVICE_TABLE(of, xpsgtr_of_match); |
| 1020 | |
| 1021 | static struct platform_driver xpsgtr_driver = { |
| 1022 | .probe = xpsgtr_probe, |
| 1023 | .driver = { |
| 1024 | .name = "xilinx-psgtr", |
| 1025 | .of_match_table = xpsgtr_of_match, |
| 1026 | .pm = &xpsgtr_pm_ops, |
| 1027 | }, |
| 1028 | }; |
| 1029 | |
| 1030 | module_platform_driver(xpsgtr_driver); |
| 1031 | |
| 1032 | MODULE_AUTHOR("Xilinx Inc."); |
| 1033 | MODULE_LICENSE("GPL v2"); |
| 1034 | MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver"); |