| 1 | /* |
| 2 | * PCI Express PCI Hot Plug Driver |
| 3 | * |
| 4 | * Copyright (C) 1995,2001 Compaq Computer Corporation |
| 5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) |
| 6 | * Copyright (C) 2001 IBM Corp. |
| 7 | * Copyright (C) 2003-2004 Intel Corporation |
| 8 | * |
| 9 | * All rights reserved. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or (at |
| 14 | * your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 19 | * NON INFRINGEMENT. See the GNU General Public License for more |
| 20 | * details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * |
| 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/types.h> |
| 33 | #include <linux/signal.h> |
| 34 | #include <linux/jiffies.h> |
| 35 | #include <linux/timer.h> |
| 36 | #include <linux/pci.h> |
| 37 | #include <linux/interrupt.h> |
| 38 | #include <linux/time.h> |
| 39 | #include <linux/slab.h> |
| 40 | |
| 41 | #include "../pci.h" |
| 42 | #include "pciehp.h" |
| 43 | |
| 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
| 45 | { |
| 46 | return ctrl->pcie->port; |
| 47 | } |
| 48 | |
| 49 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
| 50 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
| 51 | |
| 52 | /* This is the interrupt polling timeout function. */ |
| 53 | static void int_poll_timeout(unsigned long data) |
| 54 | { |
| 55 | struct controller *ctrl = (struct controller *)data; |
| 56 | |
| 57 | /* Poll for interrupt events. regs == NULL => polling */ |
| 58 | pcie_isr(0, ctrl); |
| 59 | |
| 60 | init_timer(&ctrl->poll_timer); |
| 61 | if (!pciehp_poll_time) |
| 62 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
| 63 | |
| 64 | start_int_poll_timer(ctrl, pciehp_poll_time); |
| 65 | } |
| 66 | |
| 67 | /* This function starts the interrupt polling timer. */ |
| 68 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
| 69 | { |
| 70 | /* Clamp to sane value */ |
| 71 | if ((sec <= 0) || (sec > 60)) |
| 72 | sec = 2; |
| 73 | |
| 74 | ctrl->poll_timer.function = &int_poll_timeout; |
| 75 | ctrl->poll_timer.data = (unsigned long)ctrl; |
| 76 | ctrl->poll_timer.expires = jiffies + sec * HZ; |
| 77 | add_timer(&ctrl->poll_timer); |
| 78 | } |
| 79 | |
| 80 | static inline int pciehp_request_irq(struct controller *ctrl) |
| 81 | { |
| 82 | int retval, irq = ctrl->pcie->irq; |
| 83 | |
| 84 | /* Install interrupt polling timer. Start with 10 sec delay */ |
| 85 | if (pciehp_poll_mode) { |
| 86 | init_timer(&ctrl->poll_timer); |
| 87 | start_int_poll_timer(ctrl, 10); |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | /* Installs the interrupt handler */ |
| 92 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); |
| 93 | if (retval) |
| 94 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
| 95 | irq); |
| 96 | return retval; |
| 97 | } |
| 98 | |
| 99 | static inline void pciehp_free_irq(struct controller *ctrl) |
| 100 | { |
| 101 | if (pciehp_poll_mode) |
| 102 | del_timer_sync(&ctrl->poll_timer); |
| 103 | else |
| 104 | free_irq(ctrl->pcie->irq, ctrl); |
| 105 | } |
| 106 | |
| 107 | static int pcie_poll_cmd(struct controller *ctrl) |
| 108 | { |
| 109 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 110 | u16 slot_status; |
| 111 | int timeout = 1000; |
| 112 | |
| 113 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 114 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
| 115 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
| 116 | PCI_EXP_SLTSTA_CC); |
| 117 | return 1; |
| 118 | } |
| 119 | while (timeout > 0) { |
| 120 | msleep(10); |
| 121 | timeout -= 10; |
| 122 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 123 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
| 124 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
| 125 | PCI_EXP_SLTSTA_CC); |
| 126 | return 1; |
| 127 | } |
| 128 | } |
| 129 | return 0; /* timeout */ |
| 130 | } |
| 131 | |
| 132 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
| 133 | { |
| 134 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
| 135 | unsigned long timeout = msecs_to_jiffies(msecs); |
| 136 | int rc; |
| 137 | |
| 138 | if (poll) |
| 139 | rc = pcie_poll_cmd(ctrl); |
| 140 | else |
| 141 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
| 142 | if (!rc) |
| 143 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
| 144 | } |
| 145 | |
| 146 | /** |
| 147 | * pcie_write_cmd - Issue controller command |
| 148 | * @ctrl: controller to which the command is issued |
| 149 | * @cmd: command value written to slot control register |
| 150 | * @mask: bitmask of slot control register to be modified |
| 151 | */ |
| 152 | static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
| 153 | { |
| 154 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 155 | u16 slot_status; |
| 156 | u16 slot_ctrl; |
| 157 | |
| 158 | mutex_lock(&ctrl->ctrl_lock); |
| 159 | |
| 160 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 161 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
| 162 | if (!ctrl->no_cmd_complete) { |
| 163 | /* |
| 164 | * After 1 sec and CMD_COMPLETED still not set, just |
| 165 | * proceed forward to issue the next command according |
| 166 | * to spec. Just print out the error message. |
| 167 | */ |
| 168 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
| 169 | } else if (!NO_CMD_CMPL(ctrl)) { |
| 170 | /* |
| 171 | * This controller seems to notify of command completed |
| 172 | * event even though it supports none of power |
| 173 | * controller, attention led, power led and EMI. |
| 174 | */ |
| 175 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
| 176 | "wait for command completed event.\n"); |
| 177 | ctrl->no_cmd_complete = 0; |
| 178 | } else { |
| 179 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
| 180 | "the controller is broken.\n"); |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
| 185 | slot_ctrl &= ~mask; |
| 186 | slot_ctrl |= (cmd & mask); |
| 187 | ctrl->cmd_busy = 1; |
| 188 | smp_mb(); |
| 189 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
| 190 | |
| 191 | /* |
| 192 | * Wait for command completion. |
| 193 | */ |
| 194 | if (!ctrl->no_cmd_complete) { |
| 195 | int poll = 0; |
| 196 | /* |
| 197 | * if hotplug interrupt is not enabled or command |
| 198 | * completed interrupt is not enabled, we need to poll |
| 199 | * command completed event. |
| 200 | */ |
| 201 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
| 202 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) |
| 203 | poll = 1; |
| 204 | pcie_wait_cmd(ctrl, poll); |
| 205 | } |
| 206 | mutex_unlock(&ctrl->ctrl_lock); |
| 207 | } |
| 208 | |
| 209 | static bool check_link_active(struct controller *ctrl) |
| 210 | { |
| 211 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 212 | u16 lnk_status; |
| 213 | bool ret; |
| 214 | |
| 215 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
| 216 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
| 217 | |
| 218 | if (ret) |
| 219 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
| 220 | |
| 221 | return ret; |
| 222 | } |
| 223 | |
| 224 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
| 225 | { |
| 226 | int timeout = 1000; |
| 227 | |
| 228 | if (check_link_active(ctrl) == active) |
| 229 | return; |
| 230 | while (timeout > 0) { |
| 231 | msleep(10); |
| 232 | timeout -= 10; |
| 233 | if (check_link_active(ctrl) == active) |
| 234 | return; |
| 235 | } |
| 236 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
| 237 | active ? "set" : "cleared"); |
| 238 | } |
| 239 | |
| 240 | static void pcie_wait_link_active(struct controller *ctrl) |
| 241 | { |
| 242 | __pcie_wait_link_active(ctrl, true); |
| 243 | } |
| 244 | |
| 245 | static void pcie_wait_link_not_active(struct controller *ctrl) |
| 246 | { |
| 247 | __pcie_wait_link_active(ctrl, false); |
| 248 | } |
| 249 | |
| 250 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
| 251 | { |
| 252 | u32 l; |
| 253 | int count = 0; |
| 254 | int delay = 1000, step = 20; |
| 255 | bool found = false; |
| 256 | |
| 257 | do { |
| 258 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); |
| 259 | count++; |
| 260 | |
| 261 | if (found) |
| 262 | break; |
| 263 | |
| 264 | msleep(step); |
| 265 | delay -= step; |
| 266 | } while (delay > 0); |
| 267 | |
| 268 | if (count > 1 && pciehp_debug) |
| 269 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", |
| 270 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), |
| 271 | PCI_FUNC(devfn), count, step, l); |
| 272 | |
| 273 | return found; |
| 274 | } |
| 275 | |
| 276 | int pciehp_check_link_status(struct controller *ctrl) |
| 277 | { |
| 278 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 279 | bool found; |
| 280 | u16 lnk_status; |
| 281 | |
| 282 | /* |
| 283 | * Data Link Layer Link Active Reporting must be capable for |
| 284 | * hot-plug capable downstream port. But old controller might |
| 285 | * not implement it. In this case, we wait for 1000 ms. |
| 286 | */ |
| 287 | if (ctrl->link_active_reporting) |
| 288 | pcie_wait_link_active(ctrl); |
| 289 | else |
| 290 | msleep(1000); |
| 291 | |
| 292 | /* wait 100ms before read pci conf, and try in 1s */ |
| 293 | msleep(100); |
| 294 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, |
| 295 | PCI_DEVFN(0, 0)); |
| 296 | |
| 297 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
| 298 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
| 299 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
| 300 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { |
| 301 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
| 302 | return -1; |
| 303 | } |
| 304 | |
| 305 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
| 306 | |
| 307 | if (!found) |
| 308 | return -1; |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
| 314 | { |
| 315 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 316 | u16 lnk_ctrl; |
| 317 | |
| 318 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
| 319 | |
| 320 | if (enable) |
| 321 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; |
| 322 | else |
| 323 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; |
| 324 | |
| 325 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
| 326 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
| 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | static int pciehp_link_enable(struct controller *ctrl) |
| 331 | { |
| 332 | return __pciehp_link_set(ctrl, true); |
| 333 | } |
| 334 | |
| 335 | static int pciehp_link_disable(struct controller *ctrl) |
| 336 | { |
| 337 | return __pciehp_link_set(ctrl, false); |
| 338 | } |
| 339 | |
| 340 | void pciehp_get_attention_status(struct slot *slot, u8 *status) |
| 341 | { |
| 342 | struct controller *ctrl = slot->ctrl; |
| 343 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 344 | u16 slot_ctrl; |
| 345 | |
| 346 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
| 347 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
| 348 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); |
| 349 | |
| 350 | switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { |
| 351 | case PCI_EXP_SLTCTL_ATTN_IND_ON: |
| 352 | *status = 1; /* On */ |
| 353 | break; |
| 354 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
| 355 | *status = 2; /* Blink */ |
| 356 | break; |
| 357 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
| 358 | *status = 0; /* Off */ |
| 359 | break; |
| 360 | default: |
| 361 | *status = 0xFF; |
| 362 | break; |
| 363 | } |
| 364 | } |
| 365 | |
| 366 | void pciehp_get_power_status(struct slot *slot, u8 *status) |
| 367 | { |
| 368 | struct controller *ctrl = slot->ctrl; |
| 369 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 370 | u16 slot_ctrl; |
| 371 | |
| 372 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
| 373 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
| 374 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); |
| 375 | |
| 376 | switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { |
| 377 | case PCI_EXP_SLTCTL_PWR_ON: |
| 378 | *status = 1; /* On */ |
| 379 | break; |
| 380 | case PCI_EXP_SLTCTL_PWR_OFF: |
| 381 | *status = 0; /* Off */ |
| 382 | break; |
| 383 | default: |
| 384 | *status = 0xFF; |
| 385 | break; |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | void pciehp_get_latch_status(struct slot *slot, u8 *status) |
| 390 | { |
| 391 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
| 392 | u16 slot_status; |
| 393 | |
| 394 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 395 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
| 396 | } |
| 397 | |
| 398 | void pciehp_get_adapter_status(struct slot *slot, u8 *status) |
| 399 | { |
| 400 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
| 401 | u16 slot_status; |
| 402 | |
| 403 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 404 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
| 405 | } |
| 406 | |
| 407 | int pciehp_query_power_fault(struct slot *slot) |
| 408 | { |
| 409 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
| 410 | u16 slot_status; |
| 411 | |
| 412 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 413 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
| 414 | } |
| 415 | |
| 416 | void pciehp_set_attention_status(struct slot *slot, u8 value) |
| 417 | { |
| 418 | struct controller *ctrl = slot->ctrl; |
| 419 | u16 slot_cmd; |
| 420 | |
| 421 | if (!ATTN_LED(ctrl)) |
| 422 | return; |
| 423 | |
| 424 | switch (value) { |
| 425 | case 0 : /* turn off */ |
| 426 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; |
| 427 | break; |
| 428 | case 1: /* turn on */ |
| 429 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; |
| 430 | break; |
| 431 | case 2: /* turn blink */ |
| 432 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; |
| 433 | break; |
| 434 | default: |
| 435 | return; |
| 436 | } |
| 437 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 438 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
| 439 | pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); |
| 440 | } |
| 441 | |
| 442 | void pciehp_green_led_on(struct slot *slot) |
| 443 | { |
| 444 | struct controller *ctrl = slot->ctrl; |
| 445 | |
| 446 | if (!PWR_LED(ctrl)) |
| 447 | return; |
| 448 | |
| 449 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC); |
| 450 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 451 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
| 452 | PCI_EXP_SLTCTL_PWR_IND_ON); |
| 453 | } |
| 454 | |
| 455 | void pciehp_green_led_off(struct slot *slot) |
| 456 | { |
| 457 | struct controller *ctrl = slot->ctrl; |
| 458 | |
| 459 | if (!PWR_LED(ctrl)) |
| 460 | return; |
| 461 | |
| 462 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC); |
| 463 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 464 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
| 465 | PCI_EXP_SLTCTL_PWR_IND_OFF); |
| 466 | } |
| 467 | |
| 468 | void pciehp_green_led_blink(struct slot *slot) |
| 469 | { |
| 470 | struct controller *ctrl = slot->ctrl; |
| 471 | |
| 472 | if (!PWR_LED(ctrl)) |
| 473 | return; |
| 474 | |
| 475 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC); |
| 476 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 477 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
| 478 | PCI_EXP_SLTCTL_PWR_IND_BLINK); |
| 479 | } |
| 480 | |
| 481 | int pciehp_power_on_slot(struct slot * slot) |
| 482 | { |
| 483 | struct controller *ctrl = slot->ctrl; |
| 484 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 485 | u16 slot_status; |
| 486 | int retval; |
| 487 | |
| 488 | /* Clear sticky power-fault bit from previous power failures */ |
| 489 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
| 490 | if (slot_status & PCI_EXP_SLTSTA_PFD) |
| 491 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
| 492 | PCI_EXP_SLTSTA_PFD); |
| 493 | ctrl->power_fault_detected = 0; |
| 494 | |
| 495 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); |
| 496 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 497 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
| 498 | PCI_EXP_SLTCTL_PWR_ON); |
| 499 | |
| 500 | retval = pciehp_link_enable(ctrl); |
| 501 | if (retval) |
| 502 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); |
| 503 | |
| 504 | return retval; |
| 505 | } |
| 506 | |
| 507 | void pciehp_power_off_slot(struct slot * slot) |
| 508 | { |
| 509 | struct controller *ctrl = slot->ctrl; |
| 510 | |
| 511 | /* Disable the link at first */ |
| 512 | pciehp_link_disable(ctrl); |
| 513 | /* wait the link is down */ |
| 514 | if (ctrl->link_active_reporting) |
| 515 | pcie_wait_link_not_active(ctrl); |
| 516 | else |
| 517 | msleep(1000); |
| 518 | |
| 519 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); |
| 520 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 521 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
| 522 | PCI_EXP_SLTCTL_PWR_OFF); |
| 523 | } |
| 524 | |
| 525 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
| 526 | { |
| 527 | struct controller *ctrl = (struct controller *)dev_id; |
| 528 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 529 | struct slot *slot = ctrl->slot; |
| 530 | u16 detected, intr_loc; |
| 531 | |
| 532 | /* |
| 533 | * In order to guarantee that all interrupt events are |
| 534 | * serviced, we need to re-inspect Slot Status register after |
| 535 | * clearing what is presumed to be the last pending interrupt. |
| 536 | */ |
| 537 | intr_loc = 0; |
| 538 | do { |
| 539 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); |
| 540 | |
| 541 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
| 542 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | |
| 543 | PCI_EXP_SLTSTA_CC); |
| 544 | detected &= ~intr_loc; |
| 545 | intr_loc |= detected; |
| 546 | if (!intr_loc) |
| 547 | return IRQ_NONE; |
| 548 | if (detected) |
| 549 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
| 550 | intr_loc); |
| 551 | } while (detected); |
| 552 | |
| 553 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
| 554 | |
| 555 | /* Check Command Complete Interrupt Pending */ |
| 556 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
| 557 | ctrl->cmd_busy = 0; |
| 558 | smp_mb(); |
| 559 | wake_up(&ctrl->queue); |
| 560 | } |
| 561 | |
| 562 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
| 563 | return IRQ_HANDLED; |
| 564 | |
| 565 | /* Check MRL Sensor Changed */ |
| 566 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
| 567 | pciehp_handle_switch_change(slot); |
| 568 | |
| 569 | /* Check Attention Button Pressed */ |
| 570 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
| 571 | pciehp_handle_attention_button(slot); |
| 572 | |
| 573 | /* Check Presence Detect Changed */ |
| 574 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
| 575 | pciehp_handle_presence_change(slot); |
| 576 | |
| 577 | /* Check Power Fault Detected */ |
| 578 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
| 579 | ctrl->power_fault_detected = 1; |
| 580 | pciehp_handle_power_fault(slot); |
| 581 | } |
| 582 | return IRQ_HANDLED; |
| 583 | } |
| 584 | |
| 585 | void pcie_enable_notification(struct controller *ctrl) |
| 586 | { |
| 587 | u16 cmd, mask; |
| 588 | |
| 589 | /* |
| 590 | * TBD: Power fault detected software notification support. |
| 591 | * |
| 592 | * Power fault detected software notification is not enabled |
| 593 | * now, because it caused power fault detected interrupt storm |
| 594 | * on some machines. On those machines, power fault detected |
| 595 | * bit in the slot status register was set again immediately |
| 596 | * when it is cleared in the interrupt service routine, and |
| 597 | * next power fault detected interrupt was notified again. |
| 598 | */ |
| 599 | cmd = PCI_EXP_SLTCTL_PDCE; |
| 600 | if (ATTN_BUTTN(ctrl)) |
| 601 | cmd |= PCI_EXP_SLTCTL_ABPE; |
| 602 | if (MRL_SENS(ctrl)) |
| 603 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
| 604 | if (!pciehp_poll_mode) |
| 605 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
| 606 | |
| 607 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
| 608 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | |
| 609 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); |
| 610 | |
| 611 | pcie_write_cmd(ctrl, cmd, mask); |
| 612 | } |
| 613 | |
| 614 | static void pcie_disable_notification(struct controller *ctrl) |
| 615 | { |
| 616 | u16 mask; |
| 617 | |
| 618 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
| 619 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | |
| 620 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
| 621 | PCI_EXP_SLTCTL_DLLSCE); |
| 622 | pcie_write_cmd(ctrl, 0, mask); |
| 623 | } |
| 624 | |
| 625 | /* |
| 626 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary |
| 627 | * bus reset of the bridge, but if the slot supports surprise removal we need |
| 628 | * to disable presence detection around the bus reset and clear any spurious |
| 629 | * events after. |
| 630 | */ |
| 631 | int pciehp_reset_slot(struct slot *slot, int probe) |
| 632 | { |
| 633 | struct controller *ctrl = slot->ctrl; |
| 634 | struct pci_dev *pdev = ctrl_dev(ctrl); |
| 635 | |
| 636 | if (probe) |
| 637 | return 0; |
| 638 | |
| 639 | if (HP_SUPR_RM(ctrl)) { |
| 640 | pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); |
| 641 | if (pciehp_poll_mode) |
| 642 | del_timer_sync(&ctrl->poll_timer); |
| 643 | } |
| 644 | |
| 645 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); |
| 646 | |
| 647 | if (HP_SUPR_RM(ctrl)) { |
| 648 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
| 649 | PCI_EXP_SLTSTA_PDC); |
| 650 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
| 651 | if (pciehp_poll_mode) |
| 652 | int_poll_timeout(ctrl->poll_timer.data); |
| 653 | } |
| 654 | |
| 655 | return 0; |
| 656 | } |
| 657 | |
| 658 | int pcie_init_notification(struct controller *ctrl) |
| 659 | { |
| 660 | if (pciehp_request_irq(ctrl)) |
| 661 | return -1; |
| 662 | pcie_enable_notification(ctrl); |
| 663 | ctrl->notification_enabled = 1; |
| 664 | return 0; |
| 665 | } |
| 666 | |
| 667 | static void pcie_shutdown_notification(struct controller *ctrl) |
| 668 | { |
| 669 | if (ctrl->notification_enabled) { |
| 670 | pcie_disable_notification(ctrl); |
| 671 | pciehp_free_irq(ctrl); |
| 672 | ctrl->notification_enabled = 0; |
| 673 | } |
| 674 | } |
| 675 | |
| 676 | static int pcie_init_slot(struct controller *ctrl) |
| 677 | { |
| 678 | struct slot *slot; |
| 679 | |
| 680 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 681 | if (!slot) |
| 682 | return -ENOMEM; |
| 683 | |
| 684 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
| 685 | if (!slot->wq) |
| 686 | goto abort; |
| 687 | |
| 688 | slot->ctrl = ctrl; |
| 689 | mutex_init(&slot->lock); |
| 690 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); |
| 691 | ctrl->slot = slot; |
| 692 | return 0; |
| 693 | abort: |
| 694 | kfree(slot); |
| 695 | return -ENOMEM; |
| 696 | } |
| 697 | |
| 698 | static void pcie_cleanup_slot(struct controller *ctrl) |
| 699 | { |
| 700 | struct slot *slot = ctrl->slot; |
| 701 | cancel_delayed_work(&slot->work); |
| 702 | destroy_workqueue(slot->wq); |
| 703 | kfree(slot); |
| 704 | } |
| 705 | |
| 706 | static inline void dbg_ctrl(struct controller *ctrl) |
| 707 | { |
| 708 | int i; |
| 709 | u16 reg16; |
| 710 | struct pci_dev *pdev = ctrl->pcie->port; |
| 711 | |
| 712 | if (!pciehp_debug) |
| 713 | return; |
| 714 | |
| 715 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
| 716 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", |
| 717 | pci_name(pdev), pdev->irq); |
| 718 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); |
| 719 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); |
| 720 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", |
| 721 | pdev->subsystem_device); |
| 722 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", |
| 723 | pdev->subsystem_vendor); |
| 724 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
| 725 | pci_pcie_cap(pdev)); |
| 726 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 727 | if (!pci_resource_len(pdev, i)) |
| 728 | continue; |
| 729 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
| 730 | i, &pdev->resource[i]); |
| 731 | } |
| 732 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
| 733 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
| 734 | ctrl_info(ctrl, " Attention Button : %3s\n", |
| 735 | ATTN_BUTTN(ctrl) ? "yes" : "no"); |
| 736 | ctrl_info(ctrl, " Power Controller : %3s\n", |
| 737 | POWER_CTRL(ctrl) ? "yes" : "no"); |
| 738 | ctrl_info(ctrl, " MRL Sensor : %3s\n", |
| 739 | MRL_SENS(ctrl) ? "yes" : "no"); |
| 740 | ctrl_info(ctrl, " Attention Indicator : %3s\n", |
| 741 | ATTN_LED(ctrl) ? "yes" : "no"); |
| 742 | ctrl_info(ctrl, " Power Indicator : %3s\n", |
| 743 | PWR_LED(ctrl) ? "yes" : "no"); |
| 744 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", |
| 745 | HP_SUPR_RM(ctrl) ? "yes" : "no"); |
| 746 | ctrl_info(ctrl, " EMI Present : %3s\n", |
| 747 | EMI(ctrl) ? "yes" : "no"); |
| 748 | ctrl_info(ctrl, " Command Completed : %3s\n", |
| 749 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); |
| 750 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
| 751 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
| 752 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
| 753 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
| 754 | } |
| 755 | |
| 756 | #define FLAG(x,y) (((x) & (y)) ? '+' : '-') |
| 757 | |
| 758 | struct controller *pcie_init(struct pcie_device *dev) |
| 759 | { |
| 760 | struct controller *ctrl; |
| 761 | u32 slot_cap, link_cap; |
| 762 | struct pci_dev *pdev = dev->port; |
| 763 | |
| 764 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
| 765 | if (!ctrl) { |
| 766 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
| 767 | goto abort; |
| 768 | } |
| 769 | ctrl->pcie = dev; |
| 770 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
| 771 | ctrl->slot_cap = slot_cap; |
| 772 | mutex_init(&ctrl->ctrl_lock); |
| 773 | init_waitqueue_head(&ctrl->queue); |
| 774 | dbg_ctrl(ctrl); |
| 775 | /* |
| 776 | * Controller doesn't notify of command completion if the "No |
| 777 | * Command Completed Support" bit is set in Slot Capability |
| 778 | * register or the controller supports none of power |
| 779 | * controller, attention led, power led and EMI. |
| 780 | */ |
| 781 | if (NO_CMD_CMPL(ctrl) || |
| 782 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) |
| 783 | ctrl->no_cmd_complete = 1; |
| 784 | |
| 785 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
| 786 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); |
| 787 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
| 788 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
| 789 | ctrl->link_active_reporting = 1; |
| 790 | } |
| 791 | |
| 792 | /* Clear all remaining event bits in Slot Status register */ |
| 793 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
| 794 | PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
| 795 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | |
| 796 | PCI_EXP_SLTSTA_CC); |
| 797 | |
| 798 | /* Disable software notification */ |
| 799 | pcie_disable_notification(ctrl); |
| 800 | |
| 801 | ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", |
| 802 | (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, |
| 803 | FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), |
| 804 | FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), |
| 805 | FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), |
| 806 | FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), |
| 807 | FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), |
| 808 | FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), |
| 809 | FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), |
| 810 | FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); |
| 811 | |
| 812 | if (pcie_init_slot(ctrl)) |
| 813 | goto abort_ctrl; |
| 814 | |
| 815 | return ctrl; |
| 816 | |
| 817 | abort_ctrl: |
| 818 | kfree(ctrl); |
| 819 | abort: |
| 820 | return NULL; |
| 821 | } |
| 822 | |
| 823 | void pciehp_release_ctrl(struct controller *ctrl) |
| 824 | { |
| 825 | pcie_shutdown_notification(ctrl); |
| 826 | pcie_cleanup_slot(ctrl); |
| 827 | kfree(ctrl); |
| 828 | } |