| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * NVM Express device driver |
| 4 | * Copyright (c) 2011-2014, Intel Corporation. |
| 5 | */ |
| 6 | |
| 7 | #include <linux/aer.h> |
| 8 | #include <linux/async.h> |
| 9 | #include <linux/blkdev.h> |
| 10 | #include <linux/blk-mq.h> |
| 11 | #include <linux/blk-mq-pci.h> |
| 12 | #include <linux/dmi.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/mm.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/mutex.h> |
| 19 | #include <linux/once.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/suspend.h> |
| 22 | #include <linux/t10-pi.h> |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/io-64-nonatomic-lo-hi.h> |
| 25 | #include <linux/sed-opal.h> |
| 26 | #include <linux/pci-p2pdma.h> |
| 27 | |
| 28 | #include "trace.h" |
| 29 | #include "nvme.h" |
| 30 | |
| 31 | #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) |
| 32 | #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) |
| 33 | |
| 34 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
| 35 | |
| 36 | /* |
| 37 | * These can be higher, but we need to ensure that any command doesn't |
| 38 | * require an sg allocation that needs more than a page of data. |
| 39 | */ |
| 40 | #define NVME_MAX_KB_SZ 4096 |
| 41 | #define NVME_MAX_SEGS 127 |
| 42 | |
| 43 | static int use_threaded_interrupts; |
| 44 | module_param(use_threaded_interrupts, int, 0); |
| 45 | |
| 46 | static bool use_cmb_sqes = true; |
| 47 | module_param(use_cmb_sqes, bool, 0444); |
| 48 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); |
| 49 | |
| 50 | static unsigned int max_host_mem_size_mb = 128; |
| 51 | module_param(max_host_mem_size_mb, uint, 0444); |
| 52 | MODULE_PARM_DESC(max_host_mem_size_mb, |
| 53 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); |
| 54 | |
| 55 | static unsigned int sgl_threshold = SZ_32K; |
| 56 | module_param(sgl_threshold, uint, 0644); |
| 57 | MODULE_PARM_DESC(sgl_threshold, |
| 58 | "Use SGLs when average request segment size is larger or equal to " |
| 59 | "this size. Use 0 to disable SGLs."); |
| 60 | |
| 61 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
| 62 | static const struct kernel_param_ops io_queue_depth_ops = { |
| 63 | .set = io_queue_depth_set, |
| 64 | .get = param_get_int, |
| 65 | }; |
| 66 | |
| 67 | static int io_queue_depth = 1024; |
| 68 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); |
| 69 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); |
| 70 | |
| 71 | static unsigned int write_queues; |
| 72 | module_param(write_queues, uint, 0644); |
| 73 | MODULE_PARM_DESC(write_queues, |
| 74 | "Number of queues to use for writes. If not set, reads and writes " |
| 75 | "will share a queue set."); |
| 76 | |
| 77 | static unsigned int poll_queues; |
| 78 | module_param(poll_queues, uint, 0644); |
| 79 | MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); |
| 80 | |
| 81 | struct nvme_dev; |
| 82 | struct nvme_queue; |
| 83 | |
| 84 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
| 85 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); |
| 86 | |
| 87 | /* |
| 88 | * Represents an NVM Express device. Each nvme_dev is a PCI function. |
| 89 | */ |
| 90 | struct nvme_dev { |
| 91 | struct nvme_queue *queues; |
| 92 | struct blk_mq_tag_set tagset; |
| 93 | struct blk_mq_tag_set admin_tagset; |
| 94 | u32 __iomem *dbs; |
| 95 | struct device *dev; |
| 96 | struct dma_pool *prp_page_pool; |
| 97 | struct dma_pool *prp_small_pool; |
| 98 | unsigned online_queues; |
| 99 | unsigned max_qid; |
| 100 | unsigned io_queues[HCTX_MAX_TYPES]; |
| 101 | unsigned int num_vecs; |
| 102 | int q_depth; |
| 103 | int io_sqes; |
| 104 | u32 db_stride; |
| 105 | void __iomem *bar; |
| 106 | unsigned long bar_mapped_size; |
| 107 | struct work_struct remove_work; |
| 108 | struct mutex shutdown_lock; |
| 109 | bool subsystem; |
| 110 | u64 cmb_size; |
| 111 | bool cmb_use_sqes; |
| 112 | u32 cmbsz; |
| 113 | u32 cmbloc; |
| 114 | struct nvme_ctrl ctrl; |
| 115 | u32 last_ps; |
| 116 | |
| 117 | mempool_t *iod_mempool; |
| 118 | |
| 119 | /* shadow doorbell buffer support: */ |
| 120 | u32 *dbbuf_dbs; |
| 121 | dma_addr_t dbbuf_dbs_dma_addr; |
| 122 | u32 *dbbuf_eis; |
| 123 | dma_addr_t dbbuf_eis_dma_addr; |
| 124 | |
| 125 | /* host memory buffer support: */ |
| 126 | u64 host_mem_size; |
| 127 | u32 nr_host_mem_descs; |
| 128 | dma_addr_t host_mem_descs_dma; |
| 129 | struct nvme_host_mem_buf_desc *host_mem_descs; |
| 130 | void **host_mem_desc_bufs; |
| 131 | unsigned int nr_allocated_queues; |
| 132 | unsigned int nr_write_queues; |
| 133 | unsigned int nr_poll_queues; |
| 134 | }; |
| 135 | |
| 136 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
| 137 | { |
| 138 | int n = 0, ret; |
| 139 | |
| 140 | ret = kstrtoint(val, 10, &n); |
| 141 | if (ret != 0 || n < 2) |
| 142 | return -EINVAL; |
| 143 | |
| 144 | return param_set_int(val, kp); |
| 145 | } |
| 146 | |
| 147 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
| 148 | { |
| 149 | return qid * 2 * stride; |
| 150 | } |
| 151 | |
| 152 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) |
| 153 | { |
| 154 | return (qid * 2 + 1) * stride; |
| 155 | } |
| 156 | |
| 157 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
| 158 | { |
| 159 | return container_of(ctrl, struct nvme_dev, ctrl); |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * An NVM Express queue. Each device has at least two (one for admin |
| 164 | * commands and one for I/O commands). |
| 165 | */ |
| 166 | struct nvme_queue { |
| 167 | struct nvme_dev *dev; |
| 168 | spinlock_t sq_lock; |
| 169 | void *sq_cmds; |
| 170 | /* only used for poll queues: */ |
| 171 | spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; |
| 172 | struct nvme_completion *cqes; |
| 173 | dma_addr_t sq_dma_addr; |
| 174 | dma_addr_t cq_dma_addr; |
| 175 | u32 __iomem *q_db; |
| 176 | u16 q_depth; |
| 177 | u16 cq_vector; |
| 178 | u16 sq_tail; |
| 179 | u16 cq_head; |
| 180 | u16 qid; |
| 181 | u8 cq_phase; |
| 182 | u8 sqes; |
| 183 | unsigned long flags; |
| 184 | #define NVMEQ_ENABLED 0 |
| 185 | #define NVMEQ_SQ_CMB 1 |
| 186 | #define NVMEQ_DELETE_ERROR 2 |
| 187 | #define NVMEQ_POLLED 3 |
| 188 | u32 *dbbuf_sq_db; |
| 189 | u32 *dbbuf_cq_db; |
| 190 | u32 *dbbuf_sq_ei; |
| 191 | u32 *dbbuf_cq_ei; |
| 192 | struct completion delete_done; |
| 193 | }; |
| 194 | |
| 195 | /* |
| 196 | * The nvme_iod describes the data in an I/O. |
| 197 | * |
| 198 | * The sg pointer contains the list of PRP/SGL chunk allocations in addition |
| 199 | * to the actual struct scatterlist. |
| 200 | */ |
| 201 | struct nvme_iod { |
| 202 | struct nvme_request req; |
| 203 | struct nvme_queue *nvmeq; |
| 204 | bool use_sgl; |
| 205 | int aborted; |
| 206 | int npages; /* In the PRP list. 0 means small pool in use */ |
| 207 | int nents; /* Used in scatterlist */ |
| 208 | dma_addr_t first_dma; |
| 209 | unsigned int dma_len; /* length of single DMA segment mapping */ |
| 210 | dma_addr_t meta_dma; |
| 211 | struct scatterlist *sg; |
| 212 | }; |
| 213 | |
| 214 | static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) |
| 215 | { |
| 216 | return dev->nr_allocated_queues * 8 * dev->db_stride; |
| 217 | } |
| 218 | |
| 219 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) |
| 220 | { |
| 221 | unsigned int mem_size = nvme_dbbuf_size(dev); |
| 222 | |
| 223 | if (dev->dbbuf_dbs) |
| 224 | return 0; |
| 225 | |
| 226 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, |
| 227 | &dev->dbbuf_dbs_dma_addr, |
| 228 | GFP_KERNEL); |
| 229 | if (!dev->dbbuf_dbs) |
| 230 | return -ENOMEM; |
| 231 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, |
| 232 | &dev->dbbuf_eis_dma_addr, |
| 233 | GFP_KERNEL); |
| 234 | if (!dev->dbbuf_eis) { |
| 235 | dma_free_coherent(dev->dev, mem_size, |
| 236 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); |
| 237 | dev->dbbuf_dbs = NULL; |
| 238 | return -ENOMEM; |
| 239 | } |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) |
| 245 | { |
| 246 | unsigned int mem_size = nvme_dbbuf_size(dev); |
| 247 | |
| 248 | if (dev->dbbuf_dbs) { |
| 249 | dma_free_coherent(dev->dev, mem_size, |
| 250 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); |
| 251 | dev->dbbuf_dbs = NULL; |
| 252 | } |
| 253 | if (dev->dbbuf_eis) { |
| 254 | dma_free_coherent(dev->dev, mem_size, |
| 255 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); |
| 256 | dev->dbbuf_eis = NULL; |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | static void nvme_dbbuf_init(struct nvme_dev *dev, |
| 261 | struct nvme_queue *nvmeq, int qid) |
| 262 | { |
| 263 | if (!dev->dbbuf_dbs || !qid) |
| 264 | return; |
| 265 | |
| 266 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; |
| 267 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; |
| 268 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; |
| 269 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; |
| 270 | } |
| 271 | |
| 272 | static void nvme_dbbuf_set(struct nvme_dev *dev) |
| 273 | { |
| 274 | struct nvme_command c; |
| 275 | |
| 276 | if (!dev->dbbuf_dbs) |
| 277 | return; |
| 278 | |
| 279 | memset(&c, 0, sizeof(c)); |
| 280 | c.dbbuf.opcode = nvme_admin_dbbuf; |
| 281 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); |
| 282 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); |
| 283 | |
| 284 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { |
| 285 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
| 286 | /* Free memory and continue on */ |
| 287 | nvme_dbbuf_dma_free(dev); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) |
| 292 | { |
| 293 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); |
| 294 | } |
| 295 | |
| 296 | /* Update dbbuf and return true if an MMIO is required */ |
| 297 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, |
| 298 | volatile u32 *dbbuf_ei) |
| 299 | { |
| 300 | if (dbbuf_db) { |
| 301 | u16 old_value; |
| 302 | |
| 303 | /* |
| 304 | * Ensure that the queue is written before updating |
| 305 | * the doorbell in memory |
| 306 | */ |
| 307 | wmb(); |
| 308 | |
| 309 | old_value = *dbbuf_db; |
| 310 | *dbbuf_db = value; |
| 311 | |
| 312 | /* |
| 313 | * Ensure that the doorbell is updated before reading the event |
| 314 | * index from memory. The controller needs to provide similar |
| 315 | * ordering to ensure the envent index is updated before reading |
| 316 | * the doorbell. |
| 317 | */ |
| 318 | mb(); |
| 319 | |
| 320 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) |
| 321 | return false; |
| 322 | } |
| 323 | |
| 324 | return true; |
| 325 | } |
| 326 | |
| 327 | /* |
| 328 | * Will slightly overestimate the number of pages needed. This is OK |
| 329 | * as it only leads to a small amount of wasted memory for the lifetime of |
| 330 | * the I/O. |
| 331 | */ |
| 332 | static int nvme_npages(unsigned size, struct nvme_dev *dev) |
| 333 | { |
| 334 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
| 335 | dev->ctrl.page_size); |
| 336 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
| 337 | } |
| 338 | |
| 339 | /* |
| 340 | * Calculates the number of pages needed for the SGL segments. For example a 4k |
| 341 | * page can accommodate 256 SGL descriptors. |
| 342 | */ |
| 343 | static int nvme_pci_npages_sgl(unsigned int num_seg) |
| 344 | { |
| 345 | return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); |
| 346 | } |
| 347 | |
| 348 | static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, |
| 349 | unsigned int size, unsigned int nseg, bool use_sgl) |
| 350 | { |
| 351 | size_t alloc_size; |
| 352 | |
| 353 | if (use_sgl) |
| 354 | alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); |
| 355 | else |
| 356 | alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); |
| 357 | |
| 358 | return alloc_size + sizeof(struct scatterlist) * nseg; |
| 359 | } |
| 360 | |
| 361 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
| 362 | unsigned int hctx_idx) |
| 363 | { |
| 364 | struct nvme_dev *dev = data; |
| 365 | struct nvme_queue *nvmeq = &dev->queues[0]; |
| 366 | |
| 367 | WARN_ON(hctx_idx != 0); |
| 368 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); |
| 369 | |
| 370 | hctx->driver_data = nvmeq; |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
| 375 | unsigned int hctx_idx) |
| 376 | { |
| 377 | struct nvme_dev *dev = data; |
| 378 | struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; |
| 379 | |
| 380 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
| 381 | hctx->driver_data = nvmeq; |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
| 386 | unsigned int hctx_idx, unsigned int numa_node) |
| 387 | { |
| 388 | struct nvme_dev *dev = set->driver_data; |
| 389 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 390 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
| 391 | struct nvme_queue *nvmeq = &dev->queues[queue_idx]; |
| 392 | |
| 393 | BUG_ON(!nvmeq); |
| 394 | iod->nvmeq = nvmeq; |
| 395 | |
| 396 | nvme_req(req)->ctrl = &dev->ctrl; |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | static int queue_irq_offset(struct nvme_dev *dev) |
| 401 | { |
| 402 | /* if we have more than 1 vec, admin queue offsets us by 1 */ |
| 403 | if (dev->num_vecs > 1) |
| 404 | return 1; |
| 405 | |
| 406 | return 0; |
| 407 | } |
| 408 | |
| 409 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
| 410 | { |
| 411 | struct nvme_dev *dev = set->driver_data; |
| 412 | int i, qoff, offset; |
| 413 | |
| 414 | offset = queue_irq_offset(dev); |
| 415 | for (i = 0, qoff = 0; i < set->nr_maps; i++) { |
| 416 | struct blk_mq_queue_map *map = &set->map[i]; |
| 417 | |
| 418 | map->nr_queues = dev->io_queues[i]; |
| 419 | if (!map->nr_queues) { |
| 420 | BUG_ON(i == HCTX_TYPE_DEFAULT); |
| 421 | continue; |
| 422 | } |
| 423 | |
| 424 | /* |
| 425 | * The poll queue(s) doesn't have an IRQ (and hence IRQ |
| 426 | * affinity), so use the regular blk-mq cpu mapping |
| 427 | */ |
| 428 | map->queue_offset = qoff; |
| 429 | if (i != HCTX_TYPE_POLL && offset) |
| 430 | blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); |
| 431 | else |
| 432 | blk_mq_map_queues(map); |
| 433 | qoff += map->nr_queues; |
| 434 | offset += map->nr_queues; |
| 435 | } |
| 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | static inline void nvme_write_sq_db(struct nvme_queue *nvmeq) |
| 441 | { |
| 442 | if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, |
| 443 | nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) |
| 444 | writel(nvmeq->sq_tail, nvmeq->q_db); |
| 445 | } |
| 446 | |
| 447 | /** |
| 448 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
| 449 | * @nvmeq: The queue to use |
| 450 | * @cmd: The command to send |
| 451 | * @write_sq: whether to write to the SQ doorbell |
| 452 | */ |
| 453 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, |
| 454 | bool write_sq) |
| 455 | { |
| 456 | spin_lock(&nvmeq->sq_lock); |
| 457 | memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), |
| 458 | cmd, sizeof(*cmd)); |
| 459 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
| 460 | nvmeq->sq_tail = 0; |
| 461 | if (write_sq) |
| 462 | nvme_write_sq_db(nvmeq); |
| 463 | spin_unlock(&nvmeq->sq_lock); |
| 464 | } |
| 465 | |
| 466 | static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) |
| 467 | { |
| 468 | struct nvme_queue *nvmeq = hctx->driver_data; |
| 469 | |
| 470 | spin_lock(&nvmeq->sq_lock); |
| 471 | nvme_write_sq_db(nvmeq); |
| 472 | spin_unlock(&nvmeq->sq_lock); |
| 473 | } |
| 474 | |
| 475 | static void **nvme_pci_iod_list(struct request *req) |
| 476 | { |
| 477 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 478 | return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); |
| 479 | } |
| 480 | |
| 481 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
| 482 | { |
| 483 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 484 | int nseg = blk_rq_nr_phys_segments(req); |
| 485 | unsigned int avg_seg_size; |
| 486 | |
| 487 | if (nseg == 0) |
| 488 | return false; |
| 489 | |
| 490 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); |
| 491 | |
| 492 | if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) |
| 493 | return false; |
| 494 | if (!iod->nvmeq->qid) |
| 495 | return false; |
| 496 | if (!sgl_threshold || avg_seg_size < sgl_threshold) |
| 497 | return false; |
| 498 | return true; |
| 499 | } |
| 500 | |
| 501 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
| 502 | { |
| 503 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 504 | const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; |
| 505 | dma_addr_t dma_addr = iod->first_dma, next_dma_addr; |
| 506 | int i; |
| 507 | |
| 508 | if (iod->dma_len) { |
| 509 | dma_unmap_page(dev->dev, dma_addr, iod->dma_len, |
| 510 | rq_dma_dir(req)); |
| 511 | return; |
| 512 | } |
| 513 | |
| 514 | WARN_ON_ONCE(!iod->nents); |
| 515 | |
| 516 | if (is_pci_p2pdma_page(sg_page(iod->sg))) |
| 517 | pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, |
| 518 | rq_dma_dir(req)); |
| 519 | else |
| 520 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); |
| 521 | |
| 522 | |
| 523 | if (iod->npages == 0) |
| 524 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], |
| 525 | dma_addr); |
| 526 | |
| 527 | for (i = 0; i < iod->npages; i++) { |
| 528 | void *addr = nvme_pci_iod_list(req)[i]; |
| 529 | |
| 530 | if (iod->use_sgl) { |
| 531 | struct nvme_sgl_desc *sg_list = addr; |
| 532 | |
| 533 | next_dma_addr = |
| 534 | le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); |
| 535 | } else { |
| 536 | __le64 *prp_list = addr; |
| 537 | |
| 538 | next_dma_addr = le64_to_cpu(prp_list[last_prp]); |
| 539 | } |
| 540 | |
| 541 | dma_pool_free(dev->prp_page_pool, addr, dma_addr); |
| 542 | dma_addr = next_dma_addr; |
| 543 | } |
| 544 | |
| 545 | mempool_free(iod->sg, dev->iod_mempool); |
| 546 | } |
| 547 | |
| 548 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
| 549 | { |
| 550 | int i; |
| 551 | struct scatterlist *sg; |
| 552 | |
| 553 | for_each_sg(sgl, sg, nents, i) { |
| 554 | dma_addr_t phys = sg_phys(sg); |
| 555 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " |
| 556 | "dma_address:%pad dma_length:%d\n", |
| 557 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), |
| 558 | sg_dma_len(sg)); |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
| 563 | struct request *req, struct nvme_rw_command *cmnd) |
| 564 | { |
| 565 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 566 | struct dma_pool *pool; |
| 567 | int length = blk_rq_payload_bytes(req); |
| 568 | struct scatterlist *sg = iod->sg; |
| 569 | int dma_len = sg_dma_len(sg); |
| 570 | u64 dma_addr = sg_dma_address(sg); |
| 571 | u32 page_size = dev->ctrl.page_size; |
| 572 | int offset = dma_addr & (page_size - 1); |
| 573 | __le64 *prp_list; |
| 574 | void **list = nvme_pci_iod_list(req); |
| 575 | dma_addr_t prp_dma; |
| 576 | int nprps, i; |
| 577 | |
| 578 | length -= (page_size - offset); |
| 579 | if (length <= 0) { |
| 580 | iod->first_dma = 0; |
| 581 | goto done; |
| 582 | } |
| 583 | |
| 584 | dma_len -= (page_size - offset); |
| 585 | if (dma_len) { |
| 586 | dma_addr += (page_size - offset); |
| 587 | } else { |
| 588 | sg = sg_next(sg); |
| 589 | dma_addr = sg_dma_address(sg); |
| 590 | dma_len = sg_dma_len(sg); |
| 591 | } |
| 592 | |
| 593 | if (length <= page_size) { |
| 594 | iod->first_dma = dma_addr; |
| 595 | goto done; |
| 596 | } |
| 597 | |
| 598 | nprps = DIV_ROUND_UP(length, page_size); |
| 599 | if (nprps <= (256 / 8)) { |
| 600 | pool = dev->prp_small_pool; |
| 601 | iod->npages = 0; |
| 602 | } else { |
| 603 | pool = dev->prp_page_pool; |
| 604 | iod->npages = 1; |
| 605 | } |
| 606 | |
| 607 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
| 608 | if (!prp_list) { |
| 609 | iod->first_dma = dma_addr; |
| 610 | iod->npages = -1; |
| 611 | return BLK_STS_RESOURCE; |
| 612 | } |
| 613 | list[0] = prp_list; |
| 614 | iod->first_dma = prp_dma; |
| 615 | i = 0; |
| 616 | for (;;) { |
| 617 | if (i == page_size >> 3) { |
| 618 | __le64 *old_prp_list = prp_list; |
| 619 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
| 620 | if (!prp_list) |
| 621 | return BLK_STS_RESOURCE; |
| 622 | list[iod->npages++] = prp_list; |
| 623 | prp_list[0] = old_prp_list[i - 1]; |
| 624 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); |
| 625 | i = 1; |
| 626 | } |
| 627 | prp_list[i++] = cpu_to_le64(dma_addr); |
| 628 | dma_len -= page_size; |
| 629 | dma_addr += page_size; |
| 630 | length -= page_size; |
| 631 | if (length <= 0) |
| 632 | break; |
| 633 | if (dma_len > 0) |
| 634 | continue; |
| 635 | if (unlikely(dma_len < 0)) |
| 636 | goto bad_sgl; |
| 637 | sg = sg_next(sg); |
| 638 | dma_addr = sg_dma_address(sg); |
| 639 | dma_len = sg_dma_len(sg); |
| 640 | } |
| 641 | |
| 642 | done: |
| 643 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
| 644 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); |
| 645 | |
| 646 | return BLK_STS_OK; |
| 647 | |
| 648 | bad_sgl: |
| 649 | WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), |
| 650 | "Invalid SGL for payload:%d nents:%d\n", |
| 651 | blk_rq_payload_bytes(req), iod->nents); |
| 652 | return BLK_STS_IOERR; |
| 653 | } |
| 654 | |
| 655 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
| 656 | struct scatterlist *sg) |
| 657 | { |
| 658 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
| 659 | sge->length = cpu_to_le32(sg_dma_len(sg)); |
| 660 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; |
| 661 | } |
| 662 | |
| 663 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, |
| 664 | dma_addr_t dma_addr, int entries) |
| 665 | { |
| 666 | sge->addr = cpu_to_le64(dma_addr); |
| 667 | if (entries < SGES_PER_PAGE) { |
| 668 | sge->length = cpu_to_le32(entries * sizeof(*sge)); |
| 669 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; |
| 670 | } else { |
| 671 | sge->length = cpu_to_le32(PAGE_SIZE); |
| 672 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; |
| 673 | } |
| 674 | } |
| 675 | |
| 676 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, |
| 677 | struct request *req, struct nvme_rw_command *cmd, int entries) |
| 678 | { |
| 679 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 680 | struct dma_pool *pool; |
| 681 | struct nvme_sgl_desc *sg_list; |
| 682 | struct scatterlist *sg = iod->sg; |
| 683 | dma_addr_t sgl_dma; |
| 684 | int i = 0; |
| 685 | |
| 686 | /* setting the transfer type as SGL */ |
| 687 | cmd->flags = NVME_CMD_SGL_METABUF; |
| 688 | |
| 689 | if (entries == 1) { |
| 690 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
| 691 | return BLK_STS_OK; |
| 692 | } |
| 693 | |
| 694 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { |
| 695 | pool = dev->prp_small_pool; |
| 696 | iod->npages = 0; |
| 697 | } else { |
| 698 | pool = dev->prp_page_pool; |
| 699 | iod->npages = 1; |
| 700 | } |
| 701 | |
| 702 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); |
| 703 | if (!sg_list) { |
| 704 | iod->npages = -1; |
| 705 | return BLK_STS_RESOURCE; |
| 706 | } |
| 707 | |
| 708 | nvme_pci_iod_list(req)[0] = sg_list; |
| 709 | iod->first_dma = sgl_dma; |
| 710 | |
| 711 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); |
| 712 | |
| 713 | do { |
| 714 | if (i == SGES_PER_PAGE) { |
| 715 | struct nvme_sgl_desc *old_sg_desc = sg_list; |
| 716 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; |
| 717 | |
| 718 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); |
| 719 | if (!sg_list) |
| 720 | return BLK_STS_RESOURCE; |
| 721 | |
| 722 | i = 0; |
| 723 | nvme_pci_iod_list(req)[iod->npages++] = sg_list; |
| 724 | sg_list[i++] = *link; |
| 725 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); |
| 726 | } |
| 727 | |
| 728 | nvme_pci_sgl_set_data(&sg_list[i++], sg); |
| 729 | sg = sg_next(sg); |
| 730 | } while (--entries > 0); |
| 731 | |
| 732 | return BLK_STS_OK; |
| 733 | } |
| 734 | |
| 735 | static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, |
| 736 | struct request *req, struct nvme_rw_command *cmnd, |
| 737 | struct bio_vec *bv) |
| 738 | { |
| 739 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 740 | unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); |
| 741 | unsigned int first_prp_len = dev->ctrl.page_size - offset; |
| 742 | |
| 743 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); |
| 744 | if (dma_mapping_error(dev->dev, iod->first_dma)) |
| 745 | return BLK_STS_RESOURCE; |
| 746 | iod->dma_len = bv->bv_len; |
| 747 | |
| 748 | cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); |
| 749 | if (bv->bv_len > first_prp_len) |
| 750 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, |
| 755 | struct request *req, struct nvme_rw_command *cmnd, |
| 756 | struct bio_vec *bv) |
| 757 | { |
| 758 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 759 | |
| 760 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); |
| 761 | if (dma_mapping_error(dev->dev, iod->first_dma)) |
| 762 | return BLK_STS_RESOURCE; |
| 763 | iod->dma_len = bv->bv_len; |
| 764 | |
| 765 | cmnd->flags = NVME_CMD_SGL_METABUF; |
| 766 | cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); |
| 767 | cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); |
| 768 | cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
| 773 | struct nvme_command *cmnd) |
| 774 | { |
| 775 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 776 | blk_status_t ret = BLK_STS_RESOURCE; |
| 777 | int nr_mapped; |
| 778 | |
| 779 | if (blk_rq_nr_phys_segments(req) == 1) { |
| 780 | struct bio_vec bv = req_bvec(req); |
| 781 | |
| 782 | if (!is_pci_p2pdma_page(bv.bv_page)) { |
| 783 | if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) |
| 784 | return nvme_setup_prp_simple(dev, req, |
| 785 | &cmnd->rw, &bv); |
| 786 | |
| 787 | if (iod->nvmeq->qid && |
| 788 | dev->ctrl.sgls & ((1 << 0) | (1 << 1))) |
| 789 | return nvme_setup_sgl_simple(dev, req, |
| 790 | &cmnd->rw, &bv); |
| 791 | } |
| 792 | } |
| 793 | |
| 794 | iod->dma_len = 0; |
| 795 | iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); |
| 796 | if (!iod->sg) |
| 797 | return BLK_STS_RESOURCE; |
| 798 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
| 799 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
| 800 | if (!iod->nents) |
| 801 | goto out; |
| 802 | |
| 803 | if (is_pci_p2pdma_page(sg_page(iod->sg))) |
| 804 | nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, |
| 805 | iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); |
| 806 | else |
| 807 | nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, |
| 808 | rq_dma_dir(req), DMA_ATTR_NO_WARN); |
| 809 | if (!nr_mapped) |
| 810 | goto out; |
| 811 | |
| 812 | iod->use_sgl = nvme_pci_use_sgls(dev, req); |
| 813 | if (iod->use_sgl) |
| 814 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); |
| 815 | else |
| 816 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); |
| 817 | out: |
| 818 | if (ret != BLK_STS_OK) |
| 819 | nvme_unmap_data(dev, req); |
| 820 | return ret; |
| 821 | } |
| 822 | |
| 823 | static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, |
| 824 | struct nvme_command *cmnd) |
| 825 | { |
| 826 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 827 | |
| 828 | iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), |
| 829 | rq_dma_dir(req), 0); |
| 830 | if (dma_mapping_error(dev->dev, iod->meta_dma)) |
| 831 | return BLK_STS_IOERR; |
| 832 | cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); |
| 833 | return 0; |
| 834 | } |
| 835 | |
| 836 | /* |
| 837 | * NOTE: ns is NULL when called on the admin queue. |
| 838 | */ |
| 839 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
| 840 | const struct blk_mq_queue_data *bd) |
| 841 | { |
| 842 | struct nvme_ns *ns = hctx->queue->queuedata; |
| 843 | struct nvme_queue *nvmeq = hctx->driver_data; |
| 844 | struct nvme_dev *dev = nvmeq->dev; |
| 845 | struct request *req = bd->rq; |
| 846 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 847 | struct nvme_command cmnd; |
| 848 | blk_status_t ret; |
| 849 | |
| 850 | iod->aborted = 0; |
| 851 | iod->npages = -1; |
| 852 | iod->nents = 0; |
| 853 | |
| 854 | /* |
| 855 | * We should not need to do this, but we're still using this to |
| 856 | * ensure we can drain requests on a dying queue. |
| 857 | */ |
| 858 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) |
| 859 | return BLK_STS_IOERR; |
| 860 | |
| 861 | ret = nvme_setup_cmd(ns, req, &cmnd); |
| 862 | if (ret) |
| 863 | return ret; |
| 864 | |
| 865 | if (blk_rq_nr_phys_segments(req)) { |
| 866 | ret = nvme_map_data(dev, req, &cmnd); |
| 867 | if (ret) |
| 868 | goto out_free_cmd; |
| 869 | } |
| 870 | |
| 871 | if (blk_integrity_rq(req)) { |
| 872 | ret = nvme_map_metadata(dev, req, &cmnd); |
| 873 | if (ret) |
| 874 | goto out_unmap_data; |
| 875 | } |
| 876 | |
| 877 | blk_mq_start_request(req); |
| 878 | nvme_submit_cmd(nvmeq, &cmnd, bd->last); |
| 879 | return BLK_STS_OK; |
| 880 | out_unmap_data: |
| 881 | nvme_unmap_data(dev, req); |
| 882 | out_free_cmd: |
| 883 | nvme_cleanup_cmd(req); |
| 884 | return ret; |
| 885 | } |
| 886 | |
| 887 | static void nvme_pci_complete_rq(struct request *req) |
| 888 | { |
| 889 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 890 | struct nvme_dev *dev = iod->nvmeq->dev; |
| 891 | |
| 892 | if (blk_integrity_rq(req)) |
| 893 | dma_unmap_page(dev->dev, iod->meta_dma, |
| 894 | rq_integrity_vec(req)->bv_len, rq_data_dir(req)); |
| 895 | if (blk_rq_nr_phys_segments(req)) |
| 896 | nvme_unmap_data(dev, req); |
| 897 | nvme_complete_rq(req); |
| 898 | } |
| 899 | |
| 900 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
| 901 | static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) |
| 902 | { |
| 903 | struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; |
| 904 | |
| 905 | return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; |
| 906 | } |
| 907 | |
| 908 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
| 909 | { |
| 910 | u16 head = nvmeq->cq_head; |
| 911 | |
| 912 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
| 913 | nvmeq->dbbuf_cq_ei)) |
| 914 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
| 915 | } |
| 916 | |
| 917 | static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) |
| 918 | { |
| 919 | if (!nvmeq->qid) |
| 920 | return nvmeq->dev->admin_tagset.tags[0]; |
| 921 | return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; |
| 922 | } |
| 923 | |
| 924 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) |
| 925 | { |
| 926 | struct nvme_completion *cqe = &nvmeq->cqes[idx]; |
| 927 | struct request *req; |
| 928 | |
| 929 | if (unlikely(cqe->command_id >= nvmeq->q_depth)) { |
| 930 | dev_warn(nvmeq->dev->ctrl.device, |
| 931 | "invalid id %d completed on queue %d\n", |
| 932 | cqe->command_id, le16_to_cpu(cqe->sq_id)); |
| 933 | return; |
| 934 | } |
| 935 | |
| 936 | /* |
| 937 | * AEN requests are special as they don't time out and can |
| 938 | * survive any kind of queue freeze and often don't respond to |
| 939 | * aborts. We don't even bother to allocate a struct request |
| 940 | * for them but rather special case them here. |
| 941 | */ |
| 942 | if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { |
| 943 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
| 944 | cqe->status, &cqe->result); |
| 945 | return; |
| 946 | } |
| 947 | |
| 948 | req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); |
| 949 | trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); |
| 950 | nvme_end_request(req, cqe->status, cqe->result); |
| 951 | } |
| 952 | |
| 953 | static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) |
| 954 | { |
| 955 | u16 tmp = nvmeq->cq_head + 1; |
| 956 | |
| 957 | if (tmp == nvmeq->q_depth) { |
| 958 | nvmeq->cq_head = 0; |
| 959 | nvmeq->cq_phase ^= 1; |
| 960 | } else { |
| 961 | nvmeq->cq_head = tmp; |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | static inline int nvme_process_cq(struct nvme_queue *nvmeq) |
| 966 | { |
| 967 | int found = 0; |
| 968 | |
| 969 | while (nvme_cqe_pending(nvmeq)) { |
| 970 | found++; |
| 971 | nvme_handle_cqe(nvmeq, nvmeq->cq_head); |
| 972 | nvme_update_cq_head(nvmeq); |
| 973 | } |
| 974 | |
| 975 | if (found) |
| 976 | nvme_ring_cq_doorbell(nvmeq); |
| 977 | return found; |
| 978 | } |
| 979 | |
| 980 | static irqreturn_t nvme_irq(int irq, void *data) |
| 981 | { |
| 982 | struct nvme_queue *nvmeq = data; |
| 983 | irqreturn_t ret = IRQ_NONE; |
| 984 | |
| 985 | /* |
| 986 | * The rmb/wmb pair ensures we see all updates from a previous run of |
| 987 | * the irq handler, even if that was on another CPU. |
| 988 | */ |
| 989 | rmb(); |
| 990 | if (nvme_process_cq(nvmeq)) |
| 991 | ret = IRQ_HANDLED; |
| 992 | wmb(); |
| 993 | |
| 994 | return ret; |
| 995 | } |
| 996 | |
| 997 | static irqreturn_t nvme_irq_check(int irq, void *data) |
| 998 | { |
| 999 | struct nvme_queue *nvmeq = data; |
| 1000 | if (nvme_cqe_pending(nvmeq)) |
| 1001 | return IRQ_WAKE_THREAD; |
| 1002 | return IRQ_NONE; |
| 1003 | } |
| 1004 | |
| 1005 | /* |
| 1006 | * Poll for completions for any interrupt driven queue |
| 1007 | * Can be called from any context. |
| 1008 | */ |
| 1009 | static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) |
| 1010 | { |
| 1011 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
| 1012 | |
| 1013 | WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); |
| 1014 | |
| 1015 | disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
| 1016 | nvme_process_cq(nvmeq); |
| 1017 | enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
| 1018 | } |
| 1019 | |
| 1020 | static int nvme_poll(struct blk_mq_hw_ctx *hctx) |
| 1021 | { |
| 1022 | struct nvme_queue *nvmeq = hctx->driver_data; |
| 1023 | bool found; |
| 1024 | |
| 1025 | if (!nvme_cqe_pending(nvmeq)) |
| 1026 | return 0; |
| 1027 | |
| 1028 | spin_lock(&nvmeq->cq_poll_lock); |
| 1029 | found = nvme_process_cq(nvmeq); |
| 1030 | spin_unlock(&nvmeq->cq_poll_lock); |
| 1031 | |
| 1032 | return found; |
| 1033 | } |
| 1034 | |
| 1035 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
| 1036 | { |
| 1037 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
| 1038 | struct nvme_queue *nvmeq = &dev->queues[0]; |
| 1039 | struct nvme_command c; |
| 1040 | |
| 1041 | memset(&c, 0, sizeof(c)); |
| 1042 | c.common.opcode = nvme_admin_async_event; |
| 1043 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
| 1044 | nvme_submit_cmd(nvmeq, &c, true); |
| 1045 | } |
| 1046 | |
| 1047 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
| 1048 | { |
| 1049 | struct nvme_command c; |
| 1050 | |
| 1051 | memset(&c, 0, sizeof(c)); |
| 1052 | c.delete_queue.opcode = opcode; |
| 1053 | c.delete_queue.qid = cpu_to_le16(id); |
| 1054 | |
| 1055 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
| 1056 | } |
| 1057 | |
| 1058 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
| 1059 | struct nvme_queue *nvmeq, s16 vector) |
| 1060 | { |
| 1061 | struct nvme_command c; |
| 1062 | int flags = NVME_QUEUE_PHYS_CONTIG; |
| 1063 | |
| 1064 | if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
| 1065 | flags |= NVME_CQ_IRQ_ENABLED; |
| 1066 | |
| 1067 | /* |
| 1068 | * Note: we (ab)use the fact that the prp fields survive if no data |
| 1069 | * is attached to the request. |
| 1070 | */ |
| 1071 | memset(&c, 0, sizeof(c)); |
| 1072 | c.create_cq.opcode = nvme_admin_create_cq; |
| 1073 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); |
| 1074 | c.create_cq.cqid = cpu_to_le16(qid); |
| 1075 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); |
| 1076 | c.create_cq.cq_flags = cpu_to_le16(flags); |
| 1077 | c.create_cq.irq_vector = cpu_to_le16(vector); |
| 1078 | |
| 1079 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
| 1080 | } |
| 1081 | |
| 1082 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, |
| 1083 | struct nvme_queue *nvmeq) |
| 1084 | { |
| 1085 | struct nvme_ctrl *ctrl = &dev->ctrl; |
| 1086 | struct nvme_command c; |
| 1087 | int flags = NVME_QUEUE_PHYS_CONTIG; |
| 1088 | |
| 1089 | /* |
| 1090 | * Some drives have a bug that auto-enables WRRU if MEDIUM isn't |
| 1091 | * set. Since URGENT priority is zeroes, it makes all queues |
| 1092 | * URGENT. |
| 1093 | */ |
| 1094 | if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) |
| 1095 | flags |= NVME_SQ_PRIO_MEDIUM; |
| 1096 | |
| 1097 | /* |
| 1098 | * Note: we (ab)use the fact that the prp fields survive if no data |
| 1099 | * is attached to the request. |
| 1100 | */ |
| 1101 | memset(&c, 0, sizeof(c)); |
| 1102 | c.create_sq.opcode = nvme_admin_create_sq; |
| 1103 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); |
| 1104 | c.create_sq.sqid = cpu_to_le16(qid); |
| 1105 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); |
| 1106 | c.create_sq.sq_flags = cpu_to_le16(flags); |
| 1107 | c.create_sq.cqid = cpu_to_le16(qid); |
| 1108 | |
| 1109 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
| 1110 | } |
| 1111 | |
| 1112 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) |
| 1113 | { |
| 1114 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); |
| 1115 | } |
| 1116 | |
| 1117 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) |
| 1118 | { |
| 1119 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); |
| 1120 | } |
| 1121 | |
| 1122 | static void abort_endio(struct request *req, blk_status_t error) |
| 1123 | { |
| 1124 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 1125 | struct nvme_queue *nvmeq = iod->nvmeq; |
| 1126 | |
| 1127 | dev_warn(nvmeq->dev->ctrl.device, |
| 1128 | "Abort status: 0x%x", nvme_req(req)->status); |
| 1129 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
| 1130 | blk_mq_free_request(req); |
| 1131 | } |
| 1132 | |
| 1133 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
| 1134 | { |
| 1135 | |
| 1136 | /* If true, indicates loss of adapter communication, possibly by a |
| 1137 | * NVMe Subsystem reset. |
| 1138 | */ |
| 1139 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); |
| 1140 | |
| 1141 | /* If there is a reset/reinit ongoing, we shouldn't reset again. */ |
| 1142 | switch (dev->ctrl.state) { |
| 1143 | case NVME_CTRL_RESETTING: |
| 1144 | case NVME_CTRL_CONNECTING: |
| 1145 | return false; |
| 1146 | default: |
| 1147 | break; |
| 1148 | } |
| 1149 | |
| 1150 | /* We shouldn't reset unless the controller is on fatal error state |
| 1151 | * _or_ if we lost the communication with it. |
| 1152 | */ |
| 1153 | if (!(csts & NVME_CSTS_CFS) && !nssro) |
| 1154 | return false; |
| 1155 | |
| 1156 | return true; |
| 1157 | } |
| 1158 | |
| 1159 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
| 1160 | { |
| 1161 | /* Read a config register to help see what died. */ |
| 1162 | u16 pci_status; |
| 1163 | int result; |
| 1164 | |
| 1165 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, |
| 1166 | &pci_status); |
| 1167 | if (result == PCIBIOS_SUCCESSFUL) |
| 1168 | dev_warn(dev->ctrl.device, |
| 1169 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", |
| 1170 | csts, pci_status); |
| 1171 | else |
| 1172 | dev_warn(dev->ctrl.device, |
| 1173 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", |
| 1174 | csts, result); |
| 1175 | } |
| 1176 | |
| 1177 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
| 1178 | { |
| 1179 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
| 1180 | struct nvme_queue *nvmeq = iod->nvmeq; |
| 1181 | struct nvme_dev *dev = nvmeq->dev; |
| 1182 | struct request *abort_req; |
| 1183 | struct nvme_command cmd; |
| 1184 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
| 1185 | |
| 1186 | /* If PCI error recovery process is happening, we cannot reset or |
| 1187 | * the recovery mechanism will surely fail. |
| 1188 | */ |
| 1189 | mb(); |
| 1190 | if (pci_channel_offline(to_pci_dev(dev->dev))) |
| 1191 | return BLK_EH_RESET_TIMER; |
| 1192 | |
| 1193 | /* |
| 1194 | * Reset immediately if the controller is failed |
| 1195 | */ |
| 1196 | if (nvme_should_reset(dev, csts)) { |
| 1197 | nvme_warn_reset(dev, csts); |
| 1198 | nvme_dev_disable(dev, false); |
| 1199 | nvme_reset_ctrl(&dev->ctrl); |
| 1200 | return BLK_EH_DONE; |
| 1201 | } |
| 1202 | |
| 1203 | /* |
| 1204 | * Did we miss an interrupt? |
| 1205 | */ |
| 1206 | if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
| 1207 | nvme_poll(req->mq_hctx); |
| 1208 | else |
| 1209 | nvme_poll_irqdisable(nvmeq); |
| 1210 | |
| 1211 | if (blk_mq_request_completed(req)) { |
| 1212 | dev_warn(dev->ctrl.device, |
| 1213 | "I/O %d QID %d timeout, completion polled\n", |
| 1214 | req->tag, nvmeq->qid); |
| 1215 | return BLK_EH_DONE; |
| 1216 | } |
| 1217 | |
| 1218 | /* |
| 1219 | * Shutdown immediately if controller times out while starting. The |
| 1220 | * reset work will see the pci device disabled when it gets the forced |
| 1221 | * cancellation error. All outstanding requests are completed on |
| 1222 | * shutdown, so we return BLK_EH_DONE. |
| 1223 | */ |
| 1224 | switch (dev->ctrl.state) { |
| 1225 | case NVME_CTRL_CONNECTING: |
| 1226 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
| 1227 | /* fall through */ |
| 1228 | case NVME_CTRL_DELETING: |
| 1229 | dev_warn_ratelimited(dev->ctrl.device, |
| 1230 | "I/O %d QID %d timeout, disable controller\n", |
| 1231 | req->tag, nvmeq->qid); |
| 1232 | nvme_dev_disable(dev, true); |
| 1233 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
| 1234 | return BLK_EH_DONE; |
| 1235 | case NVME_CTRL_RESETTING: |
| 1236 | return BLK_EH_RESET_TIMER; |
| 1237 | default: |
| 1238 | break; |
| 1239 | } |
| 1240 | |
| 1241 | /* |
| 1242 | * Shutdown the controller immediately and schedule a reset if the |
| 1243 | * command was already aborted once before and still hasn't been |
| 1244 | * returned to the driver, or if this is the admin queue. |
| 1245 | */ |
| 1246 | if (!nvmeq->qid || iod->aborted) { |
| 1247 | dev_warn(dev->ctrl.device, |
| 1248 | "I/O %d QID %d timeout, reset controller\n", |
| 1249 | req->tag, nvmeq->qid); |
| 1250 | nvme_dev_disable(dev, false); |
| 1251 | nvme_reset_ctrl(&dev->ctrl); |
| 1252 | |
| 1253 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
| 1254 | return BLK_EH_DONE; |
| 1255 | } |
| 1256 | |
| 1257 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
| 1258 | atomic_inc(&dev->ctrl.abort_limit); |
| 1259 | return BLK_EH_RESET_TIMER; |
| 1260 | } |
| 1261 | iod->aborted = 1; |
| 1262 | |
| 1263 | memset(&cmd, 0, sizeof(cmd)); |
| 1264 | cmd.abort.opcode = nvme_admin_abort_cmd; |
| 1265 | cmd.abort.cid = req->tag; |
| 1266 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
| 1267 | |
| 1268 | dev_warn(nvmeq->dev->ctrl.device, |
| 1269 | "I/O %d QID %d timeout, aborting\n", |
| 1270 | req->tag, nvmeq->qid); |
| 1271 | |
| 1272 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, |
| 1273 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
| 1274 | if (IS_ERR(abort_req)) { |
| 1275 | atomic_inc(&dev->ctrl.abort_limit); |
| 1276 | return BLK_EH_RESET_TIMER; |
| 1277 | } |
| 1278 | |
| 1279 | abort_req->timeout = ADMIN_TIMEOUT; |
| 1280 | abort_req->end_io_data = NULL; |
| 1281 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); |
| 1282 | |
| 1283 | /* |
| 1284 | * The aborted req will be completed on receiving the abort req. |
| 1285 | * We enable the timer again. If hit twice, it'll cause a device reset, |
| 1286 | * as the device then is in a faulty state. |
| 1287 | */ |
| 1288 | return BLK_EH_RESET_TIMER; |
| 1289 | } |
| 1290 | |
| 1291 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
| 1292 | { |
| 1293 | dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), |
| 1294 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); |
| 1295 | if (!nvmeq->sq_cmds) |
| 1296 | return; |
| 1297 | |
| 1298 | if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { |
| 1299 | pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), |
| 1300 | nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
| 1301 | } else { |
| 1302 | dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), |
| 1303 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
| 1304 | } |
| 1305 | } |
| 1306 | |
| 1307 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
| 1308 | { |
| 1309 | int i; |
| 1310 | |
| 1311 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
| 1312 | dev->ctrl.queue_count--; |
| 1313 | nvme_free_queue(&dev->queues[i]); |
| 1314 | } |
| 1315 | } |
| 1316 | |
| 1317 | /** |
| 1318 | * nvme_suspend_queue - put queue into suspended state |
| 1319 | * @nvmeq: queue to suspend |
| 1320 | */ |
| 1321 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) |
| 1322 | { |
| 1323 | if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) |
| 1324 | return 1; |
| 1325 | |
| 1326 | /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ |
| 1327 | mb(); |
| 1328 | |
| 1329 | nvmeq->dev->online_queues--; |
| 1330 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
| 1331 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
| 1332 | if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) |
| 1333 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); |
| 1334 | return 0; |
| 1335 | } |
| 1336 | |
| 1337 | static void nvme_suspend_io_queues(struct nvme_dev *dev) |
| 1338 | { |
| 1339 | int i; |
| 1340 | |
| 1341 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) |
| 1342 | nvme_suspend_queue(&dev->queues[i]); |
| 1343 | } |
| 1344 | |
| 1345 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
| 1346 | { |
| 1347 | struct nvme_queue *nvmeq = &dev->queues[0]; |
| 1348 | |
| 1349 | if (shutdown) |
| 1350 | nvme_shutdown_ctrl(&dev->ctrl); |
| 1351 | else |
| 1352 | nvme_disable_ctrl(&dev->ctrl); |
| 1353 | |
| 1354 | nvme_poll_irqdisable(nvmeq); |
| 1355 | } |
| 1356 | |
| 1357 | /* |
| 1358 | * Called only on a device that has been disabled and after all other threads |
| 1359 | * that can check this device's completion queues have synced. This is the |
| 1360 | * last chance for the driver to see a natural completion before |
| 1361 | * nvme_cancel_request() terminates all incomplete requests. |
| 1362 | */ |
| 1363 | static void nvme_reap_pending_cqes(struct nvme_dev *dev) |
| 1364 | { |
| 1365 | int i; |
| 1366 | |
| 1367 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) |
| 1368 | nvme_process_cq(&dev->queues[i]); |
| 1369 | } |
| 1370 | |
| 1371 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
| 1372 | int entry_size) |
| 1373 | { |
| 1374 | int q_depth = dev->q_depth; |
| 1375 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
| 1376 | dev->ctrl.page_size); |
| 1377 | |
| 1378 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { |
| 1379 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
| 1380 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
| 1381 | q_depth = div_u64(mem_per_q, entry_size); |
| 1382 | |
| 1383 | /* |
| 1384 | * Ensure the reduced q_depth is above some threshold where it |
| 1385 | * would be better to map queues in system memory with the |
| 1386 | * original depth |
| 1387 | */ |
| 1388 | if (q_depth < 64) |
| 1389 | return -ENOMEM; |
| 1390 | } |
| 1391 | |
| 1392 | return q_depth; |
| 1393 | } |
| 1394 | |
| 1395 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
| 1396 | int qid) |
| 1397 | { |
| 1398 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 1399 | |
| 1400 | if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { |
| 1401 | nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); |
| 1402 | if (nvmeq->sq_cmds) { |
| 1403 | nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, |
| 1404 | nvmeq->sq_cmds); |
| 1405 | if (nvmeq->sq_dma_addr) { |
| 1406 | set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); |
| 1407 | return 0; |
| 1408 | } |
| 1409 | |
| 1410 | pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
| 1411 | } |
| 1412 | } |
| 1413 | |
| 1414 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), |
| 1415 | &nvmeq->sq_dma_addr, GFP_KERNEL); |
| 1416 | if (!nvmeq->sq_cmds) |
| 1417 | return -ENOMEM; |
| 1418 | return 0; |
| 1419 | } |
| 1420 | |
| 1421 | static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) |
| 1422 | { |
| 1423 | struct nvme_queue *nvmeq = &dev->queues[qid]; |
| 1424 | |
| 1425 | if (dev->ctrl.queue_count > qid) |
| 1426 | return 0; |
| 1427 | |
| 1428 | nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; |
| 1429 | nvmeq->q_depth = depth; |
| 1430 | nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), |
| 1431 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
| 1432 | if (!nvmeq->cqes) |
| 1433 | goto free_nvmeq; |
| 1434 | |
| 1435 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) |
| 1436 | goto free_cqdma; |
| 1437 | |
| 1438 | nvmeq->dev = dev; |
| 1439 | spin_lock_init(&nvmeq->sq_lock); |
| 1440 | spin_lock_init(&nvmeq->cq_poll_lock); |
| 1441 | nvmeq->cq_head = 0; |
| 1442 | nvmeq->cq_phase = 1; |
| 1443 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
| 1444 | nvmeq->qid = qid; |
| 1445 | dev->ctrl.queue_count++; |
| 1446 | |
| 1447 | return 0; |
| 1448 | |
| 1449 | free_cqdma: |
| 1450 | dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, |
| 1451 | nvmeq->cq_dma_addr); |
| 1452 | free_nvmeq: |
| 1453 | return -ENOMEM; |
| 1454 | } |
| 1455 | |
| 1456 | static int queue_request_irq(struct nvme_queue *nvmeq) |
| 1457 | { |
| 1458 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
| 1459 | int nr = nvmeq->dev->ctrl.instance; |
| 1460 | |
| 1461 | if (use_threaded_interrupts) { |
| 1462 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, |
| 1463 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); |
| 1464 | } else { |
| 1465 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, |
| 1466 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); |
| 1467 | } |
| 1468 | } |
| 1469 | |
| 1470 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
| 1471 | { |
| 1472 | struct nvme_dev *dev = nvmeq->dev; |
| 1473 | |
| 1474 | nvmeq->sq_tail = 0; |
| 1475 | nvmeq->cq_head = 0; |
| 1476 | nvmeq->cq_phase = 1; |
| 1477 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
| 1478 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); |
| 1479 | nvme_dbbuf_init(dev, nvmeq, qid); |
| 1480 | dev->online_queues++; |
| 1481 | wmb(); /* ensure the first interrupt sees the initialization */ |
| 1482 | } |
| 1483 | |
| 1484 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) |
| 1485 | { |
| 1486 | struct nvme_dev *dev = nvmeq->dev; |
| 1487 | int result; |
| 1488 | u16 vector = 0; |
| 1489 | |
| 1490 | clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); |
| 1491 | |
| 1492 | /* |
| 1493 | * A queue's vector matches the queue identifier unless the controller |
| 1494 | * has only one vector available. |
| 1495 | */ |
| 1496 | if (!polled) |
| 1497 | vector = dev->num_vecs == 1 ? 0 : qid; |
| 1498 | else |
| 1499 | set_bit(NVMEQ_POLLED, &nvmeq->flags); |
| 1500 | |
| 1501 | result = adapter_alloc_cq(dev, qid, nvmeq, vector); |
| 1502 | if (result) |
| 1503 | return result; |
| 1504 | |
| 1505 | result = adapter_alloc_sq(dev, qid, nvmeq); |
| 1506 | if (result < 0) |
| 1507 | return result; |
| 1508 | if (result) |
| 1509 | goto release_cq; |
| 1510 | |
| 1511 | nvmeq->cq_vector = vector; |
| 1512 | nvme_init_queue(nvmeq, qid); |
| 1513 | |
| 1514 | if (!polled) { |
| 1515 | result = queue_request_irq(nvmeq); |
| 1516 | if (result < 0) |
| 1517 | goto release_sq; |
| 1518 | } |
| 1519 | |
| 1520 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
| 1521 | return result; |
| 1522 | |
| 1523 | release_sq: |
| 1524 | dev->online_queues--; |
| 1525 | adapter_delete_sq(dev, qid); |
| 1526 | release_cq: |
| 1527 | adapter_delete_cq(dev, qid); |
| 1528 | return result; |
| 1529 | } |
| 1530 | |
| 1531 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
| 1532 | .queue_rq = nvme_queue_rq, |
| 1533 | .complete = nvme_pci_complete_rq, |
| 1534 | .init_hctx = nvme_admin_init_hctx, |
| 1535 | .init_request = nvme_init_request, |
| 1536 | .timeout = nvme_timeout, |
| 1537 | }; |
| 1538 | |
| 1539 | static const struct blk_mq_ops nvme_mq_ops = { |
| 1540 | .queue_rq = nvme_queue_rq, |
| 1541 | .complete = nvme_pci_complete_rq, |
| 1542 | .commit_rqs = nvme_commit_rqs, |
| 1543 | .init_hctx = nvme_init_hctx, |
| 1544 | .init_request = nvme_init_request, |
| 1545 | .map_queues = nvme_pci_map_queues, |
| 1546 | .timeout = nvme_timeout, |
| 1547 | .poll = nvme_poll, |
| 1548 | }; |
| 1549 | |
| 1550 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
| 1551 | { |
| 1552 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
| 1553 | /* |
| 1554 | * If the controller was reset during removal, it's possible |
| 1555 | * user requests may be waiting on a stopped queue. Start the |
| 1556 | * queue to flush these to completion. |
| 1557 | */ |
| 1558 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
| 1559 | blk_cleanup_queue(dev->ctrl.admin_q); |
| 1560 | blk_mq_free_tag_set(&dev->admin_tagset); |
| 1561 | } |
| 1562 | } |
| 1563 | |
| 1564 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
| 1565 | { |
| 1566 | if (!dev->ctrl.admin_q) { |
| 1567 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
| 1568 | dev->admin_tagset.nr_hw_queues = 1; |
| 1569 | |
| 1570 | dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
| 1571 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
| 1572 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
| 1573 | dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); |
| 1574 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
| 1575 | dev->admin_tagset.driver_data = dev; |
| 1576 | |
| 1577 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) |
| 1578 | return -ENOMEM; |
| 1579 | dev->ctrl.admin_tagset = &dev->admin_tagset; |
| 1580 | |
| 1581 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
| 1582 | if (IS_ERR(dev->ctrl.admin_q)) { |
| 1583 | blk_mq_free_tag_set(&dev->admin_tagset); |
| 1584 | return -ENOMEM; |
| 1585 | } |
| 1586 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
| 1587 | nvme_dev_remove_admin(dev); |
| 1588 | dev->ctrl.admin_q = NULL; |
| 1589 | return -ENODEV; |
| 1590 | } |
| 1591 | } else |
| 1592 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
| 1593 | |
| 1594 | return 0; |
| 1595 | } |
| 1596 | |
| 1597 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
| 1598 | { |
| 1599 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); |
| 1600 | } |
| 1601 | |
| 1602 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) |
| 1603 | { |
| 1604 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 1605 | |
| 1606 | if (size <= dev->bar_mapped_size) |
| 1607 | return 0; |
| 1608 | if (size > pci_resource_len(pdev, 0)) |
| 1609 | return -ENOMEM; |
| 1610 | if (dev->bar) |
| 1611 | iounmap(dev->bar); |
| 1612 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); |
| 1613 | if (!dev->bar) { |
| 1614 | dev->bar_mapped_size = 0; |
| 1615 | return -ENOMEM; |
| 1616 | } |
| 1617 | dev->bar_mapped_size = size; |
| 1618 | dev->dbs = dev->bar + NVME_REG_DBS; |
| 1619 | |
| 1620 | return 0; |
| 1621 | } |
| 1622 | |
| 1623 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
| 1624 | { |
| 1625 | int result; |
| 1626 | u32 aqa; |
| 1627 | struct nvme_queue *nvmeq; |
| 1628 | |
| 1629 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
| 1630 | if (result < 0) |
| 1631 | return result; |
| 1632 | |
| 1633 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
| 1634 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
| 1635 | |
| 1636 | if (dev->subsystem && |
| 1637 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) |
| 1638 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); |
| 1639 | |
| 1640 | result = nvme_disable_ctrl(&dev->ctrl); |
| 1641 | if (result < 0) |
| 1642 | return result; |
| 1643 | |
| 1644 | result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
| 1645 | if (result) |
| 1646 | return result; |
| 1647 | |
| 1648 | nvmeq = &dev->queues[0]; |
| 1649 | aqa = nvmeq->q_depth - 1; |
| 1650 | aqa |= aqa << 16; |
| 1651 | |
| 1652 | writel(aqa, dev->bar + NVME_REG_AQA); |
| 1653 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); |
| 1654 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); |
| 1655 | |
| 1656 | result = nvme_enable_ctrl(&dev->ctrl); |
| 1657 | if (result) |
| 1658 | return result; |
| 1659 | |
| 1660 | nvmeq->cq_vector = 0; |
| 1661 | nvme_init_queue(nvmeq, 0); |
| 1662 | result = queue_request_irq(nvmeq); |
| 1663 | if (result) { |
| 1664 | dev->online_queues--; |
| 1665 | return result; |
| 1666 | } |
| 1667 | |
| 1668 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
| 1669 | return result; |
| 1670 | } |
| 1671 | |
| 1672 | static int nvme_create_io_queues(struct nvme_dev *dev) |
| 1673 | { |
| 1674 | unsigned i, max, rw_queues; |
| 1675 | int ret = 0; |
| 1676 | |
| 1677 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
| 1678 | if (nvme_alloc_queue(dev, i, dev->q_depth)) { |
| 1679 | ret = -ENOMEM; |
| 1680 | break; |
| 1681 | } |
| 1682 | } |
| 1683 | |
| 1684 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
| 1685 | if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { |
| 1686 | rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + |
| 1687 | dev->io_queues[HCTX_TYPE_READ]; |
| 1688 | } else { |
| 1689 | rw_queues = max; |
| 1690 | } |
| 1691 | |
| 1692 | for (i = dev->online_queues; i <= max; i++) { |
| 1693 | bool polled = i > rw_queues; |
| 1694 | |
| 1695 | ret = nvme_create_queue(&dev->queues[i], i, polled); |
| 1696 | if (ret) |
| 1697 | break; |
| 1698 | } |
| 1699 | |
| 1700 | /* |
| 1701 | * Ignore failing Create SQ/CQ commands, we can continue with less |
| 1702 | * than the desired amount of queues, and even a controller without |
| 1703 | * I/O queues can still be used to issue admin commands. This might |
| 1704 | * be useful to upgrade a buggy firmware for example. |
| 1705 | */ |
| 1706 | return ret >= 0 ? 0 : ret; |
| 1707 | } |
| 1708 | |
| 1709 | static ssize_t nvme_cmb_show(struct device *dev, |
| 1710 | struct device_attribute *attr, |
| 1711 | char *buf) |
| 1712 | { |
| 1713 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); |
| 1714 | |
| 1715 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
| 1716 | ndev->cmbloc, ndev->cmbsz); |
| 1717 | } |
| 1718 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); |
| 1719 | |
| 1720 | static u64 nvme_cmb_size_unit(struct nvme_dev *dev) |
| 1721 | { |
| 1722 | u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; |
| 1723 | |
| 1724 | return 1ULL << (12 + 4 * szu); |
| 1725 | } |
| 1726 | |
| 1727 | static u32 nvme_cmb_size(struct nvme_dev *dev) |
| 1728 | { |
| 1729 | return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; |
| 1730 | } |
| 1731 | |
| 1732 | static void nvme_map_cmb(struct nvme_dev *dev) |
| 1733 | { |
| 1734 | u64 size, offset; |
| 1735 | resource_size_t bar_size; |
| 1736 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 1737 | int bar; |
| 1738 | |
| 1739 | if (dev->cmb_size) |
| 1740 | return; |
| 1741 | |
| 1742 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
| 1743 | if (!dev->cmbsz) |
| 1744 | return; |
| 1745 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
| 1746 | |
| 1747 | size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); |
| 1748 | offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); |
| 1749 | bar = NVME_CMB_BIR(dev->cmbloc); |
| 1750 | bar_size = pci_resource_len(pdev, bar); |
| 1751 | |
| 1752 | if (offset > bar_size) |
| 1753 | return; |
| 1754 | |
| 1755 | /* |
| 1756 | * Controllers may support a CMB size larger than their BAR, |
| 1757 | * for example, due to being behind a bridge. Reduce the CMB to |
| 1758 | * the reported size of the BAR |
| 1759 | */ |
| 1760 | if (size > bar_size - offset) |
| 1761 | size = bar_size - offset; |
| 1762 | |
| 1763 | if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { |
| 1764 | dev_warn(dev->ctrl.device, |
| 1765 | "failed to register the CMB\n"); |
| 1766 | return; |
| 1767 | } |
| 1768 | |
| 1769 | dev->cmb_size = size; |
| 1770 | dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); |
| 1771 | |
| 1772 | if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == |
| 1773 | (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) |
| 1774 | pci_p2pmem_publish(pdev, true); |
| 1775 | |
| 1776 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, |
| 1777 | &dev_attr_cmb.attr, NULL)) |
| 1778 | dev_warn(dev->ctrl.device, |
| 1779 | "failed to add sysfs attribute for CMB\n"); |
| 1780 | } |
| 1781 | |
| 1782 | static inline void nvme_release_cmb(struct nvme_dev *dev) |
| 1783 | { |
| 1784 | if (dev->cmb_size) { |
| 1785 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, |
| 1786 | &dev_attr_cmb.attr, NULL); |
| 1787 | dev->cmb_size = 0; |
| 1788 | } |
| 1789 | } |
| 1790 | |
| 1791 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
| 1792 | { |
| 1793 | u64 dma_addr = dev->host_mem_descs_dma; |
| 1794 | struct nvme_command c; |
| 1795 | int ret; |
| 1796 | |
| 1797 | memset(&c, 0, sizeof(c)); |
| 1798 | c.features.opcode = nvme_admin_set_features; |
| 1799 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); |
| 1800 | c.features.dword11 = cpu_to_le32(bits); |
| 1801 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> |
| 1802 | ilog2(dev->ctrl.page_size)); |
| 1803 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); |
| 1804 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); |
| 1805 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); |
| 1806 | |
| 1807 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
| 1808 | if (ret) { |
| 1809 | dev_warn(dev->ctrl.device, |
| 1810 | "failed to set host mem (err %d, flags %#x).\n", |
| 1811 | ret, bits); |
| 1812 | } |
| 1813 | return ret; |
| 1814 | } |
| 1815 | |
| 1816 | static void nvme_free_host_mem(struct nvme_dev *dev) |
| 1817 | { |
| 1818 | int i; |
| 1819 | |
| 1820 | for (i = 0; i < dev->nr_host_mem_descs; i++) { |
| 1821 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; |
| 1822 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; |
| 1823 | |
| 1824 | dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], |
| 1825 | le64_to_cpu(desc->addr), |
| 1826 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); |
| 1827 | } |
| 1828 | |
| 1829 | kfree(dev->host_mem_desc_bufs); |
| 1830 | dev->host_mem_desc_bufs = NULL; |
| 1831 | dma_free_coherent(dev->dev, |
| 1832 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), |
| 1833 | dev->host_mem_descs, dev->host_mem_descs_dma); |
| 1834 | dev->host_mem_descs = NULL; |
| 1835 | dev->nr_host_mem_descs = 0; |
| 1836 | } |
| 1837 | |
| 1838 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
| 1839 | u32 chunk_size) |
| 1840 | { |
| 1841 | struct nvme_host_mem_buf_desc *descs; |
| 1842 | u32 max_entries, len; |
| 1843 | dma_addr_t descs_dma; |
| 1844 | int i = 0; |
| 1845 | void **bufs; |
| 1846 | u64 size, tmp; |
| 1847 | |
| 1848 | tmp = (preferred + chunk_size - 1); |
| 1849 | do_div(tmp, chunk_size); |
| 1850 | max_entries = tmp; |
| 1851 | |
| 1852 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) |
| 1853 | max_entries = dev->ctrl.hmmaxd; |
| 1854 | |
| 1855 | descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), |
| 1856 | &descs_dma, GFP_KERNEL); |
| 1857 | if (!descs) |
| 1858 | goto out; |
| 1859 | |
| 1860 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); |
| 1861 | if (!bufs) |
| 1862 | goto out_free_descs; |
| 1863 | |
| 1864 | for (size = 0; size < preferred && i < max_entries; size += len) { |
| 1865 | dma_addr_t dma_addr; |
| 1866 | |
| 1867 | len = min_t(u64, chunk_size, preferred - size); |
| 1868 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
| 1869 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); |
| 1870 | if (!bufs[i]) |
| 1871 | break; |
| 1872 | |
| 1873 | descs[i].addr = cpu_to_le64(dma_addr); |
| 1874 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); |
| 1875 | i++; |
| 1876 | } |
| 1877 | |
| 1878 | if (!size) |
| 1879 | goto out_free_bufs; |
| 1880 | |
| 1881 | dev->nr_host_mem_descs = i; |
| 1882 | dev->host_mem_size = size; |
| 1883 | dev->host_mem_descs = descs; |
| 1884 | dev->host_mem_descs_dma = descs_dma; |
| 1885 | dev->host_mem_desc_bufs = bufs; |
| 1886 | return 0; |
| 1887 | |
| 1888 | out_free_bufs: |
| 1889 | while (--i >= 0) { |
| 1890 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; |
| 1891 | |
| 1892 | dma_free_attrs(dev->dev, size, bufs[i], |
| 1893 | le64_to_cpu(descs[i].addr), |
| 1894 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); |
| 1895 | } |
| 1896 | |
| 1897 | kfree(bufs); |
| 1898 | out_free_descs: |
| 1899 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
| 1900 | descs_dma); |
| 1901 | out: |
| 1902 | dev->host_mem_descs = NULL; |
| 1903 | return -ENOMEM; |
| 1904 | } |
| 1905 | |
| 1906 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
| 1907 | { |
| 1908 | u32 chunk_size; |
| 1909 | |
| 1910 | /* start big and work our way down */ |
| 1911 | for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
| 1912 | chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); |
| 1913 | chunk_size /= 2) { |
| 1914 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { |
| 1915 | if (!min || dev->host_mem_size >= min) |
| 1916 | return 0; |
| 1917 | nvme_free_host_mem(dev); |
| 1918 | } |
| 1919 | } |
| 1920 | |
| 1921 | return -ENOMEM; |
| 1922 | } |
| 1923 | |
| 1924 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
| 1925 | { |
| 1926 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; |
| 1927 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; |
| 1928 | u64 min = (u64)dev->ctrl.hmmin * 4096; |
| 1929 | u32 enable_bits = NVME_HOST_MEM_ENABLE; |
| 1930 | int ret; |
| 1931 | |
| 1932 | preferred = min(preferred, max); |
| 1933 | if (min > max) { |
| 1934 | dev_warn(dev->ctrl.device, |
| 1935 | "min host memory (%lld MiB) above limit (%d MiB).\n", |
| 1936 | min >> ilog2(SZ_1M), max_host_mem_size_mb); |
| 1937 | nvme_free_host_mem(dev); |
| 1938 | return 0; |
| 1939 | } |
| 1940 | |
| 1941 | /* |
| 1942 | * If we already have a buffer allocated check if we can reuse it. |
| 1943 | */ |
| 1944 | if (dev->host_mem_descs) { |
| 1945 | if (dev->host_mem_size >= min) |
| 1946 | enable_bits |= NVME_HOST_MEM_RETURN; |
| 1947 | else |
| 1948 | nvme_free_host_mem(dev); |
| 1949 | } |
| 1950 | |
| 1951 | if (!dev->host_mem_descs) { |
| 1952 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
| 1953 | dev_warn(dev->ctrl.device, |
| 1954 | "failed to allocate host memory buffer.\n"); |
| 1955 | return 0; /* controller must work without HMB */ |
| 1956 | } |
| 1957 | |
| 1958 | dev_info(dev->ctrl.device, |
| 1959 | "allocated %lld MiB host memory buffer.\n", |
| 1960 | dev->host_mem_size >> ilog2(SZ_1M)); |
| 1961 | } |
| 1962 | |
| 1963 | ret = nvme_set_host_mem(dev, enable_bits); |
| 1964 | if (ret) |
| 1965 | nvme_free_host_mem(dev); |
| 1966 | return ret; |
| 1967 | } |
| 1968 | |
| 1969 | /* |
| 1970 | * nirqs is the number of interrupts available for write and read |
| 1971 | * queues. The core already reserved an interrupt for the admin queue. |
| 1972 | */ |
| 1973 | static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) |
| 1974 | { |
| 1975 | struct nvme_dev *dev = affd->priv; |
| 1976 | unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; |
| 1977 | |
| 1978 | /* |
| 1979 | * If there is no interupt available for queues, ensure that |
| 1980 | * the default queue is set to 1. The affinity set size is |
| 1981 | * also set to one, but the irq core ignores it for this case. |
| 1982 | * |
| 1983 | * If only one interrupt is available or 'write_queue' == 0, combine |
| 1984 | * write and read queues. |
| 1985 | * |
| 1986 | * If 'write_queues' > 0, ensure it leaves room for at least one read |
| 1987 | * queue. |
| 1988 | */ |
| 1989 | if (!nrirqs) { |
| 1990 | nrirqs = 1; |
| 1991 | nr_read_queues = 0; |
| 1992 | } else if (nrirqs == 1 || !nr_write_queues) { |
| 1993 | nr_read_queues = 0; |
| 1994 | } else if (nr_write_queues >= nrirqs) { |
| 1995 | nr_read_queues = 1; |
| 1996 | } else { |
| 1997 | nr_read_queues = nrirqs - nr_write_queues; |
| 1998 | } |
| 1999 | |
| 2000 | dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; |
| 2001 | affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; |
| 2002 | dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; |
| 2003 | affd->set_size[HCTX_TYPE_READ] = nr_read_queues; |
| 2004 | affd->nr_sets = nr_read_queues ? 2 : 1; |
| 2005 | } |
| 2006 | |
| 2007 | static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) |
| 2008 | { |
| 2009 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2010 | struct irq_affinity affd = { |
| 2011 | .pre_vectors = 1, |
| 2012 | .calc_sets = nvme_calc_irq_sets, |
| 2013 | .priv = dev, |
| 2014 | }; |
| 2015 | unsigned int irq_queues, this_p_queues; |
| 2016 | |
| 2017 | /* |
| 2018 | * Poll queues don't need interrupts, but we need at least one IO |
| 2019 | * queue left over for non-polled IO. |
| 2020 | */ |
| 2021 | this_p_queues = dev->nr_poll_queues; |
| 2022 | if (this_p_queues >= nr_io_queues) { |
| 2023 | this_p_queues = nr_io_queues - 1; |
| 2024 | irq_queues = 1; |
| 2025 | } else { |
| 2026 | irq_queues = nr_io_queues - this_p_queues + 1; |
| 2027 | } |
| 2028 | dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; |
| 2029 | |
| 2030 | /* Initialize for the single interrupt case */ |
| 2031 | dev->io_queues[HCTX_TYPE_DEFAULT] = 1; |
| 2032 | dev->io_queues[HCTX_TYPE_READ] = 0; |
| 2033 | |
| 2034 | /* |
| 2035 | * Some Apple controllers require all queues to use the |
| 2036 | * first vector. |
| 2037 | */ |
| 2038 | if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) |
| 2039 | irq_queues = 1; |
| 2040 | |
| 2041 | return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, |
| 2042 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); |
| 2043 | } |
| 2044 | |
| 2045 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
| 2046 | { |
| 2047 | if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) |
| 2048 | __nvme_disable_io_queues(dev, nvme_admin_delete_cq); |
| 2049 | } |
| 2050 | |
| 2051 | static unsigned int nvme_max_io_queues(struct nvme_dev *dev) |
| 2052 | { |
| 2053 | return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; |
| 2054 | } |
| 2055 | |
| 2056 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
| 2057 | { |
| 2058 | struct nvme_queue *adminq = &dev->queues[0]; |
| 2059 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2060 | unsigned int nr_io_queues; |
| 2061 | unsigned long size; |
| 2062 | int result; |
| 2063 | |
| 2064 | /* |
| 2065 | * Sample the module parameters once at reset time so that we have |
| 2066 | * stable values to work with. |
| 2067 | */ |
| 2068 | dev->nr_write_queues = write_queues; |
| 2069 | dev->nr_poll_queues = poll_queues; |
| 2070 | |
| 2071 | /* |
| 2072 | * If tags are shared with admin queue (Apple bug), then |
| 2073 | * make sure we only use one IO queue. |
| 2074 | */ |
| 2075 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) |
| 2076 | nr_io_queues = 1; |
| 2077 | else |
| 2078 | nr_io_queues = min(nvme_max_io_queues(dev), |
| 2079 | dev->nr_allocated_queues - 1); |
| 2080 | |
| 2081 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
| 2082 | if (result < 0) |
| 2083 | return result; |
| 2084 | |
| 2085 | if (nr_io_queues == 0) |
| 2086 | return 0; |
| 2087 | |
| 2088 | clear_bit(NVMEQ_ENABLED, &adminq->flags); |
| 2089 | |
| 2090 | if (dev->cmb_use_sqes) { |
| 2091 | result = nvme_cmb_qdepth(dev, nr_io_queues, |
| 2092 | sizeof(struct nvme_command)); |
| 2093 | if (result > 0) |
| 2094 | dev->q_depth = result; |
| 2095 | else |
| 2096 | dev->cmb_use_sqes = false; |
| 2097 | } |
| 2098 | |
| 2099 | do { |
| 2100 | size = db_bar_size(dev, nr_io_queues); |
| 2101 | result = nvme_remap_bar(dev, size); |
| 2102 | if (!result) |
| 2103 | break; |
| 2104 | if (!--nr_io_queues) |
| 2105 | return -ENOMEM; |
| 2106 | } while (1); |
| 2107 | adminq->q_db = dev->dbs; |
| 2108 | |
| 2109 | retry: |
| 2110 | /* Deregister the admin queue's interrupt */ |
| 2111 | pci_free_irq(pdev, 0, adminq); |
| 2112 | |
| 2113 | /* |
| 2114 | * If we enable msix early due to not intx, disable it again before |
| 2115 | * setting up the full range we need. |
| 2116 | */ |
| 2117 | pci_free_irq_vectors(pdev); |
| 2118 | |
| 2119 | result = nvme_setup_irqs(dev, nr_io_queues); |
| 2120 | if (result <= 0) |
| 2121 | return -EIO; |
| 2122 | |
| 2123 | dev->num_vecs = result; |
| 2124 | result = max(result - 1, 1); |
| 2125 | dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; |
| 2126 | |
| 2127 | /* |
| 2128 | * Should investigate if there's a performance win from allocating |
| 2129 | * more queues than interrupt vectors; it might allow the submission |
| 2130 | * path to scale better, even if the receive path is limited by the |
| 2131 | * number of interrupts. |
| 2132 | */ |
| 2133 | result = queue_request_irq(adminq); |
| 2134 | if (result) |
| 2135 | return result; |
| 2136 | set_bit(NVMEQ_ENABLED, &adminq->flags); |
| 2137 | |
| 2138 | result = nvme_create_io_queues(dev); |
| 2139 | if (result || dev->online_queues < 2) |
| 2140 | return result; |
| 2141 | |
| 2142 | if (dev->online_queues - 1 < dev->max_qid) { |
| 2143 | nr_io_queues = dev->online_queues - 1; |
| 2144 | nvme_disable_io_queues(dev); |
| 2145 | nvme_suspend_io_queues(dev); |
| 2146 | goto retry; |
| 2147 | } |
| 2148 | dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", |
| 2149 | dev->io_queues[HCTX_TYPE_DEFAULT], |
| 2150 | dev->io_queues[HCTX_TYPE_READ], |
| 2151 | dev->io_queues[HCTX_TYPE_POLL]); |
| 2152 | return 0; |
| 2153 | } |
| 2154 | |
| 2155 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
| 2156 | { |
| 2157 | struct nvme_queue *nvmeq = req->end_io_data; |
| 2158 | |
| 2159 | blk_mq_free_request(req); |
| 2160 | complete(&nvmeq->delete_done); |
| 2161 | } |
| 2162 | |
| 2163 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
| 2164 | { |
| 2165 | struct nvme_queue *nvmeq = req->end_io_data; |
| 2166 | |
| 2167 | if (error) |
| 2168 | set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); |
| 2169 | |
| 2170 | nvme_del_queue_end(req, error); |
| 2171 | } |
| 2172 | |
| 2173 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
| 2174 | { |
| 2175 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
| 2176 | struct request *req; |
| 2177 | struct nvme_command cmd; |
| 2178 | |
| 2179 | memset(&cmd, 0, sizeof(cmd)); |
| 2180 | cmd.delete_queue.opcode = opcode; |
| 2181 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); |
| 2182 | |
| 2183 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
| 2184 | if (IS_ERR(req)) |
| 2185 | return PTR_ERR(req); |
| 2186 | |
| 2187 | req->timeout = ADMIN_TIMEOUT; |
| 2188 | req->end_io_data = nvmeq; |
| 2189 | |
| 2190 | init_completion(&nvmeq->delete_done); |
| 2191 | blk_execute_rq_nowait(q, NULL, req, false, |
| 2192 | opcode == nvme_admin_delete_cq ? |
| 2193 | nvme_del_cq_end : nvme_del_queue_end); |
| 2194 | return 0; |
| 2195 | } |
| 2196 | |
| 2197 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) |
| 2198 | { |
| 2199 | int nr_queues = dev->online_queues - 1, sent = 0; |
| 2200 | unsigned long timeout; |
| 2201 | |
| 2202 | retry: |
| 2203 | timeout = ADMIN_TIMEOUT; |
| 2204 | while (nr_queues > 0) { |
| 2205 | if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) |
| 2206 | break; |
| 2207 | nr_queues--; |
| 2208 | sent++; |
| 2209 | } |
| 2210 | while (sent) { |
| 2211 | struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; |
| 2212 | |
| 2213 | timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, |
| 2214 | timeout); |
| 2215 | if (timeout == 0) |
| 2216 | return false; |
| 2217 | |
| 2218 | sent--; |
| 2219 | if (nr_queues) |
| 2220 | goto retry; |
| 2221 | } |
| 2222 | return true; |
| 2223 | } |
| 2224 | |
| 2225 | static void nvme_dev_add(struct nvme_dev *dev) |
| 2226 | { |
| 2227 | int ret; |
| 2228 | |
| 2229 | if (!dev->ctrl.tagset) { |
| 2230 | dev->tagset.ops = &nvme_mq_ops; |
| 2231 | dev->tagset.nr_hw_queues = dev->online_queues - 1; |
| 2232 | dev->tagset.nr_maps = 2; /* default + read */ |
| 2233 | if (dev->io_queues[HCTX_TYPE_POLL]) |
| 2234 | dev->tagset.nr_maps++; |
| 2235 | dev->tagset.timeout = NVME_IO_TIMEOUT; |
| 2236 | dev->tagset.numa_node = dev_to_node(dev->dev); |
| 2237 | dev->tagset.queue_depth = |
| 2238 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
| 2239 | dev->tagset.cmd_size = sizeof(struct nvme_iod); |
| 2240 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
| 2241 | dev->tagset.driver_data = dev; |
| 2242 | |
| 2243 | /* |
| 2244 | * Some Apple controllers requires tags to be unique |
| 2245 | * across admin and IO queue, so reserve the first 32 |
| 2246 | * tags of the IO queue. |
| 2247 | */ |
| 2248 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) |
| 2249 | dev->tagset.reserved_tags = NVME_AQ_DEPTH; |
| 2250 | |
| 2251 | ret = blk_mq_alloc_tag_set(&dev->tagset); |
| 2252 | if (ret) { |
| 2253 | dev_warn(dev->ctrl.device, |
| 2254 | "IO queues tagset allocation failed %d\n", ret); |
| 2255 | return; |
| 2256 | } |
| 2257 | dev->ctrl.tagset = &dev->tagset; |
| 2258 | } else { |
| 2259 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); |
| 2260 | |
| 2261 | /* Free previously allocated queues that are no longer usable */ |
| 2262 | nvme_free_queues(dev, dev->online_queues); |
| 2263 | } |
| 2264 | |
| 2265 | nvme_dbbuf_set(dev); |
| 2266 | } |
| 2267 | |
| 2268 | static int nvme_pci_enable(struct nvme_dev *dev) |
| 2269 | { |
| 2270 | int result = -ENOMEM; |
| 2271 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2272 | |
| 2273 | if (pci_enable_device_mem(pdev)) |
| 2274 | return result; |
| 2275 | |
| 2276 | pci_set_master(pdev); |
| 2277 | |
| 2278 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) |
| 2279 | goto disable; |
| 2280 | |
| 2281 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
| 2282 | result = -ENODEV; |
| 2283 | goto disable; |
| 2284 | } |
| 2285 | |
| 2286 | /* |
| 2287 | * Some devices and/or platforms don't advertise or work with INTx |
| 2288 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll |
| 2289 | * adjust this later. |
| 2290 | */ |
| 2291 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
| 2292 | if (result < 0) |
| 2293 | return result; |
| 2294 | |
| 2295 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
| 2296 | |
| 2297 | dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
| 2298 | io_queue_depth); |
| 2299 | dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ |
| 2300 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
| 2301 | dev->dbs = dev->bar + 4096; |
| 2302 | |
| 2303 | /* |
| 2304 | * Some Apple controllers require a non-standard SQE size. |
| 2305 | * Interestingly they also seem to ignore the CC:IOSQES register |
| 2306 | * so we don't bother updating it here. |
| 2307 | */ |
| 2308 | if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) |
| 2309 | dev->io_sqes = 7; |
| 2310 | else |
| 2311 | dev->io_sqes = NVME_NVM_IOSQES; |
| 2312 | |
| 2313 | /* |
| 2314 | * Temporary fix for the Apple controller found in the MacBook8,1 and |
| 2315 | * some MacBook7,1 to avoid controller resets and data loss. |
| 2316 | */ |
| 2317 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { |
| 2318 | dev->q_depth = 2; |
| 2319 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
| 2320 | "set queue depth=%u to work around controller resets\n", |
| 2321 | dev->q_depth); |
| 2322 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
| 2323 | (pdev->device == 0xa821 || pdev->device == 0xa822) && |
| 2324 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
| 2325 | dev->q_depth = 64; |
| 2326 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " |
| 2327 | "set queue depth=%u\n", dev->q_depth); |
| 2328 | } |
| 2329 | |
| 2330 | /* |
| 2331 | * Controllers with the shared tags quirk need the IO queue to be |
| 2332 | * big enough so that we get 32 tags for the admin queue |
| 2333 | */ |
| 2334 | if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && |
| 2335 | (dev->q_depth < (NVME_AQ_DEPTH + 2))) { |
| 2336 | dev->q_depth = NVME_AQ_DEPTH + 2; |
| 2337 | dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", |
| 2338 | dev->q_depth); |
| 2339 | } |
| 2340 | |
| 2341 | |
| 2342 | nvme_map_cmb(dev); |
| 2343 | |
| 2344 | pci_enable_pcie_error_reporting(pdev); |
| 2345 | pci_save_state(pdev); |
| 2346 | return 0; |
| 2347 | |
| 2348 | disable: |
| 2349 | pci_disable_device(pdev); |
| 2350 | return result; |
| 2351 | } |
| 2352 | |
| 2353 | static void nvme_dev_unmap(struct nvme_dev *dev) |
| 2354 | { |
| 2355 | if (dev->bar) |
| 2356 | iounmap(dev->bar); |
| 2357 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
| 2358 | } |
| 2359 | |
| 2360 | static void nvme_pci_disable(struct nvme_dev *dev) |
| 2361 | { |
| 2362 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2363 | |
| 2364 | pci_free_irq_vectors(pdev); |
| 2365 | |
| 2366 | if (pci_is_enabled(pdev)) { |
| 2367 | pci_disable_pcie_error_reporting(pdev); |
| 2368 | pci_disable_device(pdev); |
| 2369 | } |
| 2370 | } |
| 2371 | |
| 2372 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
| 2373 | { |
| 2374 | bool dead = true, freeze = false; |
| 2375 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2376 | |
| 2377 | mutex_lock(&dev->shutdown_lock); |
| 2378 | if (pci_is_enabled(pdev)) { |
| 2379 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
| 2380 | |
| 2381 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
| 2382 | dev->ctrl.state == NVME_CTRL_RESETTING) { |
| 2383 | freeze = true; |
| 2384 | nvme_start_freeze(&dev->ctrl); |
| 2385 | } |
| 2386 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || |
| 2387 | pdev->error_state != pci_channel_io_normal); |
| 2388 | } |
| 2389 | |
| 2390 | /* |
| 2391 | * Give the controller a chance to complete all entered requests if |
| 2392 | * doing a safe shutdown. |
| 2393 | */ |
| 2394 | if (!dead && shutdown && freeze) |
| 2395 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); |
| 2396 | |
| 2397 | nvme_stop_queues(&dev->ctrl); |
| 2398 | |
| 2399 | if (!dead && dev->ctrl.queue_count > 0) { |
| 2400 | nvme_disable_io_queues(dev); |
| 2401 | nvme_disable_admin_queue(dev, shutdown); |
| 2402 | } |
| 2403 | nvme_suspend_io_queues(dev); |
| 2404 | nvme_suspend_queue(&dev->queues[0]); |
| 2405 | nvme_pci_disable(dev); |
| 2406 | nvme_reap_pending_cqes(dev); |
| 2407 | |
| 2408 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
| 2409 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); |
| 2410 | blk_mq_tagset_wait_completed_request(&dev->tagset); |
| 2411 | blk_mq_tagset_wait_completed_request(&dev->admin_tagset); |
| 2412 | |
| 2413 | /* |
| 2414 | * The driver will not be starting up queues again if shutting down so |
| 2415 | * must flush all entered requests to their failed completion to avoid |
| 2416 | * deadlocking blk-mq hot-cpu notifier. |
| 2417 | */ |
| 2418 | if (shutdown) { |
| 2419 | nvme_start_queues(&dev->ctrl); |
| 2420 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) |
| 2421 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
| 2422 | } |
| 2423 | mutex_unlock(&dev->shutdown_lock); |
| 2424 | } |
| 2425 | |
| 2426 | static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) |
| 2427 | { |
| 2428 | if (!nvme_wait_reset(&dev->ctrl)) |
| 2429 | return -EBUSY; |
| 2430 | nvme_dev_disable(dev, shutdown); |
| 2431 | return 0; |
| 2432 | } |
| 2433 | |
| 2434 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
| 2435 | { |
| 2436 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
| 2437 | PAGE_SIZE, PAGE_SIZE, 0); |
| 2438 | if (!dev->prp_page_pool) |
| 2439 | return -ENOMEM; |
| 2440 | |
| 2441 | /* Optimisation for I/Os between 4k and 128k */ |
| 2442 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
| 2443 | 256, 256, 0); |
| 2444 | if (!dev->prp_small_pool) { |
| 2445 | dma_pool_destroy(dev->prp_page_pool); |
| 2446 | return -ENOMEM; |
| 2447 | } |
| 2448 | return 0; |
| 2449 | } |
| 2450 | |
| 2451 | static void nvme_release_prp_pools(struct nvme_dev *dev) |
| 2452 | { |
| 2453 | dma_pool_destroy(dev->prp_page_pool); |
| 2454 | dma_pool_destroy(dev->prp_small_pool); |
| 2455 | } |
| 2456 | |
| 2457 | static void nvme_free_tagset(struct nvme_dev *dev) |
| 2458 | { |
| 2459 | if (dev->tagset.tags) |
| 2460 | blk_mq_free_tag_set(&dev->tagset); |
| 2461 | dev->ctrl.tagset = NULL; |
| 2462 | } |
| 2463 | |
| 2464 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
| 2465 | { |
| 2466 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
| 2467 | |
| 2468 | nvme_dbbuf_dma_free(dev); |
| 2469 | nvme_free_tagset(dev); |
| 2470 | if (dev->ctrl.admin_q) |
| 2471 | blk_put_queue(dev->ctrl.admin_q); |
| 2472 | free_opal_dev(dev->ctrl.opal_dev); |
| 2473 | mempool_destroy(dev->iod_mempool); |
| 2474 | put_device(dev->dev); |
| 2475 | kfree(dev->queues); |
| 2476 | kfree(dev); |
| 2477 | } |
| 2478 | |
| 2479 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
| 2480 | { |
| 2481 | /* |
| 2482 | * Set state to deleting now to avoid blocking nvme_wait_reset(), which |
| 2483 | * may be holding this pci_dev's device lock. |
| 2484 | */ |
| 2485 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
| 2486 | nvme_get_ctrl(&dev->ctrl); |
| 2487 | nvme_dev_disable(dev, false); |
| 2488 | nvme_kill_queues(&dev->ctrl); |
| 2489 | if (!queue_work(nvme_wq, &dev->remove_work)) |
| 2490 | nvme_put_ctrl(&dev->ctrl); |
| 2491 | } |
| 2492 | |
| 2493 | static void nvme_reset_work(struct work_struct *work) |
| 2494 | { |
| 2495 | struct nvme_dev *dev = |
| 2496 | container_of(work, struct nvme_dev, ctrl.reset_work); |
| 2497 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
| 2498 | int result; |
| 2499 | |
| 2500 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { |
| 2501 | result = -ENODEV; |
| 2502 | goto out; |
| 2503 | } |
| 2504 | |
| 2505 | /* |
| 2506 | * If we're called to reset a live controller first shut it down before |
| 2507 | * moving on. |
| 2508 | */ |
| 2509 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
| 2510 | nvme_dev_disable(dev, false); |
| 2511 | nvme_sync_queues(&dev->ctrl); |
| 2512 | |
| 2513 | mutex_lock(&dev->shutdown_lock); |
| 2514 | result = nvme_pci_enable(dev); |
| 2515 | if (result) |
| 2516 | goto out_unlock; |
| 2517 | |
| 2518 | result = nvme_pci_configure_admin_queue(dev); |
| 2519 | if (result) |
| 2520 | goto out_unlock; |
| 2521 | |
| 2522 | result = nvme_alloc_admin_tags(dev); |
| 2523 | if (result) |
| 2524 | goto out_unlock; |
| 2525 | |
| 2526 | /* |
| 2527 | * Limit the max command size to prevent iod->sg allocations going |
| 2528 | * over a single page. |
| 2529 | */ |
| 2530 | dev->ctrl.max_hw_sectors = min_t(u32, |
| 2531 | NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); |
| 2532 | dev->ctrl.max_segments = NVME_MAX_SEGS; |
| 2533 | |
| 2534 | /* |
| 2535 | * Don't limit the IOMMU merged segment size. |
| 2536 | */ |
| 2537 | dma_set_max_seg_size(dev->dev, 0xffffffff); |
| 2538 | |
| 2539 | mutex_unlock(&dev->shutdown_lock); |
| 2540 | |
| 2541 | /* |
| 2542 | * Introduce CONNECTING state from nvme-fc/rdma transports to mark the |
| 2543 | * initializing procedure here. |
| 2544 | */ |
| 2545 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { |
| 2546 | dev_warn(dev->ctrl.device, |
| 2547 | "failed to mark controller CONNECTING\n"); |
| 2548 | result = -EBUSY; |
| 2549 | goto out; |
| 2550 | } |
| 2551 | |
| 2552 | result = nvme_init_identify(&dev->ctrl); |
| 2553 | if (result) |
| 2554 | goto out; |
| 2555 | |
| 2556 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
| 2557 | if (!dev->ctrl.opal_dev) |
| 2558 | dev->ctrl.opal_dev = |
| 2559 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); |
| 2560 | else if (was_suspend) |
| 2561 | opal_unlock_from_suspend(dev->ctrl.opal_dev); |
| 2562 | } else { |
| 2563 | free_opal_dev(dev->ctrl.opal_dev); |
| 2564 | dev->ctrl.opal_dev = NULL; |
| 2565 | } |
| 2566 | |
| 2567 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
| 2568 | result = nvme_dbbuf_dma_alloc(dev); |
| 2569 | if (result) |
| 2570 | dev_warn(dev->dev, |
| 2571 | "unable to allocate dma for dbbuf\n"); |
| 2572 | } |
| 2573 | |
| 2574 | if (dev->ctrl.hmpre) { |
| 2575 | result = nvme_setup_host_mem(dev); |
| 2576 | if (result < 0) |
| 2577 | goto out; |
| 2578 | } |
| 2579 | |
| 2580 | result = nvme_setup_io_queues(dev); |
| 2581 | if (result) |
| 2582 | goto out; |
| 2583 | |
| 2584 | /* |
| 2585 | * Keep the controller around but remove all namespaces if we don't have |
| 2586 | * any working I/O queue. |
| 2587 | */ |
| 2588 | if (dev->online_queues < 2) { |
| 2589 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
| 2590 | nvme_kill_queues(&dev->ctrl); |
| 2591 | nvme_remove_namespaces(&dev->ctrl); |
| 2592 | nvme_free_tagset(dev); |
| 2593 | } else { |
| 2594 | nvme_start_queues(&dev->ctrl); |
| 2595 | nvme_wait_freeze(&dev->ctrl); |
| 2596 | nvme_dev_add(dev); |
| 2597 | nvme_unfreeze(&dev->ctrl); |
| 2598 | } |
| 2599 | |
| 2600 | /* |
| 2601 | * If only admin queue live, keep it to do further investigation or |
| 2602 | * recovery. |
| 2603 | */ |
| 2604 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
| 2605 | dev_warn(dev->ctrl.device, |
| 2606 | "failed to mark controller live state\n"); |
| 2607 | result = -ENODEV; |
| 2608 | goto out; |
| 2609 | } |
| 2610 | |
| 2611 | nvme_start_ctrl(&dev->ctrl); |
| 2612 | return; |
| 2613 | |
| 2614 | out_unlock: |
| 2615 | mutex_unlock(&dev->shutdown_lock); |
| 2616 | out: |
| 2617 | if (result) |
| 2618 | dev_warn(dev->ctrl.device, |
| 2619 | "Removing after probe failure status: %d\n", result); |
| 2620 | nvme_remove_dead_ctrl(dev); |
| 2621 | } |
| 2622 | |
| 2623 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
| 2624 | { |
| 2625 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
| 2626 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2627 | |
| 2628 | if (pci_get_drvdata(pdev)) |
| 2629 | device_release_driver(&pdev->dev); |
| 2630 | nvme_put_ctrl(&dev->ctrl); |
| 2631 | } |
| 2632 | |
| 2633 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
| 2634 | { |
| 2635 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
| 2636 | return 0; |
| 2637 | } |
| 2638 | |
| 2639 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
| 2640 | { |
| 2641 | writel(val, to_nvme_dev(ctrl)->bar + off); |
| 2642 | return 0; |
| 2643 | } |
| 2644 | |
| 2645 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
| 2646 | { |
| 2647 | *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); |
| 2648 | return 0; |
| 2649 | } |
| 2650 | |
| 2651 | static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) |
| 2652 | { |
| 2653 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); |
| 2654 | |
| 2655 | return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); |
| 2656 | } |
| 2657 | |
| 2658 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
| 2659 | .name = "pcie", |
| 2660 | .module = THIS_MODULE, |
| 2661 | .flags = NVME_F_METADATA_SUPPORTED | |
| 2662 | NVME_F_PCI_P2PDMA, |
| 2663 | .reg_read32 = nvme_pci_reg_read32, |
| 2664 | .reg_write32 = nvme_pci_reg_write32, |
| 2665 | .reg_read64 = nvme_pci_reg_read64, |
| 2666 | .free_ctrl = nvme_pci_free_ctrl, |
| 2667 | .submit_async_event = nvme_pci_submit_async_event, |
| 2668 | .get_address = nvme_pci_get_address, |
| 2669 | }; |
| 2670 | |
| 2671 | static int nvme_dev_map(struct nvme_dev *dev) |
| 2672 | { |
| 2673 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
| 2674 | |
| 2675 | if (pci_request_mem_regions(pdev, "nvme")) |
| 2676 | return -ENODEV; |
| 2677 | |
| 2678 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
| 2679 | goto release; |
| 2680 | |
| 2681 | return 0; |
| 2682 | release: |
| 2683 | pci_release_mem_regions(pdev); |
| 2684 | return -ENODEV; |
| 2685 | } |
| 2686 | |
| 2687 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
| 2688 | { |
| 2689 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { |
| 2690 | /* |
| 2691 | * Several Samsung devices seem to drop off the PCIe bus |
| 2692 | * randomly when APST is on and uses the deepest sleep state. |
| 2693 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG |
| 2694 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD |
| 2695 | * 950 PRO 256GB", but it seems to be restricted to two Dell |
| 2696 | * laptops. |
| 2697 | */ |
| 2698 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && |
| 2699 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || |
| 2700 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) |
| 2701 | return NVME_QUIRK_NO_DEEPEST_PS; |
| 2702 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
| 2703 | /* |
| 2704 | * Samsung SSD 960 EVO drops off the PCIe bus after system |
| 2705 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
| 2706 | * within few minutes after bootup on a Coffee Lake board - |
| 2707 | * ASUS PRIME Z370-A |
| 2708 | */ |
| 2709 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && |
| 2710 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
| 2711 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) |
| 2712 | return NVME_QUIRK_NO_APST; |
| 2713 | } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || |
| 2714 | pdev->device == 0xa808 || pdev->device == 0xa809)) || |
| 2715 | (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { |
| 2716 | /* |
| 2717 | * Forcing to use host managed nvme power settings for |
| 2718 | * lowest idle power with quick resume latency on |
| 2719 | * Samsung and Toshiba SSDs based on suspend behavior |
| 2720 | * on Coffee Lake board for LENOVO C640 |
| 2721 | */ |
| 2722 | if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && |
| 2723 | dmi_match(DMI_BOARD_NAME, "LNVNB161216")) |
| 2724 | return NVME_QUIRK_SIMPLE_SUSPEND; |
| 2725 | } |
| 2726 | |
| 2727 | return 0; |
| 2728 | } |
| 2729 | |
| 2730 | static void nvme_async_probe(void *data, async_cookie_t cookie) |
| 2731 | { |
| 2732 | struct nvme_dev *dev = data; |
| 2733 | |
| 2734 | flush_work(&dev->ctrl.reset_work); |
| 2735 | flush_work(&dev->ctrl.scan_work); |
| 2736 | nvme_put_ctrl(&dev->ctrl); |
| 2737 | } |
| 2738 | |
| 2739 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 2740 | { |
| 2741 | int node, result = -ENOMEM; |
| 2742 | struct nvme_dev *dev; |
| 2743 | unsigned long quirks = id->driver_data; |
| 2744 | size_t alloc_size; |
| 2745 | |
| 2746 | node = dev_to_node(&pdev->dev); |
| 2747 | if (node == NUMA_NO_NODE) |
| 2748 | set_dev_node(&pdev->dev, first_memory_node); |
| 2749 | |
| 2750 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); |
| 2751 | if (!dev) |
| 2752 | return -ENOMEM; |
| 2753 | |
| 2754 | dev->nr_write_queues = write_queues; |
| 2755 | dev->nr_poll_queues = poll_queues; |
| 2756 | dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; |
| 2757 | dev->queues = kcalloc_node(dev->nr_allocated_queues, |
| 2758 | sizeof(struct nvme_queue), GFP_KERNEL, node); |
| 2759 | if (!dev->queues) |
| 2760 | goto free; |
| 2761 | |
| 2762 | dev->dev = get_device(&pdev->dev); |
| 2763 | pci_set_drvdata(pdev, dev); |
| 2764 | |
| 2765 | result = nvme_dev_map(dev); |
| 2766 | if (result) |
| 2767 | goto put_pci; |
| 2768 | |
| 2769 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
| 2770 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
| 2771 | mutex_init(&dev->shutdown_lock); |
| 2772 | |
| 2773 | result = nvme_setup_prp_pools(dev); |
| 2774 | if (result) |
| 2775 | goto unmap; |
| 2776 | |
| 2777 | quirks |= check_vendor_combination_bug(pdev); |
| 2778 | |
| 2779 | /* |
| 2780 | * Double check that our mempool alloc size will cover the biggest |
| 2781 | * command we support. |
| 2782 | */ |
| 2783 | alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, |
| 2784 | NVME_MAX_SEGS, true); |
| 2785 | WARN_ON_ONCE(alloc_size > PAGE_SIZE); |
| 2786 | |
| 2787 | dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, |
| 2788 | mempool_kfree, |
| 2789 | (void *) alloc_size, |
| 2790 | GFP_KERNEL, node); |
| 2791 | if (!dev->iod_mempool) { |
| 2792 | result = -ENOMEM; |
| 2793 | goto release_pools; |
| 2794 | } |
| 2795 | |
| 2796 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
| 2797 | quirks); |
| 2798 | if (result) |
| 2799 | goto release_mempool; |
| 2800 | |
| 2801 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
| 2802 | |
| 2803 | nvme_reset_ctrl(&dev->ctrl); |
| 2804 | async_schedule(nvme_async_probe, dev); |
| 2805 | |
| 2806 | return 0; |
| 2807 | |
| 2808 | release_mempool: |
| 2809 | mempool_destroy(dev->iod_mempool); |
| 2810 | release_pools: |
| 2811 | nvme_release_prp_pools(dev); |
| 2812 | unmap: |
| 2813 | nvme_dev_unmap(dev); |
| 2814 | put_pci: |
| 2815 | put_device(dev->dev); |
| 2816 | free: |
| 2817 | kfree(dev->queues); |
| 2818 | kfree(dev); |
| 2819 | return result; |
| 2820 | } |
| 2821 | |
| 2822 | static void nvme_reset_prepare(struct pci_dev *pdev) |
| 2823 | { |
| 2824 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 2825 | |
| 2826 | /* |
| 2827 | * We don't need to check the return value from waiting for the reset |
| 2828 | * state as pci_dev device lock is held, making it impossible to race |
| 2829 | * with ->remove(). |
| 2830 | */ |
| 2831 | nvme_disable_prepare_reset(dev, false); |
| 2832 | nvme_sync_queues(&dev->ctrl); |
| 2833 | } |
| 2834 | |
| 2835 | static void nvme_reset_done(struct pci_dev *pdev) |
| 2836 | { |
| 2837 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 2838 | |
| 2839 | if (!nvme_try_sched_reset(&dev->ctrl)) |
| 2840 | flush_work(&dev->ctrl.reset_work); |
| 2841 | } |
| 2842 | |
| 2843 | static void nvme_shutdown(struct pci_dev *pdev) |
| 2844 | { |
| 2845 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 2846 | nvme_disable_prepare_reset(dev, true); |
| 2847 | } |
| 2848 | |
| 2849 | /* |
| 2850 | * The driver's remove may be called on a device in a partially initialized |
| 2851 | * state. This function must not have any dependencies on the device state in |
| 2852 | * order to proceed. |
| 2853 | */ |
| 2854 | static void nvme_remove(struct pci_dev *pdev) |
| 2855 | { |
| 2856 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 2857 | |
| 2858 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
| 2859 | pci_set_drvdata(pdev, NULL); |
| 2860 | |
| 2861 | if (!pci_device_is_present(pdev)) { |
| 2862 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
| 2863 | nvme_dev_disable(dev, true); |
| 2864 | nvme_dev_remove_admin(dev); |
| 2865 | } |
| 2866 | |
| 2867 | flush_work(&dev->ctrl.reset_work); |
| 2868 | nvme_stop_ctrl(&dev->ctrl); |
| 2869 | nvme_remove_namespaces(&dev->ctrl); |
| 2870 | nvme_dev_disable(dev, true); |
| 2871 | nvme_release_cmb(dev); |
| 2872 | nvme_free_host_mem(dev); |
| 2873 | nvme_dev_remove_admin(dev); |
| 2874 | nvme_free_queues(dev, 0); |
| 2875 | nvme_release_prp_pools(dev); |
| 2876 | nvme_dev_unmap(dev); |
| 2877 | nvme_uninit_ctrl(&dev->ctrl); |
| 2878 | } |
| 2879 | |
| 2880 | #ifdef CONFIG_PM_SLEEP |
| 2881 | static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) |
| 2882 | { |
| 2883 | return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); |
| 2884 | } |
| 2885 | |
| 2886 | static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) |
| 2887 | { |
| 2888 | return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); |
| 2889 | } |
| 2890 | |
| 2891 | static int nvme_resume(struct device *dev) |
| 2892 | { |
| 2893 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); |
| 2894 | struct nvme_ctrl *ctrl = &ndev->ctrl; |
| 2895 | |
| 2896 | if (ndev->last_ps == U32_MAX || |
| 2897 | nvme_set_power_state(ctrl, ndev->last_ps) != 0) |
| 2898 | return nvme_try_sched_reset(&ndev->ctrl); |
| 2899 | return 0; |
| 2900 | } |
| 2901 | |
| 2902 | static int nvme_suspend(struct device *dev) |
| 2903 | { |
| 2904 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2905 | struct nvme_dev *ndev = pci_get_drvdata(pdev); |
| 2906 | struct nvme_ctrl *ctrl = &ndev->ctrl; |
| 2907 | int ret = -EBUSY; |
| 2908 | |
| 2909 | ndev->last_ps = U32_MAX; |
| 2910 | |
| 2911 | /* |
| 2912 | * The platform does not remove power for a kernel managed suspend so |
| 2913 | * use host managed nvme power settings for lowest idle power if |
| 2914 | * possible. This should have quicker resume latency than a full device |
| 2915 | * shutdown. But if the firmware is involved after the suspend or the |
| 2916 | * device does not support any non-default power states, shut down the |
| 2917 | * device fully. |
| 2918 | * |
| 2919 | * If ASPM is not enabled for the device, shut down the device and allow |
| 2920 | * the PCI bus layer to put it into D3 in order to take the PCIe link |
| 2921 | * down, so as to allow the platform to achieve its minimum low-power |
| 2922 | * state (which may not be possible if the link is up). |
| 2923 | */ |
| 2924 | if (pm_suspend_via_firmware() || !ctrl->npss || |
| 2925 | !pcie_aspm_enabled(pdev) || |
| 2926 | (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) |
| 2927 | return nvme_disable_prepare_reset(ndev, true); |
| 2928 | |
| 2929 | nvme_start_freeze(ctrl); |
| 2930 | nvme_wait_freeze(ctrl); |
| 2931 | nvme_sync_queues(ctrl); |
| 2932 | |
| 2933 | if (ctrl->state != NVME_CTRL_LIVE) |
| 2934 | goto unfreeze; |
| 2935 | |
| 2936 | ret = nvme_get_power_state(ctrl, &ndev->last_ps); |
| 2937 | if (ret < 0) |
| 2938 | goto unfreeze; |
| 2939 | |
| 2940 | /* |
| 2941 | * A saved state prevents pci pm from generically controlling the |
| 2942 | * device's power. If we're using protocol specific settings, we don't |
| 2943 | * want pci interfering. |
| 2944 | */ |
| 2945 | pci_save_state(pdev); |
| 2946 | |
| 2947 | ret = nvme_set_power_state(ctrl, ctrl->npss); |
| 2948 | if (ret < 0) |
| 2949 | goto unfreeze; |
| 2950 | |
| 2951 | if (ret) { |
| 2952 | /* discard the saved state */ |
| 2953 | pci_load_saved_state(pdev, NULL); |
| 2954 | |
| 2955 | /* |
| 2956 | * Clearing npss forces a controller reset on resume. The |
| 2957 | * correct value will be rediscovered then. |
| 2958 | */ |
| 2959 | ret = nvme_disable_prepare_reset(ndev, true); |
| 2960 | ctrl->npss = 0; |
| 2961 | } |
| 2962 | unfreeze: |
| 2963 | nvme_unfreeze(ctrl); |
| 2964 | return ret; |
| 2965 | } |
| 2966 | |
| 2967 | static int nvme_simple_suspend(struct device *dev) |
| 2968 | { |
| 2969 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); |
| 2970 | return nvme_disable_prepare_reset(ndev, true); |
| 2971 | } |
| 2972 | |
| 2973 | static int nvme_simple_resume(struct device *dev) |
| 2974 | { |
| 2975 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2976 | struct nvme_dev *ndev = pci_get_drvdata(pdev); |
| 2977 | |
| 2978 | return nvme_try_sched_reset(&ndev->ctrl); |
| 2979 | } |
| 2980 | |
| 2981 | static const struct dev_pm_ops nvme_dev_pm_ops = { |
| 2982 | .suspend = nvme_suspend, |
| 2983 | .resume = nvme_resume, |
| 2984 | .freeze = nvme_simple_suspend, |
| 2985 | .thaw = nvme_simple_resume, |
| 2986 | .poweroff = nvme_simple_suspend, |
| 2987 | .restore = nvme_simple_resume, |
| 2988 | }; |
| 2989 | #endif /* CONFIG_PM_SLEEP */ |
| 2990 | |
| 2991 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
| 2992 | pci_channel_state_t state) |
| 2993 | { |
| 2994 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 2995 | |
| 2996 | /* |
| 2997 | * A frozen channel requires a reset. When detected, this method will |
| 2998 | * shutdown the controller to quiesce. The controller will be restarted |
| 2999 | * after the slot reset through driver's slot_reset callback. |
| 3000 | */ |
| 3001 | switch (state) { |
| 3002 | case pci_channel_io_normal: |
| 3003 | return PCI_ERS_RESULT_CAN_RECOVER; |
| 3004 | case pci_channel_io_frozen: |
| 3005 | dev_warn(dev->ctrl.device, |
| 3006 | "frozen state error detected, reset controller\n"); |
| 3007 | nvme_dev_disable(dev, false); |
| 3008 | return PCI_ERS_RESULT_NEED_RESET; |
| 3009 | case pci_channel_io_perm_failure: |
| 3010 | dev_warn(dev->ctrl.device, |
| 3011 | "failure state error detected, request disconnect\n"); |
| 3012 | return PCI_ERS_RESULT_DISCONNECT; |
| 3013 | } |
| 3014 | return PCI_ERS_RESULT_NEED_RESET; |
| 3015 | } |
| 3016 | |
| 3017 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) |
| 3018 | { |
| 3019 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 3020 | |
| 3021 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
| 3022 | pci_restore_state(pdev); |
| 3023 | nvme_reset_ctrl(&dev->ctrl); |
| 3024 | return PCI_ERS_RESULT_RECOVERED; |
| 3025 | } |
| 3026 | |
| 3027 | static void nvme_error_resume(struct pci_dev *pdev) |
| 3028 | { |
| 3029 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
| 3030 | |
| 3031 | flush_work(&dev->ctrl.reset_work); |
| 3032 | } |
| 3033 | |
| 3034 | static const struct pci_error_handlers nvme_err_handler = { |
| 3035 | .error_detected = nvme_error_detected, |
| 3036 | .slot_reset = nvme_slot_reset, |
| 3037 | .resume = nvme_error_resume, |
| 3038 | .reset_prepare = nvme_reset_prepare, |
| 3039 | .reset_done = nvme_reset_done, |
| 3040 | }; |
| 3041 | |
| 3042 | static const struct pci_device_id nvme_id_table[] = { |
| 3043 | { PCI_VDEVICE(INTEL, 0x0953), |
| 3044 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
| 3045 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
| 3046 | { PCI_VDEVICE(INTEL, 0x0a53), |
| 3047 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
| 3048 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
| 3049 | { PCI_VDEVICE(INTEL, 0x0a54), |
| 3050 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
| 3051 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
| 3052 | { PCI_VDEVICE(INTEL, 0x0a55), |
| 3053 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
| 3054 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
| 3055 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
| 3056 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
| 3057 | NVME_QUIRK_MEDIUM_PRIO_SQ | |
| 3058 | NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, |
| 3059 | { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ |
| 3060 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
| 3061 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
| 3062 | .driver_data = NVME_QUIRK_IDENTIFY_CNS | |
| 3063 | NVME_QUIRK_DISABLE_WRITE_ZEROES, }, |
| 3064 | { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ |
| 3065 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, |
| 3066 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
| 3067 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, |
| 3068 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
| 3069 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, |
| 3070 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
| 3071 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, |
| 3072 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
| 3073 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, |
| 3074 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ |
| 3075 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, |
| 3076 | { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ |
| 3077 | .driver_data = NVME_QUIRK_LIGHTNVM, }, |
| 3078 | { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ |
| 3079 | .driver_data = NVME_QUIRK_LIGHTNVM, }, |
| 3080 | { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ |
| 3081 | .driver_data = NVME_QUIRK_LIGHTNVM, }, |
| 3082 | { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ |
| 3083 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
| 3084 | { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ |
| 3085 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
| 3086 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
| 3087 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
| 3088 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), |
| 3089 | .driver_data = NVME_QUIRK_SINGLE_VECTOR }, |
| 3090 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
| 3091 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), |
| 3092 | .driver_data = NVME_QUIRK_SINGLE_VECTOR | |
| 3093 | NVME_QUIRK_128_BYTES_SQES | |
| 3094 | NVME_QUIRK_SHARED_TAGS }, |
| 3095 | { 0, } |
| 3096 | }; |
| 3097 | MODULE_DEVICE_TABLE(pci, nvme_id_table); |
| 3098 | |
| 3099 | static struct pci_driver nvme_driver = { |
| 3100 | .name = "nvme", |
| 3101 | .id_table = nvme_id_table, |
| 3102 | .probe = nvme_probe, |
| 3103 | .remove = nvme_remove, |
| 3104 | .shutdown = nvme_shutdown, |
| 3105 | #ifdef CONFIG_PM_SLEEP |
| 3106 | .driver = { |
| 3107 | .pm = &nvme_dev_pm_ops, |
| 3108 | }, |
| 3109 | #endif |
| 3110 | .sriov_configure = pci_sriov_configure_simple, |
| 3111 | .err_handler = &nvme_err_handler, |
| 3112 | }; |
| 3113 | |
| 3114 | static int __init nvme_init(void) |
| 3115 | { |
| 3116 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); |
| 3117 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); |
| 3118 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); |
| 3119 | BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); |
| 3120 | |
| 3121 | write_queues = min(write_queues, num_possible_cpus()); |
| 3122 | poll_queues = min(poll_queues, num_possible_cpus()); |
| 3123 | return pci_register_driver(&nvme_driver); |
| 3124 | } |
| 3125 | |
| 3126 | static void __exit nvme_exit(void) |
| 3127 | { |
| 3128 | pci_unregister_driver(&nvme_driver); |
| 3129 | flush_workqueue(nvme_wq); |
| 3130 | } |
| 3131 | |
| 3132 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); |
| 3133 | MODULE_LICENSE("GPL"); |
| 3134 | MODULE_VERSION("1.0"); |
| 3135 | module_init(nvme_init); |
| 3136 | module_exit(nvme_exit); |