| 1 | /****************************************************************************** |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
| 8 | * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. |
| 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
| 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
| 11 | * Copyright(c) 2018 - 2019 Intel Corporation |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of version 2 of the GNU General Public License as |
| 15 | * published by the Free Software Foundation. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, but |
| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 20 | * General Public License for more details. |
| 21 | * |
| 22 | * The full GNU General Public License is included in this distribution |
| 23 | * in the file called COPYING. |
| 24 | * |
| 25 | * Contact Information: |
| 26 | * Intel Linux Wireless <linuxwifi@intel.com> |
| 27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 28 | * |
| 29 | * BSD LICENSE |
| 30 | * |
| 31 | * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. |
| 32 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
| 33 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
| 34 | * Copyright(c) 2018 - 2019 Intel Corporation |
| 35 | * All rights reserved. |
| 36 | * |
| 37 | * Redistribution and use in source and binary forms, with or without |
| 38 | * modification, are permitted provided that the following conditions |
| 39 | * are met: |
| 40 | * |
| 41 | * * Redistributions of source code must retain the above copyright |
| 42 | * notice, this list of conditions and the following disclaimer. |
| 43 | * * Redistributions in binary form must reproduce the above copyright |
| 44 | * notice, this list of conditions and the following disclaimer in |
| 45 | * the documentation and/or other materials provided with the |
| 46 | * distribution. |
| 47 | * * Neither the name Intel Corporation nor the names of its |
| 48 | * contributors may be used to endorse or promote products derived |
| 49 | * from this software without specific prior written permission. |
| 50 | * |
| 51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 52 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 53 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 54 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 55 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 56 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 57 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 58 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 59 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 60 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 61 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 62 | * |
| 63 | *****************************************************************************/ |
| 64 | #include <linux/pci.h> |
| 65 | #include <linux/interrupt.h> |
| 66 | #include <linux/debugfs.h> |
| 67 | #include <linux/sched.h> |
| 68 | #include <linux/bitops.h> |
| 69 | #include <linux/gfp.h> |
| 70 | #include <linux/vmalloc.h> |
| 71 | #include <linux/module.h> |
| 72 | #include <linux/wait.h> |
| 73 | |
| 74 | #include "iwl-drv.h" |
| 75 | #include "iwl-trans.h" |
| 76 | #include "iwl-csr.h" |
| 77 | #include "iwl-prph.h" |
| 78 | #include "iwl-scd.h" |
| 79 | #include "iwl-agn-hw.h" |
| 80 | #include "fw/error-dump.h" |
| 81 | #include "fw/dbg.h" |
| 82 | #include "internal.h" |
| 83 | #include "iwl-fh.h" |
| 84 | |
| 85 | /* extended range in FW SRAM */ |
| 86 | #define IWL_FW_MEM_EXTENDED_START 0x40000 |
| 87 | #define IWL_FW_MEM_EXTENDED_END 0x57FFF |
| 88 | |
| 89 | void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) |
| 90 | { |
| 91 | #define PCI_DUMP_SIZE 352 |
| 92 | #define PCI_MEM_DUMP_SIZE 64 |
| 93 | #define PCI_PARENT_DUMP_SIZE 524 |
| 94 | #define PREFIX_LEN 32 |
| 95 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 96 | struct pci_dev *pdev = trans_pcie->pci_dev; |
| 97 | u32 i, pos, alloc_size, *ptr, *buf; |
| 98 | char *prefix; |
| 99 | |
| 100 | if (trans_pcie->pcie_dbg_dumped_once) |
| 101 | return; |
| 102 | |
| 103 | /* Should be a multiple of 4 */ |
| 104 | BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); |
| 105 | BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); |
| 106 | BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); |
| 107 | |
| 108 | /* Alloc a max size buffer */ |
| 109 | alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; |
| 110 | alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); |
| 111 | alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); |
| 112 | alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); |
| 113 | |
| 114 | buf = kmalloc(alloc_size, GFP_ATOMIC); |
| 115 | if (!buf) |
| 116 | return; |
| 117 | prefix = (char *)buf + alloc_size - PREFIX_LEN; |
| 118 | |
| 119 | IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); |
| 120 | |
| 121 | /* Print wifi device registers */ |
| 122 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); |
| 123 | IWL_ERR(trans, "iwlwifi device config registers:\n"); |
| 124 | for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) |
| 125 | if (pci_read_config_dword(pdev, i, ptr)) |
| 126 | goto err_read; |
| 127 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); |
| 128 | |
| 129 | IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); |
| 130 | for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) |
| 131 | *ptr = iwl_read32(trans, i); |
| 132 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); |
| 133 | |
| 134 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); |
| 135 | if (pos) { |
| 136 | IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); |
| 137 | for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) |
| 138 | if (pci_read_config_dword(pdev, pos + i, ptr)) |
| 139 | goto err_read; |
| 140 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, |
| 141 | 32, 4, buf, i, 0); |
| 142 | } |
| 143 | |
| 144 | /* Print parent device registers next */ |
| 145 | if (!pdev->bus->self) |
| 146 | goto out; |
| 147 | |
| 148 | pdev = pdev->bus->self; |
| 149 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); |
| 150 | |
| 151 | IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", |
| 152 | pci_name(pdev)); |
| 153 | for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) |
| 154 | if (pci_read_config_dword(pdev, i, ptr)) |
| 155 | goto err_read; |
| 156 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); |
| 157 | |
| 158 | /* Print root port AER registers */ |
| 159 | pos = 0; |
| 160 | pdev = pcie_find_root_port(pdev); |
| 161 | if (pdev) |
| 162 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); |
| 163 | if (pos) { |
| 164 | IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", |
| 165 | pci_name(pdev)); |
| 166 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); |
| 167 | for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) |
| 168 | if (pci_read_config_dword(pdev, pos + i, ptr)) |
| 169 | goto err_read; |
| 170 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, |
| 171 | 4, buf, i, 0); |
| 172 | } |
| 173 | goto out; |
| 174 | |
| 175 | err_read: |
| 176 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); |
| 177 | IWL_ERR(trans, "Read failed at 0x%X\n", i); |
| 178 | out: |
| 179 | trans_pcie->pcie_dbg_dumped_once = 1; |
| 180 | kfree(buf); |
| 181 | } |
| 182 | |
| 183 | static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) |
| 184 | { |
| 185 | /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ |
| 186 | iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset, |
| 187 | BIT(trans->trans_cfg->csr->flag_sw_reset)); |
| 188 | usleep_range(5000, 6000); |
| 189 | } |
| 190 | |
| 191 | static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) |
| 192 | { |
| 193 | struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
| 194 | |
| 195 | if (!fw_mon->size) |
| 196 | return; |
| 197 | |
| 198 | dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, |
| 199 | fw_mon->physical); |
| 200 | |
| 201 | fw_mon->block = NULL; |
| 202 | fw_mon->physical = 0; |
| 203 | fw_mon->size = 0; |
| 204 | } |
| 205 | |
| 206 | static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, |
| 207 | u8 max_power, u8 min_power) |
| 208 | { |
| 209 | struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
| 210 | void *block = NULL; |
| 211 | dma_addr_t physical = 0; |
| 212 | u32 size = 0; |
| 213 | u8 power; |
| 214 | |
| 215 | if (fw_mon->size) |
| 216 | return; |
| 217 | |
| 218 | for (power = max_power; power >= min_power; power--) { |
| 219 | size = BIT(power); |
| 220 | block = dma_alloc_coherent(trans->dev, size, &physical, |
| 221 | GFP_KERNEL | __GFP_NOWARN); |
| 222 | if (!block) |
| 223 | continue; |
| 224 | |
| 225 | IWL_INFO(trans, |
| 226 | "Allocated 0x%08x bytes for firmware monitor.\n", |
| 227 | size); |
| 228 | break; |
| 229 | } |
| 230 | |
| 231 | if (WARN_ON_ONCE(!block)) |
| 232 | return; |
| 233 | |
| 234 | if (power != max_power) |
| 235 | IWL_ERR(trans, |
| 236 | "Sorry - debug buffer is only %luK while you requested %luK\n", |
| 237 | (unsigned long)BIT(power - 10), |
| 238 | (unsigned long)BIT(max_power - 10)); |
| 239 | |
| 240 | fw_mon->block = block; |
| 241 | fw_mon->physical = physical; |
| 242 | fw_mon->size = size; |
| 243 | } |
| 244 | |
| 245 | void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) |
| 246 | { |
| 247 | if (!max_power) { |
| 248 | /* default max_power is maximum */ |
| 249 | max_power = 26; |
| 250 | } else { |
| 251 | max_power += 11; |
| 252 | } |
| 253 | |
| 254 | if (WARN(max_power > 26, |
| 255 | "External buffer size for monitor is too big %d, check the FW TLV\n", |
| 256 | max_power)) |
| 257 | return; |
| 258 | |
| 259 | if (trans->dbg.fw_mon.size) |
| 260 | return; |
| 261 | |
| 262 | iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); |
| 263 | } |
| 264 | |
| 265 | static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) |
| 266 | { |
| 267 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, |
| 268 | ((reg & 0x0000ffff) | (2 << 28))); |
| 269 | return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); |
| 270 | } |
| 271 | |
| 272 | static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) |
| 273 | { |
| 274 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); |
| 275 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, |
| 276 | ((reg & 0x0000ffff) | (3 << 28))); |
| 277 | } |
| 278 | |
| 279 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
| 280 | { |
| 281 | if (trans->cfg->apmg_not_supported) |
| 282 | return; |
| 283 | |
| 284 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
| 285 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
| 286 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
| 287 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
| 288 | else |
| 289 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
| 290 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
| 291 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
| 292 | } |
| 293 | |
| 294 | /* PCI registers */ |
| 295 | #define PCI_CFG_RETRY_TIMEOUT 0x041 |
| 296 | |
| 297 | void iwl_pcie_apm_config(struct iwl_trans *trans) |
| 298 | { |
| 299 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 300 | u16 lctl; |
| 301 | u16 cap; |
| 302 | |
| 303 | /* |
| 304 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. |
| 305 | * Check if BIOS (or OS) enabled L1-ASPM on this device. |
| 306 | * If so (likely), disable L0S, so device moves directly L0->L1; |
| 307 | * costs negligible amount of power savings. |
| 308 | * If not (unlikely), enable L0S, so there is at least some |
| 309 | * power savings, even without L1. |
| 310 | */ |
| 311 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
| 312 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) |
| 313 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
| 314 | else |
| 315 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
| 316 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
| 317 | |
| 318 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); |
| 319 | trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; |
| 320 | IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", |
| 321 | (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", |
| 322 | trans->ltr_enabled ? "En" : "Dis"); |
| 323 | } |
| 324 | |
| 325 | /* |
| 326 | * Start up NIC's basic functionality after it has been reset |
| 327 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
| 328 | * NOTE: This does not load uCode nor start the embedded processor |
| 329 | */ |
| 330 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
| 331 | { |
| 332 | int ret; |
| 333 | |
| 334 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); |
| 335 | |
| 336 | /* |
| 337 | * Use "set_bit" below rather than "write", to preserve any hardware |
| 338 | * bits already set by default after reset. |
| 339 | */ |
| 340 | |
| 341 | /* Disable L0S exit timer (platform NMI Work/Around) */ |
| 342 | if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) |
| 343 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, |
| 344 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
| 345 | |
| 346 | /* |
| 347 | * Disable L0s without affecting L1; |
| 348 | * don't wait for ICH L0s (ICH bug W/A) |
| 349 | */ |
| 350 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, |
| 351 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
| 352 | |
| 353 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ |
| 354 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
| 355 | |
| 356 | /* |
| 357 | * Enable HAP INTA (interrupt from management bus) to |
| 358 | * wake device's PCI Express link L1a -> L0s |
| 359 | */ |
| 360 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 361 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
| 362 | |
| 363 | iwl_pcie_apm_config(trans); |
| 364 | |
| 365 | /* Configure analog phase-lock-loop before activating to D0A */ |
| 366 | if (trans->trans_cfg->base_params->pll_cfg) |
| 367 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); |
| 368 | |
| 369 | ret = iwl_finish_nic_init(trans, trans->trans_cfg); |
| 370 | if (ret) |
| 371 | return ret; |
| 372 | |
| 373 | if (trans->cfg->host_interrupt_operation_mode) { |
| 374 | /* |
| 375 | * This is a bit of an abuse - This is needed for 7260 / 3160 |
| 376 | * only check host_interrupt_operation_mode even if this is |
| 377 | * not related to host_interrupt_operation_mode. |
| 378 | * |
| 379 | * Enable the oscillator to count wake up time for L1 exit. This |
| 380 | * consumes slightly more power (100uA) - but allows to be sure |
| 381 | * that we wake up from L1 on time. |
| 382 | * |
| 383 | * This looks weird: read twice the same register, discard the |
| 384 | * value, set a bit, and yet again, read that same register |
| 385 | * just to discard the value. But that's the way the hardware |
| 386 | * seems to like it. |
| 387 | */ |
| 388 | iwl_read_prph(trans, OSC_CLK); |
| 389 | iwl_read_prph(trans, OSC_CLK); |
| 390 | iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); |
| 391 | iwl_read_prph(trans, OSC_CLK); |
| 392 | iwl_read_prph(trans, OSC_CLK); |
| 393 | } |
| 394 | |
| 395 | /* |
| 396 | * Enable DMA clock and wait for it to stabilize. |
| 397 | * |
| 398 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" |
| 399 | * bits do not disable clocks. This preserves any hardware |
| 400 | * bits already set by default in "CLK_CTRL_REG" after reset. |
| 401 | */ |
| 402 | if (!trans->cfg->apmg_not_supported) { |
| 403 | iwl_write_prph(trans, APMG_CLK_EN_REG, |
| 404 | APMG_CLK_VAL_DMA_CLK_RQT); |
| 405 | udelay(20); |
| 406 | |
| 407 | /* Disable L1-Active */ |
| 408 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, |
| 409 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
| 410 | |
| 411 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ |
| 412 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, |
| 413 | APMG_RTC_INT_STT_RFKILL); |
| 414 | } |
| 415 | |
| 416 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | /* |
| 422 | * Enable LP XTAL to avoid HW bug where device may consume much power if |
| 423 | * FW is not loaded after device reset. LP XTAL is disabled by default |
| 424 | * after device HW reset. Do it only if XTAL is fed by internal source. |
| 425 | * Configure device's "persistence" mode to avoid resetting XTAL again when |
| 426 | * SHRD_HW_RST occurs in S3. |
| 427 | */ |
| 428 | static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) |
| 429 | { |
| 430 | int ret; |
| 431 | u32 apmg_gp1_reg; |
| 432 | u32 apmg_xtal_cfg_reg; |
| 433 | u32 dl_cfg_reg; |
| 434 | |
| 435 | /* Force XTAL ON */ |
| 436 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
| 437 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); |
| 438 | |
| 439 | iwl_trans_pcie_sw_reset(trans); |
| 440 | |
| 441 | ret = iwl_finish_nic_init(trans, trans->trans_cfg); |
| 442 | if (WARN_ON(ret)) { |
| 443 | /* Release XTAL ON request */ |
| 444 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
| 445 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); |
| 446 | return; |
| 447 | } |
| 448 | |
| 449 | /* |
| 450 | * Clear "disable persistence" to avoid LP XTAL resetting when |
| 451 | * SHRD_HW_RST is applied in S3. |
| 452 | */ |
| 453 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, |
| 454 | APMG_PCIDEV_STT_VAL_PERSIST_DIS); |
| 455 | |
| 456 | /* |
| 457 | * Force APMG XTAL to be active to prevent its disabling by HW |
| 458 | * caused by APMG idle state. |
| 459 | */ |
| 460 | apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, |
| 461 | SHR_APMG_XTAL_CFG_REG); |
| 462 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, |
| 463 | apmg_xtal_cfg_reg | |
| 464 | SHR_APMG_XTAL_CFG_XTAL_ON_REQ); |
| 465 | |
| 466 | iwl_trans_pcie_sw_reset(trans); |
| 467 | |
| 468 | /* Enable LP XTAL by indirect access through CSR */ |
| 469 | apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); |
| 470 | iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | |
| 471 | SHR_APMG_GP1_WF_XTAL_LP_EN | |
| 472 | SHR_APMG_GP1_CHICKEN_BIT_SELECT); |
| 473 | |
| 474 | /* Clear delay line clock power up */ |
| 475 | dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); |
| 476 | iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & |
| 477 | ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); |
| 478 | |
| 479 | /* |
| 480 | * Enable persistence mode to avoid LP XTAL resetting when |
| 481 | * SHRD_HW_RST is applied in S3. |
| 482 | */ |
| 483 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 484 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); |
| 485 | |
| 486 | /* |
| 487 | * Clear "initialization complete" bit to move adapter from |
| 488 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. |
| 489 | */ |
| 490 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
| 491 | BIT(trans->trans_cfg->csr->flag_init_done)); |
| 492 | |
| 493 | /* Activates XTAL resources monitor */ |
| 494 | __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, |
| 495 | CSR_MONITOR_XTAL_RESOURCES); |
| 496 | |
| 497 | /* Release XTAL ON request */ |
| 498 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
| 499 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); |
| 500 | udelay(10); |
| 501 | |
| 502 | /* Release APMG XTAL */ |
| 503 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, |
| 504 | apmg_xtal_cfg_reg & |
| 505 | ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); |
| 506 | } |
| 507 | |
| 508 | void iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
| 509 | { |
| 510 | int ret; |
| 511 | |
| 512 | /* stop device's busmaster DMA activity */ |
| 513 | iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset, |
| 514 | BIT(trans->trans_cfg->csr->flag_stop_master)); |
| 515 | |
| 516 | ret = iwl_poll_bit(trans, trans->trans_cfg->csr->addr_sw_reset, |
| 517 | BIT(trans->trans_cfg->csr->flag_master_dis), |
| 518 | BIT(trans->trans_cfg->csr->flag_master_dis), 100); |
| 519 | if (ret < 0) |
| 520 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); |
| 521 | |
| 522 | IWL_DEBUG_INFO(trans, "stop master\n"); |
| 523 | } |
| 524 | |
| 525 | static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) |
| 526 | { |
| 527 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
| 528 | |
| 529 | if (op_mode_leave) { |
| 530 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) |
| 531 | iwl_pcie_apm_init(trans); |
| 532 | |
| 533 | /* inform ME that we are leaving */ |
| 534 | if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) |
| 535 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, |
| 536 | APMG_PCIDEV_STT_VAL_WAKE_ME); |
| 537 | else if (trans->trans_cfg->device_family >= |
| 538 | IWL_DEVICE_FAMILY_8000) { |
| 539 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
| 540 | CSR_RESET_LINK_PWR_MGMT_DISABLED); |
| 541 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 542 | CSR_HW_IF_CONFIG_REG_PREPARE | |
| 543 | CSR_HW_IF_CONFIG_REG_ENABLE_PME); |
| 544 | mdelay(1); |
| 545 | iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
| 546 | CSR_RESET_LINK_PWR_MGMT_DISABLED); |
| 547 | } |
| 548 | mdelay(5); |
| 549 | } |
| 550 | |
| 551 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
| 552 | |
| 553 | /* Stop device's DMA activity */ |
| 554 | iwl_pcie_apm_stop_master(trans); |
| 555 | |
| 556 | if (trans->cfg->lp_xtal_workaround) { |
| 557 | iwl_pcie_apm_lp_xtal_enable(trans); |
| 558 | return; |
| 559 | } |
| 560 | |
| 561 | iwl_trans_pcie_sw_reset(trans); |
| 562 | |
| 563 | /* |
| 564 | * Clear "initialization complete" bit to move adapter from |
| 565 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. |
| 566 | */ |
| 567 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
| 568 | BIT(trans->trans_cfg->csr->flag_init_done)); |
| 569 | } |
| 570 | |
| 571 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
| 572 | { |
| 573 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 574 | int ret; |
| 575 | |
| 576 | /* nic_init */ |
| 577 | spin_lock(&trans_pcie->irq_lock); |
| 578 | ret = iwl_pcie_apm_init(trans); |
| 579 | spin_unlock(&trans_pcie->irq_lock); |
| 580 | |
| 581 | if (ret) |
| 582 | return ret; |
| 583 | |
| 584 | iwl_pcie_set_pwr(trans, false); |
| 585 | |
| 586 | iwl_op_mode_nic_config(trans->op_mode); |
| 587 | |
| 588 | /* Allocate the RX queue, or reset if it is already allocated */ |
| 589 | iwl_pcie_rx_init(trans); |
| 590 | |
| 591 | /* Allocate or reset and init all Tx and Command queues */ |
| 592 | if (iwl_pcie_tx_init(trans)) |
| 593 | return -ENOMEM; |
| 594 | |
| 595 | if (trans->trans_cfg->base_params->shadow_reg_enable) { |
| 596 | /* enable shadow regs in HW */ |
| 597 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
| 598 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
| 599 | } |
| 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | #define HW_READY_TIMEOUT (50) |
| 605 | |
| 606 | /* Note: returns poll_bit return value, which is >= 0 if success */ |
| 607 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
| 608 | { |
| 609 | int ret; |
| 610 | |
| 611 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 612 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
| 613 | |
| 614 | /* See if we got it */ |
| 615 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 616 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
| 617 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
| 618 | HW_READY_TIMEOUT); |
| 619 | |
| 620 | if (ret >= 0) |
| 621 | iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); |
| 622 | |
| 623 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
| 624 | return ret; |
| 625 | } |
| 626 | |
| 627 | /* Note: returns standard 0/-ERROR code */ |
| 628 | int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
| 629 | { |
| 630 | int ret; |
| 631 | int t = 0; |
| 632 | int iter; |
| 633 | |
| 634 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
| 635 | |
| 636 | ret = iwl_pcie_set_hw_ready(trans); |
| 637 | /* If the card is ready, exit 0 */ |
| 638 | if (ret >= 0) |
| 639 | return 0; |
| 640 | |
| 641 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
| 642 | CSR_RESET_LINK_PWR_MGMT_DISABLED); |
| 643 | usleep_range(1000, 2000); |
| 644 | |
| 645 | for (iter = 0; iter < 10; iter++) { |
| 646 | /* If HW is not ready, prepare the conditions to check again */ |
| 647 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 648 | CSR_HW_IF_CONFIG_REG_PREPARE); |
| 649 | |
| 650 | do { |
| 651 | ret = iwl_pcie_set_hw_ready(trans); |
| 652 | if (ret >= 0) |
| 653 | return 0; |
| 654 | |
| 655 | usleep_range(200, 1000); |
| 656 | t += 200; |
| 657 | } while (t < 150000); |
| 658 | msleep(25); |
| 659 | } |
| 660 | |
| 661 | IWL_ERR(trans, "Couldn't prepare the card\n"); |
| 662 | |
| 663 | return ret; |
| 664 | } |
| 665 | |
| 666 | /* |
| 667 | * ucode |
| 668 | */ |
| 669 | static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, |
| 670 | u32 dst_addr, dma_addr_t phy_addr, |
| 671 | u32 byte_cnt) |
| 672 | { |
| 673 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
| 674 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); |
| 675 | |
| 676 | iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
| 677 | dst_addr); |
| 678 | |
| 679 | iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
| 680 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); |
| 681 | |
| 682 | iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
| 683 | (iwl_get_dma_hi_addr(phy_addr) |
| 684 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); |
| 685 | |
| 686 | iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
| 687 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | |
| 688 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | |
| 689 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); |
| 690 | |
| 691 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
| 692 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
| 693 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
| 694 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
| 695 | } |
| 696 | |
| 697 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, |
| 698 | u32 dst_addr, dma_addr_t phy_addr, |
| 699 | u32 byte_cnt) |
| 700 | { |
| 701 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 702 | unsigned long flags; |
| 703 | int ret; |
| 704 | |
| 705 | trans_pcie->ucode_write_complete = false; |
| 706 | |
| 707 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
| 708 | return -EIO; |
| 709 | |
| 710 | iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, |
| 711 | byte_cnt); |
| 712 | iwl_trans_release_nic_access(trans, &flags); |
| 713 | |
| 714 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
| 715 | trans_pcie->ucode_write_complete, 5 * HZ); |
| 716 | if (!ret) { |
| 717 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
| 718 | iwl_trans_pcie_dump_regs(trans); |
| 719 | return -ETIMEDOUT; |
| 720 | } |
| 721 | |
| 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
| 726 | const struct fw_desc *section) |
| 727 | { |
| 728 | u8 *v_addr; |
| 729 | dma_addr_t p_addr; |
| 730 | u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); |
| 731 | int ret = 0; |
| 732 | |
| 733 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
| 734 | section_num); |
| 735 | |
| 736 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
| 737 | GFP_KERNEL | __GFP_NOWARN); |
| 738 | if (!v_addr) { |
| 739 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); |
| 740 | chunk_sz = PAGE_SIZE; |
| 741 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, |
| 742 | &p_addr, GFP_KERNEL); |
| 743 | if (!v_addr) |
| 744 | return -ENOMEM; |
| 745 | } |
| 746 | |
| 747 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
| 748 | u32 copy_size, dst_addr; |
| 749 | bool extended_addr = false; |
| 750 | |
| 751 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
| 752 | dst_addr = section->offset + offset; |
| 753 | |
| 754 | if (dst_addr >= IWL_FW_MEM_EXTENDED_START && |
| 755 | dst_addr <= IWL_FW_MEM_EXTENDED_END) |
| 756 | extended_addr = true; |
| 757 | |
| 758 | if (extended_addr) |
| 759 | iwl_set_bits_prph(trans, LMPM_CHICK, |
| 760 | LMPM_CHICK_EXTENDED_ADDR_SPACE); |
| 761 | |
| 762 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
| 763 | ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, |
| 764 | copy_size); |
| 765 | |
| 766 | if (extended_addr) |
| 767 | iwl_clear_bits_prph(trans, LMPM_CHICK, |
| 768 | LMPM_CHICK_EXTENDED_ADDR_SPACE); |
| 769 | |
| 770 | if (ret) { |
| 771 | IWL_ERR(trans, |
| 772 | "Could not load the [%d] uCode section\n", |
| 773 | section_num); |
| 774 | break; |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
| 779 | return ret; |
| 780 | } |
| 781 | |
| 782 | static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, |
| 783 | const struct fw_img *image, |
| 784 | int cpu, |
| 785 | int *first_ucode_section) |
| 786 | { |
| 787 | int shift_param; |
| 788 | int i, ret = 0, sec_num = 0x1; |
| 789 | u32 val, last_read_idx = 0; |
| 790 | |
| 791 | if (cpu == 1) { |
| 792 | shift_param = 0; |
| 793 | *first_ucode_section = 0; |
| 794 | } else { |
| 795 | shift_param = 16; |
| 796 | (*first_ucode_section)++; |
| 797 | } |
| 798 | |
| 799 | for (i = *first_ucode_section; i < image->num_sec; i++) { |
| 800 | last_read_idx = i; |
| 801 | |
| 802 | /* |
| 803 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between |
| 804 | * CPU1 to CPU2. |
| 805 | * PAGING_SEPARATOR_SECTION delimiter - separate between |
| 806 | * CPU2 non paged to CPU2 paging sec. |
| 807 | */ |
| 808 | if (!image->sec[i].data || |
| 809 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
| 810 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { |
| 811 | IWL_DEBUG_FW(trans, |
| 812 | "Break since Data not valid or Empty section, sec = %d\n", |
| 813 | i); |
| 814 | break; |
| 815 | } |
| 816 | |
| 817 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
| 818 | if (ret) |
| 819 | return ret; |
| 820 | |
| 821 | /* Notify ucode of loaded section number and status */ |
| 822 | val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); |
| 823 | val = val | (sec_num << shift_param); |
| 824 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); |
| 825 | |
| 826 | sec_num = (sec_num << 1) | 0x1; |
| 827 | } |
| 828 | |
| 829 | *first_ucode_section = last_read_idx; |
| 830 | |
| 831 | iwl_enable_interrupts(trans); |
| 832 | |
| 833 | if (trans->trans_cfg->use_tfh) { |
| 834 | if (cpu == 1) |
| 835 | iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, |
| 836 | 0xFFFF); |
| 837 | else |
| 838 | iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, |
| 839 | 0xFFFFFFFF); |
| 840 | } else { |
| 841 | if (cpu == 1) |
| 842 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, |
| 843 | 0xFFFF); |
| 844 | else |
| 845 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, |
| 846 | 0xFFFFFFFF); |
| 847 | } |
| 848 | |
| 849 | return 0; |
| 850 | } |
| 851 | |
| 852 | static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, |
| 853 | const struct fw_img *image, |
| 854 | int cpu, |
| 855 | int *first_ucode_section) |
| 856 | { |
| 857 | int i, ret = 0; |
| 858 | u32 last_read_idx = 0; |
| 859 | |
| 860 | if (cpu == 1) |
| 861 | *first_ucode_section = 0; |
| 862 | else |
| 863 | (*first_ucode_section)++; |
| 864 | |
| 865 | for (i = *first_ucode_section; i < image->num_sec; i++) { |
| 866 | last_read_idx = i; |
| 867 | |
| 868 | /* |
| 869 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between |
| 870 | * CPU1 to CPU2. |
| 871 | * PAGING_SEPARATOR_SECTION delimiter - separate between |
| 872 | * CPU2 non paged to CPU2 paging sec. |
| 873 | */ |
| 874 | if (!image->sec[i].data || |
| 875 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
| 876 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { |
| 877 | IWL_DEBUG_FW(trans, |
| 878 | "Break since Data not valid or Empty section, sec = %d\n", |
| 879 | i); |
| 880 | break; |
| 881 | } |
| 882 | |
| 883 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
| 884 | if (ret) |
| 885 | return ret; |
| 886 | } |
| 887 | |
| 888 | *first_ucode_section = last_read_idx; |
| 889 | |
| 890 | return 0; |
| 891 | } |
| 892 | |
| 893 | static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) |
| 894 | { |
| 895 | enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; |
| 896 | struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = |
| 897 | &trans->dbg.fw_mon_cfg[alloc_id]; |
| 898 | struct iwl_dram_data *frag; |
| 899 | |
| 900 | if (!iwl_trans_dbg_ini_valid(trans)) |
| 901 | return; |
| 902 | |
| 903 | if (le32_to_cpu(fw_mon_cfg->buf_location) == |
| 904 | IWL_FW_INI_LOCATION_SRAM_PATH) { |
| 905 | IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); |
| 906 | /* set sram monitor by enabling bit 7 */ |
| 907 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 908 | CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); |
| 909 | |
| 910 | return; |
| 911 | } |
| 912 | |
| 913 | if (le32_to_cpu(fw_mon_cfg->buf_location) != |
| 914 | IWL_FW_INI_LOCATION_DRAM_PATH || |
| 915 | !trans->dbg.fw_mon_ini[alloc_id].num_frags) |
| 916 | return; |
| 917 | |
| 918 | frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; |
| 919 | |
| 920 | IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", |
| 921 | alloc_id); |
| 922 | |
| 923 | iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, |
| 924 | frag->physical >> MON_BUFF_SHIFT_VER2); |
| 925 | iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, |
| 926 | (frag->physical + frag->size - 256) >> |
| 927 | MON_BUFF_SHIFT_VER2); |
| 928 | } |
| 929 | |
| 930 | void iwl_pcie_apply_destination(struct iwl_trans *trans) |
| 931 | { |
| 932 | const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; |
| 933 | const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
| 934 | int i; |
| 935 | |
| 936 | if (iwl_trans_dbg_ini_valid(trans)) { |
| 937 | iwl_pcie_apply_destination_ini(trans); |
| 938 | return; |
| 939 | } |
| 940 | |
| 941 | IWL_INFO(trans, "Applying debug destination %s\n", |
| 942 | get_fw_dbg_mode_string(dest->monitor_mode)); |
| 943 | |
| 944 | if (dest->monitor_mode == EXTERNAL_MODE) |
| 945 | iwl_pcie_alloc_fw_monitor(trans, dest->size_power); |
| 946 | else |
| 947 | IWL_WARN(trans, "PCI should have external buffer debug\n"); |
| 948 | |
| 949 | for (i = 0; i < trans->dbg.n_dest_reg; i++) { |
| 950 | u32 addr = le32_to_cpu(dest->reg_ops[i].addr); |
| 951 | u32 val = le32_to_cpu(dest->reg_ops[i].val); |
| 952 | |
| 953 | switch (dest->reg_ops[i].op) { |
| 954 | case CSR_ASSIGN: |
| 955 | iwl_write32(trans, addr, val); |
| 956 | break; |
| 957 | case CSR_SETBIT: |
| 958 | iwl_set_bit(trans, addr, BIT(val)); |
| 959 | break; |
| 960 | case CSR_CLEARBIT: |
| 961 | iwl_clear_bit(trans, addr, BIT(val)); |
| 962 | break; |
| 963 | case PRPH_ASSIGN: |
| 964 | iwl_write_prph(trans, addr, val); |
| 965 | break; |
| 966 | case PRPH_SETBIT: |
| 967 | iwl_set_bits_prph(trans, addr, BIT(val)); |
| 968 | break; |
| 969 | case PRPH_CLEARBIT: |
| 970 | iwl_clear_bits_prph(trans, addr, BIT(val)); |
| 971 | break; |
| 972 | case PRPH_BLOCKBIT: |
| 973 | if (iwl_read_prph(trans, addr) & BIT(val)) { |
| 974 | IWL_ERR(trans, |
| 975 | "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", |
| 976 | val, addr); |
| 977 | goto monitor; |
| 978 | } |
| 979 | break; |
| 980 | default: |
| 981 | IWL_ERR(trans, "FW debug - unknown OP %d\n", |
| 982 | dest->reg_ops[i].op); |
| 983 | break; |
| 984 | } |
| 985 | } |
| 986 | |
| 987 | monitor: |
| 988 | if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { |
| 989 | iwl_write_prph(trans, le32_to_cpu(dest->base_reg), |
| 990 | fw_mon->physical >> dest->base_shift); |
| 991 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
| 992 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), |
| 993 | (fw_mon->physical + fw_mon->size - |
| 994 | 256) >> dest->end_shift); |
| 995 | else |
| 996 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), |
| 997 | (fw_mon->physical + fw_mon->size) >> |
| 998 | dest->end_shift); |
| 999 | } |
| 1000 | } |
| 1001 | |
| 1002 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
| 1003 | const struct fw_img *image) |
| 1004 | { |
| 1005 | int ret = 0; |
| 1006 | int first_ucode_section; |
| 1007 | |
| 1008 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
| 1009 | image->is_dual_cpus ? "Dual" : "Single"); |
| 1010 | |
| 1011 | /* load to FW the binary non secured sections of CPU1 */ |
| 1012 | ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); |
| 1013 | if (ret) |
| 1014 | return ret; |
| 1015 | |
| 1016 | if (image->is_dual_cpus) { |
| 1017 | /* set CPU2 header address */ |
| 1018 | iwl_write_prph(trans, |
| 1019 | LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, |
| 1020 | LMPM_SECURE_CPU2_HDR_MEM_SPACE); |
| 1021 | |
| 1022 | /* load to FW the binary sections of CPU2 */ |
| 1023 | ret = iwl_pcie_load_cpu_sections(trans, image, 2, |
| 1024 | &first_ucode_section); |
| 1025 | if (ret) |
| 1026 | return ret; |
| 1027 | } |
| 1028 | |
| 1029 | /* supported for 7000 only for the moment */ |
| 1030 | if (iwlwifi_mod_params.fw_monitor && |
| 1031 | trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { |
| 1032 | struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
| 1033 | |
| 1034 | iwl_pcie_alloc_fw_monitor(trans, 0); |
| 1035 | if (fw_mon->size) { |
| 1036 | iwl_write_prph(trans, MON_BUFF_BASE_ADDR, |
| 1037 | fw_mon->physical >> 4); |
| 1038 | iwl_write_prph(trans, MON_BUFF_END_ADDR, |
| 1039 | (fw_mon->physical + fw_mon->size) >> 4); |
| 1040 | } |
| 1041 | } else if (iwl_pcie_dbg_on(trans)) { |
| 1042 | iwl_pcie_apply_destination(trans); |
| 1043 | } |
| 1044 | |
| 1045 | iwl_enable_interrupts(trans); |
| 1046 | |
| 1047 | /* release CPU reset */ |
| 1048 | iwl_write32(trans, CSR_RESET, 0); |
| 1049 | |
| 1050 | return 0; |
| 1051 | } |
| 1052 | |
| 1053 | static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, |
| 1054 | const struct fw_img *image) |
| 1055 | { |
| 1056 | int ret = 0; |
| 1057 | int first_ucode_section; |
| 1058 | |
| 1059 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
| 1060 | image->is_dual_cpus ? "Dual" : "Single"); |
| 1061 | |
| 1062 | if (iwl_pcie_dbg_on(trans)) |
| 1063 | iwl_pcie_apply_destination(trans); |
| 1064 | |
| 1065 | IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", |
| 1066 | iwl_read_prph(trans, WFPM_GP2)); |
| 1067 | |
| 1068 | /* |
| 1069 | * Set default value. On resume reading the values that were |
| 1070 | * zeored can provide debug data on the resume flow. |
| 1071 | * This is for debugging only and has no functional impact. |
| 1072 | */ |
| 1073 | iwl_write_prph(trans, WFPM_GP2, 0x01010101); |
| 1074 | |
| 1075 | /* configure the ucode to be ready to get the secured image */ |
| 1076 | /* release CPU reset */ |
| 1077 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); |
| 1078 | |
| 1079 | /* load to FW the binary Secured sections of CPU1 */ |
| 1080 | ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, |
| 1081 | &first_ucode_section); |
| 1082 | if (ret) |
| 1083 | return ret; |
| 1084 | |
| 1085 | /* load to FW the binary sections of CPU2 */ |
| 1086 | return iwl_pcie_load_cpu_sections_8000(trans, image, 2, |
| 1087 | &first_ucode_section); |
| 1088 | } |
| 1089 | |
| 1090 | bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) |
| 1091 | { |
| 1092 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1093 | bool hw_rfkill = iwl_is_rfkill_set(trans); |
| 1094 | bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1095 | bool report; |
| 1096 | |
| 1097 | if (hw_rfkill) { |
| 1098 | set_bit(STATUS_RFKILL_HW, &trans->status); |
| 1099 | set_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1100 | } else { |
| 1101 | clear_bit(STATUS_RFKILL_HW, &trans->status); |
| 1102 | if (trans_pcie->opmode_down) |
| 1103 | clear_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1104 | } |
| 1105 | |
| 1106 | report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1107 | |
| 1108 | if (prev != report) |
| 1109 | iwl_trans_pcie_rf_kill(trans, report); |
| 1110 | |
| 1111 | return hw_rfkill; |
| 1112 | } |
| 1113 | |
| 1114 | struct iwl_causes_list { |
| 1115 | u32 cause_num; |
| 1116 | u32 mask_reg; |
| 1117 | u8 addr; |
| 1118 | }; |
| 1119 | |
| 1120 | static struct iwl_causes_list causes_list[] = { |
| 1121 | {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, |
| 1122 | {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, |
| 1123 | {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, |
| 1124 | {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, |
| 1125 | {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, |
| 1126 | {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, |
| 1127 | {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, |
| 1128 | {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, |
| 1129 | {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, |
| 1130 | {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, |
| 1131 | {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, |
| 1132 | {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, |
| 1133 | {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, |
| 1134 | {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, |
| 1135 | {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, |
| 1136 | }; |
| 1137 | |
| 1138 | static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) |
| 1139 | { |
| 1140 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1141 | int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; |
| 1142 | int i, arr_size = ARRAY_SIZE(causes_list); |
| 1143 | struct iwl_causes_list *causes = causes_list; |
| 1144 | |
| 1145 | /* |
| 1146 | * Access all non RX causes and map them to the default irq. |
| 1147 | * In case we are missing at least one interrupt vector, |
| 1148 | * the first interrupt vector will serve non-RX and FBQ causes. |
| 1149 | */ |
| 1150 | for (i = 0; i < arr_size; i++) { |
| 1151 | iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); |
| 1152 | iwl_clear_bit(trans, causes[i].mask_reg, |
| 1153 | causes[i].cause_num); |
| 1154 | } |
| 1155 | } |
| 1156 | |
| 1157 | static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) |
| 1158 | { |
| 1159 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1160 | u32 offset = |
| 1161 | trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; |
| 1162 | u32 val, idx; |
| 1163 | |
| 1164 | /* |
| 1165 | * The first RX queue - fallback queue, which is designated for |
| 1166 | * management frame, command responses etc, is always mapped to the |
| 1167 | * first interrupt vector. The other RX queues are mapped to |
| 1168 | * the other (N - 2) interrupt vectors. |
| 1169 | */ |
| 1170 | val = BIT(MSIX_FH_INT_CAUSES_Q(0)); |
| 1171 | for (idx = 1; idx < trans->num_rx_queues; idx++) { |
| 1172 | iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), |
| 1173 | MSIX_FH_INT_CAUSES_Q(idx - offset)); |
| 1174 | val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); |
| 1175 | } |
| 1176 | iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); |
| 1177 | |
| 1178 | val = MSIX_FH_INT_CAUSES_Q(0); |
| 1179 | if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) |
| 1180 | val |= MSIX_NON_AUTO_CLEAR_CAUSE; |
| 1181 | iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); |
| 1182 | |
| 1183 | if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) |
| 1184 | iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); |
| 1185 | } |
| 1186 | |
| 1187 | void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) |
| 1188 | { |
| 1189 | struct iwl_trans *trans = trans_pcie->trans; |
| 1190 | |
| 1191 | if (!trans_pcie->msix_enabled) { |
| 1192 | if (trans->trans_cfg->mq_rx_supported && |
| 1193 | test_bit(STATUS_DEVICE_ENABLED, &trans->status)) |
| 1194 | iwl_write_umac_prph(trans, UREG_CHICK, |
| 1195 | UREG_CHICK_MSI_ENABLE); |
| 1196 | return; |
| 1197 | } |
| 1198 | /* |
| 1199 | * The IVAR table needs to be configured again after reset, |
| 1200 | * but if the device is disabled, we can't write to |
| 1201 | * prph. |
| 1202 | */ |
| 1203 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) |
| 1204 | iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); |
| 1205 | |
| 1206 | /* |
| 1207 | * Each cause from the causes list above and the RX causes is |
| 1208 | * represented as a byte in the IVAR table. The first nibble |
| 1209 | * represents the bound interrupt vector of the cause, the second |
| 1210 | * represents no auto clear for this cause. This will be set if its |
| 1211 | * interrupt vector is bound to serve other causes. |
| 1212 | */ |
| 1213 | iwl_pcie_map_rx_causes(trans); |
| 1214 | |
| 1215 | iwl_pcie_map_non_rx_causes(trans); |
| 1216 | } |
| 1217 | |
| 1218 | static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) |
| 1219 | { |
| 1220 | struct iwl_trans *trans = trans_pcie->trans; |
| 1221 | |
| 1222 | iwl_pcie_conf_msix_hw(trans_pcie); |
| 1223 | |
| 1224 | if (!trans_pcie->msix_enabled) |
| 1225 | return; |
| 1226 | |
| 1227 | trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); |
| 1228 | trans_pcie->fh_mask = trans_pcie->fh_init_mask; |
| 1229 | trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); |
| 1230 | trans_pcie->hw_mask = trans_pcie->hw_init_mask; |
| 1231 | } |
| 1232 | |
| 1233 | static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
| 1234 | { |
| 1235 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1236 | |
| 1237 | lockdep_assert_held(&trans_pcie->mutex); |
| 1238 | |
| 1239 | if (trans_pcie->is_down) |
| 1240 | return; |
| 1241 | |
| 1242 | trans_pcie->is_down = true; |
| 1243 | |
| 1244 | /* tell the device to stop sending interrupts */ |
| 1245 | iwl_disable_interrupts(trans); |
| 1246 | |
| 1247 | /* device going down, Stop using ICT table */ |
| 1248 | iwl_pcie_disable_ict(trans); |
| 1249 | |
| 1250 | /* |
| 1251 | * If a HW restart happens during firmware loading, |
| 1252 | * then the firmware loading might call this function |
| 1253 | * and later it might be called again due to the |
| 1254 | * restart. So don't process again if the device is |
| 1255 | * already dead. |
| 1256 | */ |
| 1257 | if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
| 1258 | IWL_DEBUG_INFO(trans, |
| 1259 | "DEVICE_ENABLED bit was set and is now cleared\n"); |
| 1260 | iwl_pcie_tx_stop(trans); |
| 1261 | iwl_pcie_rx_stop(trans); |
| 1262 | |
| 1263 | /* Power-down device's busmaster DMA clocks */ |
| 1264 | if (!trans->cfg->apmg_not_supported) { |
| 1265 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
| 1266 | APMG_CLK_VAL_DMA_CLK_RQT); |
| 1267 | udelay(5); |
| 1268 | } |
| 1269 | } |
| 1270 | |
| 1271 | /* Make sure (redundant) we've released our request to stay awake */ |
| 1272 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
| 1273 | BIT(trans->trans_cfg->csr->flag_mac_access_req)); |
| 1274 | |
| 1275 | /* Stop the device, and put it in low power state */ |
| 1276 | iwl_pcie_apm_stop(trans, false); |
| 1277 | |
| 1278 | iwl_trans_pcie_sw_reset(trans); |
| 1279 | |
| 1280 | /* |
| 1281 | * Upon stop, the IVAR table gets erased, so msi-x won't |
| 1282 | * work. This causes a bug in RF-KILL flows, since the interrupt |
| 1283 | * that enables radio won't fire on the correct irq, and the |
| 1284 | * driver won't be able to handle the interrupt. |
| 1285 | * Configure the IVAR table again after reset. |
| 1286 | */ |
| 1287 | iwl_pcie_conf_msix_hw(trans_pcie); |
| 1288 | |
| 1289 | /* |
| 1290 | * Upon stop, the APM issues an interrupt if HW RF kill is set. |
| 1291 | * This is a bug in certain verions of the hardware. |
| 1292 | * Certain devices also keep sending HW RF kill interrupt all |
| 1293 | * the time, unless the interrupt is ACKed even if the interrupt |
| 1294 | * should be masked. Re-ACK all the interrupts here. |
| 1295 | */ |
| 1296 | iwl_disable_interrupts(trans); |
| 1297 | |
| 1298 | /* clear all status bits */ |
| 1299 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
| 1300 | clear_bit(STATUS_INT_ENABLED, &trans->status); |
| 1301 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
| 1302 | |
| 1303 | /* |
| 1304 | * Even if we stop the HW, we still want the RF kill |
| 1305 | * interrupt |
| 1306 | */ |
| 1307 | iwl_enable_rfkill_int(trans); |
| 1308 | |
| 1309 | /* re-take ownership to prevent other users from stealing the device */ |
| 1310 | iwl_pcie_prepare_card_hw(trans); |
| 1311 | } |
| 1312 | |
| 1313 | void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) |
| 1314 | { |
| 1315 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1316 | |
| 1317 | if (trans_pcie->msix_enabled) { |
| 1318 | int i; |
| 1319 | |
| 1320 | for (i = 0; i < trans_pcie->alloc_vecs; i++) |
| 1321 | synchronize_irq(trans_pcie->msix_entries[i].vector); |
| 1322 | } else { |
| 1323 | synchronize_irq(trans_pcie->pci_dev->irq); |
| 1324 | } |
| 1325 | } |
| 1326 | |
| 1327 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
| 1328 | const struct fw_img *fw, bool run_in_rfkill) |
| 1329 | { |
| 1330 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1331 | bool hw_rfkill; |
| 1332 | int ret; |
| 1333 | |
| 1334 | /* This may fail if AMT took ownership of the device */ |
| 1335 | if (iwl_pcie_prepare_card_hw(trans)) { |
| 1336 | IWL_WARN(trans, "Exit HW not ready\n"); |
| 1337 | ret = -EIO; |
| 1338 | goto out; |
| 1339 | } |
| 1340 | |
| 1341 | iwl_enable_rfkill_int(trans); |
| 1342 | |
| 1343 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
| 1344 | |
| 1345 | /* |
| 1346 | * We enabled the RF-Kill interrupt and the handler may very |
| 1347 | * well be running. Disable the interrupts to make sure no other |
| 1348 | * interrupt can be fired. |
| 1349 | */ |
| 1350 | iwl_disable_interrupts(trans); |
| 1351 | |
| 1352 | /* Make sure it finished running */ |
| 1353 | iwl_pcie_synchronize_irqs(trans); |
| 1354 | |
| 1355 | mutex_lock(&trans_pcie->mutex); |
| 1356 | |
| 1357 | /* If platform's RF_KILL switch is NOT set to KILL */ |
| 1358 | hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); |
| 1359 | if (hw_rfkill && !run_in_rfkill) { |
| 1360 | ret = -ERFKILL; |
| 1361 | goto out; |
| 1362 | } |
| 1363 | |
| 1364 | /* Someone called stop_device, don't try to start_fw */ |
| 1365 | if (trans_pcie->is_down) { |
| 1366 | IWL_WARN(trans, |
| 1367 | "Can't start_fw since the HW hasn't been started\n"); |
| 1368 | ret = -EIO; |
| 1369 | goto out; |
| 1370 | } |
| 1371 | |
| 1372 | /* make sure rfkill handshake bits are cleared */ |
| 1373 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
| 1374 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, |
| 1375 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
| 1376 | |
| 1377 | /* clear (again), then enable host interrupts */ |
| 1378 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
| 1379 | |
| 1380 | ret = iwl_pcie_nic_init(trans); |
| 1381 | if (ret) { |
| 1382 | IWL_ERR(trans, "Unable to init nic\n"); |
| 1383 | goto out; |
| 1384 | } |
| 1385 | |
| 1386 | /* |
| 1387 | * Now, we load the firmware and don't want to be interrupted, even |
| 1388 | * by the RF-Kill interrupt (hence mask all the interrupt besides the |
| 1389 | * FH_TX interrupt which is needed to load the firmware). If the |
| 1390 | * RF-Kill switch is toggled, we will find out after having loaded |
| 1391 | * the firmware and return the proper value to the caller. |
| 1392 | */ |
| 1393 | iwl_enable_fw_load_int(trans); |
| 1394 | |
| 1395 | /* really make sure rfkill handshake bits are cleared */ |
| 1396 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
| 1397 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
| 1398 | |
| 1399 | /* Load the given image to the HW */ |
| 1400 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
| 1401 | ret = iwl_pcie_load_given_ucode_8000(trans, fw); |
| 1402 | else |
| 1403 | ret = iwl_pcie_load_given_ucode(trans, fw); |
| 1404 | |
| 1405 | /* re-check RF-Kill state since we may have missed the interrupt */ |
| 1406 | hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); |
| 1407 | if (hw_rfkill && !run_in_rfkill) |
| 1408 | ret = -ERFKILL; |
| 1409 | |
| 1410 | out: |
| 1411 | mutex_unlock(&trans_pcie->mutex); |
| 1412 | return ret; |
| 1413 | } |
| 1414 | |
| 1415 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
| 1416 | { |
| 1417 | iwl_pcie_reset_ict(trans); |
| 1418 | iwl_pcie_tx_start(trans, scd_addr); |
| 1419 | } |
| 1420 | |
| 1421 | void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, |
| 1422 | bool was_in_rfkill) |
| 1423 | { |
| 1424 | bool hw_rfkill; |
| 1425 | |
| 1426 | /* |
| 1427 | * Check again since the RF kill state may have changed while |
| 1428 | * all the interrupts were disabled, in this case we couldn't |
| 1429 | * receive the RF kill interrupt and update the state in the |
| 1430 | * op_mode. |
| 1431 | * Don't call the op_mode if the rkfill state hasn't changed. |
| 1432 | * This allows the op_mode to call stop_device from the rfkill |
| 1433 | * notification without endless recursion. Under very rare |
| 1434 | * circumstances, we might have a small recursion if the rfkill |
| 1435 | * state changed exactly now while we were called from stop_device. |
| 1436 | * This is very unlikely but can happen and is supported. |
| 1437 | */ |
| 1438 | hw_rfkill = iwl_is_rfkill_set(trans); |
| 1439 | if (hw_rfkill) { |
| 1440 | set_bit(STATUS_RFKILL_HW, &trans->status); |
| 1441 | set_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1442 | } else { |
| 1443 | clear_bit(STATUS_RFKILL_HW, &trans->status); |
| 1444 | clear_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1445 | } |
| 1446 | if (hw_rfkill != was_in_rfkill) |
| 1447 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
| 1448 | } |
| 1449 | |
| 1450 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
| 1451 | { |
| 1452 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1453 | bool was_in_rfkill; |
| 1454 | |
| 1455 | mutex_lock(&trans_pcie->mutex); |
| 1456 | trans_pcie->opmode_down = true; |
| 1457 | was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); |
| 1458 | _iwl_trans_pcie_stop_device(trans); |
| 1459 | iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); |
| 1460 | mutex_unlock(&trans_pcie->mutex); |
| 1461 | } |
| 1462 | |
| 1463 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) |
| 1464 | { |
| 1465 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
| 1466 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1467 | |
| 1468 | lockdep_assert_held(&trans_pcie->mutex); |
| 1469 | |
| 1470 | IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", |
| 1471 | state ? "disabled" : "enabled"); |
| 1472 | if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { |
| 1473 | if (trans->trans_cfg->gen2) |
| 1474 | _iwl_trans_pcie_gen2_stop_device(trans); |
| 1475 | else |
| 1476 | _iwl_trans_pcie_stop_device(trans); |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, |
| 1481 | bool test, bool reset) |
| 1482 | { |
| 1483 | iwl_disable_interrupts(trans); |
| 1484 | |
| 1485 | /* |
| 1486 | * in testing mode, the host stays awake and the |
| 1487 | * hardware won't be reset (not even partially) |
| 1488 | */ |
| 1489 | if (test) |
| 1490 | return; |
| 1491 | |
| 1492 | iwl_pcie_disable_ict(trans); |
| 1493 | |
| 1494 | iwl_pcie_synchronize_irqs(trans); |
| 1495 | |
| 1496 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
| 1497 | BIT(trans->trans_cfg->csr->flag_mac_access_req)); |
| 1498 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
| 1499 | BIT(trans->trans_cfg->csr->flag_init_done)); |
| 1500 | |
| 1501 | if (reset) { |
| 1502 | /* |
| 1503 | * reset TX queues -- some of their registers reset during S3 |
| 1504 | * so if we don't reset everything here the D3 image would try |
| 1505 | * to execute some invalid memory upon resume |
| 1506 | */ |
| 1507 | iwl_trans_pcie_tx_reset(trans); |
| 1508 | } |
| 1509 | |
| 1510 | iwl_pcie_set_pwr(trans, true); |
| 1511 | } |
| 1512 | |
| 1513 | static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, |
| 1514 | bool reset) |
| 1515 | { |
| 1516 | int ret; |
| 1517 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1518 | |
| 1519 | /* |
| 1520 | * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW. |
| 1521 | */ |
| 1522 | if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { |
| 1523 | /* Enable persistence mode to avoid reset */ |
| 1524 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
| 1525 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); |
| 1526 | } |
| 1527 | |
| 1528 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { |
| 1529 | iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, |
| 1530 | UREG_DOORBELL_TO_ISR6_SUSPEND); |
| 1531 | |
| 1532 | ret = wait_event_timeout(trans_pcie->sx_waitq, |
| 1533 | trans_pcie->sx_complete, 2 * HZ); |
| 1534 | /* |
| 1535 | * Invalidate it toward resume. |
| 1536 | */ |
| 1537 | trans_pcie->sx_complete = false; |
| 1538 | |
| 1539 | if (!ret) { |
| 1540 | IWL_ERR(trans, "Timeout entering D3\n"); |
| 1541 | return -ETIMEDOUT; |
| 1542 | } |
| 1543 | } |
| 1544 | iwl_pcie_d3_complete_suspend(trans, test, reset); |
| 1545 | |
| 1546 | return 0; |
| 1547 | } |
| 1548 | |
| 1549 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, |
| 1550 | enum iwl_d3_status *status, |
| 1551 | bool test, bool reset) |
| 1552 | { |
| 1553 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1554 | u32 val; |
| 1555 | int ret; |
| 1556 | |
| 1557 | if (test) { |
| 1558 | iwl_enable_interrupts(trans); |
| 1559 | *status = IWL_D3_STATUS_ALIVE; |
| 1560 | goto out; |
| 1561 | } |
| 1562 | |
| 1563 | iwl_set_bit(trans, CSR_GP_CNTRL, |
| 1564 | BIT(trans->trans_cfg->csr->flag_mac_access_req)); |
| 1565 | |
| 1566 | ret = iwl_finish_nic_init(trans, trans->trans_cfg); |
| 1567 | if (ret) |
| 1568 | return ret; |
| 1569 | |
| 1570 | /* |
| 1571 | * Reconfigure IVAR table in case of MSIX or reset ict table in |
| 1572 | * MSI mode since HW reset erased it. |
| 1573 | * Also enables interrupts - none will happen as |
| 1574 | * the device doesn't know we're waking it up, only when |
| 1575 | * the opmode actually tells it after this call. |
| 1576 | */ |
| 1577 | iwl_pcie_conf_msix_hw(trans_pcie); |
| 1578 | if (!trans_pcie->msix_enabled) |
| 1579 | iwl_pcie_reset_ict(trans); |
| 1580 | iwl_enable_interrupts(trans); |
| 1581 | |
| 1582 | iwl_pcie_set_pwr(trans, false); |
| 1583 | |
| 1584 | if (!reset) { |
| 1585 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
| 1586 | BIT(trans->trans_cfg->csr->flag_mac_access_req)); |
| 1587 | } else { |
| 1588 | iwl_trans_pcie_tx_reset(trans); |
| 1589 | |
| 1590 | ret = iwl_pcie_rx_init(trans); |
| 1591 | if (ret) { |
| 1592 | IWL_ERR(trans, |
| 1593 | "Failed to resume the device (RX reset)\n"); |
| 1594 | return ret; |
| 1595 | } |
| 1596 | } |
| 1597 | |
| 1598 | IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", |
| 1599 | iwl_read_umac_prph(trans, WFPM_GP2)); |
| 1600 | |
| 1601 | val = iwl_read32(trans, CSR_RESET); |
| 1602 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) |
| 1603 | *status = IWL_D3_STATUS_RESET; |
| 1604 | else |
| 1605 | *status = IWL_D3_STATUS_ALIVE; |
| 1606 | |
| 1607 | out: |
| 1608 | if (*status == IWL_D3_STATUS_ALIVE && |
| 1609 | trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { |
| 1610 | trans_pcie->sx_complete = false; |
| 1611 | iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, |
| 1612 | UREG_DOORBELL_TO_ISR6_RESUME); |
| 1613 | |
| 1614 | ret = wait_event_timeout(trans_pcie->sx_waitq, |
| 1615 | trans_pcie->sx_complete, 2 * HZ); |
| 1616 | /* |
| 1617 | * Invalidate it toward next suspend. |
| 1618 | */ |
| 1619 | trans_pcie->sx_complete = false; |
| 1620 | |
| 1621 | if (!ret) { |
| 1622 | IWL_ERR(trans, "Timeout exiting D3\n"); |
| 1623 | return -ETIMEDOUT; |
| 1624 | } |
| 1625 | } |
| 1626 | return 0; |
| 1627 | } |
| 1628 | |
| 1629 | static void |
| 1630 | iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, |
| 1631 | struct iwl_trans *trans, |
| 1632 | const struct iwl_cfg_trans_params *cfg_trans) |
| 1633 | { |
| 1634 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1635 | int max_irqs, num_irqs, i, ret; |
| 1636 | u16 pci_cmd; |
| 1637 | |
| 1638 | if (!cfg_trans->mq_rx_supported) |
| 1639 | goto enable_msi; |
| 1640 | |
| 1641 | max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); |
| 1642 | for (i = 0; i < max_irqs; i++) |
| 1643 | trans_pcie->msix_entries[i].entry = i; |
| 1644 | |
| 1645 | num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, |
| 1646 | MSIX_MIN_INTERRUPT_VECTORS, |
| 1647 | max_irqs); |
| 1648 | if (num_irqs < 0) { |
| 1649 | IWL_DEBUG_INFO(trans, |
| 1650 | "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", |
| 1651 | num_irqs); |
| 1652 | goto enable_msi; |
| 1653 | } |
| 1654 | trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; |
| 1655 | |
| 1656 | IWL_DEBUG_INFO(trans, |
| 1657 | "MSI-X enabled. %d interrupt vectors were allocated\n", |
| 1658 | num_irqs); |
| 1659 | |
| 1660 | /* |
| 1661 | * In case the OS provides fewer interrupts than requested, different |
| 1662 | * causes will share the same interrupt vector as follows: |
| 1663 | * One interrupt less: non rx causes shared with FBQ. |
| 1664 | * Two interrupts less: non rx causes shared with FBQ and RSS. |
| 1665 | * More than two interrupts: we will use fewer RSS queues. |
| 1666 | */ |
| 1667 | if (num_irqs <= max_irqs - 2) { |
| 1668 | trans_pcie->trans->num_rx_queues = num_irqs + 1; |
| 1669 | trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | |
| 1670 | IWL_SHARED_IRQ_FIRST_RSS; |
| 1671 | } else if (num_irqs == max_irqs - 1) { |
| 1672 | trans_pcie->trans->num_rx_queues = num_irqs; |
| 1673 | trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; |
| 1674 | } else { |
| 1675 | trans_pcie->trans->num_rx_queues = num_irqs - 1; |
| 1676 | } |
| 1677 | WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); |
| 1678 | |
| 1679 | trans_pcie->alloc_vecs = num_irqs; |
| 1680 | trans_pcie->msix_enabled = true; |
| 1681 | return; |
| 1682 | |
| 1683 | enable_msi: |
| 1684 | ret = pci_enable_msi(pdev); |
| 1685 | if (ret) { |
| 1686 | dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); |
| 1687 | /* enable rfkill interrupt: hw bug w/a */ |
| 1688 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
| 1689 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { |
| 1690 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; |
| 1691 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
| 1692 | } |
| 1693 | } |
| 1694 | } |
| 1695 | |
| 1696 | static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) |
| 1697 | { |
| 1698 | int iter_rx_q, i, ret, cpu, offset; |
| 1699 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1700 | |
| 1701 | i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; |
| 1702 | iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; |
| 1703 | offset = 1 + i; |
| 1704 | for (; i < iter_rx_q ; i++) { |
| 1705 | /* |
| 1706 | * Get the cpu prior to the place to search |
| 1707 | * (i.e. return will be > i - 1). |
| 1708 | */ |
| 1709 | cpu = cpumask_next(i - offset, cpu_online_mask); |
| 1710 | cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); |
| 1711 | ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, |
| 1712 | &trans_pcie->affinity_mask[i]); |
| 1713 | if (ret) |
| 1714 | IWL_ERR(trans_pcie->trans, |
| 1715 | "Failed to set affinity mask for IRQ %d\n", |
| 1716 | i); |
| 1717 | } |
| 1718 | } |
| 1719 | |
| 1720 | static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, |
| 1721 | struct iwl_trans_pcie *trans_pcie) |
| 1722 | { |
| 1723 | int i; |
| 1724 | |
| 1725 | for (i = 0; i < trans_pcie->alloc_vecs; i++) { |
| 1726 | int ret; |
| 1727 | struct msix_entry *msix_entry; |
| 1728 | const char *qname = queue_name(&pdev->dev, trans_pcie, i); |
| 1729 | |
| 1730 | if (!qname) |
| 1731 | return -ENOMEM; |
| 1732 | |
| 1733 | msix_entry = &trans_pcie->msix_entries[i]; |
| 1734 | ret = devm_request_threaded_irq(&pdev->dev, |
| 1735 | msix_entry->vector, |
| 1736 | iwl_pcie_msix_isr, |
| 1737 | (i == trans_pcie->def_irq) ? |
| 1738 | iwl_pcie_irq_msix_handler : |
| 1739 | iwl_pcie_irq_rx_msix_handler, |
| 1740 | IRQF_SHARED, |
| 1741 | qname, |
| 1742 | msix_entry); |
| 1743 | if (ret) { |
| 1744 | IWL_ERR(trans_pcie->trans, |
| 1745 | "Error allocating IRQ %d\n", i); |
| 1746 | |
| 1747 | return ret; |
| 1748 | } |
| 1749 | } |
| 1750 | iwl_pcie_irq_set_affinity(trans_pcie->trans); |
| 1751 | |
| 1752 | return 0; |
| 1753 | } |
| 1754 | |
| 1755 | static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) |
| 1756 | { |
| 1757 | u32 hpm, wprot; |
| 1758 | |
| 1759 | switch (trans->trans_cfg->device_family) { |
| 1760 | case IWL_DEVICE_FAMILY_9000: |
| 1761 | wprot = PREG_PRPH_WPROT_9000; |
| 1762 | break; |
| 1763 | case IWL_DEVICE_FAMILY_22000: |
| 1764 | wprot = PREG_PRPH_WPROT_22000; |
| 1765 | break; |
| 1766 | default: |
| 1767 | return 0; |
| 1768 | } |
| 1769 | |
| 1770 | hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); |
| 1771 | if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { |
| 1772 | u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); |
| 1773 | |
| 1774 | if (wprot_val & PREG_WFPM_ACCESS) { |
| 1775 | IWL_ERR(trans, |
| 1776 | "Error, can not clear persistence bit\n"); |
| 1777 | return -EPERM; |
| 1778 | } |
| 1779 | iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, |
| 1780 | hpm & ~PERSISTENCE_BIT); |
| 1781 | } |
| 1782 | |
| 1783 | return 0; |
| 1784 | } |
| 1785 | |
| 1786 | static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
| 1787 | { |
| 1788 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1789 | int err; |
| 1790 | |
| 1791 | lockdep_assert_held(&trans_pcie->mutex); |
| 1792 | |
| 1793 | err = iwl_pcie_prepare_card_hw(trans); |
| 1794 | if (err) { |
| 1795 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
| 1796 | return err; |
| 1797 | } |
| 1798 | |
| 1799 | err = iwl_trans_pcie_clear_persistence_bit(trans); |
| 1800 | if (err) |
| 1801 | return err; |
| 1802 | |
| 1803 | iwl_trans_pcie_sw_reset(trans); |
| 1804 | |
| 1805 | err = iwl_pcie_apm_init(trans); |
| 1806 | if (err) |
| 1807 | return err; |
| 1808 | |
| 1809 | iwl_pcie_init_msix(trans_pcie); |
| 1810 | |
| 1811 | /* From now on, the op_mode will be kept updated about RF kill state */ |
| 1812 | iwl_enable_rfkill_int(trans); |
| 1813 | |
| 1814 | trans_pcie->opmode_down = false; |
| 1815 | |
| 1816 | /* Set is_down to false here so that...*/ |
| 1817 | trans_pcie->is_down = false; |
| 1818 | |
| 1819 | /* ...rfkill can call stop_device and set it false if needed */ |
| 1820 | iwl_pcie_check_hw_rf_kill(trans); |
| 1821 | |
| 1822 | return 0; |
| 1823 | } |
| 1824 | |
| 1825 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
| 1826 | { |
| 1827 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1828 | int ret; |
| 1829 | |
| 1830 | mutex_lock(&trans_pcie->mutex); |
| 1831 | ret = _iwl_trans_pcie_start_hw(trans); |
| 1832 | mutex_unlock(&trans_pcie->mutex); |
| 1833 | |
| 1834 | return ret; |
| 1835 | } |
| 1836 | |
| 1837 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
| 1838 | { |
| 1839 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1840 | |
| 1841 | mutex_lock(&trans_pcie->mutex); |
| 1842 | |
| 1843 | /* disable interrupts - don't enable HW RF kill interrupt */ |
| 1844 | iwl_disable_interrupts(trans); |
| 1845 | |
| 1846 | iwl_pcie_apm_stop(trans, true); |
| 1847 | |
| 1848 | iwl_disable_interrupts(trans); |
| 1849 | |
| 1850 | iwl_pcie_disable_ict(trans); |
| 1851 | |
| 1852 | mutex_unlock(&trans_pcie->mutex); |
| 1853 | |
| 1854 | iwl_pcie_synchronize_irqs(trans); |
| 1855 | } |
| 1856 | |
| 1857 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
| 1858 | { |
| 1859 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
| 1860 | } |
| 1861 | |
| 1862 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) |
| 1863 | { |
| 1864 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
| 1865 | } |
| 1866 | |
| 1867 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) |
| 1868 | { |
| 1869 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
| 1870 | } |
| 1871 | |
| 1872 | static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) |
| 1873 | { |
| 1874 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) |
| 1875 | return 0x00FFFFFF; |
| 1876 | else |
| 1877 | return 0x000FFFFF; |
| 1878 | } |
| 1879 | |
| 1880 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
| 1881 | { |
| 1882 | u32 mask = iwl_trans_pcie_prph_msk(trans); |
| 1883 | |
| 1884 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
| 1885 | ((reg & mask) | (3 << 24))); |
| 1886 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
| 1887 | } |
| 1888 | |
| 1889 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, |
| 1890 | u32 val) |
| 1891 | { |
| 1892 | u32 mask = iwl_trans_pcie_prph_msk(trans); |
| 1893 | |
| 1894 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, |
| 1895 | ((addr & mask) | (3 << 24))); |
| 1896 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
| 1897 | } |
| 1898 | |
| 1899 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
| 1900 | const struct iwl_trans_config *trans_cfg) |
| 1901 | { |
| 1902 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1903 | |
| 1904 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; |
| 1905 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
| 1906 | trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; |
| 1907 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
| 1908 | trans_pcie->n_no_reclaim_cmds = 0; |
| 1909 | else |
| 1910 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; |
| 1911 | if (trans_pcie->n_no_reclaim_cmds) |
| 1912 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, |
| 1913 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); |
| 1914 | |
| 1915 | trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; |
| 1916 | trans_pcie->rx_page_order = |
| 1917 | iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); |
| 1918 | |
| 1919 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
| 1920 | trans_pcie->scd_set_active = trans_cfg->scd_set_active; |
| 1921 | trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; |
| 1922 | |
| 1923 | trans_pcie->page_offs = trans_cfg->cb_data_offs; |
| 1924 | trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); |
| 1925 | |
| 1926 | trans->command_groups = trans_cfg->command_groups; |
| 1927 | trans->command_groups_size = trans_cfg->command_groups_size; |
| 1928 | |
| 1929 | /* Initialize NAPI here - it should be before registering to mac80211 |
| 1930 | * in the opmode but after the HW struct is allocated. |
| 1931 | * As this function may be called again in some corner cases don't |
| 1932 | * do anything if NAPI was already initialized. |
| 1933 | */ |
| 1934 | if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) |
| 1935 | init_dummy_netdev(&trans_pcie->napi_dev); |
| 1936 | } |
| 1937 | |
| 1938 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
| 1939 | { |
| 1940 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1941 | int i; |
| 1942 | |
| 1943 | iwl_pcie_synchronize_irqs(trans); |
| 1944 | |
| 1945 | if (trans->trans_cfg->gen2) |
| 1946 | iwl_pcie_gen2_tx_free(trans); |
| 1947 | else |
| 1948 | iwl_pcie_tx_free(trans); |
| 1949 | iwl_pcie_rx_free(trans); |
| 1950 | |
| 1951 | if (trans_pcie->rba.alloc_wq) { |
| 1952 | destroy_workqueue(trans_pcie->rba.alloc_wq); |
| 1953 | trans_pcie->rba.alloc_wq = NULL; |
| 1954 | } |
| 1955 | |
| 1956 | if (trans_pcie->msix_enabled) { |
| 1957 | for (i = 0; i < trans_pcie->alloc_vecs; i++) { |
| 1958 | irq_set_affinity_hint( |
| 1959 | trans_pcie->msix_entries[i].vector, |
| 1960 | NULL); |
| 1961 | } |
| 1962 | |
| 1963 | trans_pcie->msix_enabled = false; |
| 1964 | } else { |
| 1965 | iwl_pcie_free_ict(trans); |
| 1966 | } |
| 1967 | |
| 1968 | iwl_pcie_free_fw_monitor(trans); |
| 1969 | |
| 1970 | for_each_possible_cpu(i) { |
| 1971 | struct iwl_tso_hdr_page *p = |
| 1972 | per_cpu_ptr(trans_pcie->tso_hdr_page, i); |
| 1973 | |
| 1974 | if (p->page) |
| 1975 | __free_page(p->page); |
| 1976 | } |
| 1977 | |
| 1978 | free_percpu(trans_pcie->tso_hdr_page); |
| 1979 | mutex_destroy(&trans_pcie->mutex); |
| 1980 | iwl_trans_free(trans); |
| 1981 | } |
| 1982 | |
| 1983 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
| 1984 | { |
| 1985 | if (state) |
| 1986 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
| 1987 | else |
| 1988 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
| 1989 | } |
| 1990 | |
| 1991 | struct iwl_trans_pcie_removal { |
| 1992 | struct pci_dev *pdev; |
| 1993 | struct work_struct work; |
| 1994 | }; |
| 1995 | |
| 1996 | static void iwl_trans_pcie_removal_wk(struct work_struct *wk) |
| 1997 | { |
| 1998 | struct iwl_trans_pcie_removal *removal = |
| 1999 | container_of(wk, struct iwl_trans_pcie_removal, work); |
| 2000 | struct pci_dev *pdev = removal->pdev; |
| 2001 | static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; |
| 2002 | |
| 2003 | dev_err(&pdev->dev, "Device gone - attempting removal\n"); |
| 2004 | kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); |
| 2005 | pci_lock_rescan_remove(); |
| 2006 | pci_dev_put(pdev); |
| 2007 | pci_stop_and_remove_bus_device(pdev); |
| 2008 | pci_unlock_rescan_remove(); |
| 2009 | |
| 2010 | kfree(removal); |
| 2011 | module_put(THIS_MODULE); |
| 2012 | } |
| 2013 | |
| 2014 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, |
| 2015 | unsigned long *flags) |
| 2016 | { |
| 2017 | int ret; |
| 2018 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2019 | |
| 2020 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); |
| 2021 | |
| 2022 | if (trans_pcie->cmd_hold_nic_awake) |
| 2023 | goto out; |
| 2024 | |
| 2025 | /* this bit wakes up the NIC */ |
| 2026 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
| 2027 | BIT(trans->trans_cfg->csr->flag_mac_access_req)); |
| 2028 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
| 2029 | udelay(2); |
| 2030 | |
| 2031 | /* |
| 2032 | * These bits say the device is running, and should keep running for |
| 2033 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), |
| 2034 | * but they do not indicate that embedded SRAM is restored yet; |
| 2035 | * HW with volatile SRAM must save/restore contents to/from |
| 2036 | * host DRAM when sleeping/waking for power-saving. |
| 2037 | * Each direction takes approximately 1/4 millisecond; with this |
| 2038 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a |
| 2039 | * series of register accesses are expected (e.g. reading Event Log), |
| 2040 | * to keep device from sleeping. |
| 2041 | * |
| 2042 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that |
| 2043 | * SRAM is okay/restored. We don't check that here because this call |
| 2044 | * is just for hardware register access; but GP1 MAC_SLEEP |
| 2045 | * check is a good idea before accessing the SRAM of HW with |
| 2046 | * volatile SRAM (e.g. reading Event Log). |
| 2047 | * |
| 2048 | * 5000 series and later (including 1000 series) have non-volatile SRAM, |
| 2049 | * and do not save/restore SRAM when power cycling. |
| 2050 | */ |
| 2051 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, |
| 2052 | BIT(trans->trans_cfg->csr->flag_val_mac_access_en), |
| 2053 | (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) | |
| 2054 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); |
| 2055 | if (unlikely(ret < 0)) { |
| 2056 | u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); |
| 2057 | |
| 2058 | WARN_ONCE(1, |
| 2059 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", |
| 2060 | cntrl); |
| 2061 | |
| 2062 | iwl_trans_pcie_dump_regs(trans); |
| 2063 | |
| 2064 | if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { |
| 2065 | struct iwl_trans_pcie_removal *removal; |
| 2066 | |
| 2067 | if (test_bit(STATUS_TRANS_DEAD, &trans->status)) |
| 2068 | goto err; |
| 2069 | |
| 2070 | IWL_ERR(trans, "Device gone - scheduling removal!\n"); |
| 2071 | |
| 2072 | /* |
| 2073 | * get a module reference to avoid doing this |
| 2074 | * while unloading anyway and to avoid |
| 2075 | * scheduling a work with code that's being |
| 2076 | * removed. |
| 2077 | */ |
| 2078 | if (!try_module_get(THIS_MODULE)) { |
| 2079 | IWL_ERR(trans, |
| 2080 | "Module is being unloaded - abort\n"); |
| 2081 | goto err; |
| 2082 | } |
| 2083 | |
| 2084 | removal = kzalloc(sizeof(*removal), GFP_ATOMIC); |
| 2085 | if (!removal) { |
| 2086 | module_put(THIS_MODULE); |
| 2087 | goto err; |
| 2088 | } |
| 2089 | /* |
| 2090 | * we don't need to clear this flag, because |
| 2091 | * the trans will be freed and reallocated. |
| 2092 | */ |
| 2093 | set_bit(STATUS_TRANS_DEAD, &trans->status); |
| 2094 | |
| 2095 | removal->pdev = to_pci_dev(trans->dev); |
| 2096 | INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); |
| 2097 | pci_dev_get(removal->pdev); |
| 2098 | schedule_work(&removal->work); |
| 2099 | } else { |
| 2100 | iwl_write32(trans, CSR_RESET, |
| 2101 | CSR_RESET_REG_FLAG_FORCE_NMI); |
| 2102 | } |
| 2103 | |
| 2104 | err: |
| 2105 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
| 2106 | return false; |
| 2107 | } |
| 2108 | |
| 2109 | out: |
| 2110 | /* |
| 2111 | * Fool sparse by faking we release the lock - sparse will |
| 2112 | * track nic_access anyway. |
| 2113 | */ |
| 2114 | __release(&trans_pcie->reg_lock); |
| 2115 | return true; |
| 2116 | } |
| 2117 | |
| 2118 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
| 2119 | unsigned long *flags) |
| 2120 | { |
| 2121 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2122 | |
| 2123 | lockdep_assert_held(&trans_pcie->reg_lock); |
| 2124 | |
| 2125 | /* |
| 2126 | * Fool sparse by faking we acquiring the lock - sparse will |
| 2127 | * track nic_access anyway. |
| 2128 | */ |
| 2129 | __acquire(&trans_pcie->reg_lock); |
| 2130 | |
| 2131 | if (trans_pcie->cmd_hold_nic_awake) |
| 2132 | goto out; |
| 2133 | |
| 2134 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
| 2135 | BIT(trans->trans_cfg->csr->flag_mac_access_req)); |
| 2136 | /* |
| 2137 | * Above we read the CSR_GP_CNTRL register, which will flush |
| 2138 | * any previous writes, but we need the write that clears the |
| 2139 | * MAC_ACCESS_REQ bit to be performed before any other writes |
| 2140 | * scheduled on different CPUs (after we drop reg_lock). |
| 2141 | */ |
| 2142 | out: |
| 2143 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
| 2144 | } |
| 2145 | |
| 2146 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
| 2147 | void *buf, int dwords) |
| 2148 | { |
| 2149 | unsigned long flags; |
| 2150 | int offs, ret = 0; |
| 2151 | u32 *vals = buf; |
| 2152 | |
| 2153 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
| 2154 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
| 2155 | for (offs = 0; offs < dwords; offs++) |
| 2156 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); |
| 2157 | iwl_trans_release_nic_access(trans, &flags); |
| 2158 | } else { |
| 2159 | ret = -EBUSY; |
| 2160 | } |
| 2161 | return ret; |
| 2162 | } |
| 2163 | |
| 2164 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, |
| 2165 | const void *buf, int dwords) |
| 2166 | { |
| 2167 | unsigned long flags; |
| 2168 | int offs, ret = 0; |
| 2169 | const u32 *vals = buf; |
| 2170 | |
| 2171 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
| 2172 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
| 2173 | for (offs = 0; offs < dwords; offs++) |
| 2174 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
| 2175 | vals ? vals[offs] : 0); |
| 2176 | iwl_trans_release_nic_access(trans, &flags); |
| 2177 | } else { |
| 2178 | ret = -EBUSY; |
| 2179 | } |
| 2180 | return ret; |
| 2181 | } |
| 2182 | |
| 2183 | static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, |
| 2184 | unsigned long txqs, |
| 2185 | bool freeze) |
| 2186 | { |
| 2187 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2188 | int queue; |
| 2189 | |
| 2190 | for_each_set_bit(queue, &txqs, BITS_PER_LONG) { |
| 2191 | struct iwl_txq *txq = trans_pcie->txq[queue]; |
| 2192 | unsigned long now; |
| 2193 | |
| 2194 | spin_lock_bh(&txq->lock); |
| 2195 | |
| 2196 | now = jiffies; |
| 2197 | |
| 2198 | if (txq->frozen == freeze) |
| 2199 | goto next_queue; |
| 2200 | |
| 2201 | IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", |
| 2202 | freeze ? "Freezing" : "Waking", queue); |
| 2203 | |
| 2204 | txq->frozen = freeze; |
| 2205 | |
| 2206 | if (txq->read_ptr == txq->write_ptr) |
| 2207 | goto next_queue; |
| 2208 | |
| 2209 | if (freeze) { |
| 2210 | if (unlikely(time_after(now, |
| 2211 | txq->stuck_timer.expires))) { |
| 2212 | /* |
| 2213 | * The timer should have fired, maybe it is |
| 2214 | * spinning right now on the lock. |
| 2215 | */ |
| 2216 | goto next_queue; |
| 2217 | } |
| 2218 | /* remember how long until the timer fires */ |
| 2219 | txq->frozen_expiry_remainder = |
| 2220 | txq->stuck_timer.expires - now; |
| 2221 | del_timer(&txq->stuck_timer); |
| 2222 | goto next_queue; |
| 2223 | } |
| 2224 | |
| 2225 | /* |
| 2226 | * Wake a non-empty queue -> arm timer with the |
| 2227 | * remainder before it froze |
| 2228 | */ |
| 2229 | mod_timer(&txq->stuck_timer, |
| 2230 | now + txq->frozen_expiry_remainder); |
| 2231 | |
| 2232 | next_queue: |
| 2233 | spin_unlock_bh(&txq->lock); |
| 2234 | } |
| 2235 | } |
| 2236 | |
| 2237 | static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) |
| 2238 | { |
| 2239 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2240 | int i; |
| 2241 | |
| 2242 | for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { |
| 2243 | struct iwl_txq *txq = trans_pcie->txq[i]; |
| 2244 | |
| 2245 | if (i == trans_pcie->cmd_queue) |
| 2246 | continue; |
| 2247 | |
| 2248 | spin_lock_bh(&txq->lock); |
| 2249 | |
| 2250 | if (!block && !(WARN_ON_ONCE(!txq->block))) { |
| 2251 | txq->block--; |
| 2252 | if (!txq->block) { |
| 2253 | iwl_write32(trans, HBUS_TARG_WRPTR, |
| 2254 | txq->write_ptr | (i << 8)); |
| 2255 | } |
| 2256 | } else if (block) { |
| 2257 | txq->block++; |
| 2258 | } |
| 2259 | |
| 2260 | spin_unlock_bh(&txq->lock); |
| 2261 | } |
| 2262 | } |
| 2263 | |
| 2264 | #define IWL_FLUSH_WAIT_MS 2000 |
| 2265 | |
| 2266 | void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) |
| 2267 | { |
| 2268 | u32 txq_id = txq->id; |
| 2269 | u32 status; |
| 2270 | bool active; |
| 2271 | u8 fifo; |
| 2272 | |
| 2273 | if (trans->trans_cfg->use_tfh) { |
| 2274 | IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, |
| 2275 | txq->read_ptr, txq->write_ptr); |
| 2276 | /* TODO: access new SCD registers and dump them */ |
| 2277 | return; |
| 2278 | } |
| 2279 | |
| 2280 | status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); |
| 2281 | fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; |
| 2282 | active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); |
| 2283 | |
| 2284 | IWL_ERR(trans, |
| 2285 | "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", |
| 2286 | txq_id, active ? "" : "in", fifo, |
| 2287 | jiffies_to_msecs(txq->wd_timeout), |
| 2288 | txq->read_ptr, txq->write_ptr, |
| 2289 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & |
| 2290 | (trans->trans_cfg->base_params->max_tfd_queue_size - 1), |
| 2291 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & |
| 2292 | (trans->trans_cfg->base_params->max_tfd_queue_size - 1), |
| 2293 | iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); |
| 2294 | } |
| 2295 | |
| 2296 | static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, |
| 2297 | struct iwl_trans_rxq_dma_data *data) |
| 2298 | { |
| 2299 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2300 | |
| 2301 | if (queue >= trans->num_rx_queues || !trans_pcie->rxq) |
| 2302 | return -EINVAL; |
| 2303 | |
| 2304 | data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; |
| 2305 | data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; |
| 2306 | data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; |
| 2307 | data->fr_bd_wid = 0; |
| 2308 | |
| 2309 | return 0; |
| 2310 | } |
| 2311 | |
| 2312 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) |
| 2313 | { |
| 2314 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2315 | struct iwl_txq *txq; |
| 2316 | unsigned long now = jiffies; |
| 2317 | bool overflow_tx; |
| 2318 | u8 wr_ptr; |
| 2319 | |
| 2320 | /* Make sure the NIC is still alive in the bus */ |
| 2321 | if (test_bit(STATUS_TRANS_DEAD, &trans->status)) |
| 2322 | return -ENODEV; |
| 2323 | |
| 2324 | if (!test_bit(txq_idx, trans_pcie->queue_used)) |
| 2325 | return -EINVAL; |
| 2326 | |
| 2327 | IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); |
| 2328 | txq = trans_pcie->txq[txq_idx]; |
| 2329 | |
| 2330 | spin_lock_bh(&txq->lock); |
| 2331 | overflow_tx = txq->overflow_tx || |
| 2332 | !skb_queue_empty(&txq->overflow_q); |
| 2333 | spin_unlock_bh(&txq->lock); |
| 2334 | |
| 2335 | wr_ptr = READ_ONCE(txq->write_ptr); |
| 2336 | |
| 2337 | while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || |
| 2338 | overflow_tx) && |
| 2339 | !time_after(jiffies, |
| 2340 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { |
| 2341 | u8 write_ptr = READ_ONCE(txq->write_ptr); |
| 2342 | |
| 2343 | /* |
| 2344 | * If write pointer moved during the wait, warn only |
| 2345 | * if the TX came from op mode. In case TX came from |
| 2346 | * trans layer (overflow TX) don't warn. |
| 2347 | */ |
| 2348 | if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, |
| 2349 | "WR pointer moved while flushing %d -> %d\n", |
| 2350 | wr_ptr, write_ptr)) |
| 2351 | return -ETIMEDOUT; |
| 2352 | wr_ptr = write_ptr; |
| 2353 | |
| 2354 | usleep_range(1000, 2000); |
| 2355 | |
| 2356 | spin_lock_bh(&txq->lock); |
| 2357 | overflow_tx = txq->overflow_tx || |
| 2358 | !skb_queue_empty(&txq->overflow_q); |
| 2359 | spin_unlock_bh(&txq->lock); |
| 2360 | } |
| 2361 | |
| 2362 | if (txq->read_ptr != txq->write_ptr) { |
| 2363 | IWL_ERR(trans, |
| 2364 | "fail to flush all tx fifo queues Q %d\n", txq_idx); |
| 2365 | iwl_trans_pcie_log_scd_error(trans, txq); |
| 2366 | return -ETIMEDOUT; |
| 2367 | } |
| 2368 | |
| 2369 | IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); |
| 2370 | |
| 2371 | return 0; |
| 2372 | } |
| 2373 | |
| 2374 | static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) |
| 2375 | { |
| 2376 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2377 | int cnt; |
| 2378 | int ret = 0; |
| 2379 | |
| 2380 | /* waiting for all the tx frames complete might take a while */ |
| 2381 | for (cnt = 0; |
| 2382 | cnt < trans->trans_cfg->base_params->num_of_queues; |
| 2383 | cnt++) { |
| 2384 | |
| 2385 | if (cnt == trans_pcie->cmd_queue) |
| 2386 | continue; |
| 2387 | if (!test_bit(cnt, trans_pcie->queue_used)) |
| 2388 | continue; |
| 2389 | if (!(BIT(cnt) & txq_bm)) |
| 2390 | continue; |
| 2391 | |
| 2392 | ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); |
| 2393 | if (ret) |
| 2394 | break; |
| 2395 | } |
| 2396 | |
| 2397 | return ret; |
| 2398 | } |
| 2399 | |
| 2400 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
| 2401 | u32 mask, u32 value) |
| 2402 | { |
| 2403 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2404 | unsigned long flags; |
| 2405 | |
| 2406 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
| 2407 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
| 2408 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
| 2409 | } |
| 2410 | |
| 2411 | static const char *get_csr_string(int cmd) |
| 2412 | { |
| 2413 | #define IWL_CMD(x) case x: return #x |
| 2414 | switch (cmd) { |
| 2415 | IWL_CMD(CSR_HW_IF_CONFIG_REG); |
| 2416 | IWL_CMD(CSR_INT_COALESCING); |
| 2417 | IWL_CMD(CSR_INT); |
| 2418 | IWL_CMD(CSR_INT_MASK); |
| 2419 | IWL_CMD(CSR_FH_INT_STATUS); |
| 2420 | IWL_CMD(CSR_GPIO_IN); |
| 2421 | IWL_CMD(CSR_RESET); |
| 2422 | IWL_CMD(CSR_GP_CNTRL); |
| 2423 | IWL_CMD(CSR_HW_REV); |
| 2424 | IWL_CMD(CSR_EEPROM_REG); |
| 2425 | IWL_CMD(CSR_EEPROM_GP); |
| 2426 | IWL_CMD(CSR_OTP_GP_REG); |
| 2427 | IWL_CMD(CSR_GIO_REG); |
| 2428 | IWL_CMD(CSR_GP_UCODE_REG); |
| 2429 | IWL_CMD(CSR_GP_DRIVER_REG); |
| 2430 | IWL_CMD(CSR_UCODE_DRV_GP1); |
| 2431 | IWL_CMD(CSR_UCODE_DRV_GP2); |
| 2432 | IWL_CMD(CSR_LED_REG); |
| 2433 | IWL_CMD(CSR_DRAM_INT_TBL_REG); |
| 2434 | IWL_CMD(CSR_GIO_CHICKEN_BITS); |
| 2435 | IWL_CMD(CSR_ANA_PLL_CFG); |
| 2436 | IWL_CMD(CSR_HW_REV_WA_REG); |
| 2437 | IWL_CMD(CSR_MONITOR_STATUS_REG); |
| 2438 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
| 2439 | default: |
| 2440 | return "UNKNOWN"; |
| 2441 | } |
| 2442 | #undef IWL_CMD |
| 2443 | } |
| 2444 | |
| 2445 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
| 2446 | { |
| 2447 | int i; |
| 2448 | static const u32 csr_tbl[] = { |
| 2449 | CSR_HW_IF_CONFIG_REG, |
| 2450 | CSR_INT_COALESCING, |
| 2451 | CSR_INT, |
| 2452 | CSR_INT_MASK, |
| 2453 | CSR_FH_INT_STATUS, |
| 2454 | CSR_GPIO_IN, |
| 2455 | CSR_RESET, |
| 2456 | CSR_GP_CNTRL, |
| 2457 | CSR_HW_REV, |
| 2458 | CSR_EEPROM_REG, |
| 2459 | CSR_EEPROM_GP, |
| 2460 | CSR_OTP_GP_REG, |
| 2461 | CSR_GIO_REG, |
| 2462 | CSR_GP_UCODE_REG, |
| 2463 | CSR_GP_DRIVER_REG, |
| 2464 | CSR_UCODE_DRV_GP1, |
| 2465 | CSR_UCODE_DRV_GP2, |
| 2466 | CSR_LED_REG, |
| 2467 | CSR_DRAM_INT_TBL_REG, |
| 2468 | CSR_GIO_CHICKEN_BITS, |
| 2469 | CSR_ANA_PLL_CFG, |
| 2470 | CSR_MONITOR_STATUS_REG, |
| 2471 | CSR_HW_REV_WA_REG, |
| 2472 | CSR_DBG_HPET_MEM_REG |
| 2473 | }; |
| 2474 | IWL_ERR(trans, "CSR values:\n"); |
| 2475 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " |
| 2476 | "CSR_INT_PERIODIC_REG)\n"); |
| 2477 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { |
| 2478 | IWL_ERR(trans, " %25s: 0X%08x\n", |
| 2479 | get_csr_string(csr_tbl[i]), |
| 2480 | iwl_read32(trans, csr_tbl[i])); |
| 2481 | } |
| 2482 | } |
| 2483 | |
| 2484 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 2485 | /* create and remove of files */ |
| 2486 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ |
| 2487 | debugfs_create_file(#name, mode, parent, trans, \ |
| 2488 | &iwl_dbgfs_##name##_ops); \ |
| 2489 | } while (0) |
| 2490 | |
| 2491 | /* file operation */ |
| 2492 | #define DEBUGFS_READ_FILE_OPS(name) \ |
| 2493 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
| 2494 | .read = iwl_dbgfs_##name##_read, \ |
| 2495 | .open = simple_open, \ |
| 2496 | .llseek = generic_file_llseek, \ |
| 2497 | }; |
| 2498 | |
| 2499 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
| 2500 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
| 2501 | .write = iwl_dbgfs_##name##_write, \ |
| 2502 | .open = simple_open, \ |
| 2503 | .llseek = generic_file_llseek, \ |
| 2504 | }; |
| 2505 | |
| 2506 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
| 2507 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
| 2508 | .write = iwl_dbgfs_##name##_write, \ |
| 2509 | .read = iwl_dbgfs_##name##_read, \ |
| 2510 | .open = simple_open, \ |
| 2511 | .llseek = generic_file_llseek, \ |
| 2512 | }; |
| 2513 | |
| 2514 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
| 2515 | char __user *user_buf, |
| 2516 | size_t count, loff_t *ppos) |
| 2517 | { |
| 2518 | struct iwl_trans *trans = file->private_data; |
| 2519 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2520 | struct iwl_txq *txq; |
| 2521 | char *buf; |
| 2522 | int pos = 0; |
| 2523 | int cnt; |
| 2524 | int ret; |
| 2525 | size_t bufsz; |
| 2526 | |
| 2527 | bufsz = sizeof(char) * 75 * |
| 2528 | trans->trans_cfg->base_params->num_of_queues; |
| 2529 | |
| 2530 | if (!trans_pcie->txq_memory) |
| 2531 | return -EAGAIN; |
| 2532 | |
| 2533 | buf = kzalloc(bufsz, GFP_KERNEL); |
| 2534 | if (!buf) |
| 2535 | return -ENOMEM; |
| 2536 | |
| 2537 | for (cnt = 0; |
| 2538 | cnt < trans->trans_cfg->base_params->num_of_queues; |
| 2539 | cnt++) { |
| 2540 | txq = trans_pcie->txq[cnt]; |
| 2541 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2542 | "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", |
| 2543 | cnt, txq->read_ptr, txq->write_ptr, |
| 2544 | !!test_bit(cnt, trans_pcie->queue_used), |
| 2545 | !!test_bit(cnt, trans_pcie->queue_stopped), |
| 2546 | txq->need_update, txq->frozen, |
| 2547 | (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); |
| 2548 | } |
| 2549 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 2550 | kfree(buf); |
| 2551 | return ret; |
| 2552 | } |
| 2553 | |
| 2554 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, |
| 2555 | char __user *user_buf, |
| 2556 | size_t count, loff_t *ppos) |
| 2557 | { |
| 2558 | struct iwl_trans *trans = file->private_data; |
| 2559 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2560 | char *buf; |
| 2561 | int pos = 0, i, ret; |
| 2562 | size_t bufsz; |
| 2563 | |
| 2564 | bufsz = sizeof(char) * 121 * trans->num_rx_queues; |
| 2565 | |
| 2566 | if (!trans_pcie->rxq) |
| 2567 | return -EAGAIN; |
| 2568 | |
| 2569 | buf = kzalloc(bufsz, GFP_KERNEL); |
| 2570 | if (!buf) |
| 2571 | return -ENOMEM; |
| 2572 | |
| 2573 | for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { |
| 2574 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; |
| 2575 | |
| 2576 | pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", |
| 2577 | i); |
| 2578 | pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", |
| 2579 | rxq->read); |
| 2580 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", |
| 2581 | rxq->write); |
| 2582 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", |
| 2583 | rxq->write_actual); |
| 2584 | pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", |
| 2585 | rxq->need_update); |
| 2586 | pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", |
| 2587 | rxq->free_count); |
| 2588 | if (rxq->rb_stts) { |
| 2589 | u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, |
| 2590 | rxq)); |
| 2591 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2592 | "\tclosed_rb_num: %u\n", |
| 2593 | r & 0x0FFF); |
| 2594 | } else { |
| 2595 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2596 | "\tclosed_rb_num: Not Allocated\n"); |
| 2597 | } |
| 2598 | } |
| 2599 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 2600 | kfree(buf); |
| 2601 | |
| 2602 | return ret; |
| 2603 | } |
| 2604 | |
| 2605 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
| 2606 | char __user *user_buf, |
| 2607 | size_t count, loff_t *ppos) |
| 2608 | { |
| 2609 | struct iwl_trans *trans = file->private_data; |
| 2610 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2611 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
| 2612 | |
| 2613 | int pos = 0; |
| 2614 | char *buf; |
| 2615 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ |
| 2616 | ssize_t ret; |
| 2617 | |
| 2618 | buf = kzalloc(bufsz, GFP_KERNEL); |
| 2619 | if (!buf) |
| 2620 | return -ENOMEM; |
| 2621 | |
| 2622 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2623 | "Interrupt Statistics Report:\n"); |
| 2624 | |
| 2625 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", |
| 2626 | isr_stats->hw); |
| 2627 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", |
| 2628 | isr_stats->sw); |
| 2629 | if (isr_stats->sw || isr_stats->hw) { |
| 2630 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2631 | "\tLast Restarting Code: 0x%X\n", |
| 2632 | isr_stats->err_code); |
| 2633 | } |
| 2634 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 2635 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", |
| 2636 | isr_stats->sch); |
| 2637 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", |
| 2638 | isr_stats->alive); |
| 2639 | #endif |
| 2640 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2641 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); |
| 2642 | |
| 2643 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", |
| 2644 | isr_stats->ctkill); |
| 2645 | |
| 2646 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", |
| 2647 | isr_stats->wakeup); |
| 2648 | |
| 2649 | pos += scnprintf(buf + pos, bufsz - pos, |
| 2650 | "Rx command responses:\t\t %u\n", isr_stats->rx); |
| 2651 | |
| 2652 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", |
| 2653 | isr_stats->tx); |
| 2654 | |
| 2655 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", |
| 2656 | isr_stats->unhandled); |
| 2657 | |
| 2658 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 2659 | kfree(buf); |
| 2660 | return ret; |
| 2661 | } |
| 2662 | |
| 2663 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, |
| 2664 | const char __user *user_buf, |
| 2665 | size_t count, loff_t *ppos) |
| 2666 | { |
| 2667 | struct iwl_trans *trans = file->private_data; |
| 2668 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2669 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
| 2670 | u32 reset_flag; |
| 2671 | int ret; |
| 2672 | |
| 2673 | ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); |
| 2674 | if (ret) |
| 2675 | return ret; |
| 2676 | if (reset_flag == 0) |
| 2677 | memset(isr_stats, 0, sizeof(*isr_stats)); |
| 2678 | |
| 2679 | return count; |
| 2680 | } |
| 2681 | |
| 2682 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
| 2683 | const char __user *user_buf, |
| 2684 | size_t count, loff_t *ppos) |
| 2685 | { |
| 2686 | struct iwl_trans *trans = file->private_data; |
| 2687 | |
| 2688 | iwl_pcie_dump_csr(trans); |
| 2689 | |
| 2690 | return count; |
| 2691 | } |
| 2692 | |
| 2693 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
| 2694 | char __user *user_buf, |
| 2695 | size_t count, loff_t *ppos) |
| 2696 | { |
| 2697 | struct iwl_trans *trans = file->private_data; |
| 2698 | char *buf = NULL; |
| 2699 | ssize_t ret; |
| 2700 | |
| 2701 | ret = iwl_dump_fh(trans, &buf); |
| 2702 | if (ret < 0) |
| 2703 | return ret; |
| 2704 | if (!buf) |
| 2705 | return -EINVAL; |
| 2706 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); |
| 2707 | kfree(buf); |
| 2708 | return ret; |
| 2709 | } |
| 2710 | |
| 2711 | static ssize_t iwl_dbgfs_rfkill_read(struct file *file, |
| 2712 | char __user *user_buf, |
| 2713 | size_t count, loff_t *ppos) |
| 2714 | { |
| 2715 | struct iwl_trans *trans = file->private_data; |
| 2716 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2717 | char buf[100]; |
| 2718 | int pos; |
| 2719 | |
| 2720 | pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", |
| 2721 | trans_pcie->debug_rfkill, |
| 2722 | !(iwl_read32(trans, CSR_GP_CNTRL) & |
| 2723 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); |
| 2724 | |
| 2725 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 2726 | } |
| 2727 | |
| 2728 | static ssize_t iwl_dbgfs_rfkill_write(struct file *file, |
| 2729 | const char __user *user_buf, |
| 2730 | size_t count, loff_t *ppos) |
| 2731 | { |
| 2732 | struct iwl_trans *trans = file->private_data; |
| 2733 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2734 | bool new_value; |
| 2735 | int ret; |
| 2736 | |
| 2737 | ret = kstrtobool_from_user(user_buf, count, &new_value); |
| 2738 | if (ret) |
| 2739 | return ret; |
| 2740 | if (new_value == trans_pcie->debug_rfkill) |
| 2741 | return count; |
| 2742 | IWL_WARN(trans, "changing debug rfkill %d->%d\n", |
| 2743 | trans_pcie->debug_rfkill, new_value); |
| 2744 | trans_pcie->debug_rfkill = new_value; |
| 2745 | iwl_pcie_handle_rfkill_irq(trans); |
| 2746 | |
| 2747 | return count; |
| 2748 | } |
| 2749 | |
| 2750 | static int iwl_dbgfs_monitor_data_open(struct inode *inode, |
| 2751 | struct file *file) |
| 2752 | { |
| 2753 | struct iwl_trans *trans = inode->i_private; |
| 2754 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2755 | |
| 2756 | if (!trans->dbg.dest_tlv || |
| 2757 | trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { |
| 2758 | IWL_ERR(trans, "Debug destination is not set to DRAM\n"); |
| 2759 | return -ENOENT; |
| 2760 | } |
| 2761 | |
| 2762 | if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) |
| 2763 | return -EBUSY; |
| 2764 | |
| 2765 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; |
| 2766 | return simple_open(inode, file); |
| 2767 | } |
| 2768 | |
| 2769 | static int iwl_dbgfs_monitor_data_release(struct inode *inode, |
| 2770 | struct file *file) |
| 2771 | { |
| 2772 | struct iwl_trans_pcie *trans_pcie = |
| 2773 | IWL_TRANS_GET_PCIE_TRANS(inode->i_private); |
| 2774 | |
| 2775 | if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) |
| 2776 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; |
| 2777 | return 0; |
| 2778 | } |
| 2779 | |
| 2780 | static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, |
| 2781 | void *buf, ssize_t *size, |
| 2782 | ssize_t *bytes_copied) |
| 2783 | { |
| 2784 | int buf_size_left = count - *bytes_copied; |
| 2785 | |
| 2786 | buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); |
| 2787 | if (*size > buf_size_left) |
| 2788 | *size = buf_size_left; |
| 2789 | |
| 2790 | *size -= copy_to_user(user_buf, buf, *size); |
| 2791 | *bytes_copied += *size; |
| 2792 | |
| 2793 | if (buf_size_left == *size) |
| 2794 | return true; |
| 2795 | return false; |
| 2796 | } |
| 2797 | |
| 2798 | static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, |
| 2799 | char __user *user_buf, |
| 2800 | size_t count, loff_t *ppos) |
| 2801 | { |
| 2802 | struct iwl_trans *trans = file->private_data; |
| 2803 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2804 | void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; |
| 2805 | struct cont_rec *data = &trans_pcie->fw_mon_data; |
| 2806 | u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; |
| 2807 | ssize_t size, bytes_copied = 0; |
| 2808 | bool b_full; |
| 2809 | |
| 2810 | if (trans->dbg.dest_tlv) { |
| 2811 | write_ptr_addr = |
| 2812 | le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); |
| 2813 | wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); |
| 2814 | } else { |
| 2815 | write_ptr_addr = MON_BUFF_WRPTR; |
| 2816 | wrap_cnt_addr = MON_BUFF_CYCLE_CNT; |
| 2817 | } |
| 2818 | |
| 2819 | if (unlikely(!trans->dbg.rec_on)) |
| 2820 | return 0; |
| 2821 | |
| 2822 | mutex_lock(&data->mutex); |
| 2823 | if (data->state == |
| 2824 | IWL_FW_MON_DBGFS_STATE_DISABLED) { |
| 2825 | mutex_unlock(&data->mutex); |
| 2826 | return 0; |
| 2827 | } |
| 2828 | |
| 2829 | /* write_ptr position in bytes rather then DW */ |
| 2830 | write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); |
| 2831 | wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); |
| 2832 | |
| 2833 | if (data->prev_wrap_cnt == wrap_cnt) { |
| 2834 | size = write_ptr - data->prev_wr_ptr; |
| 2835 | curr_buf = cpu_addr + data->prev_wr_ptr; |
| 2836 | b_full = iwl_write_to_user_buf(user_buf, count, |
| 2837 | curr_buf, &size, |
| 2838 | &bytes_copied); |
| 2839 | data->prev_wr_ptr += size; |
| 2840 | |
| 2841 | } else if (data->prev_wrap_cnt == wrap_cnt - 1 && |
| 2842 | write_ptr < data->prev_wr_ptr) { |
| 2843 | size = trans->dbg.fw_mon.size - data->prev_wr_ptr; |
| 2844 | curr_buf = cpu_addr + data->prev_wr_ptr; |
| 2845 | b_full = iwl_write_to_user_buf(user_buf, count, |
| 2846 | curr_buf, &size, |
| 2847 | &bytes_copied); |
| 2848 | data->prev_wr_ptr += size; |
| 2849 | |
| 2850 | if (!b_full) { |
| 2851 | size = write_ptr; |
| 2852 | b_full = iwl_write_to_user_buf(user_buf, count, |
| 2853 | cpu_addr, &size, |
| 2854 | &bytes_copied); |
| 2855 | data->prev_wr_ptr = size; |
| 2856 | data->prev_wrap_cnt++; |
| 2857 | } |
| 2858 | } else { |
| 2859 | if (data->prev_wrap_cnt == wrap_cnt - 1 && |
| 2860 | write_ptr > data->prev_wr_ptr) |
| 2861 | IWL_WARN(trans, |
| 2862 | "write pointer passed previous write pointer, start copying from the beginning\n"); |
| 2863 | else if (!unlikely(data->prev_wrap_cnt == 0 && |
| 2864 | data->prev_wr_ptr == 0)) |
| 2865 | IWL_WARN(trans, |
| 2866 | "monitor data is out of sync, start copying from the beginning\n"); |
| 2867 | |
| 2868 | size = write_ptr; |
| 2869 | b_full = iwl_write_to_user_buf(user_buf, count, |
| 2870 | cpu_addr, &size, |
| 2871 | &bytes_copied); |
| 2872 | data->prev_wr_ptr = size; |
| 2873 | data->prev_wrap_cnt = wrap_cnt; |
| 2874 | } |
| 2875 | |
| 2876 | mutex_unlock(&data->mutex); |
| 2877 | |
| 2878 | return bytes_copied; |
| 2879 | } |
| 2880 | |
| 2881 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
| 2882 | DEBUGFS_READ_FILE_OPS(fh_reg); |
| 2883 | DEBUGFS_READ_FILE_OPS(rx_queue); |
| 2884 | DEBUGFS_READ_FILE_OPS(tx_queue); |
| 2885 | DEBUGFS_WRITE_FILE_OPS(csr); |
| 2886 | DEBUGFS_READ_WRITE_FILE_OPS(rfkill); |
| 2887 | |
| 2888 | static const struct file_operations iwl_dbgfs_monitor_data_ops = { |
| 2889 | .read = iwl_dbgfs_monitor_data_read, |
| 2890 | .open = iwl_dbgfs_monitor_data_open, |
| 2891 | .release = iwl_dbgfs_monitor_data_release, |
| 2892 | }; |
| 2893 | |
| 2894 | /* Create the debugfs files and directories */ |
| 2895 | void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) |
| 2896 | { |
| 2897 | struct dentry *dir = trans->dbgfs_dir; |
| 2898 | |
| 2899 | DEBUGFS_ADD_FILE(rx_queue, dir, 0400); |
| 2900 | DEBUGFS_ADD_FILE(tx_queue, dir, 0400); |
| 2901 | DEBUGFS_ADD_FILE(interrupt, dir, 0600); |
| 2902 | DEBUGFS_ADD_FILE(csr, dir, 0200); |
| 2903 | DEBUGFS_ADD_FILE(fh_reg, dir, 0400); |
| 2904 | DEBUGFS_ADD_FILE(rfkill, dir, 0600); |
| 2905 | DEBUGFS_ADD_FILE(monitor_data, dir, 0400); |
| 2906 | } |
| 2907 | |
| 2908 | static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) |
| 2909 | { |
| 2910 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2911 | struct cont_rec *data = &trans_pcie->fw_mon_data; |
| 2912 | |
| 2913 | mutex_lock(&data->mutex); |
| 2914 | data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; |
| 2915 | mutex_unlock(&data->mutex); |
| 2916 | } |
| 2917 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
| 2918 | |
| 2919 | static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) |
| 2920 | { |
| 2921 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2922 | u32 cmdlen = 0; |
| 2923 | int i; |
| 2924 | |
| 2925 | for (i = 0; i < trans_pcie->max_tbs; i++) |
| 2926 | cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); |
| 2927 | |
| 2928 | return cmdlen; |
| 2929 | } |
| 2930 | |
| 2931 | static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, |
| 2932 | struct iwl_fw_error_dump_data **data, |
| 2933 | int allocated_rb_nums) |
| 2934 | { |
| 2935 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 2936 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; |
| 2937 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
| 2938 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; |
| 2939 | u32 i, r, j, rb_len = 0; |
| 2940 | |
| 2941 | spin_lock(&rxq->lock); |
| 2942 | |
| 2943 | r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; |
| 2944 | |
| 2945 | for (i = rxq->read, j = 0; |
| 2946 | i != r && j < allocated_rb_nums; |
| 2947 | i = (i + 1) & RX_QUEUE_MASK, j++) { |
| 2948 | struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; |
| 2949 | struct iwl_fw_error_dump_rb *rb; |
| 2950 | |
| 2951 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, |
| 2952 | DMA_FROM_DEVICE); |
| 2953 | |
| 2954 | rb_len += sizeof(**data) + sizeof(*rb) + max_len; |
| 2955 | |
| 2956 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); |
| 2957 | (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); |
| 2958 | rb = (void *)(*data)->data; |
| 2959 | rb->index = cpu_to_le32(i); |
| 2960 | memcpy(rb->data, page_address(rxb->page), max_len); |
| 2961 | /* remap the page for the free benefit */ |
| 2962 | rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, |
| 2963 | max_len, |
| 2964 | DMA_FROM_DEVICE); |
| 2965 | |
| 2966 | *data = iwl_fw_error_next_data(*data); |
| 2967 | } |
| 2968 | |
| 2969 | spin_unlock(&rxq->lock); |
| 2970 | |
| 2971 | return rb_len; |
| 2972 | } |
| 2973 | #define IWL_CSR_TO_DUMP (0x250) |
| 2974 | |
| 2975 | static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, |
| 2976 | struct iwl_fw_error_dump_data **data) |
| 2977 | { |
| 2978 | u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; |
| 2979 | __le32 *val; |
| 2980 | int i; |
| 2981 | |
| 2982 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); |
| 2983 | (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); |
| 2984 | val = (void *)(*data)->data; |
| 2985 | |
| 2986 | for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) |
| 2987 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); |
| 2988 | |
| 2989 | *data = iwl_fw_error_next_data(*data); |
| 2990 | |
| 2991 | return csr_len; |
| 2992 | } |
| 2993 | |
| 2994 | static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, |
| 2995 | struct iwl_fw_error_dump_data **data) |
| 2996 | { |
| 2997 | u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; |
| 2998 | unsigned long flags; |
| 2999 | __le32 *val; |
| 3000 | int i; |
| 3001 | |
| 3002 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
| 3003 | return 0; |
| 3004 | |
| 3005 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); |
| 3006 | (*data)->len = cpu_to_le32(fh_regs_len); |
| 3007 | val = (void *)(*data)->data; |
| 3008 | |
| 3009 | if (!trans->trans_cfg->gen2) |
| 3010 | for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; |
| 3011 | i += sizeof(u32)) |
| 3012 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); |
| 3013 | else |
| 3014 | for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); |
| 3015 | i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); |
| 3016 | i += sizeof(u32)) |
| 3017 | *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, |
| 3018 | i)); |
| 3019 | |
| 3020 | iwl_trans_release_nic_access(trans, &flags); |
| 3021 | |
| 3022 | *data = iwl_fw_error_next_data(*data); |
| 3023 | |
| 3024 | return sizeof(**data) + fh_regs_len; |
| 3025 | } |
| 3026 | |
| 3027 | static u32 |
| 3028 | iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, |
| 3029 | struct iwl_fw_error_dump_fw_mon *fw_mon_data, |
| 3030 | u32 monitor_len) |
| 3031 | { |
| 3032 | u32 buf_size_in_dwords = (monitor_len >> 2); |
| 3033 | u32 *buffer = (u32 *)fw_mon_data->data; |
| 3034 | unsigned long flags; |
| 3035 | u32 i; |
| 3036 | |
| 3037 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
| 3038 | return 0; |
| 3039 | |
| 3040 | iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); |
| 3041 | for (i = 0; i < buf_size_in_dwords; i++) |
| 3042 | buffer[i] = iwl_read_umac_prph_no_grab(trans, |
| 3043 | MON_DMARB_RD_DATA_ADDR); |
| 3044 | iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); |
| 3045 | |
| 3046 | iwl_trans_release_nic_access(trans, &flags); |
| 3047 | |
| 3048 | return monitor_len; |
| 3049 | } |
| 3050 | |
| 3051 | static void |
| 3052 | iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, |
| 3053 | struct iwl_fw_error_dump_fw_mon *fw_mon_data) |
| 3054 | { |
| 3055 | u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; |
| 3056 | |
| 3057 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { |
| 3058 | base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; |
| 3059 | base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; |
| 3060 | write_ptr = DBGC_CUR_DBGBUF_STATUS; |
| 3061 | wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; |
| 3062 | } else if (trans->dbg.dest_tlv) { |
| 3063 | write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); |
| 3064 | wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); |
| 3065 | base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); |
| 3066 | } else { |
| 3067 | base = MON_BUFF_BASE_ADDR; |
| 3068 | write_ptr = MON_BUFF_WRPTR; |
| 3069 | wrap_cnt = MON_BUFF_CYCLE_CNT; |
| 3070 | } |
| 3071 | |
| 3072 | write_ptr_val = iwl_read_prph(trans, write_ptr); |
| 3073 | fw_mon_data->fw_mon_cycle_cnt = |
| 3074 | cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); |
| 3075 | fw_mon_data->fw_mon_base_ptr = |
| 3076 | cpu_to_le32(iwl_read_prph(trans, base)); |
| 3077 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { |
| 3078 | fw_mon_data->fw_mon_base_high_ptr = |
| 3079 | cpu_to_le32(iwl_read_prph(trans, base_high)); |
| 3080 | write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; |
| 3081 | } |
| 3082 | fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); |
| 3083 | } |
| 3084 | |
| 3085 | static u32 |
| 3086 | iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, |
| 3087 | struct iwl_fw_error_dump_data **data, |
| 3088 | u32 monitor_len) |
| 3089 | { |
| 3090 | struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
| 3091 | u32 len = 0; |
| 3092 | |
| 3093 | if (trans->dbg.dest_tlv || |
| 3094 | (fw_mon->size && |
| 3095 | (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || |
| 3096 | trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { |
| 3097 | struct iwl_fw_error_dump_fw_mon *fw_mon_data; |
| 3098 | |
| 3099 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); |
| 3100 | fw_mon_data = (void *)(*data)->data; |
| 3101 | |
| 3102 | iwl_trans_pcie_dump_pointers(trans, fw_mon_data); |
| 3103 | |
| 3104 | len += sizeof(**data) + sizeof(*fw_mon_data); |
| 3105 | if (fw_mon->size) { |
| 3106 | memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); |
| 3107 | monitor_len = fw_mon->size; |
| 3108 | } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { |
| 3109 | u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); |
| 3110 | /* |
| 3111 | * Update pointers to reflect actual values after |
| 3112 | * shifting |
| 3113 | */ |
| 3114 | if (trans->dbg.dest_tlv->version) { |
| 3115 | base = (iwl_read_prph(trans, base) & |
| 3116 | IWL_LDBG_M2S_BUF_BA_MSK) << |
| 3117 | trans->dbg.dest_tlv->base_shift; |
| 3118 | base *= IWL_M2S_UNIT_SIZE; |
| 3119 | base += trans->cfg->smem_offset; |
| 3120 | } else { |
| 3121 | base = iwl_read_prph(trans, base) << |
| 3122 | trans->dbg.dest_tlv->base_shift; |
| 3123 | } |
| 3124 | |
| 3125 | iwl_trans_read_mem(trans, base, fw_mon_data->data, |
| 3126 | monitor_len / sizeof(u32)); |
| 3127 | } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { |
| 3128 | monitor_len = |
| 3129 | iwl_trans_pci_dump_marbh_monitor(trans, |
| 3130 | fw_mon_data, |
| 3131 | monitor_len); |
| 3132 | } else { |
| 3133 | /* Didn't match anything - output no monitor data */ |
| 3134 | monitor_len = 0; |
| 3135 | } |
| 3136 | |
| 3137 | len += monitor_len; |
| 3138 | (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); |
| 3139 | } |
| 3140 | |
| 3141 | return len; |
| 3142 | } |
| 3143 | |
| 3144 | static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) |
| 3145 | { |
| 3146 | if (trans->dbg.fw_mon.size) { |
| 3147 | *len += sizeof(struct iwl_fw_error_dump_data) + |
| 3148 | sizeof(struct iwl_fw_error_dump_fw_mon) + |
| 3149 | trans->dbg.fw_mon.size; |
| 3150 | return trans->dbg.fw_mon.size; |
| 3151 | } else if (trans->dbg.dest_tlv) { |
| 3152 | u32 base, end, cfg_reg, monitor_len; |
| 3153 | |
| 3154 | if (trans->dbg.dest_tlv->version == 1) { |
| 3155 | cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); |
| 3156 | cfg_reg = iwl_read_prph(trans, cfg_reg); |
| 3157 | base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << |
| 3158 | trans->dbg.dest_tlv->base_shift; |
| 3159 | base *= IWL_M2S_UNIT_SIZE; |
| 3160 | base += trans->cfg->smem_offset; |
| 3161 | |
| 3162 | monitor_len = |
| 3163 | (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> |
| 3164 | trans->dbg.dest_tlv->end_shift; |
| 3165 | monitor_len *= IWL_M2S_UNIT_SIZE; |
| 3166 | } else { |
| 3167 | base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); |
| 3168 | end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); |
| 3169 | |
| 3170 | base = iwl_read_prph(trans, base) << |
| 3171 | trans->dbg.dest_tlv->base_shift; |
| 3172 | end = iwl_read_prph(trans, end) << |
| 3173 | trans->dbg.dest_tlv->end_shift; |
| 3174 | |
| 3175 | /* Make "end" point to the actual end */ |
| 3176 | if (trans->trans_cfg->device_family >= |
| 3177 | IWL_DEVICE_FAMILY_8000 || |
| 3178 | trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) |
| 3179 | end += (1 << trans->dbg.dest_tlv->end_shift); |
| 3180 | monitor_len = end - base; |
| 3181 | } |
| 3182 | *len += sizeof(struct iwl_fw_error_dump_data) + |
| 3183 | sizeof(struct iwl_fw_error_dump_fw_mon) + |
| 3184 | monitor_len; |
| 3185 | return monitor_len; |
| 3186 | } |
| 3187 | return 0; |
| 3188 | } |
| 3189 | |
| 3190 | static struct iwl_trans_dump_data |
| 3191 | *iwl_trans_pcie_dump_data(struct iwl_trans *trans, |
| 3192 | u32 dump_mask) |
| 3193 | { |
| 3194 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 3195 | struct iwl_fw_error_dump_data *data; |
| 3196 | struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; |
| 3197 | struct iwl_fw_error_dump_txcmd *txcmd; |
| 3198 | struct iwl_trans_dump_data *dump_data; |
| 3199 | u32 len, num_rbs = 0, monitor_len = 0; |
| 3200 | int i, ptr; |
| 3201 | bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && |
| 3202 | !trans->trans_cfg->mq_rx_supported && |
| 3203 | dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); |
| 3204 | |
| 3205 | if (!dump_mask) |
| 3206 | return NULL; |
| 3207 | |
| 3208 | /* transport dump header */ |
| 3209 | len = sizeof(*dump_data); |
| 3210 | |
| 3211 | /* host commands */ |
| 3212 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) |
| 3213 | len += sizeof(*data) + |
| 3214 | cmdq->n_window * (sizeof(*txcmd) + |
| 3215 | TFD_MAX_PAYLOAD_SIZE); |
| 3216 | |
| 3217 | /* FW monitor */ |
| 3218 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) |
| 3219 | monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); |
| 3220 | |
| 3221 | /* CSR registers */ |
| 3222 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) |
| 3223 | len += sizeof(*data) + IWL_CSR_TO_DUMP; |
| 3224 | |
| 3225 | /* FH registers */ |
| 3226 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { |
| 3227 | if (trans->trans_cfg->gen2) |
| 3228 | len += sizeof(*data) + |
| 3229 | (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - |
| 3230 | iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); |
| 3231 | else |
| 3232 | len += sizeof(*data) + |
| 3233 | (FH_MEM_UPPER_BOUND - |
| 3234 | FH_MEM_LOWER_BOUND); |
| 3235 | } |
| 3236 | |
| 3237 | if (dump_rbs) { |
| 3238 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
| 3239 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; |
| 3240 | /* RBs */ |
| 3241 | num_rbs = |
| 3242 | le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) |
| 3243 | & 0x0FFF; |
| 3244 | num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; |
| 3245 | len += num_rbs * (sizeof(*data) + |
| 3246 | sizeof(struct iwl_fw_error_dump_rb) + |
| 3247 | (PAGE_SIZE << trans_pcie->rx_page_order)); |
| 3248 | } |
| 3249 | |
| 3250 | /* Paged memory for gen2 HW */ |
| 3251 | if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) |
| 3252 | for (i = 0; i < trans->init_dram.paging_cnt; i++) |
| 3253 | len += sizeof(*data) + |
| 3254 | sizeof(struct iwl_fw_error_dump_paging) + |
| 3255 | trans->init_dram.paging[i].size; |
| 3256 | |
| 3257 | dump_data = vzalloc(len); |
| 3258 | if (!dump_data) |
| 3259 | return NULL; |
| 3260 | |
| 3261 | len = 0; |
| 3262 | data = (void *)dump_data->data; |
| 3263 | |
| 3264 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { |
| 3265 | u16 tfd_size = trans_pcie->tfd_size; |
| 3266 | |
| 3267 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); |
| 3268 | txcmd = (void *)data->data; |
| 3269 | spin_lock_bh(&cmdq->lock); |
| 3270 | ptr = cmdq->write_ptr; |
| 3271 | for (i = 0; i < cmdq->n_window; i++) { |
| 3272 | u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); |
| 3273 | u8 tfdidx; |
| 3274 | u32 caplen, cmdlen; |
| 3275 | |
| 3276 | if (trans->trans_cfg->use_tfh) |
| 3277 | tfdidx = idx; |
| 3278 | else |
| 3279 | tfdidx = ptr; |
| 3280 | |
| 3281 | cmdlen = iwl_trans_pcie_get_cmdlen(trans, |
| 3282 | (u8 *)cmdq->tfds + |
| 3283 | tfd_size * tfdidx); |
| 3284 | caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); |
| 3285 | |
| 3286 | if (cmdlen) { |
| 3287 | len += sizeof(*txcmd) + caplen; |
| 3288 | txcmd->cmdlen = cpu_to_le32(cmdlen); |
| 3289 | txcmd->caplen = cpu_to_le32(caplen); |
| 3290 | memcpy(txcmd->data, cmdq->entries[idx].cmd, |
| 3291 | caplen); |
| 3292 | txcmd = (void *)((u8 *)txcmd->data + caplen); |
| 3293 | } |
| 3294 | |
| 3295 | ptr = iwl_queue_dec_wrap(trans, ptr); |
| 3296 | } |
| 3297 | spin_unlock_bh(&cmdq->lock); |
| 3298 | |
| 3299 | data->len = cpu_to_le32(len); |
| 3300 | len += sizeof(*data); |
| 3301 | data = iwl_fw_error_next_data(data); |
| 3302 | } |
| 3303 | |
| 3304 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) |
| 3305 | len += iwl_trans_pcie_dump_csr(trans, &data); |
| 3306 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) |
| 3307 | len += iwl_trans_pcie_fh_regs_dump(trans, &data); |
| 3308 | if (dump_rbs) |
| 3309 | len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); |
| 3310 | |
| 3311 | /* Paged memory for gen2 HW */ |
| 3312 | if (trans->trans_cfg->gen2 && |
| 3313 | dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { |
| 3314 | for (i = 0; i < trans->init_dram.paging_cnt; i++) { |
| 3315 | struct iwl_fw_error_dump_paging *paging; |
| 3316 | u32 page_len = trans->init_dram.paging[i].size; |
| 3317 | |
| 3318 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); |
| 3319 | data->len = cpu_to_le32(sizeof(*paging) + page_len); |
| 3320 | paging = (void *)data->data; |
| 3321 | paging->index = cpu_to_le32(i); |
| 3322 | memcpy(paging->data, |
| 3323 | trans->init_dram.paging[i].block, page_len); |
| 3324 | data = iwl_fw_error_next_data(data); |
| 3325 | |
| 3326 | len += sizeof(*data) + sizeof(*paging) + page_len; |
| 3327 | } |
| 3328 | } |
| 3329 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) |
| 3330 | len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); |
| 3331 | |
| 3332 | dump_data->len = len; |
| 3333 | |
| 3334 | return dump_data; |
| 3335 | } |
| 3336 | |
| 3337 | #ifdef CONFIG_PM_SLEEP |
| 3338 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
| 3339 | { |
| 3340 | return 0; |
| 3341 | } |
| 3342 | |
| 3343 | static void iwl_trans_pcie_resume(struct iwl_trans *trans) |
| 3344 | { |
| 3345 | } |
| 3346 | #endif /* CONFIG_PM_SLEEP */ |
| 3347 | |
| 3348 | #define IWL_TRANS_COMMON_OPS \ |
| 3349 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ |
| 3350 | .write8 = iwl_trans_pcie_write8, \ |
| 3351 | .write32 = iwl_trans_pcie_write32, \ |
| 3352 | .read32 = iwl_trans_pcie_read32, \ |
| 3353 | .read_prph = iwl_trans_pcie_read_prph, \ |
| 3354 | .write_prph = iwl_trans_pcie_write_prph, \ |
| 3355 | .read_mem = iwl_trans_pcie_read_mem, \ |
| 3356 | .write_mem = iwl_trans_pcie_write_mem, \ |
| 3357 | .configure = iwl_trans_pcie_configure, \ |
| 3358 | .set_pmi = iwl_trans_pcie_set_pmi, \ |
| 3359 | .sw_reset = iwl_trans_pcie_sw_reset, \ |
| 3360 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ |
| 3361 | .release_nic_access = iwl_trans_pcie_release_nic_access, \ |
| 3362 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ |
| 3363 | .dump_data = iwl_trans_pcie_dump_data, \ |
| 3364 | .d3_suspend = iwl_trans_pcie_d3_suspend, \ |
| 3365 | .d3_resume = iwl_trans_pcie_d3_resume, \ |
| 3366 | .sync_nmi = iwl_trans_pcie_sync_nmi |
| 3367 | |
| 3368 | #ifdef CONFIG_PM_SLEEP |
| 3369 | #define IWL_TRANS_PM_OPS \ |
| 3370 | .suspend = iwl_trans_pcie_suspend, \ |
| 3371 | .resume = iwl_trans_pcie_resume, |
| 3372 | #else |
| 3373 | #define IWL_TRANS_PM_OPS |
| 3374 | #endif /* CONFIG_PM_SLEEP */ |
| 3375 | |
| 3376 | static const struct iwl_trans_ops trans_ops_pcie = { |
| 3377 | IWL_TRANS_COMMON_OPS, |
| 3378 | IWL_TRANS_PM_OPS |
| 3379 | .start_hw = iwl_trans_pcie_start_hw, |
| 3380 | .fw_alive = iwl_trans_pcie_fw_alive, |
| 3381 | .start_fw = iwl_trans_pcie_start_fw, |
| 3382 | .stop_device = iwl_trans_pcie_stop_device, |
| 3383 | |
| 3384 | .send_cmd = iwl_trans_pcie_send_hcmd, |
| 3385 | |
| 3386 | .tx = iwl_trans_pcie_tx, |
| 3387 | .reclaim = iwl_trans_pcie_reclaim, |
| 3388 | |
| 3389 | .txq_disable = iwl_trans_pcie_txq_disable, |
| 3390 | .txq_enable = iwl_trans_pcie_txq_enable, |
| 3391 | |
| 3392 | .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, |
| 3393 | |
| 3394 | .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, |
| 3395 | |
| 3396 | .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, |
| 3397 | .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, |
| 3398 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 3399 | .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, |
| 3400 | #endif |
| 3401 | }; |
| 3402 | |
| 3403 | static const struct iwl_trans_ops trans_ops_pcie_gen2 = { |
| 3404 | IWL_TRANS_COMMON_OPS, |
| 3405 | IWL_TRANS_PM_OPS |
| 3406 | .start_hw = iwl_trans_pcie_start_hw, |
| 3407 | .fw_alive = iwl_trans_pcie_gen2_fw_alive, |
| 3408 | .start_fw = iwl_trans_pcie_gen2_start_fw, |
| 3409 | .stop_device = iwl_trans_pcie_gen2_stop_device, |
| 3410 | |
| 3411 | .send_cmd = iwl_trans_pcie_gen2_send_hcmd, |
| 3412 | |
| 3413 | .tx = iwl_trans_pcie_gen2_tx, |
| 3414 | .reclaim = iwl_trans_pcie_reclaim, |
| 3415 | |
| 3416 | .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, |
| 3417 | |
| 3418 | .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, |
| 3419 | .txq_free = iwl_trans_pcie_dyn_txq_free, |
| 3420 | .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, |
| 3421 | .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, |
| 3422 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 3423 | .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, |
| 3424 | #endif |
| 3425 | }; |
| 3426 | |
| 3427 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
| 3428 | const struct pci_device_id *ent, |
| 3429 | const struct iwl_cfg_trans_params *cfg_trans) |
| 3430 | { |
| 3431 | struct iwl_trans_pcie *trans_pcie; |
| 3432 | struct iwl_trans *trans; |
| 3433 | int ret, addr_size; |
| 3434 | |
| 3435 | ret = pcim_enable_device(pdev); |
| 3436 | if (ret) |
| 3437 | return ERR_PTR(ret); |
| 3438 | |
| 3439 | if (cfg_trans->gen2) |
| 3440 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), |
| 3441 | &pdev->dev, &trans_ops_pcie_gen2); |
| 3442 | else |
| 3443 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), |
| 3444 | &pdev->dev, &trans_ops_pcie); |
| 3445 | |
| 3446 | if (!trans) |
| 3447 | return ERR_PTR(-ENOMEM); |
| 3448 | |
| 3449 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 3450 | |
| 3451 | trans_pcie->trans = trans; |
| 3452 | trans_pcie->opmode_down = true; |
| 3453 | spin_lock_init(&trans_pcie->irq_lock); |
| 3454 | spin_lock_init(&trans_pcie->reg_lock); |
| 3455 | mutex_init(&trans_pcie->mutex); |
| 3456 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
| 3457 | |
| 3458 | trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", |
| 3459 | WQ_HIGHPRI | WQ_UNBOUND, 1); |
| 3460 | if (!trans_pcie->rba.alloc_wq) { |
| 3461 | ret = -ENOMEM; |
| 3462 | goto out_free_trans; |
| 3463 | } |
| 3464 | INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); |
| 3465 | |
| 3466 | trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); |
| 3467 | if (!trans_pcie->tso_hdr_page) { |
| 3468 | ret = -ENOMEM; |
| 3469 | goto out_no_pci; |
| 3470 | } |
| 3471 | trans_pcie->debug_rfkill = -1; |
| 3472 | |
| 3473 | if (!cfg_trans->base_params->pcie_l1_allowed) { |
| 3474 | /* |
| 3475 | * W/A - seems to solve weird behavior. We need to remove this |
| 3476 | * if we don't want to stay in L1 all the time. This wastes a |
| 3477 | * lot of power. |
| 3478 | */ |
| 3479 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | |
| 3480 | PCIE_LINK_STATE_L1 | |
| 3481 | PCIE_LINK_STATE_CLKPM); |
| 3482 | } |
| 3483 | |
| 3484 | trans_pcie->def_rx_queue = 0; |
| 3485 | |
| 3486 | if (cfg_trans->use_tfh) { |
| 3487 | addr_size = 64; |
| 3488 | trans_pcie->max_tbs = IWL_TFH_NUM_TBS; |
| 3489 | trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); |
| 3490 | } else { |
| 3491 | addr_size = 36; |
| 3492 | trans_pcie->max_tbs = IWL_NUM_OF_TBS; |
| 3493 | trans_pcie->tfd_size = sizeof(struct iwl_tfd); |
| 3494 | } |
| 3495 | trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); |
| 3496 | |
| 3497 | pci_set_master(pdev); |
| 3498 | |
| 3499 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); |
| 3500 | if (!ret) |
| 3501 | ret = pci_set_consistent_dma_mask(pdev, |
| 3502 | DMA_BIT_MASK(addr_size)); |
| 3503 | if (ret) { |
| 3504 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 3505 | if (!ret) |
| 3506 | ret = pci_set_consistent_dma_mask(pdev, |
| 3507 | DMA_BIT_MASK(32)); |
| 3508 | /* both attempts failed: */ |
| 3509 | if (ret) { |
| 3510 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
| 3511 | goto out_no_pci; |
| 3512 | } |
| 3513 | } |
| 3514 | |
| 3515 | ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); |
| 3516 | if (ret) { |
| 3517 | dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); |
| 3518 | goto out_no_pci; |
| 3519 | } |
| 3520 | |
| 3521 | trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; |
| 3522 | if (!trans_pcie->hw_base) { |
| 3523 | dev_err(&pdev->dev, "pcim_iomap_table failed\n"); |
| 3524 | ret = -ENODEV; |
| 3525 | goto out_no_pci; |
| 3526 | } |
| 3527 | |
| 3528 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
| 3529 | * PCI Tx retries from interfering with C3 CPU state */ |
| 3530 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); |
| 3531 | |
| 3532 | trans_pcie->pci_dev = pdev; |
| 3533 | iwl_disable_interrupts(trans); |
| 3534 | |
| 3535 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
| 3536 | if (trans->hw_rev == 0xffffffff) { |
| 3537 | dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); |
| 3538 | ret = -EIO; |
| 3539 | goto out_no_pci; |
| 3540 | } |
| 3541 | |
| 3542 | /* |
| 3543 | * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have |
| 3544 | * changed, and now the revision step also includes bit 0-1 (no more |
| 3545 | * "dash" value). To keep hw_rev backwards compatible - we'll store it |
| 3546 | * in the old format. |
| 3547 | */ |
| 3548 | if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) { |
| 3549 | trans->hw_rev = (trans->hw_rev & 0xfff0) | |
| 3550 | (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); |
| 3551 | |
| 3552 | ret = iwl_pcie_prepare_card_hw(trans); |
| 3553 | if (ret) { |
| 3554 | IWL_WARN(trans, "Exit HW not ready\n"); |
| 3555 | goto out_no_pci; |
| 3556 | } |
| 3557 | |
| 3558 | /* |
| 3559 | * in-order to recognize C step driver should read chip version |
| 3560 | * id located at the AUX bus MISC address space. |
| 3561 | */ |
| 3562 | ret = iwl_finish_nic_init(trans, cfg_trans); |
| 3563 | if (ret) |
| 3564 | goto out_no_pci; |
| 3565 | |
| 3566 | } |
| 3567 | |
| 3568 | IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); |
| 3569 | |
| 3570 | iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); |
| 3571 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
| 3572 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
| 3573 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); |
| 3574 | |
| 3575 | /* Initialize the wait queue for commands */ |
| 3576 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
| 3577 | |
| 3578 | init_waitqueue_head(&trans_pcie->sx_waitq); |
| 3579 | |
| 3580 | if (trans_pcie->msix_enabled) { |
| 3581 | ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); |
| 3582 | if (ret) |
| 3583 | goto out_no_pci; |
| 3584 | } else { |
| 3585 | ret = iwl_pcie_alloc_ict(trans); |
| 3586 | if (ret) |
| 3587 | goto out_no_pci; |
| 3588 | |
| 3589 | ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, |
| 3590 | iwl_pcie_isr, |
| 3591 | iwl_pcie_irq_handler, |
| 3592 | IRQF_SHARED, DRV_NAME, trans); |
| 3593 | if (ret) { |
| 3594 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
| 3595 | goto out_free_ict; |
| 3596 | } |
| 3597 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
| 3598 | } |
| 3599 | |
| 3600 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 3601 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; |
| 3602 | mutex_init(&trans_pcie->fw_mon_data.mutex); |
| 3603 | #endif |
| 3604 | |
| 3605 | iwl_dbg_tlv_init(trans); |
| 3606 | |
| 3607 | return trans; |
| 3608 | |
| 3609 | out_free_ict: |
| 3610 | iwl_pcie_free_ict(trans); |
| 3611 | out_no_pci: |
| 3612 | free_percpu(trans_pcie->tso_hdr_page); |
| 3613 | destroy_workqueue(trans_pcie->rba.alloc_wq); |
| 3614 | out_free_trans: |
| 3615 | iwl_trans_free(trans); |
| 3616 | return ERR_PTR(ret); |
| 3617 | } |
| 3618 | |
| 3619 | void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) |
| 3620 | { |
| 3621 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 3622 | unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; |
| 3623 | bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); |
| 3624 | u32 inta_addr, sw_err_bit; |
| 3625 | |
| 3626 | if (trans_pcie->msix_enabled) { |
| 3627 | inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; |
| 3628 | sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; |
| 3629 | } else { |
| 3630 | inta_addr = CSR_INT; |
| 3631 | sw_err_bit = CSR_INT_BIT_SW_ERR; |
| 3632 | } |
| 3633 | |
| 3634 | /* if the interrupts were already disabled, there is no point in |
| 3635 | * calling iwl_disable_interrupts |
| 3636 | */ |
| 3637 | if (interrupts_enabled) |
| 3638 | iwl_disable_interrupts(trans); |
| 3639 | |
| 3640 | iwl_force_nmi(trans); |
| 3641 | while (time_after(timeout, jiffies)) { |
| 3642 | u32 inta_hw = iwl_read32(trans, inta_addr); |
| 3643 | |
| 3644 | /* Error detected by uCode */ |
| 3645 | if (inta_hw & sw_err_bit) { |
| 3646 | /* Clear causes register */ |
| 3647 | iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); |
| 3648 | break; |
| 3649 | } |
| 3650 | |
| 3651 | mdelay(1); |
| 3652 | } |
| 3653 | |
| 3654 | /* enable interrupts only if there were already enabled before this |
| 3655 | * function to avoid a case were the driver enable interrupts before |
| 3656 | * proper configurations were made |
| 3657 | */ |
| 3658 | if (interrupts_enabled) |
| 3659 | iwl_enable_interrupts(trans); |
| 3660 | |
| 3661 | iwl_trans_fw_error(trans); |
| 3662 | } |