| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /******************************************************************************* |
| 3 | STMMAC Common Header File |
| 4 | |
| 5 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
| 6 | |
| 7 | |
| 8 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 9 | *******************************************************************************/ |
| 10 | |
| 11 | #ifndef __COMMON_H__ |
| 12 | #define __COMMON_H__ |
| 13 | |
| 14 | #include <linux/etherdevice.h> |
| 15 | #include <linux/netdevice.h> |
| 16 | #include <linux/stmmac.h> |
| 17 | #include <linux/phy.h> |
| 18 | #include <linux/pcs/pcs-xpcs.h> |
| 19 | #include <linux/module.h> |
| 20 | #if IS_ENABLED(CONFIG_VLAN_8021Q) |
| 21 | #define STMMAC_VLAN_TAG_USED |
| 22 | #include <linux/if_vlan.h> |
| 23 | #endif |
| 24 | |
| 25 | #include "descs.h" |
| 26 | #include "hwif.h" |
| 27 | #include "mmc.h" |
| 28 | |
| 29 | /* Synopsys Core versions */ |
| 30 | #define DWMAC_CORE_3_40 0x34 |
| 31 | #define DWMAC_CORE_3_50 0x35 |
| 32 | #define DWMAC_CORE_4_00 0x40 |
| 33 | #define DWMAC_CORE_4_10 0x41 |
| 34 | #define DWMAC_CORE_5_00 0x50 |
| 35 | #define DWMAC_CORE_5_10 0x51 |
| 36 | #define DWXGMAC_CORE_2_10 0x21 |
| 37 | #define DWXLGMAC_CORE_2_00 0x20 |
| 38 | |
| 39 | /* Device ID */ |
| 40 | #define DWXGMAC_ID 0x76 |
| 41 | #define DWXLGMAC_ID 0x27 |
| 42 | |
| 43 | #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ |
| 44 | |
| 45 | /* TX and RX Descriptor Length, these need to be power of two. |
| 46 | * TX descriptor length less than 64 may cause transmit queue timed out error. |
| 47 | * RX descriptor length less than 64 may cause inconsistent Rx chain error. |
| 48 | */ |
| 49 | #define DMA_MIN_TX_SIZE 64 |
| 50 | #define DMA_MAX_TX_SIZE 1024 |
| 51 | #define DMA_DEFAULT_TX_SIZE 512 |
| 52 | #define DMA_MIN_RX_SIZE 64 |
| 53 | #define DMA_MAX_RX_SIZE 1024 |
| 54 | #define DMA_DEFAULT_RX_SIZE 512 |
| 55 | #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) |
| 56 | |
| 57 | #undef FRAME_FILTER_DEBUG |
| 58 | /* #define FRAME_FILTER_DEBUG */ |
| 59 | |
| 60 | /* Extra statistic and debug information exposed by ethtool */ |
| 61 | struct stmmac_extra_stats { |
| 62 | /* Transmit errors */ |
| 63 | unsigned long tx_underflow ____cacheline_aligned; |
| 64 | unsigned long tx_carrier; |
| 65 | unsigned long tx_losscarrier; |
| 66 | unsigned long vlan_tag; |
| 67 | unsigned long tx_deferred; |
| 68 | unsigned long tx_vlan; |
| 69 | unsigned long tx_jabber; |
| 70 | unsigned long tx_frame_flushed; |
| 71 | unsigned long tx_payload_error; |
| 72 | unsigned long tx_ip_header_error; |
| 73 | /* Receive errors */ |
| 74 | unsigned long rx_desc; |
| 75 | unsigned long sa_filter_fail; |
| 76 | unsigned long overflow_error; |
| 77 | unsigned long ipc_csum_error; |
| 78 | unsigned long rx_collision; |
| 79 | unsigned long rx_crc_errors; |
| 80 | unsigned long dribbling_bit; |
| 81 | unsigned long rx_length; |
| 82 | unsigned long rx_mii; |
| 83 | unsigned long rx_multicast; |
| 84 | unsigned long rx_gmac_overflow; |
| 85 | unsigned long rx_watchdog; |
| 86 | unsigned long da_rx_filter_fail; |
| 87 | unsigned long sa_rx_filter_fail; |
| 88 | unsigned long rx_missed_cntr; |
| 89 | unsigned long rx_overflow_cntr; |
| 90 | unsigned long rx_vlan; |
| 91 | unsigned long rx_split_hdr_pkt_n; |
| 92 | /* Tx/Rx IRQ error info */ |
| 93 | unsigned long tx_undeflow_irq; |
| 94 | unsigned long tx_process_stopped_irq; |
| 95 | unsigned long tx_jabber_irq; |
| 96 | unsigned long rx_overflow_irq; |
| 97 | unsigned long rx_buf_unav_irq; |
| 98 | unsigned long rx_process_stopped_irq; |
| 99 | unsigned long rx_watchdog_irq; |
| 100 | unsigned long tx_early_irq; |
| 101 | unsigned long fatal_bus_error_irq; |
| 102 | /* Tx/Rx IRQ Events */ |
| 103 | unsigned long rx_early_irq; |
| 104 | unsigned long threshold; |
| 105 | unsigned long tx_pkt_n; |
| 106 | unsigned long rx_pkt_n; |
| 107 | unsigned long normal_irq_n; |
| 108 | unsigned long rx_normal_irq_n; |
| 109 | unsigned long napi_poll; |
| 110 | unsigned long tx_normal_irq_n; |
| 111 | unsigned long tx_clean; |
| 112 | unsigned long tx_set_ic_bit; |
| 113 | unsigned long irq_receive_pmt_irq_n; |
| 114 | /* MMC info */ |
| 115 | unsigned long mmc_tx_irq_n; |
| 116 | unsigned long mmc_rx_irq_n; |
| 117 | unsigned long mmc_rx_csum_offload_irq_n; |
| 118 | /* EEE */ |
| 119 | unsigned long irq_tx_path_in_lpi_mode_n; |
| 120 | unsigned long irq_tx_path_exit_lpi_mode_n; |
| 121 | unsigned long irq_rx_path_in_lpi_mode_n; |
| 122 | unsigned long irq_rx_path_exit_lpi_mode_n; |
| 123 | unsigned long phy_eee_wakeup_error_n; |
| 124 | /* Extended RDES status */ |
| 125 | unsigned long ip_hdr_err; |
| 126 | unsigned long ip_payload_err; |
| 127 | unsigned long ip_csum_bypassed; |
| 128 | unsigned long ipv4_pkt_rcvd; |
| 129 | unsigned long ipv6_pkt_rcvd; |
| 130 | unsigned long no_ptp_rx_msg_type_ext; |
| 131 | unsigned long ptp_rx_msg_type_sync; |
| 132 | unsigned long ptp_rx_msg_type_follow_up; |
| 133 | unsigned long ptp_rx_msg_type_delay_req; |
| 134 | unsigned long ptp_rx_msg_type_delay_resp; |
| 135 | unsigned long ptp_rx_msg_type_pdelay_req; |
| 136 | unsigned long ptp_rx_msg_type_pdelay_resp; |
| 137 | unsigned long ptp_rx_msg_type_pdelay_follow_up; |
| 138 | unsigned long ptp_rx_msg_type_announce; |
| 139 | unsigned long ptp_rx_msg_type_management; |
| 140 | unsigned long ptp_rx_msg_pkt_reserved_type; |
| 141 | unsigned long ptp_frame_type; |
| 142 | unsigned long ptp_ver; |
| 143 | unsigned long timestamp_dropped; |
| 144 | unsigned long av_pkt_rcvd; |
| 145 | unsigned long av_tagged_pkt_rcvd; |
| 146 | unsigned long vlan_tag_priority_val; |
| 147 | unsigned long l3_filter_match; |
| 148 | unsigned long l4_filter_match; |
| 149 | unsigned long l3_l4_filter_no_match; |
| 150 | /* PCS */ |
| 151 | unsigned long irq_pcs_ane_n; |
| 152 | unsigned long irq_pcs_link_n; |
| 153 | unsigned long irq_rgmii_n; |
| 154 | unsigned long pcs_link; |
| 155 | unsigned long pcs_duplex; |
| 156 | unsigned long pcs_speed; |
| 157 | /* debug register */ |
| 158 | unsigned long mtl_tx_status_fifo_full; |
| 159 | unsigned long mtl_tx_fifo_not_empty; |
| 160 | unsigned long mmtl_fifo_ctrl; |
| 161 | unsigned long mtl_tx_fifo_read_ctrl_write; |
| 162 | unsigned long mtl_tx_fifo_read_ctrl_wait; |
| 163 | unsigned long mtl_tx_fifo_read_ctrl_read; |
| 164 | unsigned long mtl_tx_fifo_read_ctrl_idle; |
| 165 | unsigned long mac_tx_in_pause; |
| 166 | unsigned long mac_tx_frame_ctrl_xfer; |
| 167 | unsigned long mac_tx_frame_ctrl_idle; |
| 168 | unsigned long mac_tx_frame_ctrl_wait; |
| 169 | unsigned long mac_tx_frame_ctrl_pause; |
| 170 | unsigned long mac_gmii_tx_proto_engine; |
| 171 | unsigned long mtl_rx_fifo_fill_level_full; |
| 172 | unsigned long mtl_rx_fifo_fill_above_thresh; |
| 173 | unsigned long mtl_rx_fifo_fill_below_thresh; |
| 174 | unsigned long mtl_rx_fifo_fill_level_empty; |
| 175 | unsigned long mtl_rx_fifo_read_ctrl_flush; |
| 176 | unsigned long mtl_rx_fifo_read_ctrl_read_data; |
| 177 | unsigned long mtl_rx_fifo_read_ctrl_status; |
| 178 | unsigned long mtl_rx_fifo_read_ctrl_idle; |
| 179 | unsigned long mtl_rx_fifo_ctrl_active; |
| 180 | unsigned long mac_rx_frame_ctrl_fifo; |
| 181 | unsigned long mac_gmii_rx_proto_engine; |
| 182 | /* TSO */ |
| 183 | unsigned long tx_tso_frames; |
| 184 | unsigned long tx_tso_nfrags; |
| 185 | /* EST */ |
| 186 | unsigned long mtl_est_cgce; |
| 187 | unsigned long mtl_est_hlbs; |
| 188 | unsigned long mtl_est_hlbf; |
| 189 | unsigned long mtl_est_btre; |
| 190 | unsigned long mtl_est_btrlm; |
| 191 | }; |
| 192 | |
| 193 | /* Safety Feature statistics exposed by ethtool */ |
| 194 | struct stmmac_safety_stats { |
| 195 | unsigned long mac_errors[32]; |
| 196 | unsigned long mtl_errors[32]; |
| 197 | unsigned long dma_errors[32]; |
| 198 | }; |
| 199 | |
| 200 | /* Number of fields in Safety Stats */ |
| 201 | #define STMMAC_SAFETY_FEAT_SIZE \ |
| 202 | (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) |
| 203 | |
| 204 | /* CSR Frequency Access Defines*/ |
| 205 | #define CSR_F_35M 35000000 |
| 206 | #define CSR_F_60M 60000000 |
| 207 | #define CSR_F_100M 100000000 |
| 208 | #define CSR_F_150M 150000000 |
| 209 | #define CSR_F_250M 250000000 |
| 210 | #define CSR_F_300M 300000000 |
| 211 | |
| 212 | #define MAC_CSR_H_FRQ_MASK 0x20 |
| 213 | |
| 214 | #define HASH_TABLE_SIZE 64 |
| 215 | #define PAUSE_TIME 0xffff |
| 216 | |
| 217 | /* Flow Control defines */ |
| 218 | #define FLOW_OFF 0 |
| 219 | #define FLOW_RX 1 |
| 220 | #define FLOW_TX 2 |
| 221 | #define FLOW_AUTO (FLOW_TX | FLOW_RX) |
| 222 | |
| 223 | /* PCS defines */ |
| 224 | #define STMMAC_PCS_RGMII (1 << 0) |
| 225 | #define STMMAC_PCS_SGMII (1 << 1) |
| 226 | #define STMMAC_PCS_TBI (1 << 2) |
| 227 | #define STMMAC_PCS_RTBI (1 << 3) |
| 228 | |
| 229 | #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ |
| 230 | |
| 231 | /* DAM HW feature register fields */ |
| 232 | #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ |
| 233 | #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ |
| 234 | #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ |
| 235 | #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ |
| 236 | #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ |
| 237 | #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ |
| 238 | #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ |
| 239 | #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ |
| 240 | #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ |
| 241 | #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ |
| 242 | #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ |
| 243 | #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ |
| 244 | #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ |
| 245 | #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ |
| 246 | #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ |
| 247 | #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ |
| 248 | #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ |
| 249 | #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ |
| 250 | #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ |
| 251 | #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ |
| 252 | #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ |
| 253 | #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ |
| 254 | #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ |
| 255 | /* Timestamping with Internal System Time */ |
| 256 | #define DMA_HW_FEAT_INTTSEN 0x02000000 |
| 257 | #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ |
| 258 | #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ |
| 259 | #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ |
| 260 | #define DEFAULT_DMA_PBL 8 |
| 261 | |
| 262 | /* PCS status and mask defines */ |
| 263 | #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ |
| 264 | #define PCS_LINK_IRQ BIT(1) /* PCS Link */ |
| 265 | #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ |
| 266 | |
| 267 | /* Max/Min RI Watchdog Timer count value */ |
| 268 | #define MAX_DMA_RIWT 0xff |
| 269 | #define MIN_DMA_RIWT 0x10 |
| 270 | #define DEF_DMA_RIWT 0xa0 |
| 271 | /* Tx coalesce parameters */ |
| 272 | #define STMMAC_COAL_TX_TIMER 1000 |
| 273 | #define STMMAC_MAX_COAL_TX_TICK 100000 |
| 274 | #define STMMAC_TX_MAX_FRAMES 256 |
| 275 | #define STMMAC_TX_FRAMES 25 |
| 276 | #define STMMAC_RX_FRAMES 0 |
| 277 | |
| 278 | /* Packets types */ |
| 279 | enum packets_types { |
| 280 | PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ |
| 281 | PACKET_PTPQ = 0x2, /* PTP Packets */ |
| 282 | PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ |
| 283 | PACKET_UPQ = 0x4, /* Untagged Packets */ |
| 284 | PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ |
| 285 | }; |
| 286 | |
| 287 | /* Rx IPC status */ |
| 288 | enum rx_frame_status { |
| 289 | good_frame = 0x0, |
| 290 | discard_frame = 0x1, |
| 291 | csum_none = 0x2, |
| 292 | llc_snap = 0x4, |
| 293 | dma_own = 0x8, |
| 294 | rx_not_ls = 0x10, |
| 295 | }; |
| 296 | |
| 297 | /* Tx status */ |
| 298 | enum tx_frame_status { |
| 299 | tx_done = 0x0, |
| 300 | tx_not_ls = 0x1, |
| 301 | tx_err = 0x2, |
| 302 | tx_dma_own = 0x4, |
| 303 | }; |
| 304 | |
| 305 | enum dma_irq_status { |
| 306 | tx_hard_error = 0x1, |
| 307 | tx_hard_error_bump_tc = 0x2, |
| 308 | handle_rx = 0x4, |
| 309 | handle_tx = 0x8, |
| 310 | }; |
| 311 | |
| 312 | /* EEE and LPI defines */ |
| 313 | #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) |
| 314 | #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) |
| 315 | #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) |
| 316 | #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) |
| 317 | |
| 318 | #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) |
| 319 | |
| 320 | /* Physical Coding Sublayer */ |
| 321 | struct rgmii_adv { |
| 322 | unsigned int pause; |
| 323 | unsigned int duplex; |
| 324 | unsigned int lp_pause; |
| 325 | unsigned int lp_duplex; |
| 326 | }; |
| 327 | |
| 328 | #define STMMAC_PCS_PAUSE 1 |
| 329 | #define STMMAC_PCS_ASYM_PAUSE 2 |
| 330 | |
| 331 | /* DMA HW capabilities */ |
| 332 | struct dma_features { |
| 333 | unsigned int mbps_10_100; |
| 334 | unsigned int mbps_1000; |
| 335 | unsigned int half_duplex; |
| 336 | unsigned int hash_filter; |
| 337 | unsigned int multi_addr; |
| 338 | unsigned int pcs; |
| 339 | unsigned int sma_mdio; |
| 340 | unsigned int pmt_remote_wake_up; |
| 341 | unsigned int pmt_magic_frame; |
| 342 | unsigned int rmon; |
| 343 | /* IEEE 1588-2002 */ |
| 344 | unsigned int time_stamp; |
| 345 | /* IEEE 1588-2008 */ |
| 346 | unsigned int atime_stamp; |
| 347 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
| 348 | unsigned int eee; |
| 349 | unsigned int av; |
| 350 | unsigned int hash_tb_sz; |
| 351 | unsigned int tsoen; |
| 352 | /* TX and RX csum */ |
| 353 | unsigned int tx_coe; |
| 354 | unsigned int rx_coe; |
| 355 | unsigned int rx_coe_type1; |
| 356 | unsigned int rx_coe_type2; |
| 357 | unsigned int rxfifo_over_2048; |
| 358 | /* TX and RX number of channels */ |
| 359 | unsigned int number_rx_channel; |
| 360 | unsigned int number_tx_channel; |
| 361 | /* TX and RX number of queues */ |
| 362 | unsigned int number_rx_queues; |
| 363 | unsigned int number_tx_queues; |
| 364 | /* PPS output */ |
| 365 | unsigned int pps_out_num; |
| 366 | /* Alternate (enhanced) DESC mode */ |
| 367 | unsigned int enh_desc; |
| 368 | /* TX and RX FIFO sizes */ |
| 369 | unsigned int tx_fifo_size; |
| 370 | unsigned int rx_fifo_size; |
| 371 | /* Automotive Safety Package */ |
| 372 | unsigned int asp; |
| 373 | /* RX Parser */ |
| 374 | unsigned int frpsel; |
| 375 | unsigned int frpbs; |
| 376 | unsigned int frpes; |
| 377 | unsigned int addr64; |
| 378 | unsigned int rssen; |
| 379 | unsigned int vlhash; |
| 380 | unsigned int sphen; |
| 381 | unsigned int vlins; |
| 382 | unsigned int dvlan; |
| 383 | unsigned int l3l4fnum; |
| 384 | unsigned int arpoffsel; |
| 385 | /* TSN Features */ |
| 386 | unsigned int estwid; |
| 387 | unsigned int estdep; |
| 388 | unsigned int estsel; |
| 389 | unsigned int fpesel; |
| 390 | unsigned int tbssel; |
| 391 | /* Numbers of Auxiliary Snapshot Inputs */ |
| 392 | unsigned int aux_snapshot_n; |
| 393 | }; |
| 394 | |
| 395 | /* RX Buffer size must be multiple of 4/8/16 bytes */ |
| 396 | #define BUF_SIZE_16KiB 16368 |
| 397 | #define BUF_SIZE_8KiB 8188 |
| 398 | #define BUF_SIZE_4KiB 4096 |
| 399 | #define BUF_SIZE_2KiB 2048 |
| 400 | |
| 401 | /* Power Down and WOL */ |
| 402 | #define PMT_NOT_SUPPORTED 0 |
| 403 | #define PMT_SUPPORTED 1 |
| 404 | |
| 405 | /* Common MAC defines */ |
| 406 | #define MAC_CTRL_REG 0x00000000 /* MAC Control */ |
| 407 | #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ |
| 408 | #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ |
| 409 | |
| 410 | /* Default LPI timers */ |
| 411 | #define STMMAC_DEFAULT_LIT_LS 0x3E8 |
| 412 | #define STMMAC_DEFAULT_TWT_LS 0x1E |
| 413 | #define STMMAC_ET_MAX 0xFFFFF |
| 414 | |
| 415 | #define STMMAC_CHAIN_MODE 0x1 |
| 416 | #define STMMAC_RING_MODE 0x2 |
| 417 | |
| 418 | #define JUMBO_LEN 9000 |
| 419 | |
| 420 | /* Receive Side Scaling */ |
| 421 | #define STMMAC_RSS_HASH_KEY_SIZE 40 |
| 422 | #define STMMAC_RSS_MAX_TABLE_SIZE 256 |
| 423 | |
| 424 | /* VLAN */ |
| 425 | #define STMMAC_VLAN_NONE 0x0 |
| 426 | #define STMMAC_VLAN_REMOVE 0x1 |
| 427 | #define STMMAC_VLAN_INSERT 0x2 |
| 428 | #define STMMAC_VLAN_REPLACE 0x3 |
| 429 | |
| 430 | extern const struct stmmac_desc_ops enh_desc_ops; |
| 431 | extern const struct stmmac_desc_ops ndesc_ops; |
| 432 | |
| 433 | struct mac_device_info; |
| 434 | |
| 435 | extern const struct stmmac_hwtimestamp stmmac_ptp; |
| 436 | extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; |
| 437 | |
| 438 | struct mac_link { |
| 439 | u32 speed_mask; |
| 440 | u32 speed10; |
| 441 | u32 speed100; |
| 442 | u32 speed1000; |
| 443 | u32 speed2500; |
| 444 | u32 duplex; |
| 445 | struct { |
| 446 | u32 speed2500; |
| 447 | u32 speed5000; |
| 448 | u32 speed10000; |
| 449 | } xgmii; |
| 450 | struct { |
| 451 | u32 speed25000; |
| 452 | u32 speed40000; |
| 453 | u32 speed50000; |
| 454 | u32 speed100000; |
| 455 | } xlgmii; |
| 456 | }; |
| 457 | |
| 458 | struct mii_regs { |
| 459 | unsigned int addr; /* MII Address */ |
| 460 | unsigned int data; /* MII Data */ |
| 461 | unsigned int addr_shift; /* MII address shift */ |
| 462 | unsigned int reg_shift; /* MII reg shift */ |
| 463 | unsigned int addr_mask; /* MII address mask */ |
| 464 | unsigned int reg_mask; /* MII reg mask */ |
| 465 | unsigned int clk_csr_shift; |
| 466 | unsigned int clk_csr_mask; |
| 467 | }; |
| 468 | |
| 469 | struct mac_device_info { |
| 470 | const struct stmmac_ops *mac; |
| 471 | const struct stmmac_desc_ops *desc; |
| 472 | const struct stmmac_dma_ops *dma; |
| 473 | const struct stmmac_mode_ops *mode; |
| 474 | const struct stmmac_hwtimestamp *ptp; |
| 475 | const struct stmmac_tc_ops *tc; |
| 476 | const struct stmmac_mmc_ops *mmc; |
| 477 | const struct mdio_xpcs_ops *xpcs; |
| 478 | struct mdio_xpcs_args xpcs_args; |
| 479 | struct mii_regs mii; /* MII register Addresses */ |
| 480 | struct mac_link link; |
| 481 | void __iomem *pcsr; /* vpointer to device CSRs */ |
| 482 | unsigned int multicast_filter_bins; |
| 483 | unsigned int unicast_filter_entries; |
| 484 | unsigned int mcast_bits_log2; |
| 485 | unsigned int rx_csum; |
| 486 | unsigned int pcs; |
| 487 | unsigned int pmt; |
| 488 | unsigned int ps; |
| 489 | unsigned int xlgmac; |
| 490 | unsigned int num_vlan; |
| 491 | u32 vlan_filter[32]; |
| 492 | unsigned int promisc; |
| 493 | bool vlan_fail_q_en; |
| 494 | u8 vlan_fail_q; |
| 495 | }; |
| 496 | |
| 497 | struct stmmac_rx_routing { |
| 498 | u32 reg_mask; |
| 499 | u32 reg_shift; |
| 500 | }; |
| 501 | |
| 502 | int dwmac100_setup(struct stmmac_priv *priv); |
| 503 | int dwmac1000_setup(struct stmmac_priv *priv); |
| 504 | int dwmac4_setup(struct stmmac_priv *priv); |
| 505 | int dwxgmac2_setup(struct stmmac_priv *priv); |
| 506 | int dwxlgmac2_setup(struct stmmac_priv *priv); |
| 507 | |
| 508 | void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], |
| 509 | unsigned int high, unsigned int low); |
| 510 | void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
| 511 | unsigned int high, unsigned int low); |
| 512 | void stmmac_set_mac(void __iomem *ioaddr, bool enable); |
| 513 | |
| 514 | void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], |
| 515 | unsigned int high, unsigned int low); |
| 516 | void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
| 517 | unsigned int high, unsigned int low); |
| 518 | void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); |
| 519 | |
| 520 | void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); |
| 521 | |
| 522 | extern const struct stmmac_mode_ops ring_mode_ops; |
| 523 | extern const struct stmmac_mode_ops chain_mode_ops; |
| 524 | extern const struct stmmac_desc_ops dwmac4_desc_ops; |
| 525 | |
| 526 | #endif /* __COMMON_H__ */ |