| 1 | /* Intel PRO/1000 Linux driver |
| 2 | * Copyright(c) 1999 - 2014 Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * The full GNU General Public License is included in this distribution in |
| 14 | * the file called "COPYING". |
| 15 | * |
| 16 | * Contact Information: |
| 17 | * Linux NICS <linux.nics@intel.com> |
| 18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 20 | */ |
| 21 | |
| 22 | /* Linux PRO/1000 Ethernet Driver main header file */ |
| 23 | |
| 24 | #ifndef _E1000_H_ |
| 25 | #define _E1000_H_ |
| 26 | |
| 27 | #include <linux/bitops.h> |
| 28 | #include <linux/types.h> |
| 29 | #include <linux/timer.h> |
| 30 | #include <linux/workqueue.h> |
| 31 | #include <linux/io.h> |
| 32 | #include <linux/netdevice.h> |
| 33 | #include <linux/pci.h> |
| 34 | #include <linux/pci-aspm.h> |
| 35 | #include <linux/crc32.h> |
| 36 | #include <linux/if_vlan.h> |
| 37 | #include <linux/clocksource.h> |
| 38 | #include <linux/net_tstamp.h> |
| 39 | #include <linux/ptp_clock_kernel.h> |
| 40 | #include <linux/ptp_classify.h> |
| 41 | #include <linux/mii.h> |
| 42 | #include <linux/mdio.h> |
| 43 | #include "hw.h" |
| 44 | |
| 45 | struct e1000_info; |
| 46 | |
| 47 | #define e_dbg(format, arg...) \ |
| 48 | netdev_dbg(hw->adapter->netdev, format, ## arg) |
| 49 | #define e_err(format, arg...) \ |
| 50 | netdev_err(adapter->netdev, format, ## arg) |
| 51 | #define e_info(format, arg...) \ |
| 52 | netdev_info(adapter->netdev, format, ## arg) |
| 53 | #define e_warn(format, arg...) \ |
| 54 | netdev_warn(adapter->netdev, format, ## arg) |
| 55 | #define e_notice(format, arg...) \ |
| 56 | netdev_notice(adapter->netdev, format, ## arg) |
| 57 | |
| 58 | /* Interrupt modes, as used by the IntMode parameter */ |
| 59 | #define E1000E_INT_MODE_LEGACY 0 |
| 60 | #define E1000E_INT_MODE_MSI 1 |
| 61 | #define E1000E_INT_MODE_MSIX 2 |
| 62 | |
| 63 | /* Tx/Rx descriptor defines */ |
| 64 | #define E1000_DEFAULT_TXD 256 |
| 65 | #define E1000_MAX_TXD 4096 |
| 66 | #define E1000_MIN_TXD 64 |
| 67 | |
| 68 | #define E1000_DEFAULT_RXD 256 |
| 69 | #define E1000_MAX_RXD 4096 |
| 70 | #define E1000_MIN_RXD 64 |
| 71 | |
| 72 | #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ |
| 73 | #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ |
| 74 | |
| 75 | #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ |
| 76 | |
| 77 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ |
| 78 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
| 79 | #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| 80 | |
| 81 | #define AUTO_ALL_MODES 0 |
| 82 | #define E1000_EEPROM_APME 0x0400 |
| 83 | |
| 84 | #define E1000_MNG_VLAN_NONE (-1) |
| 85 | |
| 86 | #define DEFAULT_JUMBO 9234 |
| 87 | |
| 88 | /* Time to wait before putting the device into D3 if there's no link (in ms). */ |
| 89 | #define LINK_TIMEOUT 100 |
| 90 | |
| 91 | /* Count for polling __E1000_RESET condition every 10-20msec. |
| 92 | * Experimentation has shown the reset can take approximately 210msec. |
| 93 | */ |
| 94 | #define E1000_CHECK_RESET_COUNT 25 |
| 95 | |
| 96 | #define DEFAULT_RDTR 0 |
| 97 | #define DEFAULT_RADV 8 |
| 98 | #define BURST_RDTR 0x20 |
| 99 | #define BURST_RADV 0x20 |
| 100 | |
| 101 | /* in the case of WTHRESH, it appears at least the 82571/2 hardware |
| 102 | * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when |
| 103 | * WTHRESH=4, so a setting of 5 gives the most efficient bus |
| 104 | * utilization but to avoid possible Tx stalls, set it to 1 |
| 105 | */ |
| 106 | #define E1000_TXDCTL_DMA_BURST_ENABLE \ |
| 107 | (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ |
| 108 | E1000_TXDCTL_COUNT_DESC | \ |
| 109 | (1 << 16) | /* wthresh must be +1 more than desired */\ |
| 110 | (1 << 8) | /* hthresh */ \ |
| 111 | 0x1f) /* pthresh */ |
| 112 | |
| 113 | #define E1000_RXDCTL_DMA_BURST_ENABLE \ |
| 114 | (0x01000000 | /* set descriptor granularity */ \ |
| 115 | (4 << 16) | /* set writeback threshold */ \ |
| 116 | (4 << 8) | /* set prefetch threshold */ \ |
| 117 | 0x20) /* set hthresh */ |
| 118 | |
| 119 | #define E1000_TIDV_FPD (1 << 31) |
| 120 | #define E1000_RDTR_FPD (1 << 31) |
| 121 | |
| 122 | enum e1000_boards { |
| 123 | board_82571, |
| 124 | board_82572, |
| 125 | board_82573, |
| 126 | board_82574, |
| 127 | board_82583, |
| 128 | board_80003es2lan, |
| 129 | board_ich8lan, |
| 130 | board_ich9lan, |
| 131 | board_ich10lan, |
| 132 | board_pchlan, |
| 133 | board_pch2lan, |
| 134 | board_pch_lpt, |
| 135 | }; |
| 136 | |
| 137 | struct e1000_ps_page { |
| 138 | struct page *page; |
| 139 | u64 dma; /* must be u64 - written to hw */ |
| 140 | }; |
| 141 | |
| 142 | /* wrappers around a pointer to a socket buffer, |
| 143 | * so a DMA handle can be stored along with the buffer |
| 144 | */ |
| 145 | struct e1000_buffer { |
| 146 | dma_addr_t dma; |
| 147 | struct sk_buff *skb; |
| 148 | union { |
| 149 | /* Tx */ |
| 150 | struct { |
| 151 | unsigned long time_stamp; |
| 152 | u16 length; |
| 153 | u16 next_to_watch; |
| 154 | unsigned int segs; |
| 155 | unsigned int bytecount; |
| 156 | u16 mapped_as_page; |
| 157 | }; |
| 158 | /* Rx */ |
| 159 | struct { |
| 160 | /* arrays of page information for packet split */ |
| 161 | struct e1000_ps_page *ps_pages; |
| 162 | struct page *page; |
| 163 | }; |
| 164 | }; |
| 165 | }; |
| 166 | |
| 167 | struct e1000_ring { |
| 168 | struct e1000_adapter *adapter; /* back pointer to adapter */ |
| 169 | void *desc; /* pointer to ring memory */ |
| 170 | dma_addr_t dma; /* phys address of ring */ |
| 171 | unsigned int size; /* length of ring in bytes */ |
| 172 | unsigned int count; /* number of desc. in ring */ |
| 173 | |
| 174 | u16 next_to_use; |
| 175 | u16 next_to_clean; |
| 176 | |
| 177 | void __iomem *head; |
| 178 | void __iomem *tail; |
| 179 | |
| 180 | /* array of buffer information structs */ |
| 181 | struct e1000_buffer *buffer_info; |
| 182 | |
| 183 | char name[IFNAMSIZ + 5]; |
| 184 | u32 ims_val; |
| 185 | u32 itr_val; |
| 186 | void __iomem *itr_register; |
| 187 | int set_itr; |
| 188 | |
| 189 | struct sk_buff *rx_skb_top; |
| 190 | }; |
| 191 | |
| 192 | /* PHY register snapshot values */ |
| 193 | struct e1000_phy_regs { |
| 194 | u16 bmcr; /* basic mode control register */ |
| 195 | u16 bmsr; /* basic mode status register */ |
| 196 | u16 advertise; /* auto-negotiation advertisement */ |
| 197 | u16 lpa; /* link partner ability register */ |
| 198 | u16 expansion; /* auto-negotiation expansion reg */ |
| 199 | u16 ctrl1000; /* 1000BASE-T control register */ |
| 200 | u16 stat1000; /* 1000BASE-T status register */ |
| 201 | u16 estatus; /* extended status register */ |
| 202 | }; |
| 203 | |
| 204 | /* board specific private data structure */ |
| 205 | struct e1000_adapter { |
| 206 | struct timer_list watchdog_timer; |
| 207 | struct timer_list phy_info_timer; |
| 208 | struct timer_list blink_timer; |
| 209 | |
| 210 | struct work_struct reset_task; |
| 211 | struct work_struct watchdog_task; |
| 212 | |
| 213 | const struct e1000_info *ei; |
| 214 | |
| 215 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
| 216 | u32 bd_number; |
| 217 | u32 rx_buffer_len; |
| 218 | u16 mng_vlan_id; |
| 219 | u16 link_speed; |
| 220 | u16 link_duplex; |
| 221 | u16 eeprom_vers; |
| 222 | |
| 223 | /* track device up/down/testing state */ |
| 224 | unsigned long state; |
| 225 | |
| 226 | /* Interrupt Throttle Rate */ |
| 227 | u32 itr; |
| 228 | u32 itr_setting; |
| 229 | u16 tx_itr; |
| 230 | u16 rx_itr; |
| 231 | |
| 232 | /* Tx - one ring per active queue */ |
| 233 | struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; |
| 234 | u32 tx_fifo_limit; |
| 235 | |
| 236 | struct napi_struct napi; |
| 237 | |
| 238 | unsigned int uncorr_errors; /* uncorrectable ECC errors */ |
| 239 | unsigned int corr_errors; /* correctable ECC errors */ |
| 240 | unsigned int restart_queue; |
| 241 | u32 txd_cmd; |
| 242 | |
| 243 | bool detect_tx_hung; |
| 244 | bool tx_hang_recheck; |
| 245 | u8 tx_timeout_factor; |
| 246 | |
| 247 | u32 tx_int_delay; |
| 248 | u32 tx_abs_int_delay; |
| 249 | |
| 250 | unsigned int total_tx_bytes; |
| 251 | unsigned int total_tx_packets; |
| 252 | unsigned int total_rx_bytes; |
| 253 | unsigned int total_rx_packets; |
| 254 | |
| 255 | /* Tx stats */ |
| 256 | u64 tpt_old; |
| 257 | u64 colc_old; |
| 258 | u32 gotc; |
| 259 | u64 gotc_old; |
| 260 | u32 tx_timeout_count; |
| 261 | u32 tx_fifo_head; |
| 262 | u32 tx_head_addr; |
| 263 | u32 tx_fifo_size; |
| 264 | u32 tx_dma_failed; |
| 265 | |
| 266 | /* Rx */ |
| 267 | bool (*clean_rx) (struct e1000_ring *ring, int *work_done, |
| 268 | int work_to_do) ____cacheline_aligned_in_smp; |
| 269 | void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count, |
| 270 | gfp_t gfp); |
| 271 | struct e1000_ring *rx_ring; |
| 272 | |
| 273 | u32 rx_int_delay; |
| 274 | u32 rx_abs_int_delay; |
| 275 | |
| 276 | /* Rx stats */ |
| 277 | u64 hw_csum_err; |
| 278 | u64 hw_csum_good; |
| 279 | u64 rx_hdr_split; |
| 280 | u32 gorc; |
| 281 | u64 gorc_old; |
| 282 | u32 alloc_rx_buff_failed; |
| 283 | u32 rx_dma_failed; |
| 284 | u32 rx_hwtstamp_cleared; |
| 285 | |
| 286 | unsigned int rx_ps_pages; |
| 287 | u16 rx_ps_bsize0; |
| 288 | u32 max_frame_size; |
| 289 | u32 min_frame_size; |
| 290 | |
| 291 | /* OS defined structs */ |
| 292 | struct net_device *netdev; |
| 293 | struct pci_dev *pdev; |
| 294 | |
| 295 | /* structs defined in e1000_hw.h */ |
| 296 | struct e1000_hw hw; |
| 297 | |
| 298 | spinlock_t stats64_lock; /* protects statistics counters */ |
| 299 | struct e1000_hw_stats stats; |
| 300 | struct e1000_phy_info phy_info; |
| 301 | struct e1000_phy_stats phy_stats; |
| 302 | |
| 303 | /* Snapshot of PHY registers */ |
| 304 | struct e1000_phy_regs phy_regs; |
| 305 | |
| 306 | struct e1000_ring test_tx_ring; |
| 307 | struct e1000_ring test_rx_ring; |
| 308 | u32 test_icr; |
| 309 | |
| 310 | u32 msg_enable; |
| 311 | unsigned int num_vectors; |
| 312 | struct msix_entry *msix_entries; |
| 313 | int int_mode; |
| 314 | u32 eiac_mask; |
| 315 | |
| 316 | u32 eeprom_wol; |
| 317 | u32 wol; |
| 318 | u32 pba; |
| 319 | u32 max_hw_frame_size; |
| 320 | |
| 321 | bool fc_autoneg; |
| 322 | |
| 323 | unsigned int flags; |
| 324 | unsigned int flags2; |
| 325 | struct work_struct downshift_task; |
| 326 | struct work_struct update_phy_task; |
| 327 | struct work_struct print_hang_task; |
| 328 | |
| 329 | int phy_hang_count; |
| 330 | |
| 331 | u16 tx_ring_count; |
| 332 | u16 rx_ring_count; |
| 333 | |
| 334 | struct hwtstamp_config hwtstamp_config; |
| 335 | struct delayed_work systim_overflow_work; |
| 336 | struct sk_buff *tx_hwtstamp_skb; |
| 337 | struct work_struct tx_hwtstamp_work; |
| 338 | spinlock_t systim_lock; /* protects SYSTIML/H regsters */ |
| 339 | struct cyclecounter cc; |
| 340 | struct timecounter tc; |
| 341 | struct ptp_clock *ptp_clock; |
| 342 | struct ptp_clock_info ptp_clock_info; |
| 343 | |
| 344 | u16 eee_advert; |
| 345 | }; |
| 346 | |
| 347 | struct e1000_info { |
| 348 | enum e1000_mac_type mac; |
| 349 | unsigned int flags; |
| 350 | unsigned int flags2; |
| 351 | u32 pba; |
| 352 | u32 max_hw_frame_size; |
| 353 | s32 (*get_variants)(struct e1000_adapter *); |
| 354 | const struct e1000_mac_operations *mac_ops; |
| 355 | const struct e1000_phy_operations *phy_ops; |
| 356 | const struct e1000_nvm_operations *nvm_ops; |
| 357 | }; |
| 358 | |
| 359 | s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); |
| 360 | |
| 361 | /* The system time is maintained by a 64-bit counter comprised of the 32-bit |
| 362 | * SYSTIMH and SYSTIML registers. How the counter increments (and therefore |
| 363 | * its resolution) is based on the contents of the TIMINCA register - it |
| 364 | * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). |
| 365 | * For the best accuracy, the incperiod should be as small as possible. The |
| 366 | * incvalue is scaled by a factor as large as possible (while still fitting |
| 367 | * in bits 23:0) so that relatively small clock corrections can be made. |
| 368 | * |
| 369 | * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of |
| 370 | * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) |
| 371 | * bits to count nanoseconds leaving the rest for fractional nonseconds. |
| 372 | */ |
| 373 | #define INCVALUE_96MHz 125 |
| 374 | #define INCVALUE_SHIFT_96MHz 17 |
| 375 | #define INCPERIOD_SHIFT_96MHz 2 |
| 376 | #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) |
| 377 | |
| 378 | #define INCVALUE_25MHz 40 |
| 379 | #define INCVALUE_SHIFT_25MHz 18 |
| 380 | #define INCPERIOD_25MHz 1 |
| 381 | |
| 382 | /* Another drawback of scaling the incvalue by a large factor is the |
| 383 | * 64-bit SYSTIM register overflows more quickly. This is dealt with |
| 384 | * by simply reading the clock before it overflows. |
| 385 | * |
| 386 | * Clock ns bits Overflows after |
| 387 | * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ |
| 388 | * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs |
| 389 | * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours |
| 390 | */ |
| 391 | #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) |
| 392 | |
| 393 | /* hardware capability, feature, and workaround flags */ |
| 394 | #define FLAG_HAS_AMT (1 << 0) |
| 395 | #define FLAG_HAS_FLASH (1 << 1) |
| 396 | #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) |
| 397 | #define FLAG_HAS_WOL (1 << 3) |
| 398 | /* reserved bit4 */ |
| 399 | #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) |
| 400 | #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) |
| 401 | #define FLAG_HAS_JUMBO_FRAMES (1 << 7) |
| 402 | #define FLAG_READ_ONLY_NVM (1 << 8) |
| 403 | #define FLAG_IS_ICH (1 << 9) |
| 404 | #define FLAG_HAS_MSIX (1 << 10) |
| 405 | #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
| 406 | #define FLAG_IS_QUAD_PORT_A (1 << 12) |
| 407 | #define FLAG_IS_QUAD_PORT (1 << 13) |
| 408 | #define FLAG_HAS_HW_TIMESTAMP (1 << 14) |
| 409 | #define FLAG_APME_IN_WUC (1 << 15) |
| 410 | #define FLAG_APME_IN_CTRL3 (1 << 16) |
| 411 | #define FLAG_APME_CHECK_PORT_B (1 << 17) |
| 412 | #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) |
| 413 | #define FLAG_NO_WAKE_UCAST (1 << 19) |
| 414 | #define FLAG_MNG_PT_ENABLED (1 << 20) |
| 415 | #define FLAG_RESET_OVERWRITES_LAA (1 << 21) |
| 416 | #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) |
| 417 | #define FLAG_TARC_SET_BIT_ZERO (1 << 23) |
| 418 | #define FLAG_RX_NEEDS_RESTART (1 << 24) |
| 419 | #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) |
| 420 | #define FLAG_SMART_POWER_DOWN (1 << 26) |
| 421 | #define FLAG_MSI_ENABLED (1 << 27) |
| 422 | /* reserved (1 << 28) */ |
| 423 | #define FLAG_TSO_FORCE (1 << 29) |
| 424 | #define FLAG_RESTART_NOW (1 << 30) |
| 425 | #define FLAG_MSI_TEST_FAILED (1 << 31) |
| 426 | |
| 427 | #define FLAG2_CRC_STRIPPING (1 << 0) |
| 428 | #define FLAG2_HAS_PHY_WAKEUP (1 << 1) |
| 429 | #define FLAG2_IS_DISCARDING (1 << 2) |
| 430 | #define FLAG2_DISABLE_ASPM_L1 (1 << 3) |
| 431 | #define FLAG2_HAS_PHY_STATS (1 << 4) |
| 432 | #define FLAG2_HAS_EEE (1 << 5) |
| 433 | #define FLAG2_DMA_BURST (1 << 6) |
| 434 | #define FLAG2_DISABLE_ASPM_L0S (1 << 7) |
| 435 | #define FLAG2_DISABLE_AIM (1 << 8) |
| 436 | #define FLAG2_CHECK_PHY_HANG (1 << 9) |
| 437 | #define FLAG2_NO_DISABLE_RX (1 << 10) |
| 438 | #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) |
| 439 | #define FLAG2_DFLT_CRC_STRIPPING (1 << 12) |
| 440 | #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) |
| 441 | |
| 442 | #define E1000_RX_DESC_PS(R, i) \ |
| 443 | (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |
| 444 | #define E1000_RX_DESC_EXT(R, i) \ |
| 445 | (&(((union e1000_rx_desc_extended *)((R).desc))[i])) |
| 446 | #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
| 447 | #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
| 448 | #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) |
| 449 | |
| 450 | enum e1000_state_t { |
| 451 | __E1000_TESTING, |
| 452 | __E1000_RESETTING, |
| 453 | __E1000_ACCESS_SHARED_RESOURCE, |
| 454 | __E1000_DOWN |
| 455 | }; |
| 456 | |
| 457 | enum latency_range { |
| 458 | lowest_latency = 0, |
| 459 | low_latency = 1, |
| 460 | bulk_latency = 2, |
| 461 | latency_invalid = 255 |
| 462 | }; |
| 463 | |
| 464 | extern char e1000e_driver_name[]; |
| 465 | extern const char e1000e_driver_version[]; |
| 466 | |
| 467 | void e1000e_check_options(struct e1000_adapter *adapter); |
| 468 | void e1000e_set_ethtool_ops(struct net_device *netdev); |
| 469 | |
| 470 | int e1000e_up(struct e1000_adapter *adapter); |
| 471 | void e1000e_down(struct e1000_adapter *adapter, bool reset); |
| 472 | void e1000e_reinit_locked(struct e1000_adapter *adapter); |
| 473 | void e1000e_reset(struct e1000_adapter *adapter); |
| 474 | void e1000e_power_up_phy(struct e1000_adapter *adapter); |
| 475 | int e1000e_setup_rx_resources(struct e1000_ring *ring); |
| 476 | int e1000e_setup_tx_resources(struct e1000_ring *ring); |
| 477 | void e1000e_free_rx_resources(struct e1000_ring *ring); |
| 478 | void e1000e_free_tx_resources(struct e1000_ring *ring); |
| 479 | struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, |
| 480 | struct rtnl_link_stats64 *stats); |
| 481 | void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); |
| 482 | void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); |
| 483 | void e1000e_get_hw_control(struct e1000_adapter *adapter); |
| 484 | void e1000e_release_hw_control(struct e1000_adapter *adapter); |
| 485 | void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); |
| 486 | |
| 487 | extern unsigned int copybreak; |
| 488 | |
| 489 | extern const struct e1000_info e1000_82571_info; |
| 490 | extern const struct e1000_info e1000_82572_info; |
| 491 | extern const struct e1000_info e1000_82573_info; |
| 492 | extern const struct e1000_info e1000_82574_info; |
| 493 | extern const struct e1000_info e1000_82583_info; |
| 494 | extern const struct e1000_info e1000_ich8_info; |
| 495 | extern const struct e1000_info e1000_ich9_info; |
| 496 | extern const struct e1000_info e1000_ich10_info; |
| 497 | extern const struct e1000_info e1000_pch_info; |
| 498 | extern const struct e1000_info e1000_pch2_info; |
| 499 | extern const struct e1000_info e1000_pch_lpt_info; |
| 500 | extern const struct e1000_info e1000_es2_info; |
| 501 | |
| 502 | void e1000e_ptp_init(struct e1000_adapter *adapter); |
| 503 | void e1000e_ptp_remove(struct e1000_adapter *adapter); |
| 504 | |
| 505 | static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
| 506 | { |
| 507 | return hw->phy.ops.reset(hw); |
| 508 | } |
| 509 | |
| 510 | static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) |
| 511 | { |
| 512 | return hw->phy.ops.read_reg(hw, offset, data); |
| 513 | } |
| 514 | |
| 515 | static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
| 516 | { |
| 517 | return hw->phy.ops.read_reg_locked(hw, offset, data); |
| 518 | } |
| 519 | |
| 520 | static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) |
| 521 | { |
| 522 | return hw->phy.ops.write_reg(hw, offset, data); |
| 523 | } |
| 524 | |
| 525 | static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) |
| 526 | { |
| 527 | return hw->phy.ops.write_reg_locked(hw, offset, data); |
| 528 | } |
| 529 | |
| 530 | void e1000e_reload_nvm_generic(struct e1000_hw *hw); |
| 531 | |
| 532 | static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) |
| 533 | { |
| 534 | if (hw->mac.ops.read_mac_addr) |
| 535 | return hw->mac.ops.read_mac_addr(hw); |
| 536 | |
| 537 | return e1000_read_mac_addr_generic(hw); |
| 538 | } |
| 539 | |
| 540 | static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) |
| 541 | { |
| 542 | return hw->nvm.ops.validate(hw); |
| 543 | } |
| 544 | |
| 545 | static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) |
| 546 | { |
| 547 | return hw->nvm.ops.update(hw); |
| 548 | } |
| 549 | |
| 550 | static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
| 551 | u16 *data) |
| 552 | { |
| 553 | return hw->nvm.ops.read(hw, offset, words, data); |
| 554 | } |
| 555 | |
| 556 | static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
| 557 | u16 *data) |
| 558 | { |
| 559 | return hw->nvm.ops.write(hw, offset, words, data); |
| 560 | } |
| 561 | |
| 562 | static inline s32 e1000_get_phy_info(struct e1000_hw *hw) |
| 563 | { |
| 564 | return hw->phy.ops.get_info(hw); |
| 565 | } |
| 566 | |
| 567 | static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) |
| 568 | { |
| 569 | return readl(hw->hw_addr + reg); |
| 570 | } |
| 571 | |
| 572 | #define er32(reg) __er32(hw, E1000_##reg) |
| 573 | |
| 574 | /** |
| 575 | * __ew32_prepare - prepare to write to MAC CSR register on certain parts |
| 576 | * @hw: pointer to the HW structure |
| 577 | * |
| 578 | * When updating the MAC CSR registers, the Manageability Engine (ME) could |
| 579 | * be accessing the registers at the same time. Normally, this is handled in |
| 580 | * h/w by an arbiter but on some parts there is a bug that acknowledges Host |
| 581 | * accesses later than it should which could result in the register to have |
| 582 | * an incorrect value. Workaround this by checking the FWSM register which |
| 583 | * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set |
| 584 | * and try again a number of times. |
| 585 | **/ |
| 586 | static inline s32 __ew32_prepare(struct e1000_hw *hw) |
| 587 | { |
| 588 | s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; |
| 589 | |
| 590 | while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) |
| 591 | udelay(50); |
| 592 | |
| 593 | return i; |
| 594 | } |
| 595 | |
| 596 | static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) |
| 597 | { |
| 598 | if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
| 599 | __ew32_prepare(hw); |
| 600 | |
| 601 | writel(val, hw->hw_addr + reg); |
| 602 | } |
| 603 | |
| 604 | #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) |
| 605 | |
| 606 | #define e1e_flush() er32(STATUS) |
| 607 | |
| 608 | #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ |
| 609 | (__ew32((a), (reg + ((offset) << 2)), (value))) |
| 610 | |
| 611 | #define E1000_READ_REG_ARRAY(a, reg, offset) \ |
| 612 | (readl((a)->hw_addr + reg + ((offset) << 2))) |
| 613 | |
| 614 | #endif /* _E1000_H_ */ |