| 1 | /* |
| 2 | * Copyright (c) 2016-2017 Hisilicon Limited. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/acpi.h> |
| 11 | #include <linux/device.h> |
| 12 | #include <linux/etherdevice.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/netdevice.h> |
| 18 | #include <linux/pci.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/if_vlan.h> |
| 21 | #include <net/rtnetlink.h> |
| 22 | #include "hclge_cmd.h" |
| 23 | #include "hclge_dcb.h" |
| 24 | #include "hclge_main.h" |
| 25 | #include "hclge_mbx.h" |
| 26 | #include "hclge_mdio.h" |
| 27 | #include "hclge_tm.h" |
| 28 | #include "hnae3.h" |
| 29 | |
| 30 | #define HCLGE_NAME "hclge" |
| 31 | #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) |
| 32 | #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) |
| 33 | #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) |
| 34 | #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) |
| 35 | |
| 36 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, |
| 37 | enum hclge_mta_dmac_sel_type mta_mac_sel, |
| 38 | bool enable); |
| 39 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); |
| 40 | static int hclge_init_vlan_config(struct hclge_dev *hdev); |
| 41 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); |
| 42 | |
| 43 | static struct hnae3_ae_algo ae_algo; |
| 44 | |
| 45 | static const struct pci_device_id ae_algo_pci_tbl[] = { |
| 46 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, |
| 47 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, |
| 48 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, |
| 49 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, |
| 50 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, |
| 51 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, |
| 52 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, |
| 53 | /* required last entry */ |
| 54 | {0, } |
| 55 | }; |
| 56 | |
| 57 | MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); |
| 58 | |
| 59 | static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { |
| 60 | "Mac Loopback test", |
| 61 | "Serdes Loopback test", |
| 62 | "Phy Loopback test" |
| 63 | }; |
| 64 | |
| 65 | static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { |
| 66 | {"igu_rx_oversize_pkt", |
| 67 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, |
| 68 | {"igu_rx_undersize_pkt", |
| 69 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, |
| 70 | {"igu_rx_out_all_pkt", |
| 71 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, |
| 72 | {"igu_rx_uni_pkt", |
| 73 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, |
| 74 | {"igu_rx_multi_pkt", |
| 75 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, |
| 76 | {"igu_rx_broad_pkt", |
| 77 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, |
| 78 | {"egu_tx_out_all_pkt", |
| 79 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, |
| 80 | {"egu_tx_uni_pkt", |
| 81 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, |
| 82 | {"egu_tx_multi_pkt", |
| 83 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, |
| 84 | {"egu_tx_broad_pkt", |
| 85 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, |
| 86 | {"ssu_ppp_mac_key_num", |
| 87 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, |
| 88 | {"ssu_ppp_host_key_num", |
| 89 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, |
| 90 | {"ppp_ssu_mac_rlt_num", |
| 91 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, |
| 92 | {"ppp_ssu_host_rlt_num", |
| 93 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, |
| 94 | {"ssu_tx_in_num", |
| 95 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, |
| 96 | {"ssu_tx_out_num", |
| 97 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, |
| 98 | {"ssu_rx_in_num", |
| 99 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, |
| 100 | {"ssu_rx_out_num", |
| 101 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} |
| 102 | }; |
| 103 | |
| 104 | static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { |
| 105 | {"igu_rx_err_pkt", |
| 106 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, |
| 107 | {"igu_rx_no_eof_pkt", |
| 108 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, |
| 109 | {"igu_rx_no_sof_pkt", |
| 110 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, |
| 111 | {"egu_tx_1588_pkt", |
| 112 | HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, |
| 113 | {"ssu_full_drop_num", |
| 114 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, |
| 115 | {"ssu_part_drop_num", |
| 116 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, |
| 117 | {"ppp_key_drop_num", |
| 118 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, |
| 119 | {"ppp_rlt_drop_num", |
| 120 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, |
| 121 | {"ssu_key_drop_num", |
| 122 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, |
| 123 | {"pkt_curr_buf_cnt", |
| 124 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, |
| 125 | {"qcn_fb_rcv_cnt", |
| 126 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, |
| 127 | {"qcn_fb_drop_cnt", |
| 128 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, |
| 129 | {"qcn_fb_invaild_cnt", |
| 130 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, |
| 131 | {"rx_packet_tc0_in_cnt", |
| 132 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, |
| 133 | {"rx_packet_tc1_in_cnt", |
| 134 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, |
| 135 | {"rx_packet_tc2_in_cnt", |
| 136 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, |
| 137 | {"rx_packet_tc3_in_cnt", |
| 138 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, |
| 139 | {"rx_packet_tc4_in_cnt", |
| 140 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, |
| 141 | {"rx_packet_tc5_in_cnt", |
| 142 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, |
| 143 | {"rx_packet_tc6_in_cnt", |
| 144 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, |
| 145 | {"rx_packet_tc7_in_cnt", |
| 146 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, |
| 147 | {"rx_packet_tc0_out_cnt", |
| 148 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, |
| 149 | {"rx_packet_tc1_out_cnt", |
| 150 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, |
| 151 | {"rx_packet_tc2_out_cnt", |
| 152 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, |
| 153 | {"rx_packet_tc3_out_cnt", |
| 154 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, |
| 155 | {"rx_packet_tc4_out_cnt", |
| 156 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, |
| 157 | {"rx_packet_tc5_out_cnt", |
| 158 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, |
| 159 | {"rx_packet_tc6_out_cnt", |
| 160 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, |
| 161 | {"rx_packet_tc7_out_cnt", |
| 162 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, |
| 163 | {"tx_packet_tc0_in_cnt", |
| 164 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, |
| 165 | {"tx_packet_tc1_in_cnt", |
| 166 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, |
| 167 | {"tx_packet_tc2_in_cnt", |
| 168 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, |
| 169 | {"tx_packet_tc3_in_cnt", |
| 170 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, |
| 171 | {"tx_packet_tc4_in_cnt", |
| 172 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, |
| 173 | {"tx_packet_tc5_in_cnt", |
| 174 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, |
| 175 | {"tx_packet_tc6_in_cnt", |
| 176 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, |
| 177 | {"tx_packet_tc7_in_cnt", |
| 178 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, |
| 179 | {"tx_packet_tc0_out_cnt", |
| 180 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, |
| 181 | {"tx_packet_tc1_out_cnt", |
| 182 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, |
| 183 | {"tx_packet_tc2_out_cnt", |
| 184 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, |
| 185 | {"tx_packet_tc3_out_cnt", |
| 186 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, |
| 187 | {"tx_packet_tc4_out_cnt", |
| 188 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, |
| 189 | {"tx_packet_tc5_out_cnt", |
| 190 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, |
| 191 | {"tx_packet_tc6_out_cnt", |
| 192 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, |
| 193 | {"tx_packet_tc7_out_cnt", |
| 194 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, |
| 195 | {"pkt_curr_buf_tc0_cnt", |
| 196 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, |
| 197 | {"pkt_curr_buf_tc1_cnt", |
| 198 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, |
| 199 | {"pkt_curr_buf_tc2_cnt", |
| 200 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, |
| 201 | {"pkt_curr_buf_tc3_cnt", |
| 202 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, |
| 203 | {"pkt_curr_buf_tc4_cnt", |
| 204 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, |
| 205 | {"pkt_curr_buf_tc5_cnt", |
| 206 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, |
| 207 | {"pkt_curr_buf_tc6_cnt", |
| 208 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, |
| 209 | {"pkt_curr_buf_tc7_cnt", |
| 210 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, |
| 211 | {"mb_uncopy_num", |
| 212 | HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, |
| 213 | {"lo_pri_unicast_rlt_drop_num", |
| 214 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, |
| 215 | {"hi_pri_multicast_rlt_drop_num", |
| 216 | HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, |
| 217 | {"lo_pri_multicast_rlt_drop_num", |
| 218 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, |
| 219 | {"rx_oq_drop_pkt_cnt", |
| 220 | HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, |
| 221 | {"tx_oq_drop_pkt_cnt", |
| 222 | HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, |
| 223 | {"nic_l2_err_drop_pkt_cnt", |
| 224 | HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, |
| 225 | {"roc_l2_err_drop_pkt_cnt", |
| 226 | HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} |
| 227 | }; |
| 228 | |
| 229 | static const struct hclge_comm_stats_str g_mac_stats_string[] = { |
| 230 | {"mac_tx_mac_pause_num", |
| 231 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, |
| 232 | {"mac_rx_mac_pause_num", |
| 233 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, |
| 234 | {"mac_tx_pfc_pri0_pkt_num", |
| 235 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, |
| 236 | {"mac_tx_pfc_pri1_pkt_num", |
| 237 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, |
| 238 | {"mac_tx_pfc_pri2_pkt_num", |
| 239 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, |
| 240 | {"mac_tx_pfc_pri3_pkt_num", |
| 241 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, |
| 242 | {"mac_tx_pfc_pri4_pkt_num", |
| 243 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, |
| 244 | {"mac_tx_pfc_pri5_pkt_num", |
| 245 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, |
| 246 | {"mac_tx_pfc_pri6_pkt_num", |
| 247 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, |
| 248 | {"mac_tx_pfc_pri7_pkt_num", |
| 249 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, |
| 250 | {"mac_rx_pfc_pri0_pkt_num", |
| 251 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, |
| 252 | {"mac_rx_pfc_pri1_pkt_num", |
| 253 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, |
| 254 | {"mac_rx_pfc_pri2_pkt_num", |
| 255 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, |
| 256 | {"mac_rx_pfc_pri3_pkt_num", |
| 257 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, |
| 258 | {"mac_rx_pfc_pri4_pkt_num", |
| 259 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, |
| 260 | {"mac_rx_pfc_pri5_pkt_num", |
| 261 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, |
| 262 | {"mac_rx_pfc_pri6_pkt_num", |
| 263 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, |
| 264 | {"mac_rx_pfc_pri7_pkt_num", |
| 265 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, |
| 266 | {"mac_tx_total_pkt_num", |
| 267 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, |
| 268 | {"mac_tx_total_oct_num", |
| 269 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, |
| 270 | {"mac_tx_good_pkt_num", |
| 271 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, |
| 272 | {"mac_tx_bad_pkt_num", |
| 273 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, |
| 274 | {"mac_tx_good_oct_num", |
| 275 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, |
| 276 | {"mac_tx_bad_oct_num", |
| 277 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, |
| 278 | {"mac_tx_uni_pkt_num", |
| 279 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, |
| 280 | {"mac_tx_multi_pkt_num", |
| 281 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, |
| 282 | {"mac_tx_broad_pkt_num", |
| 283 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, |
| 284 | {"mac_tx_undersize_pkt_num", |
| 285 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, |
| 286 | {"mac_tx_oversize_pkt_num", |
| 287 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, |
| 288 | {"mac_tx_64_oct_pkt_num", |
| 289 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, |
| 290 | {"mac_tx_65_127_oct_pkt_num", |
| 291 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, |
| 292 | {"mac_tx_128_255_oct_pkt_num", |
| 293 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, |
| 294 | {"mac_tx_256_511_oct_pkt_num", |
| 295 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, |
| 296 | {"mac_tx_512_1023_oct_pkt_num", |
| 297 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, |
| 298 | {"mac_tx_1024_1518_oct_pkt_num", |
| 299 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, |
| 300 | {"mac_tx_1519_2047_oct_pkt_num", |
| 301 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, |
| 302 | {"mac_tx_2048_4095_oct_pkt_num", |
| 303 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, |
| 304 | {"mac_tx_4096_8191_oct_pkt_num", |
| 305 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, |
| 306 | {"mac_tx_8192_9216_oct_pkt_num", |
| 307 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, |
| 308 | {"mac_tx_9217_12287_oct_pkt_num", |
| 309 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, |
| 310 | {"mac_tx_12288_16383_oct_pkt_num", |
| 311 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, |
| 312 | {"mac_tx_1519_max_good_pkt_num", |
| 313 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, |
| 314 | {"mac_tx_1519_max_bad_pkt_num", |
| 315 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, |
| 316 | {"mac_rx_total_pkt_num", |
| 317 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, |
| 318 | {"mac_rx_total_oct_num", |
| 319 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, |
| 320 | {"mac_rx_good_pkt_num", |
| 321 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, |
| 322 | {"mac_rx_bad_pkt_num", |
| 323 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, |
| 324 | {"mac_rx_good_oct_num", |
| 325 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, |
| 326 | {"mac_rx_bad_oct_num", |
| 327 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, |
| 328 | {"mac_rx_uni_pkt_num", |
| 329 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, |
| 330 | {"mac_rx_multi_pkt_num", |
| 331 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, |
| 332 | {"mac_rx_broad_pkt_num", |
| 333 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, |
| 334 | {"mac_rx_undersize_pkt_num", |
| 335 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, |
| 336 | {"mac_rx_oversize_pkt_num", |
| 337 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, |
| 338 | {"mac_rx_64_oct_pkt_num", |
| 339 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, |
| 340 | {"mac_rx_65_127_oct_pkt_num", |
| 341 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, |
| 342 | {"mac_rx_128_255_oct_pkt_num", |
| 343 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, |
| 344 | {"mac_rx_256_511_oct_pkt_num", |
| 345 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, |
| 346 | {"mac_rx_512_1023_oct_pkt_num", |
| 347 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, |
| 348 | {"mac_rx_1024_1518_oct_pkt_num", |
| 349 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, |
| 350 | {"mac_rx_1519_2047_oct_pkt_num", |
| 351 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, |
| 352 | {"mac_rx_2048_4095_oct_pkt_num", |
| 353 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, |
| 354 | {"mac_rx_4096_8191_oct_pkt_num", |
| 355 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, |
| 356 | {"mac_rx_8192_9216_oct_pkt_num", |
| 357 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, |
| 358 | {"mac_rx_9217_12287_oct_pkt_num", |
| 359 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, |
| 360 | {"mac_rx_12288_16383_oct_pkt_num", |
| 361 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, |
| 362 | {"mac_rx_1519_max_good_pkt_num", |
| 363 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, |
| 364 | {"mac_rx_1519_max_bad_pkt_num", |
| 365 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, |
| 366 | |
| 367 | {"mac_tx_fragment_pkt_num", |
| 368 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, |
| 369 | {"mac_tx_undermin_pkt_num", |
| 370 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, |
| 371 | {"mac_tx_jabber_pkt_num", |
| 372 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, |
| 373 | {"mac_tx_err_all_pkt_num", |
| 374 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, |
| 375 | {"mac_tx_from_app_good_pkt_num", |
| 376 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, |
| 377 | {"mac_tx_from_app_bad_pkt_num", |
| 378 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, |
| 379 | {"mac_rx_fragment_pkt_num", |
| 380 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, |
| 381 | {"mac_rx_undermin_pkt_num", |
| 382 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, |
| 383 | {"mac_rx_jabber_pkt_num", |
| 384 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, |
| 385 | {"mac_rx_fcs_err_pkt_num", |
| 386 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, |
| 387 | {"mac_rx_send_app_good_pkt_num", |
| 388 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, |
| 389 | {"mac_rx_send_app_bad_pkt_num", |
| 390 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} |
| 391 | }; |
| 392 | |
| 393 | static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { |
| 394 | { |
| 395 | .flags = HCLGE_MAC_MGR_MASK_VLAN_B, |
| 396 | .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), |
| 397 | .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), |
| 398 | .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), |
| 399 | .i_port_bitmap = 0x1, |
| 400 | }, |
| 401 | }; |
| 402 | |
| 403 | static int hclge_64_bit_update_stats(struct hclge_dev *hdev) |
| 404 | { |
| 405 | #define HCLGE_64_BIT_CMD_NUM 5 |
| 406 | #define HCLGE_64_BIT_RTN_DATANUM 4 |
| 407 | u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); |
| 408 | struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; |
| 409 | __le64 *desc_data; |
| 410 | int i, k, n; |
| 411 | int ret; |
| 412 | |
| 413 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); |
| 414 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); |
| 415 | if (ret) { |
| 416 | dev_err(&hdev->pdev->dev, |
| 417 | "Get 64 bit pkt stats fail, status = %d.\n", ret); |
| 418 | return ret; |
| 419 | } |
| 420 | |
| 421 | for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { |
| 422 | if (unlikely(i == 0)) { |
| 423 | desc_data = (__le64 *)(&desc[i].data[0]); |
| 424 | n = HCLGE_64_BIT_RTN_DATANUM - 1; |
| 425 | } else { |
| 426 | desc_data = (__le64 *)(&desc[i]); |
| 427 | n = HCLGE_64_BIT_RTN_DATANUM; |
| 428 | } |
| 429 | for (k = 0; k < n; k++) { |
| 430 | *data++ += le64_to_cpu(*desc_data); |
| 431 | desc_data++; |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) |
| 439 | { |
| 440 | stats->pkt_curr_buf_cnt = 0; |
| 441 | stats->pkt_curr_buf_tc0_cnt = 0; |
| 442 | stats->pkt_curr_buf_tc1_cnt = 0; |
| 443 | stats->pkt_curr_buf_tc2_cnt = 0; |
| 444 | stats->pkt_curr_buf_tc3_cnt = 0; |
| 445 | stats->pkt_curr_buf_tc4_cnt = 0; |
| 446 | stats->pkt_curr_buf_tc5_cnt = 0; |
| 447 | stats->pkt_curr_buf_tc6_cnt = 0; |
| 448 | stats->pkt_curr_buf_tc7_cnt = 0; |
| 449 | } |
| 450 | |
| 451 | static int hclge_32_bit_update_stats(struct hclge_dev *hdev) |
| 452 | { |
| 453 | #define HCLGE_32_BIT_CMD_NUM 8 |
| 454 | #define HCLGE_32_BIT_RTN_DATANUM 8 |
| 455 | |
| 456 | struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; |
| 457 | struct hclge_32_bit_stats *all_32_bit_stats; |
| 458 | __le32 *desc_data; |
| 459 | int i, k, n; |
| 460 | u64 *data; |
| 461 | int ret; |
| 462 | |
| 463 | all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; |
| 464 | data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); |
| 465 | |
| 466 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); |
| 467 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); |
| 468 | if (ret) { |
| 469 | dev_err(&hdev->pdev->dev, |
| 470 | "Get 32 bit pkt stats fail, status = %d.\n", ret); |
| 471 | |
| 472 | return ret; |
| 473 | } |
| 474 | |
| 475 | hclge_reset_partial_32bit_counter(all_32_bit_stats); |
| 476 | for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { |
| 477 | if (unlikely(i == 0)) { |
| 478 | __le16 *desc_data_16bit; |
| 479 | |
| 480 | all_32_bit_stats->igu_rx_err_pkt += |
| 481 | le32_to_cpu(desc[i].data[0]); |
| 482 | |
| 483 | desc_data_16bit = (__le16 *)&desc[i].data[1]; |
| 484 | all_32_bit_stats->igu_rx_no_eof_pkt += |
| 485 | le16_to_cpu(*desc_data_16bit); |
| 486 | |
| 487 | desc_data_16bit++; |
| 488 | all_32_bit_stats->igu_rx_no_sof_pkt += |
| 489 | le16_to_cpu(*desc_data_16bit); |
| 490 | |
| 491 | desc_data = &desc[i].data[2]; |
| 492 | n = HCLGE_32_BIT_RTN_DATANUM - 4; |
| 493 | } else { |
| 494 | desc_data = (__le32 *)&desc[i]; |
| 495 | n = HCLGE_32_BIT_RTN_DATANUM; |
| 496 | } |
| 497 | for (k = 0; k < n; k++) { |
| 498 | *data++ += le32_to_cpu(*desc_data); |
| 499 | desc_data++; |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | static int hclge_mac_update_stats(struct hclge_dev *hdev) |
| 507 | { |
| 508 | #define HCLGE_MAC_CMD_NUM 21 |
| 509 | #define HCLGE_RTN_DATA_NUM 4 |
| 510 | |
| 511 | u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); |
| 512 | struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; |
| 513 | __le64 *desc_data; |
| 514 | int i, k, n; |
| 515 | int ret; |
| 516 | |
| 517 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); |
| 518 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); |
| 519 | if (ret) { |
| 520 | dev_err(&hdev->pdev->dev, |
| 521 | "Get MAC pkt stats fail, status = %d.\n", ret); |
| 522 | |
| 523 | return ret; |
| 524 | } |
| 525 | |
| 526 | for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { |
| 527 | if (unlikely(i == 0)) { |
| 528 | desc_data = (__le64 *)(&desc[i].data[0]); |
| 529 | n = HCLGE_RTN_DATA_NUM - 2; |
| 530 | } else { |
| 531 | desc_data = (__le64 *)(&desc[i]); |
| 532 | n = HCLGE_RTN_DATA_NUM; |
| 533 | } |
| 534 | for (k = 0; k < n; k++) { |
| 535 | *data++ += le64_to_cpu(*desc_data); |
| 536 | desc_data++; |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | return 0; |
| 541 | } |
| 542 | |
| 543 | static int hclge_tqps_update_stats(struct hnae3_handle *handle) |
| 544 | { |
| 545 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; |
| 546 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 547 | struct hclge_dev *hdev = vport->back; |
| 548 | struct hnae3_queue *queue; |
| 549 | struct hclge_desc desc[1]; |
| 550 | struct hclge_tqp *tqp; |
| 551 | int ret, i; |
| 552 | |
| 553 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 554 | queue = handle->kinfo.tqp[i]; |
| 555 | tqp = container_of(queue, struct hclge_tqp, q); |
| 556 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ |
| 557 | hclge_cmd_setup_basic_desc(&desc[0], |
| 558 | HCLGE_OPC_QUERY_RX_STATUS, |
| 559 | true); |
| 560 | |
| 561 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
| 562 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
| 563 | if (ret) { |
| 564 | dev_err(&hdev->pdev->dev, |
| 565 | "Query tqp stat fail, status = %d,queue = %d\n", |
| 566 | ret, i); |
| 567 | return ret; |
| 568 | } |
| 569 | tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += |
| 570 | le32_to_cpu(desc[0].data[1]); |
| 571 | } |
| 572 | |
| 573 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 574 | queue = handle->kinfo.tqp[i]; |
| 575 | tqp = container_of(queue, struct hclge_tqp, q); |
| 576 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ |
| 577 | hclge_cmd_setup_basic_desc(&desc[0], |
| 578 | HCLGE_OPC_QUERY_TX_STATUS, |
| 579 | true); |
| 580 | |
| 581 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
| 582 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
| 583 | if (ret) { |
| 584 | dev_err(&hdev->pdev->dev, |
| 585 | "Query tqp stat fail, status = %d,queue = %d\n", |
| 586 | ret, i); |
| 587 | return ret; |
| 588 | } |
| 589 | tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += |
| 590 | le32_to_cpu(desc[0].data[1]); |
| 591 | } |
| 592 | |
| 593 | return 0; |
| 594 | } |
| 595 | |
| 596 | static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) |
| 597 | { |
| 598 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; |
| 599 | struct hclge_tqp *tqp; |
| 600 | u64 *buff = data; |
| 601 | int i; |
| 602 | |
| 603 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 604 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); |
| 605 | *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; |
| 606 | } |
| 607 | |
| 608 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 609 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); |
| 610 | *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; |
| 611 | } |
| 612 | |
| 613 | return buff; |
| 614 | } |
| 615 | |
| 616 | static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) |
| 617 | { |
| 618 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; |
| 619 | |
| 620 | return kinfo->num_tqps * (2); |
| 621 | } |
| 622 | |
| 623 | static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) |
| 624 | { |
| 625 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; |
| 626 | u8 *buff = data; |
| 627 | int i = 0; |
| 628 | |
| 629 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 630 | struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], |
| 631 | struct hclge_tqp, q); |
| 632 | snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", |
| 633 | tqp->index); |
| 634 | buff = buff + ETH_GSTRING_LEN; |
| 635 | } |
| 636 | |
| 637 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 638 | struct hclge_tqp *tqp = container_of(kinfo->tqp[i], |
| 639 | struct hclge_tqp, q); |
| 640 | snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", |
| 641 | tqp->index); |
| 642 | buff = buff + ETH_GSTRING_LEN; |
| 643 | } |
| 644 | |
| 645 | return buff; |
| 646 | } |
| 647 | |
| 648 | static u64 *hclge_comm_get_stats(void *comm_stats, |
| 649 | const struct hclge_comm_stats_str strs[], |
| 650 | int size, u64 *data) |
| 651 | { |
| 652 | u64 *buf = data; |
| 653 | u32 i; |
| 654 | |
| 655 | for (i = 0; i < size; i++) |
| 656 | buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); |
| 657 | |
| 658 | return buf + size; |
| 659 | } |
| 660 | |
| 661 | static u8 *hclge_comm_get_strings(u32 stringset, |
| 662 | const struct hclge_comm_stats_str strs[], |
| 663 | int size, u8 *data) |
| 664 | { |
| 665 | char *buff = (char *)data; |
| 666 | u32 i; |
| 667 | |
| 668 | if (stringset != ETH_SS_STATS) |
| 669 | return buff; |
| 670 | |
| 671 | for (i = 0; i < size; i++) { |
| 672 | snprintf(buff, ETH_GSTRING_LEN, |
| 673 | strs[i].desc); |
| 674 | buff = buff + ETH_GSTRING_LEN; |
| 675 | } |
| 676 | |
| 677 | return (u8 *)buff; |
| 678 | } |
| 679 | |
| 680 | static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, |
| 681 | struct net_device_stats *net_stats) |
| 682 | { |
| 683 | net_stats->tx_dropped = 0; |
| 684 | net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; |
| 685 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; |
| 686 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; |
| 687 | |
| 688 | net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
| 689 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; |
| 690 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; |
| 691 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; |
| 692 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
| 693 | |
| 694 | net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; |
| 695 | net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; |
| 696 | |
| 697 | net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
| 698 | net_stats->rx_length_errors = |
| 699 | hw_stats->mac_stats.mac_rx_undersize_pkt_num; |
| 700 | net_stats->rx_length_errors += |
| 701 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
| 702 | net_stats->rx_over_errors = |
| 703 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
| 704 | } |
| 705 | |
| 706 | static void hclge_update_stats_for_all(struct hclge_dev *hdev) |
| 707 | { |
| 708 | struct hnae3_handle *handle; |
| 709 | int status; |
| 710 | |
| 711 | handle = &hdev->vport[0].nic; |
| 712 | if (handle->client) { |
| 713 | status = hclge_tqps_update_stats(handle); |
| 714 | if (status) { |
| 715 | dev_err(&hdev->pdev->dev, |
| 716 | "Update TQPS stats fail, status = %d.\n", |
| 717 | status); |
| 718 | } |
| 719 | } |
| 720 | |
| 721 | status = hclge_mac_update_stats(hdev); |
| 722 | if (status) |
| 723 | dev_err(&hdev->pdev->dev, |
| 724 | "Update MAC stats fail, status = %d.\n", status); |
| 725 | |
| 726 | status = hclge_32_bit_update_stats(hdev); |
| 727 | if (status) |
| 728 | dev_err(&hdev->pdev->dev, |
| 729 | "Update 32 bit stats fail, status = %d.\n", |
| 730 | status); |
| 731 | |
| 732 | hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); |
| 733 | } |
| 734 | |
| 735 | static void hclge_update_stats(struct hnae3_handle *handle, |
| 736 | struct net_device_stats *net_stats) |
| 737 | { |
| 738 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 739 | struct hclge_dev *hdev = vport->back; |
| 740 | struct hclge_hw_stats *hw_stats = &hdev->hw_stats; |
| 741 | int status; |
| 742 | |
| 743 | if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) |
| 744 | return; |
| 745 | |
| 746 | status = hclge_mac_update_stats(hdev); |
| 747 | if (status) |
| 748 | dev_err(&hdev->pdev->dev, |
| 749 | "Update MAC stats fail, status = %d.\n", |
| 750 | status); |
| 751 | |
| 752 | status = hclge_32_bit_update_stats(hdev); |
| 753 | if (status) |
| 754 | dev_err(&hdev->pdev->dev, |
| 755 | "Update 32 bit stats fail, status = %d.\n", |
| 756 | status); |
| 757 | |
| 758 | status = hclge_64_bit_update_stats(hdev); |
| 759 | if (status) |
| 760 | dev_err(&hdev->pdev->dev, |
| 761 | "Update 64 bit stats fail, status = %d.\n", |
| 762 | status); |
| 763 | |
| 764 | status = hclge_tqps_update_stats(handle); |
| 765 | if (status) |
| 766 | dev_err(&hdev->pdev->dev, |
| 767 | "Update TQPS stats fail, status = %d.\n", |
| 768 | status); |
| 769 | |
| 770 | hclge_update_netstat(hw_stats, net_stats); |
| 771 | |
| 772 | clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); |
| 773 | } |
| 774 | |
| 775 | static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) |
| 776 | { |
| 777 | #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 |
| 778 | |
| 779 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 780 | struct hclge_dev *hdev = vport->back; |
| 781 | int count = 0; |
| 782 | |
| 783 | /* Loopback test support rules: |
| 784 | * mac: only GE mode support |
| 785 | * serdes: all mac mode will support include GE/XGE/LGE/CGE |
| 786 | * phy: only support when phy device exist on board |
| 787 | */ |
| 788 | if (stringset == ETH_SS_TEST) { |
| 789 | /* clear loopback bit flags at first */ |
| 790 | handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); |
| 791 | if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || |
| 792 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || |
| 793 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { |
| 794 | count += 1; |
| 795 | handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; |
| 796 | } else { |
| 797 | count = -EOPNOTSUPP; |
| 798 | } |
| 799 | } else if (stringset == ETH_SS_STATS) { |
| 800 | count = ARRAY_SIZE(g_mac_stats_string) + |
| 801 | ARRAY_SIZE(g_all_32bit_stats_string) + |
| 802 | ARRAY_SIZE(g_all_64bit_stats_string) + |
| 803 | hclge_tqps_get_sset_count(handle, stringset); |
| 804 | } |
| 805 | |
| 806 | return count; |
| 807 | } |
| 808 | |
| 809 | static void hclge_get_strings(struct hnae3_handle *handle, |
| 810 | u32 stringset, |
| 811 | u8 *data) |
| 812 | { |
| 813 | u8 *p = (char *)data; |
| 814 | int size; |
| 815 | |
| 816 | if (stringset == ETH_SS_STATS) { |
| 817 | size = ARRAY_SIZE(g_mac_stats_string); |
| 818 | p = hclge_comm_get_strings(stringset, |
| 819 | g_mac_stats_string, |
| 820 | size, |
| 821 | p); |
| 822 | size = ARRAY_SIZE(g_all_32bit_stats_string); |
| 823 | p = hclge_comm_get_strings(stringset, |
| 824 | g_all_32bit_stats_string, |
| 825 | size, |
| 826 | p); |
| 827 | size = ARRAY_SIZE(g_all_64bit_stats_string); |
| 828 | p = hclge_comm_get_strings(stringset, |
| 829 | g_all_64bit_stats_string, |
| 830 | size, |
| 831 | p); |
| 832 | p = hclge_tqps_get_strings(handle, p); |
| 833 | } else if (stringset == ETH_SS_TEST) { |
| 834 | if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { |
| 835 | memcpy(p, |
| 836 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], |
| 837 | ETH_GSTRING_LEN); |
| 838 | p += ETH_GSTRING_LEN; |
| 839 | } |
| 840 | if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { |
| 841 | memcpy(p, |
| 842 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], |
| 843 | ETH_GSTRING_LEN); |
| 844 | p += ETH_GSTRING_LEN; |
| 845 | } |
| 846 | if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { |
| 847 | memcpy(p, |
| 848 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], |
| 849 | ETH_GSTRING_LEN); |
| 850 | p += ETH_GSTRING_LEN; |
| 851 | } |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) |
| 856 | { |
| 857 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 858 | struct hclge_dev *hdev = vport->back; |
| 859 | u64 *p; |
| 860 | |
| 861 | p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, |
| 862 | g_mac_stats_string, |
| 863 | ARRAY_SIZE(g_mac_stats_string), |
| 864 | data); |
| 865 | p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, |
| 866 | g_all_32bit_stats_string, |
| 867 | ARRAY_SIZE(g_all_32bit_stats_string), |
| 868 | p); |
| 869 | p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, |
| 870 | g_all_64bit_stats_string, |
| 871 | ARRAY_SIZE(g_all_64bit_stats_string), |
| 872 | p); |
| 873 | p = hclge_tqps_get_stats(handle, p); |
| 874 | } |
| 875 | |
| 876 | static int hclge_parse_func_status(struct hclge_dev *hdev, |
| 877 | struct hclge_func_status_cmd *status) |
| 878 | { |
| 879 | if (!(status->pf_state & HCLGE_PF_STATE_DONE)) |
| 880 | return -EINVAL; |
| 881 | |
| 882 | /* Set the pf to main pf */ |
| 883 | if (status->pf_state & HCLGE_PF_STATE_MAIN) |
| 884 | hdev->flag |= HCLGE_FLAG_MAIN; |
| 885 | else |
| 886 | hdev->flag &= ~HCLGE_FLAG_MAIN; |
| 887 | |
| 888 | return 0; |
| 889 | } |
| 890 | |
| 891 | static int hclge_query_function_status(struct hclge_dev *hdev) |
| 892 | { |
| 893 | struct hclge_func_status_cmd *req; |
| 894 | struct hclge_desc desc; |
| 895 | int timeout = 0; |
| 896 | int ret; |
| 897 | |
| 898 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); |
| 899 | req = (struct hclge_func_status_cmd *)desc.data; |
| 900 | |
| 901 | do { |
| 902 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 903 | if (ret) { |
| 904 | dev_err(&hdev->pdev->dev, |
| 905 | "query function status failed %d.\n", |
| 906 | ret); |
| 907 | |
| 908 | return ret; |
| 909 | } |
| 910 | |
| 911 | /* Check pf reset is done */ |
| 912 | if (req->pf_state) |
| 913 | break; |
| 914 | usleep_range(1000, 2000); |
| 915 | } while (timeout++ < 5); |
| 916 | |
| 917 | ret = hclge_parse_func_status(hdev, req); |
| 918 | |
| 919 | return ret; |
| 920 | } |
| 921 | |
| 922 | static int hclge_query_pf_resource(struct hclge_dev *hdev) |
| 923 | { |
| 924 | struct hclge_pf_res_cmd *req; |
| 925 | struct hclge_desc desc; |
| 926 | int ret; |
| 927 | |
| 928 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); |
| 929 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 930 | if (ret) { |
| 931 | dev_err(&hdev->pdev->dev, |
| 932 | "query pf resource failed %d.\n", ret); |
| 933 | return ret; |
| 934 | } |
| 935 | |
| 936 | req = (struct hclge_pf_res_cmd *)desc.data; |
| 937 | hdev->num_tqps = __le16_to_cpu(req->tqp_num); |
| 938 | hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; |
| 939 | |
| 940 | if (hnae3_dev_roce_supported(hdev)) { |
| 941 | hdev->num_roce_msi = |
| 942 | hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
| 943 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); |
| 944 | |
| 945 | /* PF should have NIC vectors and Roce vectors, |
| 946 | * NIC vectors are queued before Roce vectors. |
| 947 | */ |
| 948 | hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; |
| 949 | } else { |
| 950 | hdev->num_msi = |
| 951 | hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
| 952 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); |
| 953 | } |
| 954 | |
| 955 | return 0; |
| 956 | } |
| 957 | |
| 958 | static int hclge_parse_speed(int speed_cmd, int *speed) |
| 959 | { |
| 960 | switch (speed_cmd) { |
| 961 | case 6: |
| 962 | *speed = HCLGE_MAC_SPEED_10M; |
| 963 | break; |
| 964 | case 7: |
| 965 | *speed = HCLGE_MAC_SPEED_100M; |
| 966 | break; |
| 967 | case 0: |
| 968 | *speed = HCLGE_MAC_SPEED_1G; |
| 969 | break; |
| 970 | case 1: |
| 971 | *speed = HCLGE_MAC_SPEED_10G; |
| 972 | break; |
| 973 | case 2: |
| 974 | *speed = HCLGE_MAC_SPEED_25G; |
| 975 | break; |
| 976 | case 3: |
| 977 | *speed = HCLGE_MAC_SPEED_40G; |
| 978 | break; |
| 979 | case 4: |
| 980 | *speed = HCLGE_MAC_SPEED_50G; |
| 981 | break; |
| 982 | case 5: |
| 983 | *speed = HCLGE_MAC_SPEED_100G; |
| 984 | break; |
| 985 | default: |
| 986 | return -EINVAL; |
| 987 | } |
| 988 | |
| 989 | return 0; |
| 990 | } |
| 991 | |
| 992 | static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, |
| 993 | u8 speed_ability) |
| 994 | { |
| 995 | unsigned long *supported = hdev->hw.mac.supported; |
| 996 | |
| 997 | if (speed_ability & HCLGE_SUPPORT_1G_BIT) |
| 998 | set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, |
| 999 | supported); |
| 1000 | |
| 1001 | if (speed_ability & HCLGE_SUPPORT_10G_BIT) |
| 1002 | set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, |
| 1003 | supported); |
| 1004 | |
| 1005 | if (speed_ability & HCLGE_SUPPORT_25G_BIT) |
| 1006 | set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, |
| 1007 | supported); |
| 1008 | |
| 1009 | if (speed_ability & HCLGE_SUPPORT_50G_BIT) |
| 1010 | set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, |
| 1011 | supported); |
| 1012 | |
| 1013 | if (speed_ability & HCLGE_SUPPORT_100G_BIT) |
| 1014 | set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, |
| 1015 | supported); |
| 1016 | |
| 1017 | set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); |
| 1018 | set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); |
| 1019 | } |
| 1020 | |
| 1021 | static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) |
| 1022 | { |
| 1023 | u8 media_type = hdev->hw.mac.media_type; |
| 1024 | |
| 1025 | if (media_type != HNAE3_MEDIA_TYPE_FIBER) |
| 1026 | return; |
| 1027 | |
| 1028 | hclge_parse_fiber_link_mode(hdev, speed_ability); |
| 1029 | } |
| 1030 | |
| 1031 | static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) |
| 1032 | { |
| 1033 | struct hclge_cfg_param_cmd *req; |
| 1034 | u64 mac_addr_tmp_high; |
| 1035 | u64 mac_addr_tmp; |
| 1036 | int i; |
| 1037 | |
| 1038 | req = (struct hclge_cfg_param_cmd *)desc[0].data; |
| 1039 | |
| 1040 | /* get the configuration */ |
| 1041 | cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]), |
| 1042 | HCLGE_CFG_VMDQ_M, |
| 1043 | HCLGE_CFG_VMDQ_S); |
| 1044 | cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), |
| 1045 | HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); |
| 1046 | cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), |
| 1047 | HCLGE_CFG_TQP_DESC_N_M, |
| 1048 | HCLGE_CFG_TQP_DESC_N_S); |
| 1049 | |
| 1050 | cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), |
| 1051 | HCLGE_CFG_PHY_ADDR_M, |
| 1052 | HCLGE_CFG_PHY_ADDR_S); |
| 1053 | cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), |
| 1054 | HCLGE_CFG_MEDIA_TP_M, |
| 1055 | HCLGE_CFG_MEDIA_TP_S); |
| 1056 | cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), |
| 1057 | HCLGE_CFG_RX_BUF_LEN_M, |
| 1058 | HCLGE_CFG_RX_BUF_LEN_S); |
| 1059 | /* get mac_address */ |
| 1060 | mac_addr_tmp = __le32_to_cpu(req->param[2]); |
| 1061 | mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), |
| 1062 | HCLGE_CFG_MAC_ADDR_H_M, |
| 1063 | HCLGE_CFG_MAC_ADDR_H_S); |
| 1064 | |
| 1065 | mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; |
| 1066 | |
| 1067 | cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), |
| 1068 | HCLGE_CFG_DEFAULT_SPEED_M, |
| 1069 | HCLGE_CFG_DEFAULT_SPEED_S); |
| 1070 | cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), |
| 1071 | HCLGE_CFG_RSS_SIZE_M, |
| 1072 | HCLGE_CFG_RSS_SIZE_S); |
| 1073 | |
| 1074 | for (i = 0; i < ETH_ALEN; i++) |
| 1075 | cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; |
| 1076 | |
| 1077 | req = (struct hclge_cfg_param_cmd *)desc[1].data; |
| 1078 | cfg->numa_node_map = __le32_to_cpu(req->param[0]); |
| 1079 | |
| 1080 | cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), |
| 1081 | HCLGE_CFG_SPEED_ABILITY_M, |
| 1082 | HCLGE_CFG_SPEED_ABILITY_S); |
| 1083 | } |
| 1084 | |
| 1085 | /* hclge_get_cfg: query the static parameter from flash |
| 1086 | * @hdev: pointer to struct hclge_dev |
| 1087 | * @hcfg: the config structure to be getted |
| 1088 | */ |
| 1089 | static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) |
| 1090 | { |
| 1091 | struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; |
| 1092 | struct hclge_cfg_param_cmd *req; |
| 1093 | int i, ret; |
| 1094 | |
| 1095 | for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { |
| 1096 | u32 offset = 0; |
| 1097 | |
| 1098 | req = (struct hclge_cfg_param_cmd *)desc[i].data; |
| 1099 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, |
| 1100 | true); |
| 1101 | hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, |
| 1102 | HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); |
| 1103 | /* Len should be united by 4 bytes when send to hardware */ |
| 1104 | hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, |
| 1105 | HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); |
| 1106 | req->offset = cpu_to_le32(offset); |
| 1107 | } |
| 1108 | |
| 1109 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); |
| 1110 | if (ret) { |
| 1111 | dev_err(&hdev->pdev->dev, |
| 1112 | "get config failed %d.\n", ret); |
| 1113 | return ret; |
| 1114 | } |
| 1115 | |
| 1116 | hclge_parse_cfg(hcfg, desc); |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
| 1120 | static int hclge_get_cap(struct hclge_dev *hdev) |
| 1121 | { |
| 1122 | int ret; |
| 1123 | |
| 1124 | ret = hclge_query_function_status(hdev); |
| 1125 | if (ret) { |
| 1126 | dev_err(&hdev->pdev->dev, |
| 1127 | "query function status error %d.\n", ret); |
| 1128 | return ret; |
| 1129 | } |
| 1130 | |
| 1131 | /* get pf resource */ |
| 1132 | ret = hclge_query_pf_resource(hdev); |
| 1133 | if (ret) { |
| 1134 | dev_err(&hdev->pdev->dev, |
| 1135 | "query pf resource error %d.\n", ret); |
| 1136 | return ret; |
| 1137 | } |
| 1138 | |
| 1139 | return 0; |
| 1140 | } |
| 1141 | |
| 1142 | static int hclge_configure(struct hclge_dev *hdev) |
| 1143 | { |
| 1144 | struct hclge_cfg cfg; |
| 1145 | int ret, i; |
| 1146 | |
| 1147 | ret = hclge_get_cfg(hdev, &cfg); |
| 1148 | if (ret) { |
| 1149 | dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); |
| 1150 | return ret; |
| 1151 | } |
| 1152 | |
| 1153 | hdev->num_vmdq_vport = cfg.vmdq_vport_num; |
| 1154 | hdev->base_tqp_pid = 0; |
| 1155 | hdev->rss_size_max = cfg.rss_size_max; |
| 1156 | hdev->rx_buf_len = cfg.rx_buf_len; |
| 1157 | ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); |
| 1158 | hdev->hw.mac.media_type = cfg.media_type; |
| 1159 | hdev->hw.mac.phy_addr = cfg.phy_addr; |
| 1160 | hdev->num_desc = cfg.tqp_desc_num; |
| 1161 | hdev->tm_info.num_pg = 1; |
| 1162 | hdev->tc_max = cfg.tc_num; |
| 1163 | hdev->tm_info.hw_pfc_map = 0; |
| 1164 | |
| 1165 | ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); |
| 1166 | if (ret) { |
| 1167 | dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); |
| 1168 | return ret; |
| 1169 | } |
| 1170 | |
| 1171 | hclge_parse_link_mode(hdev, cfg.speed_ability); |
| 1172 | |
| 1173 | if ((hdev->tc_max > HNAE3_MAX_TC) || |
| 1174 | (hdev->tc_max < 1)) { |
| 1175 | dev_warn(&hdev->pdev->dev, "TC num = %d.\n", |
| 1176 | hdev->tc_max); |
| 1177 | hdev->tc_max = 1; |
| 1178 | } |
| 1179 | |
| 1180 | /* Dev does not support DCB */ |
| 1181 | if (!hnae3_dev_dcb_supported(hdev)) { |
| 1182 | hdev->tc_max = 1; |
| 1183 | hdev->pfc_max = 0; |
| 1184 | } else { |
| 1185 | hdev->pfc_max = hdev->tc_max; |
| 1186 | } |
| 1187 | |
| 1188 | hdev->tm_info.num_tc = hdev->tc_max; |
| 1189 | |
| 1190 | /* Currently not support uncontiuous tc */ |
| 1191 | for (i = 0; i < hdev->tm_info.num_tc; i++) |
| 1192 | hnae3_set_bit(hdev->hw_tc_map, i, 1); |
| 1193 | |
| 1194 | hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; |
| 1195 | |
| 1196 | return ret; |
| 1197 | } |
| 1198 | |
| 1199 | static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, |
| 1200 | int tso_mss_max) |
| 1201 | { |
| 1202 | struct hclge_cfg_tso_status_cmd *req; |
| 1203 | struct hclge_desc desc; |
| 1204 | u16 tso_mss; |
| 1205 | |
| 1206 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); |
| 1207 | |
| 1208 | req = (struct hclge_cfg_tso_status_cmd *)desc.data; |
| 1209 | |
| 1210 | tso_mss = 0; |
| 1211 | hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, |
| 1212 | HCLGE_TSO_MSS_MIN_S, tso_mss_min); |
| 1213 | req->tso_mss_min = cpu_to_le16(tso_mss); |
| 1214 | |
| 1215 | tso_mss = 0; |
| 1216 | hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, |
| 1217 | HCLGE_TSO_MSS_MIN_S, tso_mss_max); |
| 1218 | req->tso_mss_max = cpu_to_le16(tso_mss); |
| 1219 | |
| 1220 | return hclge_cmd_send(&hdev->hw, &desc, 1); |
| 1221 | } |
| 1222 | |
| 1223 | static int hclge_alloc_tqps(struct hclge_dev *hdev) |
| 1224 | { |
| 1225 | struct hclge_tqp *tqp; |
| 1226 | int i; |
| 1227 | |
| 1228 | hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, |
| 1229 | sizeof(struct hclge_tqp), GFP_KERNEL); |
| 1230 | if (!hdev->htqp) |
| 1231 | return -ENOMEM; |
| 1232 | |
| 1233 | tqp = hdev->htqp; |
| 1234 | |
| 1235 | for (i = 0; i < hdev->num_tqps; i++) { |
| 1236 | tqp->dev = &hdev->pdev->dev; |
| 1237 | tqp->index = i; |
| 1238 | |
| 1239 | tqp->q.ae_algo = &ae_algo; |
| 1240 | tqp->q.buf_size = hdev->rx_buf_len; |
| 1241 | tqp->q.desc_num = hdev->num_desc; |
| 1242 | tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + |
| 1243 | i * HCLGE_TQP_REG_SIZE; |
| 1244 | |
| 1245 | tqp++; |
| 1246 | } |
| 1247 | |
| 1248 | return 0; |
| 1249 | } |
| 1250 | |
| 1251 | static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, |
| 1252 | u16 tqp_pid, u16 tqp_vid, bool is_pf) |
| 1253 | { |
| 1254 | struct hclge_tqp_map_cmd *req; |
| 1255 | struct hclge_desc desc; |
| 1256 | int ret; |
| 1257 | |
| 1258 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); |
| 1259 | |
| 1260 | req = (struct hclge_tqp_map_cmd *)desc.data; |
| 1261 | req->tqp_id = cpu_to_le16(tqp_pid); |
| 1262 | req->tqp_vf = func_id; |
| 1263 | req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | |
| 1264 | 1 << HCLGE_TQP_MAP_EN_B; |
| 1265 | req->tqp_vid = cpu_to_le16(tqp_vid); |
| 1266 | |
| 1267 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 1268 | if (ret) { |
| 1269 | dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", |
| 1270 | ret); |
| 1271 | return ret; |
| 1272 | } |
| 1273 | |
| 1274 | return 0; |
| 1275 | } |
| 1276 | |
| 1277 | static int hclge_assign_tqp(struct hclge_vport *vport, |
| 1278 | struct hnae3_queue **tqp, u16 num_tqps) |
| 1279 | { |
| 1280 | struct hclge_dev *hdev = vport->back; |
| 1281 | int i, alloced; |
| 1282 | |
| 1283 | for (i = 0, alloced = 0; i < hdev->num_tqps && |
| 1284 | alloced < num_tqps; i++) { |
| 1285 | if (!hdev->htqp[i].alloced) { |
| 1286 | hdev->htqp[i].q.handle = &vport->nic; |
| 1287 | hdev->htqp[i].q.tqp_index = alloced; |
| 1288 | tqp[alloced] = &hdev->htqp[i].q; |
| 1289 | hdev->htqp[i].alloced = true; |
| 1290 | alloced++; |
| 1291 | } |
| 1292 | } |
| 1293 | vport->alloc_tqps = num_tqps; |
| 1294 | |
| 1295 | return 0; |
| 1296 | } |
| 1297 | |
| 1298 | static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) |
| 1299 | { |
| 1300 | struct hnae3_handle *nic = &vport->nic; |
| 1301 | struct hnae3_knic_private_info *kinfo = &nic->kinfo; |
| 1302 | struct hclge_dev *hdev = vport->back; |
| 1303 | int i, ret; |
| 1304 | |
| 1305 | kinfo->num_desc = hdev->num_desc; |
| 1306 | kinfo->rx_buf_len = hdev->rx_buf_len; |
| 1307 | kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); |
| 1308 | kinfo->rss_size |
| 1309 | = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); |
| 1310 | kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; |
| 1311 | |
| 1312 | for (i = 0; i < HNAE3_MAX_TC; i++) { |
| 1313 | if (hdev->hw_tc_map & BIT(i)) { |
| 1314 | kinfo->tc_info[i].enable = true; |
| 1315 | kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; |
| 1316 | kinfo->tc_info[i].tqp_count = kinfo->rss_size; |
| 1317 | kinfo->tc_info[i].tc = i; |
| 1318 | } else { |
| 1319 | /* Set to default queue if TC is disable */ |
| 1320 | kinfo->tc_info[i].enable = false; |
| 1321 | kinfo->tc_info[i].tqp_offset = 0; |
| 1322 | kinfo->tc_info[i].tqp_count = 1; |
| 1323 | kinfo->tc_info[i].tc = 0; |
| 1324 | } |
| 1325 | } |
| 1326 | |
| 1327 | kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, |
| 1328 | sizeof(struct hnae3_queue *), GFP_KERNEL); |
| 1329 | if (!kinfo->tqp) |
| 1330 | return -ENOMEM; |
| 1331 | |
| 1332 | ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); |
| 1333 | if (ret) { |
| 1334 | dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); |
| 1335 | return -EINVAL; |
| 1336 | } |
| 1337 | |
| 1338 | return 0; |
| 1339 | } |
| 1340 | |
| 1341 | static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, |
| 1342 | struct hclge_vport *vport) |
| 1343 | { |
| 1344 | struct hnae3_handle *nic = &vport->nic; |
| 1345 | struct hnae3_knic_private_info *kinfo; |
| 1346 | u16 i; |
| 1347 | |
| 1348 | kinfo = &nic->kinfo; |
| 1349 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 1350 | struct hclge_tqp *q = |
| 1351 | container_of(kinfo->tqp[i], struct hclge_tqp, q); |
| 1352 | bool is_pf; |
| 1353 | int ret; |
| 1354 | |
| 1355 | is_pf = !(vport->vport_id); |
| 1356 | ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, |
| 1357 | i, is_pf); |
| 1358 | if (ret) |
| 1359 | return ret; |
| 1360 | } |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | static int hclge_map_tqp(struct hclge_dev *hdev) |
| 1366 | { |
| 1367 | struct hclge_vport *vport = hdev->vport; |
| 1368 | u16 i, num_vport; |
| 1369 | |
| 1370 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; |
| 1371 | for (i = 0; i < num_vport; i++) { |
| 1372 | int ret; |
| 1373 | |
| 1374 | ret = hclge_map_tqp_to_vport(hdev, vport); |
| 1375 | if (ret) |
| 1376 | return ret; |
| 1377 | |
| 1378 | vport++; |
| 1379 | } |
| 1380 | |
| 1381 | return 0; |
| 1382 | } |
| 1383 | |
| 1384 | static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) |
| 1385 | { |
| 1386 | /* this would be initialized later */ |
| 1387 | } |
| 1388 | |
| 1389 | static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) |
| 1390 | { |
| 1391 | struct hnae3_handle *nic = &vport->nic; |
| 1392 | struct hclge_dev *hdev = vport->back; |
| 1393 | int ret; |
| 1394 | |
| 1395 | nic->pdev = hdev->pdev; |
| 1396 | nic->ae_algo = &ae_algo; |
| 1397 | nic->numa_node_mask = hdev->numa_node_mask; |
| 1398 | |
| 1399 | if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { |
| 1400 | ret = hclge_knic_setup(vport, num_tqps); |
| 1401 | if (ret) { |
| 1402 | dev_err(&hdev->pdev->dev, "knic setup failed %d\n", |
| 1403 | ret); |
| 1404 | return ret; |
| 1405 | } |
| 1406 | } else { |
| 1407 | hclge_unic_setup(vport, num_tqps); |
| 1408 | } |
| 1409 | |
| 1410 | return 0; |
| 1411 | } |
| 1412 | |
| 1413 | static int hclge_alloc_vport(struct hclge_dev *hdev) |
| 1414 | { |
| 1415 | struct pci_dev *pdev = hdev->pdev; |
| 1416 | struct hclge_vport *vport; |
| 1417 | u32 tqp_main_vport; |
| 1418 | u32 tqp_per_vport; |
| 1419 | int num_vport, i; |
| 1420 | int ret; |
| 1421 | |
| 1422 | /* We need to alloc a vport for main NIC of PF */ |
| 1423 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; |
| 1424 | |
| 1425 | if (hdev->num_tqps < num_vport) { |
| 1426 | dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", |
| 1427 | hdev->num_tqps, num_vport); |
| 1428 | return -EINVAL; |
| 1429 | } |
| 1430 | |
| 1431 | /* Alloc the same number of TQPs for every vport */ |
| 1432 | tqp_per_vport = hdev->num_tqps / num_vport; |
| 1433 | tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; |
| 1434 | |
| 1435 | vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), |
| 1436 | GFP_KERNEL); |
| 1437 | if (!vport) |
| 1438 | return -ENOMEM; |
| 1439 | |
| 1440 | hdev->vport = vport; |
| 1441 | hdev->num_alloc_vport = num_vport; |
| 1442 | |
| 1443 | if (IS_ENABLED(CONFIG_PCI_IOV)) |
| 1444 | hdev->num_alloc_vfs = hdev->num_req_vfs; |
| 1445 | |
| 1446 | for (i = 0; i < num_vport; i++) { |
| 1447 | vport->back = hdev; |
| 1448 | vport->vport_id = i; |
| 1449 | |
| 1450 | if (i == 0) |
| 1451 | ret = hclge_vport_setup(vport, tqp_main_vport); |
| 1452 | else |
| 1453 | ret = hclge_vport_setup(vport, tqp_per_vport); |
| 1454 | if (ret) { |
| 1455 | dev_err(&pdev->dev, |
| 1456 | "vport setup failed for vport %d, %d\n", |
| 1457 | i, ret); |
| 1458 | return ret; |
| 1459 | } |
| 1460 | |
| 1461 | vport++; |
| 1462 | } |
| 1463 | |
| 1464 | return 0; |
| 1465 | } |
| 1466 | |
| 1467 | static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, |
| 1468 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1469 | { |
| 1470 | /* TX buffer size is unit by 128 byte */ |
| 1471 | #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 |
| 1472 | #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) |
| 1473 | struct hclge_tx_buff_alloc_cmd *req; |
| 1474 | struct hclge_desc desc; |
| 1475 | int ret; |
| 1476 | u8 i; |
| 1477 | |
| 1478 | req = (struct hclge_tx_buff_alloc_cmd *)desc.data; |
| 1479 | |
| 1480 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); |
| 1481 | for (i = 0; i < HCLGE_TC_NUM; i++) { |
| 1482 | u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; |
| 1483 | |
| 1484 | req->tx_pkt_buff[i] = |
| 1485 | cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | |
| 1486 | HCLGE_BUF_SIZE_UPDATE_EN_MSK); |
| 1487 | } |
| 1488 | |
| 1489 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 1490 | if (ret) { |
| 1491 | dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", |
| 1492 | ret); |
| 1493 | return ret; |
| 1494 | } |
| 1495 | |
| 1496 | return 0; |
| 1497 | } |
| 1498 | |
| 1499 | static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, |
| 1500 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1501 | { |
| 1502 | int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); |
| 1503 | |
| 1504 | if (ret) { |
| 1505 | dev_err(&hdev->pdev->dev, |
| 1506 | "tx buffer alloc failed %d\n", ret); |
| 1507 | return ret; |
| 1508 | } |
| 1509 | |
| 1510 | return 0; |
| 1511 | } |
| 1512 | |
| 1513 | static int hclge_get_tc_num(struct hclge_dev *hdev) |
| 1514 | { |
| 1515 | int i, cnt = 0; |
| 1516 | |
| 1517 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) |
| 1518 | if (hdev->hw_tc_map & BIT(i)) |
| 1519 | cnt++; |
| 1520 | return cnt; |
| 1521 | } |
| 1522 | |
| 1523 | static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) |
| 1524 | { |
| 1525 | int i, cnt = 0; |
| 1526 | |
| 1527 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) |
| 1528 | if (hdev->hw_tc_map & BIT(i) && |
| 1529 | hdev->tm_info.hw_pfc_map & BIT(i)) |
| 1530 | cnt++; |
| 1531 | return cnt; |
| 1532 | } |
| 1533 | |
| 1534 | /* Get the number of pfc enabled TCs, which have private buffer */ |
| 1535 | static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, |
| 1536 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1537 | { |
| 1538 | struct hclge_priv_buf *priv; |
| 1539 | int i, cnt = 0; |
| 1540 | |
| 1541 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1542 | priv = &buf_alloc->priv_buf[i]; |
| 1543 | if ((hdev->tm_info.hw_pfc_map & BIT(i)) && |
| 1544 | priv->enable) |
| 1545 | cnt++; |
| 1546 | } |
| 1547 | |
| 1548 | return cnt; |
| 1549 | } |
| 1550 | |
| 1551 | /* Get the number of pfc disabled TCs, which have private buffer */ |
| 1552 | static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, |
| 1553 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1554 | { |
| 1555 | struct hclge_priv_buf *priv; |
| 1556 | int i, cnt = 0; |
| 1557 | |
| 1558 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1559 | priv = &buf_alloc->priv_buf[i]; |
| 1560 | if (hdev->hw_tc_map & BIT(i) && |
| 1561 | !(hdev->tm_info.hw_pfc_map & BIT(i)) && |
| 1562 | priv->enable) |
| 1563 | cnt++; |
| 1564 | } |
| 1565 | |
| 1566 | return cnt; |
| 1567 | } |
| 1568 | |
| 1569 | static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
| 1570 | { |
| 1571 | struct hclge_priv_buf *priv; |
| 1572 | u32 rx_priv = 0; |
| 1573 | int i; |
| 1574 | |
| 1575 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1576 | priv = &buf_alloc->priv_buf[i]; |
| 1577 | if (priv->enable) |
| 1578 | rx_priv += priv->buf_size; |
| 1579 | } |
| 1580 | return rx_priv; |
| 1581 | } |
| 1582 | |
| 1583 | static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
| 1584 | { |
| 1585 | u32 i, total_tx_size = 0; |
| 1586 | |
| 1587 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) |
| 1588 | total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; |
| 1589 | |
| 1590 | return total_tx_size; |
| 1591 | } |
| 1592 | |
| 1593 | static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, |
| 1594 | struct hclge_pkt_buf_alloc *buf_alloc, |
| 1595 | u32 rx_all) |
| 1596 | { |
| 1597 | u32 shared_buf_min, shared_buf_tc, shared_std; |
| 1598 | int tc_num, pfc_enable_num; |
| 1599 | u32 shared_buf; |
| 1600 | u32 rx_priv; |
| 1601 | int i; |
| 1602 | |
| 1603 | tc_num = hclge_get_tc_num(hdev); |
| 1604 | pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); |
| 1605 | |
| 1606 | if (hnae3_dev_dcb_supported(hdev)) |
| 1607 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; |
| 1608 | else |
| 1609 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; |
| 1610 | |
| 1611 | shared_buf_tc = pfc_enable_num * hdev->mps + |
| 1612 | (tc_num - pfc_enable_num) * hdev->mps / 2 + |
| 1613 | hdev->mps; |
| 1614 | shared_std = max_t(u32, shared_buf_min, shared_buf_tc); |
| 1615 | |
| 1616 | rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); |
| 1617 | if (rx_all <= rx_priv + shared_std) |
| 1618 | return false; |
| 1619 | |
| 1620 | shared_buf = rx_all - rx_priv; |
| 1621 | buf_alloc->s_buf.buf_size = shared_buf; |
| 1622 | buf_alloc->s_buf.self.high = shared_buf; |
| 1623 | buf_alloc->s_buf.self.low = 2 * hdev->mps; |
| 1624 | |
| 1625 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1626 | if ((hdev->hw_tc_map & BIT(i)) && |
| 1627 | (hdev->tm_info.hw_pfc_map & BIT(i))) { |
| 1628 | buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; |
| 1629 | buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; |
| 1630 | } else { |
| 1631 | buf_alloc->s_buf.tc_thrd[i].low = 0; |
| 1632 | buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; |
| 1633 | } |
| 1634 | } |
| 1635 | |
| 1636 | return true; |
| 1637 | } |
| 1638 | |
| 1639 | static int hclge_tx_buffer_calc(struct hclge_dev *hdev, |
| 1640 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1641 | { |
| 1642 | u32 i, total_size; |
| 1643 | |
| 1644 | total_size = hdev->pkt_buf_size; |
| 1645 | |
| 1646 | /* alloc tx buffer for all enabled tc */ |
| 1647 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1648 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
| 1649 | |
| 1650 | if (total_size < HCLGE_DEFAULT_TX_BUF) |
| 1651 | return -ENOMEM; |
| 1652 | |
| 1653 | if (hdev->hw_tc_map & BIT(i)) |
| 1654 | priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; |
| 1655 | else |
| 1656 | priv->tx_buf_size = 0; |
| 1657 | |
| 1658 | total_size -= priv->tx_buf_size; |
| 1659 | } |
| 1660 | |
| 1661 | return 0; |
| 1662 | } |
| 1663 | |
| 1664 | /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs |
| 1665 | * @hdev: pointer to struct hclge_dev |
| 1666 | * @buf_alloc: pointer to buffer calculation data |
| 1667 | * @return: 0: calculate sucessful, negative: fail |
| 1668 | */ |
| 1669 | static int hclge_rx_buffer_calc(struct hclge_dev *hdev, |
| 1670 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1671 | { |
| 1672 | u32 rx_all = hdev->pkt_buf_size; |
| 1673 | int no_pfc_priv_num, pfc_priv_num; |
| 1674 | struct hclge_priv_buf *priv; |
| 1675 | int i; |
| 1676 | |
| 1677 | rx_all -= hclge_get_tx_buff_alloced(buf_alloc); |
| 1678 | |
| 1679 | /* When DCB is not supported, rx private |
| 1680 | * buffer is not allocated. |
| 1681 | */ |
| 1682 | if (!hnae3_dev_dcb_supported(hdev)) { |
| 1683 | if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
| 1684 | return -ENOMEM; |
| 1685 | |
| 1686 | return 0; |
| 1687 | } |
| 1688 | |
| 1689 | /* step 1, try to alloc private buffer for all enabled tc */ |
| 1690 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1691 | priv = &buf_alloc->priv_buf[i]; |
| 1692 | if (hdev->hw_tc_map & BIT(i)) { |
| 1693 | priv->enable = 1; |
| 1694 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { |
| 1695 | priv->wl.low = hdev->mps; |
| 1696 | priv->wl.high = priv->wl.low + hdev->mps; |
| 1697 | priv->buf_size = priv->wl.high + |
| 1698 | HCLGE_DEFAULT_DV; |
| 1699 | } else { |
| 1700 | priv->wl.low = 0; |
| 1701 | priv->wl.high = 2 * hdev->mps; |
| 1702 | priv->buf_size = priv->wl.high; |
| 1703 | } |
| 1704 | } else { |
| 1705 | priv->enable = 0; |
| 1706 | priv->wl.low = 0; |
| 1707 | priv->wl.high = 0; |
| 1708 | priv->buf_size = 0; |
| 1709 | } |
| 1710 | } |
| 1711 | |
| 1712 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
| 1713 | return 0; |
| 1714 | |
| 1715 | /* step 2, try to decrease the buffer size of |
| 1716 | * no pfc TC's private buffer |
| 1717 | */ |
| 1718 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1719 | priv = &buf_alloc->priv_buf[i]; |
| 1720 | |
| 1721 | priv->enable = 0; |
| 1722 | priv->wl.low = 0; |
| 1723 | priv->wl.high = 0; |
| 1724 | priv->buf_size = 0; |
| 1725 | |
| 1726 | if (!(hdev->hw_tc_map & BIT(i))) |
| 1727 | continue; |
| 1728 | |
| 1729 | priv->enable = 1; |
| 1730 | |
| 1731 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { |
| 1732 | priv->wl.low = 128; |
| 1733 | priv->wl.high = priv->wl.low + hdev->mps; |
| 1734 | priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; |
| 1735 | } else { |
| 1736 | priv->wl.low = 0; |
| 1737 | priv->wl.high = hdev->mps; |
| 1738 | priv->buf_size = priv->wl.high; |
| 1739 | } |
| 1740 | } |
| 1741 | |
| 1742 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
| 1743 | return 0; |
| 1744 | |
| 1745 | /* step 3, try to reduce the number of pfc disabled TCs, |
| 1746 | * which have private buffer |
| 1747 | */ |
| 1748 | /* get the total no pfc enable TC number, which have private buffer */ |
| 1749 | no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); |
| 1750 | |
| 1751 | /* let the last to be cleared first */ |
| 1752 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { |
| 1753 | priv = &buf_alloc->priv_buf[i]; |
| 1754 | |
| 1755 | if (hdev->hw_tc_map & BIT(i) && |
| 1756 | !(hdev->tm_info.hw_pfc_map & BIT(i))) { |
| 1757 | /* Clear the no pfc TC private buffer */ |
| 1758 | priv->wl.low = 0; |
| 1759 | priv->wl.high = 0; |
| 1760 | priv->buf_size = 0; |
| 1761 | priv->enable = 0; |
| 1762 | no_pfc_priv_num--; |
| 1763 | } |
| 1764 | |
| 1765 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
| 1766 | no_pfc_priv_num == 0) |
| 1767 | break; |
| 1768 | } |
| 1769 | |
| 1770 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
| 1771 | return 0; |
| 1772 | |
| 1773 | /* step 4, try to reduce the number of pfc enabled TCs |
| 1774 | * which have private buffer. |
| 1775 | */ |
| 1776 | pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); |
| 1777 | |
| 1778 | /* let the last to be cleared first */ |
| 1779 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { |
| 1780 | priv = &buf_alloc->priv_buf[i]; |
| 1781 | |
| 1782 | if (hdev->hw_tc_map & BIT(i) && |
| 1783 | hdev->tm_info.hw_pfc_map & BIT(i)) { |
| 1784 | /* Reduce the number of pfc TC with private buffer */ |
| 1785 | priv->wl.low = 0; |
| 1786 | priv->enable = 0; |
| 1787 | priv->wl.high = 0; |
| 1788 | priv->buf_size = 0; |
| 1789 | pfc_priv_num--; |
| 1790 | } |
| 1791 | |
| 1792 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
| 1793 | pfc_priv_num == 0) |
| 1794 | break; |
| 1795 | } |
| 1796 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
| 1797 | return 0; |
| 1798 | |
| 1799 | return -ENOMEM; |
| 1800 | } |
| 1801 | |
| 1802 | static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, |
| 1803 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1804 | { |
| 1805 | struct hclge_rx_priv_buff_cmd *req; |
| 1806 | struct hclge_desc desc; |
| 1807 | int ret; |
| 1808 | int i; |
| 1809 | |
| 1810 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); |
| 1811 | req = (struct hclge_rx_priv_buff_cmd *)desc.data; |
| 1812 | |
| 1813 | /* Alloc private buffer TCs */ |
| 1814 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 1815 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
| 1816 | |
| 1817 | req->buf_num[i] = |
| 1818 | cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); |
| 1819 | req->buf_num[i] |= |
| 1820 | cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); |
| 1821 | } |
| 1822 | |
| 1823 | req->shared_buf = |
| 1824 | cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | |
| 1825 | (1 << HCLGE_TC0_PRI_BUF_EN_B)); |
| 1826 | |
| 1827 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 1828 | if (ret) { |
| 1829 | dev_err(&hdev->pdev->dev, |
| 1830 | "rx private buffer alloc cmd failed %d\n", ret); |
| 1831 | return ret; |
| 1832 | } |
| 1833 | |
| 1834 | return 0; |
| 1835 | } |
| 1836 | |
| 1837 | static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, |
| 1838 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1839 | { |
| 1840 | struct hclge_rx_priv_wl_buf *req; |
| 1841 | struct hclge_priv_buf *priv; |
| 1842 | struct hclge_desc desc[2]; |
| 1843 | int i, j; |
| 1844 | int ret; |
| 1845 | |
| 1846 | for (i = 0; i < 2; i++) { |
| 1847 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, |
| 1848 | false); |
| 1849 | req = (struct hclge_rx_priv_wl_buf *)desc[i].data; |
| 1850 | |
| 1851 | /* The first descriptor set the NEXT bit to 1 */ |
| 1852 | if (i == 0) |
| 1853 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 1854 | else |
| 1855 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 1856 | |
| 1857 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { |
| 1858 | u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; |
| 1859 | |
| 1860 | priv = &buf_alloc->priv_buf[idx]; |
| 1861 | req->tc_wl[j].high = |
| 1862 | cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); |
| 1863 | req->tc_wl[j].high |= |
| 1864 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
| 1865 | req->tc_wl[j].low = |
| 1866 | cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); |
| 1867 | req->tc_wl[j].low |= |
| 1868 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
| 1869 | } |
| 1870 | } |
| 1871 | |
| 1872 | /* Send 2 descriptor at one time */ |
| 1873 | ret = hclge_cmd_send(&hdev->hw, desc, 2); |
| 1874 | if (ret) { |
| 1875 | dev_err(&hdev->pdev->dev, |
| 1876 | "rx private waterline config cmd failed %d\n", |
| 1877 | ret); |
| 1878 | return ret; |
| 1879 | } |
| 1880 | return 0; |
| 1881 | } |
| 1882 | |
| 1883 | static int hclge_common_thrd_config(struct hclge_dev *hdev, |
| 1884 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1885 | { |
| 1886 | struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; |
| 1887 | struct hclge_rx_com_thrd *req; |
| 1888 | struct hclge_desc desc[2]; |
| 1889 | struct hclge_tc_thrd *tc; |
| 1890 | int i, j; |
| 1891 | int ret; |
| 1892 | |
| 1893 | for (i = 0; i < 2; i++) { |
| 1894 | hclge_cmd_setup_basic_desc(&desc[i], |
| 1895 | HCLGE_OPC_RX_COM_THRD_ALLOC, false); |
| 1896 | req = (struct hclge_rx_com_thrd *)&desc[i].data; |
| 1897 | |
| 1898 | /* The first descriptor set the NEXT bit to 1 */ |
| 1899 | if (i == 0) |
| 1900 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 1901 | else |
| 1902 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 1903 | |
| 1904 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { |
| 1905 | tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; |
| 1906 | |
| 1907 | req->com_thrd[j].high = |
| 1908 | cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); |
| 1909 | req->com_thrd[j].high |= |
| 1910 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
| 1911 | req->com_thrd[j].low = |
| 1912 | cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); |
| 1913 | req->com_thrd[j].low |= |
| 1914 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
| 1915 | } |
| 1916 | } |
| 1917 | |
| 1918 | /* Send 2 descriptors at one time */ |
| 1919 | ret = hclge_cmd_send(&hdev->hw, desc, 2); |
| 1920 | if (ret) { |
| 1921 | dev_err(&hdev->pdev->dev, |
| 1922 | "common threshold config cmd failed %d\n", ret); |
| 1923 | return ret; |
| 1924 | } |
| 1925 | return 0; |
| 1926 | } |
| 1927 | |
| 1928 | static int hclge_common_wl_config(struct hclge_dev *hdev, |
| 1929 | struct hclge_pkt_buf_alloc *buf_alloc) |
| 1930 | { |
| 1931 | struct hclge_shared_buf *buf = &buf_alloc->s_buf; |
| 1932 | struct hclge_rx_com_wl *req; |
| 1933 | struct hclge_desc desc; |
| 1934 | int ret; |
| 1935 | |
| 1936 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); |
| 1937 | |
| 1938 | req = (struct hclge_rx_com_wl *)desc.data; |
| 1939 | req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); |
| 1940 | req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
| 1941 | |
| 1942 | req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); |
| 1943 | req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
| 1944 | |
| 1945 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 1946 | if (ret) { |
| 1947 | dev_err(&hdev->pdev->dev, |
| 1948 | "common waterline config cmd failed %d\n", ret); |
| 1949 | return ret; |
| 1950 | } |
| 1951 | |
| 1952 | return 0; |
| 1953 | } |
| 1954 | |
| 1955 | int hclge_buffer_alloc(struct hclge_dev *hdev) |
| 1956 | { |
| 1957 | struct hclge_pkt_buf_alloc *pkt_buf; |
| 1958 | int ret; |
| 1959 | |
| 1960 | pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); |
| 1961 | if (!pkt_buf) |
| 1962 | return -ENOMEM; |
| 1963 | |
| 1964 | ret = hclge_tx_buffer_calc(hdev, pkt_buf); |
| 1965 | if (ret) { |
| 1966 | dev_err(&hdev->pdev->dev, |
| 1967 | "could not calc tx buffer size for all TCs %d\n", ret); |
| 1968 | goto out; |
| 1969 | } |
| 1970 | |
| 1971 | ret = hclge_tx_buffer_alloc(hdev, pkt_buf); |
| 1972 | if (ret) { |
| 1973 | dev_err(&hdev->pdev->dev, |
| 1974 | "could not alloc tx buffers %d\n", ret); |
| 1975 | goto out; |
| 1976 | } |
| 1977 | |
| 1978 | ret = hclge_rx_buffer_calc(hdev, pkt_buf); |
| 1979 | if (ret) { |
| 1980 | dev_err(&hdev->pdev->dev, |
| 1981 | "could not calc rx priv buffer size for all TCs %d\n", |
| 1982 | ret); |
| 1983 | goto out; |
| 1984 | } |
| 1985 | |
| 1986 | ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); |
| 1987 | if (ret) { |
| 1988 | dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", |
| 1989 | ret); |
| 1990 | goto out; |
| 1991 | } |
| 1992 | |
| 1993 | if (hnae3_dev_dcb_supported(hdev)) { |
| 1994 | ret = hclge_rx_priv_wl_config(hdev, pkt_buf); |
| 1995 | if (ret) { |
| 1996 | dev_err(&hdev->pdev->dev, |
| 1997 | "could not configure rx private waterline %d\n", |
| 1998 | ret); |
| 1999 | goto out; |
| 2000 | } |
| 2001 | |
| 2002 | ret = hclge_common_thrd_config(hdev, pkt_buf); |
| 2003 | if (ret) { |
| 2004 | dev_err(&hdev->pdev->dev, |
| 2005 | "could not configure common threshold %d\n", |
| 2006 | ret); |
| 2007 | goto out; |
| 2008 | } |
| 2009 | } |
| 2010 | |
| 2011 | ret = hclge_common_wl_config(hdev, pkt_buf); |
| 2012 | if (ret) |
| 2013 | dev_err(&hdev->pdev->dev, |
| 2014 | "could not configure common waterline %d\n", ret); |
| 2015 | |
| 2016 | out: |
| 2017 | kfree(pkt_buf); |
| 2018 | return ret; |
| 2019 | } |
| 2020 | |
| 2021 | static int hclge_init_roce_base_info(struct hclge_vport *vport) |
| 2022 | { |
| 2023 | struct hnae3_handle *roce = &vport->roce; |
| 2024 | struct hnae3_handle *nic = &vport->nic; |
| 2025 | |
| 2026 | roce->rinfo.num_vectors = vport->back->num_roce_msi; |
| 2027 | |
| 2028 | if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || |
| 2029 | vport->back->num_msi_left == 0) |
| 2030 | return -EINVAL; |
| 2031 | |
| 2032 | roce->rinfo.base_vector = vport->back->roce_base_vector; |
| 2033 | |
| 2034 | roce->rinfo.netdev = nic->kinfo.netdev; |
| 2035 | roce->rinfo.roce_io_base = vport->back->hw.io_base; |
| 2036 | |
| 2037 | roce->pdev = nic->pdev; |
| 2038 | roce->ae_algo = nic->ae_algo; |
| 2039 | roce->numa_node_mask = nic->numa_node_mask; |
| 2040 | |
| 2041 | return 0; |
| 2042 | } |
| 2043 | |
| 2044 | static int hclge_init_msi(struct hclge_dev *hdev) |
| 2045 | { |
| 2046 | struct pci_dev *pdev = hdev->pdev; |
| 2047 | int vectors; |
| 2048 | int i; |
| 2049 | |
| 2050 | vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, |
| 2051 | PCI_IRQ_MSI | PCI_IRQ_MSIX); |
| 2052 | if (vectors < 0) { |
| 2053 | dev_err(&pdev->dev, |
| 2054 | "failed(%d) to allocate MSI/MSI-X vectors\n", |
| 2055 | vectors); |
| 2056 | return vectors; |
| 2057 | } |
| 2058 | if (vectors < hdev->num_msi) |
| 2059 | dev_warn(&hdev->pdev->dev, |
| 2060 | "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", |
| 2061 | hdev->num_msi, vectors); |
| 2062 | |
| 2063 | hdev->num_msi = vectors; |
| 2064 | hdev->num_msi_left = vectors; |
| 2065 | hdev->base_msi_vector = pdev->irq; |
| 2066 | hdev->roce_base_vector = hdev->base_msi_vector + |
| 2067 | HCLGE_ROCE_VECTOR_OFFSET; |
| 2068 | |
| 2069 | hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, |
| 2070 | sizeof(u16), GFP_KERNEL); |
| 2071 | if (!hdev->vector_status) { |
| 2072 | pci_free_irq_vectors(pdev); |
| 2073 | return -ENOMEM; |
| 2074 | } |
| 2075 | |
| 2076 | for (i = 0; i < hdev->num_msi; i++) |
| 2077 | hdev->vector_status[i] = HCLGE_INVALID_VPORT; |
| 2078 | |
| 2079 | hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, |
| 2080 | sizeof(int), GFP_KERNEL); |
| 2081 | if (!hdev->vector_irq) { |
| 2082 | pci_free_irq_vectors(pdev); |
| 2083 | return -ENOMEM; |
| 2084 | } |
| 2085 | |
| 2086 | return 0; |
| 2087 | } |
| 2088 | |
| 2089 | static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) |
| 2090 | { |
| 2091 | struct hclge_mac *mac = &hdev->hw.mac; |
| 2092 | |
| 2093 | if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) |
| 2094 | mac->duplex = (u8)duplex; |
| 2095 | else |
| 2096 | mac->duplex = HCLGE_MAC_FULL; |
| 2097 | |
| 2098 | mac->speed = speed; |
| 2099 | } |
| 2100 | |
| 2101 | int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) |
| 2102 | { |
| 2103 | struct hclge_config_mac_speed_dup_cmd *req; |
| 2104 | struct hclge_desc desc; |
| 2105 | int ret; |
| 2106 | |
| 2107 | req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; |
| 2108 | |
| 2109 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); |
| 2110 | |
| 2111 | hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); |
| 2112 | |
| 2113 | switch (speed) { |
| 2114 | case HCLGE_MAC_SPEED_10M: |
| 2115 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2116 | HCLGE_CFG_SPEED_S, 6); |
| 2117 | break; |
| 2118 | case HCLGE_MAC_SPEED_100M: |
| 2119 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2120 | HCLGE_CFG_SPEED_S, 7); |
| 2121 | break; |
| 2122 | case HCLGE_MAC_SPEED_1G: |
| 2123 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2124 | HCLGE_CFG_SPEED_S, 0); |
| 2125 | break; |
| 2126 | case HCLGE_MAC_SPEED_10G: |
| 2127 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2128 | HCLGE_CFG_SPEED_S, 1); |
| 2129 | break; |
| 2130 | case HCLGE_MAC_SPEED_25G: |
| 2131 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2132 | HCLGE_CFG_SPEED_S, 2); |
| 2133 | break; |
| 2134 | case HCLGE_MAC_SPEED_40G: |
| 2135 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2136 | HCLGE_CFG_SPEED_S, 3); |
| 2137 | break; |
| 2138 | case HCLGE_MAC_SPEED_50G: |
| 2139 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2140 | HCLGE_CFG_SPEED_S, 4); |
| 2141 | break; |
| 2142 | case HCLGE_MAC_SPEED_100G: |
| 2143 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
| 2144 | HCLGE_CFG_SPEED_S, 5); |
| 2145 | break; |
| 2146 | default: |
| 2147 | dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); |
| 2148 | return -EINVAL; |
| 2149 | } |
| 2150 | |
| 2151 | hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, |
| 2152 | 1); |
| 2153 | |
| 2154 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 2155 | if (ret) { |
| 2156 | dev_err(&hdev->pdev->dev, |
| 2157 | "mac speed/duplex config cmd failed %d.\n", ret); |
| 2158 | return ret; |
| 2159 | } |
| 2160 | |
| 2161 | hclge_check_speed_dup(hdev, duplex, speed); |
| 2162 | |
| 2163 | return 0; |
| 2164 | } |
| 2165 | |
| 2166 | static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, |
| 2167 | u8 duplex) |
| 2168 | { |
| 2169 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2170 | struct hclge_dev *hdev = vport->back; |
| 2171 | |
| 2172 | return hclge_cfg_mac_speed_dup(hdev, speed, duplex); |
| 2173 | } |
| 2174 | |
| 2175 | static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, |
| 2176 | u8 *duplex) |
| 2177 | { |
| 2178 | struct hclge_query_an_speed_dup_cmd *req; |
| 2179 | struct hclge_desc desc; |
| 2180 | int speed_tmp; |
| 2181 | int ret; |
| 2182 | |
| 2183 | req = (struct hclge_query_an_speed_dup_cmd *)desc.data; |
| 2184 | |
| 2185 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); |
| 2186 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 2187 | if (ret) { |
| 2188 | dev_err(&hdev->pdev->dev, |
| 2189 | "mac speed/autoneg/duplex query cmd failed %d\n", |
| 2190 | ret); |
| 2191 | return ret; |
| 2192 | } |
| 2193 | |
| 2194 | *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); |
| 2195 | speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, |
| 2196 | HCLGE_QUERY_SPEED_S); |
| 2197 | |
| 2198 | ret = hclge_parse_speed(speed_tmp, speed); |
| 2199 | if (ret) { |
| 2200 | dev_err(&hdev->pdev->dev, |
| 2201 | "could not parse speed(=%d), %d\n", speed_tmp, ret); |
| 2202 | return -EIO; |
| 2203 | } |
| 2204 | |
| 2205 | return 0; |
| 2206 | } |
| 2207 | |
| 2208 | static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) |
| 2209 | { |
| 2210 | struct hclge_config_auto_neg_cmd *req; |
| 2211 | struct hclge_desc desc; |
| 2212 | u32 flag = 0; |
| 2213 | int ret; |
| 2214 | |
| 2215 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); |
| 2216 | |
| 2217 | req = (struct hclge_config_auto_neg_cmd *)desc.data; |
| 2218 | hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); |
| 2219 | req->cfg_an_cmd_flag = cpu_to_le32(flag); |
| 2220 | |
| 2221 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 2222 | if (ret) { |
| 2223 | dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", |
| 2224 | ret); |
| 2225 | return ret; |
| 2226 | } |
| 2227 | |
| 2228 | return 0; |
| 2229 | } |
| 2230 | |
| 2231 | static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) |
| 2232 | { |
| 2233 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2234 | struct hclge_dev *hdev = vport->back; |
| 2235 | |
| 2236 | return hclge_set_autoneg_en(hdev, enable); |
| 2237 | } |
| 2238 | |
| 2239 | static int hclge_get_autoneg(struct hnae3_handle *handle) |
| 2240 | { |
| 2241 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2242 | struct hclge_dev *hdev = vport->back; |
| 2243 | struct phy_device *phydev = hdev->hw.mac.phydev; |
| 2244 | |
| 2245 | if (phydev) |
| 2246 | return phydev->autoneg; |
| 2247 | |
| 2248 | return hdev->hw.mac.autoneg; |
| 2249 | } |
| 2250 | |
| 2251 | static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, |
| 2252 | bool mask_vlan, |
| 2253 | u8 *mac_mask) |
| 2254 | { |
| 2255 | struct hclge_mac_vlan_mask_entry_cmd *req; |
| 2256 | struct hclge_desc desc; |
| 2257 | int status; |
| 2258 | |
| 2259 | req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; |
| 2260 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); |
| 2261 | |
| 2262 | hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, |
| 2263 | mask_vlan ? 1 : 0); |
| 2264 | ether_addr_copy(req->mac_mask, mac_mask); |
| 2265 | |
| 2266 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 2267 | if (status) |
| 2268 | dev_err(&hdev->pdev->dev, |
| 2269 | "Config mac_vlan_mask failed for cmd_send, ret =%d\n", |
| 2270 | status); |
| 2271 | |
| 2272 | return status; |
| 2273 | } |
| 2274 | |
| 2275 | static int hclge_mac_init(struct hclge_dev *hdev) |
| 2276 | { |
| 2277 | struct hnae3_handle *handle = &hdev->vport[0].nic; |
| 2278 | struct net_device *netdev = handle->kinfo.netdev; |
| 2279 | struct hclge_mac *mac = &hdev->hw.mac; |
| 2280 | u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; |
| 2281 | struct hclge_vport *vport; |
| 2282 | int mtu; |
| 2283 | int ret; |
| 2284 | int i; |
| 2285 | |
| 2286 | ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); |
| 2287 | if (ret) { |
| 2288 | dev_err(&hdev->pdev->dev, |
| 2289 | "Config mac speed dup fail ret=%d\n", ret); |
| 2290 | return ret; |
| 2291 | } |
| 2292 | |
| 2293 | mac->link = 0; |
| 2294 | |
| 2295 | /* Initialize the MTA table work mode */ |
| 2296 | hdev->enable_mta = true; |
| 2297 | hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; |
| 2298 | |
| 2299 | ret = hclge_set_mta_filter_mode(hdev, |
| 2300 | hdev->mta_mac_sel_type, |
| 2301 | hdev->enable_mta); |
| 2302 | if (ret) { |
| 2303 | dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", |
| 2304 | ret); |
| 2305 | return ret; |
| 2306 | } |
| 2307 | |
| 2308 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
| 2309 | vport = &hdev->vport[i]; |
| 2310 | vport->accept_mta_mc = false; |
| 2311 | |
| 2312 | memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow)); |
| 2313 | ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false); |
| 2314 | if (ret) { |
| 2315 | dev_err(&hdev->pdev->dev, |
| 2316 | "set mta filter mode fail ret=%d\n", ret); |
| 2317 | return ret; |
| 2318 | } |
| 2319 | } |
| 2320 | |
| 2321 | ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); |
| 2322 | if (ret) { |
| 2323 | dev_err(&hdev->pdev->dev, |
| 2324 | "set default mac_vlan_mask fail ret=%d\n", ret); |
| 2325 | return ret; |
| 2326 | } |
| 2327 | |
| 2328 | if (netdev) |
| 2329 | mtu = netdev->mtu; |
| 2330 | else |
| 2331 | mtu = ETH_DATA_LEN; |
| 2332 | |
| 2333 | ret = hclge_set_mtu(handle, mtu); |
| 2334 | if (ret) { |
| 2335 | dev_err(&hdev->pdev->dev, |
| 2336 | "set mtu failed ret=%d\n", ret); |
| 2337 | return ret; |
| 2338 | } |
| 2339 | |
| 2340 | return 0; |
| 2341 | } |
| 2342 | |
| 2343 | static void hclge_mbx_task_schedule(struct hclge_dev *hdev) |
| 2344 | { |
| 2345 | if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) |
| 2346 | schedule_work(&hdev->mbx_service_task); |
| 2347 | } |
| 2348 | |
| 2349 | static void hclge_reset_task_schedule(struct hclge_dev *hdev) |
| 2350 | { |
| 2351 | if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) |
| 2352 | schedule_work(&hdev->rst_service_task); |
| 2353 | } |
| 2354 | |
| 2355 | static void hclge_task_schedule(struct hclge_dev *hdev) |
| 2356 | { |
| 2357 | if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && |
| 2358 | !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && |
| 2359 | !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) |
| 2360 | (void)schedule_work(&hdev->service_task); |
| 2361 | } |
| 2362 | |
| 2363 | static int hclge_get_mac_link_status(struct hclge_dev *hdev) |
| 2364 | { |
| 2365 | struct hclge_link_status_cmd *req; |
| 2366 | struct hclge_desc desc; |
| 2367 | int link_status; |
| 2368 | int ret; |
| 2369 | |
| 2370 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); |
| 2371 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 2372 | if (ret) { |
| 2373 | dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", |
| 2374 | ret); |
| 2375 | return ret; |
| 2376 | } |
| 2377 | |
| 2378 | req = (struct hclge_link_status_cmd *)desc.data; |
| 2379 | link_status = req->status & HCLGE_LINK_STATUS; |
| 2380 | |
| 2381 | return !!link_status; |
| 2382 | } |
| 2383 | |
| 2384 | static int hclge_get_mac_phy_link(struct hclge_dev *hdev) |
| 2385 | { |
| 2386 | int mac_state; |
| 2387 | int link_stat; |
| 2388 | |
| 2389 | mac_state = hclge_get_mac_link_status(hdev); |
| 2390 | |
| 2391 | if (hdev->hw.mac.phydev) { |
| 2392 | if (!genphy_read_status(hdev->hw.mac.phydev)) |
| 2393 | link_stat = mac_state & |
| 2394 | hdev->hw.mac.phydev->link; |
| 2395 | else |
| 2396 | link_stat = 0; |
| 2397 | |
| 2398 | } else { |
| 2399 | link_stat = mac_state; |
| 2400 | } |
| 2401 | |
| 2402 | return !!link_stat; |
| 2403 | } |
| 2404 | |
| 2405 | static void hclge_update_link_status(struct hclge_dev *hdev) |
| 2406 | { |
| 2407 | struct hnae3_client *client = hdev->nic_client; |
| 2408 | struct hnae3_handle *handle; |
| 2409 | int state; |
| 2410 | int i; |
| 2411 | |
| 2412 | if (!client) |
| 2413 | return; |
| 2414 | state = hclge_get_mac_phy_link(hdev); |
| 2415 | if (state != hdev->hw.mac.link) { |
| 2416 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
| 2417 | handle = &hdev->vport[i].nic; |
| 2418 | client->ops->link_status_change(handle, state); |
| 2419 | } |
| 2420 | hdev->hw.mac.link = state; |
| 2421 | } |
| 2422 | } |
| 2423 | |
| 2424 | static int hclge_update_speed_duplex(struct hclge_dev *hdev) |
| 2425 | { |
| 2426 | struct hclge_mac mac = hdev->hw.mac; |
| 2427 | u8 duplex; |
| 2428 | int speed; |
| 2429 | int ret; |
| 2430 | |
| 2431 | /* get the speed and duplex as autoneg'result from mac cmd when phy |
| 2432 | * doesn't exit. |
| 2433 | */ |
| 2434 | if (mac.phydev || !mac.autoneg) |
| 2435 | return 0; |
| 2436 | |
| 2437 | ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); |
| 2438 | if (ret) { |
| 2439 | dev_err(&hdev->pdev->dev, |
| 2440 | "mac autoneg/speed/duplex query failed %d\n", ret); |
| 2441 | return ret; |
| 2442 | } |
| 2443 | |
| 2444 | if ((mac.speed != speed) || (mac.duplex != duplex)) { |
| 2445 | ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); |
| 2446 | if (ret) { |
| 2447 | dev_err(&hdev->pdev->dev, |
| 2448 | "mac speed/duplex config failed %d\n", ret); |
| 2449 | return ret; |
| 2450 | } |
| 2451 | } |
| 2452 | |
| 2453 | return 0; |
| 2454 | } |
| 2455 | |
| 2456 | static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) |
| 2457 | { |
| 2458 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2459 | struct hclge_dev *hdev = vport->back; |
| 2460 | |
| 2461 | return hclge_update_speed_duplex(hdev); |
| 2462 | } |
| 2463 | |
| 2464 | static int hclge_get_status(struct hnae3_handle *handle) |
| 2465 | { |
| 2466 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2467 | struct hclge_dev *hdev = vport->back; |
| 2468 | |
| 2469 | hclge_update_link_status(hdev); |
| 2470 | |
| 2471 | return hdev->hw.mac.link; |
| 2472 | } |
| 2473 | |
| 2474 | static void hclge_service_timer(struct timer_list *t) |
| 2475 | { |
| 2476 | struct hclge_dev *hdev = from_timer(hdev, t, service_timer); |
| 2477 | |
| 2478 | mod_timer(&hdev->service_timer, jiffies + HZ); |
| 2479 | hdev->hw_stats.stats_timer++; |
| 2480 | hclge_task_schedule(hdev); |
| 2481 | } |
| 2482 | |
| 2483 | static void hclge_service_complete(struct hclge_dev *hdev) |
| 2484 | { |
| 2485 | WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); |
| 2486 | |
| 2487 | /* Flush memory before next watchdog */ |
| 2488 | smp_mb__before_atomic(); |
| 2489 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); |
| 2490 | } |
| 2491 | |
| 2492 | static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) |
| 2493 | { |
| 2494 | u32 rst_src_reg; |
| 2495 | u32 cmdq_src_reg; |
| 2496 | |
| 2497 | /* fetch the events from their corresponding regs */ |
| 2498 | rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); |
| 2499 | cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); |
| 2500 | |
| 2501 | /* Assumption: If by any chance reset and mailbox events are reported |
| 2502 | * together then we will only process reset event in this go and will |
| 2503 | * defer the processing of the mailbox events. Since, we would have not |
| 2504 | * cleared RX CMDQ event this time we would receive again another |
| 2505 | * interrupt from H/W just for the mailbox. |
| 2506 | */ |
| 2507 | |
| 2508 | /* check for vector0 reset event sources */ |
| 2509 | if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { |
| 2510 | set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); |
| 2511 | *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); |
| 2512 | return HCLGE_VECTOR0_EVENT_RST; |
| 2513 | } |
| 2514 | |
| 2515 | if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { |
| 2516 | set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); |
| 2517 | *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); |
| 2518 | return HCLGE_VECTOR0_EVENT_RST; |
| 2519 | } |
| 2520 | |
| 2521 | if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { |
| 2522 | set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); |
| 2523 | *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); |
| 2524 | return HCLGE_VECTOR0_EVENT_RST; |
| 2525 | } |
| 2526 | |
| 2527 | /* check for vector0 mailbox(=CMDQ RX) event source */ |
| 2528 | if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { |
| 2529 | cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); |
| 2530 | *clearval = cmdq_src_reg; |
| 2531 | return HCLGE_VECTOR0_EVENT_MBX; |
| 2532 | } |
| 2533 | |
| 2534 | return HCLGE_VECTOR0_EVENT_OTHER; |
| 2535 | } |
| 2536 | |
| 2537 | static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, |
| 2538 | u32 regclr) |
| 2539 | { |
| 2540 | switch (event_type) { |
| 2541 | case HCLGE_VECTOR0_EVENT_RST: |
| 2542 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); |
| 2543 | break; |
| 2544 | case HCLGE_VECTOR0_EVENT_MBX: |
| 2545 | hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); |
| 2546 | break; |
| 2547 | } |
| 2548 | } |
| 2549 | |
| 2550 | static void hclge_clear_all_event_cause(struct hclge_dev *hdev) |
| 2551 | { |
| 2552 | hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, |
| 2553 | BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | |
| 2554 | BIT(HCLGE_VECTOR0_CORERESET_INT_B) | |
| 2555 | BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); |
| 2556 | hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); |
| 2557 | } |
| 2558 | |
| 2559 | static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) |
| 2560 | { |
| 2561 | writel(enable ? 1 : 0, vector->addr); |
| 2562 | } |
| 2563 | |
| 2564 | static irqreturn_t hclge_misc_irq_handle(int irq, void *data) |
| 2565 | { |
| 2566 | struct hclge_dev *hdev = data; |
| 2567 | u32 event_cause; |
| 2568 | u32 clearval; |
| 2569 | |
| 2570 | hclge_enable_vector(&hdev->misc_vector, false); |
| 2571 | event_cause = hclge_check_event_cause(hdev, &clearval); |
| 2572 | |
| 2573 | /* vector 0 interrupt is shared with reset and mailbox source events.*/ |
| 2574 | switch (event_cause) { |
| 2575 | case HCLGE_VECTOR0_EVENT_RST: |
| 2576 | hclge_reset_task_schedule(hdev); |
| 2577 | break; |
| 2578 | case HCLGE_VECTOR0_EVENT_MBX: |
| 2579 | /* If we are here then, |
| 2580 | * 1. Either we are not handling any mbx task and we are not |
| 2581 | * scheduled as well |
| 2582 | * OR |
| 2583 | * 2. We could be handling a mbx task but nothing more is |
| 2584 | * scheduled. |
| 2585 | * In both cases, we should schedule mbx task as there are more |
| 2586 | * mbx messages reported by this interrupt. |
| 2587 | */ |
| 2588 | hclge_mbx_task_schedule(hdev); |
| 2589 | break; |
| 2590 | default: |
| 2591 | dev_warn(&hdev->pdev->dev, |
| 2592 | "received unknown or unhandled event of vector0\n"); |
| 2593 | break; |
| 2594 | } |
| 2595 | |
| 2596 | /* clear the source of interrupt if it is not cause by reset */ |
| 2597 | if (event_cause != HCLGE_VECTOR0_EVENT_RST) { |
| 2598 | hclge_clear_event_cause(hdev, event_cause, clearval); |
| 2599 | hclge_enable_vector(&hdev->misc_vector, true); |
| 2600 | } |
| 2601 | |
| 2602 | return IRQ_HANDLED; |
| 2603 | } |
| 2604 | |
| 2605 | static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) |
| 2606 | { |
| 2607 | if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { |
| 2608 | dev_warn(&hdev->pdev->dev, |
| 2609 | "vector(vector_id %d) has been freed.\n", vector_id); |
| 2610 | return; |
| 2611 | } |
| 2612 | |
| 2613 | hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; |
| 2614 | hdev->num_msi_left += 1; |
| 2615 | hdev->num_msi_used -= 1; |
| 2616 | } |
| 2617 | |
| 2618 | static void hclge_get_misc_vector(struct hclge_dev *hdev) |
| 2619 | { |
| 2620 | struct hclge_misc_vector *vector = &hdev->misc_vector; |
| 2621 | |
| 2622 | vector->vector_irq = pci_irq_vector(hdev->pdev, 0); |
| 2623 | |
| 2624 | vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; |
| 2625 | hdev->vector_status[0] = 0; |
| 2626 | |
| 2627 | hdev->num_msi_left -= 1; |
| 2628 | hdev->num_msi_used += 1; |
| 2629 | } |
| 2630 | |
| 2631 | static int hclge_misc_irq_init(struct hclge_dev *hdev) |
| 2632 | { |
| 2633 | int ret; |
| 2634 | |
| 2635 | hclge_get_misc_vector(hdev); |
| 2636 | |
| 2637 | /* this would be explicitly freed in the end */ |
| 2638 | ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, |
| 2639 | 0, "hclge_misc", hdev); |
| 2640 | if (ret) { |
| 2641 | hclge_free_vector(hdev, 0); |
| 2642 | dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", |
| 2643 | hdev->misc_vector.vector_irq); |
| 2644 | } |
| 2645 | |
| 2646 | return ret; |
| 2647 | } |
| 2648 | |
| 2649 | static void hclge_misc_irq_uninit(struct hclge_dev *hdev) |
| 2650 | { |
| 2651 | free_irq(hdev->misc_vector.vector_irq, hdev); |
| 2652 | hclge_free_vector(hdev, 0); |
| 2653 | } |
| 2654 | |
| 2655 | static int hclge_notify_client(struct hclge_dev *hdev, |
| 2656 | enum hnae3_reset_notify_type type) |
| 2657 | { |
| 2658 | struct hnae3_client *client = hdev->nic_client; |
| 2659 | u16 i; |
| 2660 | |
| 2661 | if (!client->ops->reset_notify) |
| 2662 | return -EOPNOTSUPP; |
| 2663 | |
| 2664 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
| 2665 | struct hnae3_handle *handle = &hdev->vport[i].nic; |
| 2666 | int ret; |
| 2667 | |
| 2668 | ret = client->ops->reset_notify(handle, type); |
| 2669 | if (ret) |
| 2670 | return ret; |
| 2671 | } |
| 2672 | |
| 2673 | return 0; |
| 2674 | } |
| 2675 | |
| 2676 | static int hclge_reset_wait(struct hclge_dev *hdev) |
| 2677 | { |
| 2678 | #define HCLGE_RESET_WATI_MS 100 |
| 2679 | #define HCLGE_RESET_WAIT_CNT 5 |
| 2680 | u32 val, reg, reg_bit; |
| 2681 | u32 cnt = 0; |
| 2682 | |
| 2683 | switch (hdev->reset_type) { |
| 2684 | case HNAE3_GLOBAL_RESET: |
| 2685 | reg = HCLGE_GLOBAL_RESET_REG; |
| 2686 | reg_bit = HCLGE_GLOBAL_RESET_BIT; |
| 2687 | break; |
| 2688 | case HNAE3_CORE_RESET: |
| 2689 | reg = HCLGE_GLOBAL_RESET_REG; |
| 2690 | reg_bit = HCLGE_CORE_RESET_BIT; |
| 2691 | break; |
| 2692 | case HNAE3_FUNC_RESET: |
| 2693 | reg = HCLGE_FUN_RST_ING; |
| 2694 | reg_bit = HCLGE_FUN_RST_ING_B; |
| 2695 | break; |
| 2696 | default: |
| 2697 | dev_err(&hdev->pdev->dev, |
| 2698 | "Wait for unsupported reset type: %d\n", |
| 2699 | hdev->reset_type); |
| 2700 | return -EINVAL; |
| 2701 | } |
| 2702 | |
| 2703 | val = hclge_read_dev(&hdev->hw, reg); |
| 2704 | while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { |
| 2705 | msleep(HCLGE_RESET_WATI_MS); |
| 2706 | val = hclge_read_dev(&hdev->hw, reg); |
| 2707 | cnt++; |
| 2708 | } |
| 2709 | |
| 2710 | if (cnt >= HCLGE_RESET_WAIT_CNT) { |
| 2711 | dev_warn(&hdev->pdev->dev, |
| 2712 | "Wait for reset timeout: %d\n", hdev->reset_type); |
| 2713 | return -EBUSY; |
| 2714 | } |
| 2715 | |
| 2716 | return 0; |
| 2717 | } |
| 2718 | |
| 2719 | int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) |
| 2720 | { |
| 2721 | struct hclge_desc desc; |
| 2722 | struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; |
| 2723 | int ret; |
| 2724 | |
| 2725 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); |
| 2726 | hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); |
| 2727 | req->fun_reset_vfid = func_id; |
| 2728 | |
| 2729 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 2730 | if (ret) |
| 2731 | dev_err(&hdev->pdev->dev, |
| 2732 | "send function reset cmd fail, status =%d\n", ret); |
| 2733 | |
| 2734 | return ret; |
| 2735 | } |
| 2736 | |
| 2737 | static void hclge_do_reset(struct hclge_dev *hdev) |
| 2738 | { |
| 2739 | struct pci_dev *pdev = hdev->pdev; |
| 2740 | u32 val; |
| 2741 | |
| 2742 | switch (hdev->reset_type) { |
| 2743 | case HNAE3_GLOBAL_RESET: |
| 2744 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); |
| 2745 | hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); |
| 2746 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); |
| 2747 | dev_info(&pdev->dev, "Global Reset requested\n"); |
| 2748 | break; |
| 2749 | case HNAE3_CORE_RESET: |
| 2750 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); |
| 2751 | hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1); |
| 2752 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); |
| 2753 | dev_info(&pdev->dev, "Core Reset requested\n"); |
| 2754 | break; |
| 2755 | case HNAE3_FUNC_RESET: |
| 2756 | dev_info(&pdev->dev, "PF Reset requested\n"); |
| 2757 | hclge_func_reset_cmd(hdev, 0); |
| 2758 | /* schedule again to check later */ |
| 2759 | set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); |
| 2760 | hclge_reset_task_schedule(hdev); |
| 2761 | break; |
| 2762 | default: |
| 2763 | dev_warn(&pdev->dev, |
| 2764 | "Unsupported reset type: %d\n", hdev->reset_type); |
| 2765 | break; |
| 2766 | } |
| 2767 | } |
| 2768 | |
| 2769 | static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, |
| 2770 | unsigned long *addr) |
| 2771 | { |
| 2772 | enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; |
| 2773 | |
| 2774 | /* return the highest priority reset level amongst all */ |
| 2775 | if (test_bit(HNAE3_GLOBAL_RESET, addr)) |
| 2776 | rst_level = HNAE3_GLOBAL_RESET; |
| 2777 | else if (test_bit(HNAE3_CORE_RESET, addr)) |
| 2778 | rst_level = HNAE3_CORE_RESET; |
| 2779 | else if (test_bit(HNAE3_IMP_RESET, addr)) |
| 2780 | rst_level = HNAE3_IMP_RESET; |
| 2781 | else if (test_bit(HNAE3_FUNC_RESET, addr)) |
| 2782 | rst_level = HNAE3_FUNC_RESET; |
| 2783 | |
| 2784 | /* now, clear all other resets */ |
| 2785 | clear_bit(HNAE3_GLOBAL_RESET, addr); |
| 2786 | clear_bit(HNAE3_CORE_RESET, addr); |
| 2787 | clear_bit(HNAE3_IMP_RESET, addr); |
| 2788 | clear_bit(HNAE3_FUNC_RESET, addr); |
| 2789 | |
| 2790 | return rst_level; |
| 2791 | } |
| 2792 | |
| 2793 | static void hclge_clear_reset_cause(struct hclge_dev *hdev) |
| 2794 | { |
| 2795 | u32 clearval = 0; |
| 2796 | |
| 2797 | switch (hdev->reset_type) { |
| 2798 | case HNAE3_IMP_RESET: |
| 2799 | clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); |
| 2800 | break; |
| 2801 | case HNAE3_GLOBAL_RESET: |
| 2802 | clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); |
| 2803 | break; |
| 2804 | case HNAE3_CORE_RESET: |
| 2805 | clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); |
| 2806 | break; |
| 2807 | default: |
| 2808 | break; |
| 2809 | } |
| 2810 | |
| 2811 | if (!clearval) |
| 2812 | return; |
| 2813 | |
| 2814 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval); |
| 2815 | hclge_enable_vector(&hdev->misc_vector, true); |
| 2816 | } |
| 2817 | |
| 2818 | static void hclge_reset(struct hclge_dev *hdev) |
| 2819 | { |
| 2820 | /* perform reset of the stack & ae device for a client */ |
| 2821 | |
| 2822 | hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); |
| 2823 | |
| 2824 | if (!hclge_reset_wait(hdev)) { |
| 2825 | rtnl_lock(); |
| 2826 | hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); |
| 2827 | hclge_reset_ae_dev(hdev->ae_dev); |
| 2828 | hclge_notify_client(hdev, HNAE3_INIT_CLIENT); |
| 2829 | rtnl_unlock(); |
| 2830 | |
| 2831 | hclge_clear_reset_cause(hdev); |
| 2832 | } else { |
| 2833 | /* schedule again to check pending resets later */ |
| 2834 | set_bit(hdev->reset_type, &hdev->reset_pending); |
| 2835 | hclge_reset_task_schedule(hdev); |
| 2836 | } |
| 2837 | |
| 2838 | hclge_notify_client(hdev, HNAE3_UP_CLIENT); |
| 2839 | } |
| 2840 | |
| 2841 | static void hclge_reset_event(struct hnae3_handle *handle) |
| 2842 | { |
| 2843 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2844 | struct hclge_dev *hdev = vport->back; |
| 2845 | |
| 2846 | /* check if this is a new reset request and we are not here just because |
| 2847 | * last reset attempt did not succeed and watchdog hit us again. We will |
| 2848 | * know this if last reset request did not occur very recently (watchdog |
| 2849 | * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) |
| 2850 | * In case of new request we reset the "reset level" to PF reset. |
| 2851 | */ |
| 2852 | if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) |
| 2853 | handle->reset_level = HNAE3_FUNC_RESET; |
| 2854 | |
| 2855 | dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", |
| 2856 | handle->reset_level); |
| 2857 | |
| 2858 | /* request reset & schedule reset task */ |
| 2859 | set_bit(handle->reset_level, &hdev->reset_request); |
| 2860 | hclge_reset_task_schedule(hdev); |
| 2861 | |
| 2862 | if (handle->reset_level < HNAE3_GLOBAL_RESET) |
| 2863 | handle->reset_level++; |
| 2864 | |
| 2865 | handle->last_reset_time = jiffies; |
| 2866 | } |
| 2867 | |
| 2868 | static void hclge_reset_subtask(struct hclge_dev *hdev) |
| 2869 | { |
| 2870 | /* check if there is any ongoing reset in the hardware. This status can |
| 2871 | * be checked from reset_pending. If there is then, we need to wait for |
| 2872 | * hardware to complete reset. |
| 2873 | * a. If we are able to figure out in reasonable time that hardware |
| 2874 | * has fully resetted then, we can proceed with driver, client |
| 2875 | * reset. |
| 2876 | * b. else, we can come back later to check this status so re-sched |
| 2877 | * now. |
| 2878 | */ |
| 2879 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); |
| 2880 | if (hdev->reset_type != HNAE3_NONE_RESET) |
| 2881 | hclge_reset(hdev); |
| 2882 | |
| 2883 | /* check if we got any *new* reset requests to be honored */ |
| 2884 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); |
| 2885 | if (hdev->reset_type != HNAE3_NONE_RESET) |
| 2886 | hclge_do_reset(hdev); |
| 2887 | |
| 2888 | hdev->reset_type = HNAE3_NONE_RESET; |
| 2889 | } |
| 2890 | |
| 2891 | static void hclge_reset_service_task(struct work_struct *work) |
| 2892 | { |
| 2893 | struct hclge_dev *hdev = |
| 2894 | container_of(work, struct hclge_dev, rst_service_task); |
| 2895 | |
| 2896 | if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
| 2897 | return; |
| 2898 | |
| 2899 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); |
| 2900 | |
| 2901 | hclge_reset_subtask(hdev); |
| 2902 | |
| 2903 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); |
| 2904 | } |
| 2905 | |
| 2906 | static void hclge_mailbox_service_task(struct work_struct *work) |
| 2907 | { |
| 2908 | struct hclge_dev *hdev = |
| 2909 | container_of(work, struct hclge_dev, mbx_service_task); |
| 2910 | |
| 2911 | if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) |
| 2912 | return; |
| 2913 | |
| 2914 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); |
| 2915 | |
| 2916 | hclge_mbx_handler(hdev); |
| 2917 | |
| 2918 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); |
| 2919 | } |
| 2920 | |
| 2921 | static void hclge_service_task(struct work_struct *work) |
| 2922 | { |
| 2923 | struct hclge_dev *hdev = |
| 2924 | container_of(work, struct hclge_dev, service_task); |
| 2925 | |
| 2926 | if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { |
| 2927 | hclge_update_stats_for_all(hdev); |
| 2928 | hdev->hw_stats.stats_timer = 0; |
| 2929 | } |
| 2930 | |
| 2931 | hclge_update_speed_duplex(hdev); |
| 2932 | hclge_update_link_status(hdev); |
| 2933 | hclge_service_complete(hdev); |
| 2934 | } |
| 2935 | |
| 2936 | struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) |
| 2937 | { |
| 2938 | /* VF handle has no client */ |
| 2939 | if (!handle->client) |
| 2940 | return container_of(handle, struct hclge_vport, nic); |
| 2941 | else if (handle->client->type == HNAE3_CLIENT_ROCE) |
| 2942 | return container_of(handle, struct hclge_vport, roce); |
| 2943 | else |
| 2944 | return container_of(handle, struct hclge_vport, nic); |
| 2945 | } |
| 2946 | |
| 2947 | static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, |
| 2948 | struct hnae3_vector_info *vector_info) |
| 2949 | { |
| 2950 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2951 | struct hnae3_vector_info *vector = vector_info; |
| 2952 | struct hclge_dev *hdev = vport->back; |
| 2953 | int alloc = 0; |
| 2954 | int i, j; |
| 2955 | |
| 2956 | vector_num = min(hdev->num_msi_left, vector_num); |
| 2957 | |
| 2958 | for (j = 0; j < vector_num; j++) { |
| 2959 | for (i = 1; i < hdev->num_msi; i++) { |
| 2960 | if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { |
| 2961 | vector->vector = pci_irq_vector(hdev->pdev, i); |
| 2962 | vector->io_addr = hdev->hw.io_base + |
| 2963 | HCLGE_VECTOR_REG_BASE + |
| 2964 | (i - 1) * HCLGE_VECTOR_REG_OFFSET + |
| 2965 | vport->vport_id * |
| 2966 | HCLGE_VECTOR_VF_OFFSET; |
| 2967 | hdev->vector_status[i] = vport->vport_id; |
| 2968 | hdev->vector_irq[i] = vector->vector; |
| 2969 | |
| 2970 | vector++; |
| 2971 | alloc++; |
| 2972 | |
| 2973 | break; |
| 2974 | } |
| 2975 | } |
| 2976 | } |
| 2977 | hdev->num_msi_left -= alloc; |
| 2978 | hdev->num_msi_used += alloc; |
| 2979 | |
| 2980 | return alloc; |
| 2981 | } |
| 2982 | |
| 2983 | static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) |
| 2984 | { |
| 2985 | int i; |
| 2986 | |
| 2987 | for (i = 0; i < hdev->num_msi; i++) |
| 2988 | if (vector == hdev->vector_irq[i]) |
| 2989 | return i; |
| 2990 | |
| 2991 | return -EINVAL; |
| 2992 | } |
| 2993 | |
| 2994 | static int hclge_put_vector(struct hnae3_handle *handle, int vector) |
| 2995 | { |
| 2996 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 2997 | struct hclge_dev *hdev = vport->back; |
| 2998 | int vector_id; |
| 2999 | |
| 3000 | vector_id = hclge_get_vector_index(hdev, vector); |
| 3001 | if (vector_id < 0) { |
| 3002 | dev_err(&hdev->pdev->dev, |
| 3003 | "Get vector index fail. vector_id =%d\n", vector_id); |
| 3004 | return vector_id; |
| 3005 | } |
| 3006 | |
| 3007 | hclge_free_vector(hdev, vector_id); |
| 3008 | |
| 3009 | return 0; |
| 3010 | } |
| 3011 | |
| 3012 | static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) |
| 3013 | { |
| 3014 | return HCLGE_RSS_KEY_SIZE; |
| 3015 | } |
| 3016 | |
| 3017 | static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) |
| 3018 | { |
| 3019 | return HCLGE_RSS_IND_TBL_SIZE; |
| 3020 | } |
| 3021 | |
| 3022 | static int hclge_set_rss_algo_key(struct hclge_dev *hdev, |
| 3023 | const u8 hfunc, const u8 *key) |
| 3024 | { |
| 3025 | struct hclge_rss_config_cmd *req; |
| 3026 | struct hclge_desc desc; |
| 3027 | int key_offset; |
| 3028 | int key_size; |
| 3029 | int ret; |
| 3030 | |
| 3031 | req = (struct hclge_rss_config_cmd *)desc.data; |
| 3032 | |
| 3033 | for (key_offset = 0; key_offset < 3; key_offset++) { |
| 3034 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, |
| 3035 | false); |
| 3036 | |
| 3037 | req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); |
| 3038 | req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); |
| 3039 | |
| 3040 | if (key_offset == 2) |
| 3041 | key_size = |
| 3042 | HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; |
| 3043 | else |
| 3044 | key_size = HCLGE_RSS_HASH_KEY_NUM; |
| 3045 | |
| 3046 | memcpy(req->hash_key, |
| 3047 | key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); |
| 3048 | |
| 3049 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3050 | if (ret) { |
| 3051 | dev_err(&hdev->pdev->dev, |
| 3052 | "Configure RSS config fail, status = %d\n", |
| 3053 | ret); |
| 3054 | return ret; |
| 3055 | } |
| 3056 | } |
| 3057 | return 0; |
| 3058 | } |
| 3059 | |
| 3060 | static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) |
| 3061 | { |
| 3062 | struct hclge_rss_indirection_table_cmd *req; |
| 3063 | struct hclge_desc desc; |
| 3064 | int i, j; |
| 3065 | int ret; |
| 3066 | |
| 3067 | req = (struct hclge_rss_indirection_table_cmd *)desc.data; |
| 3068 | |
| 3069 | for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { |
| 3070 | hclge_cmd_setup_basic_desc |
| 3071 | (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); |
| 3072 | |
| 3073 | req->start_table_index = |
| 3074 | cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); |
| 3075 | req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); |
| 3076 | |
| 3077 | for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) |
| 3078 | req->rss_result[j] = |
| 3079 | indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; |
| 3080 | |
| 3081 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3082 | if (ret) { |
| 3083 | dev_err(&hdev->pdev->dev, |
| 3084 | "Configure rss indir table fail,status = %d\n", |
| 3085 | ret); |
| 3086 | return ret; |
| 3087 | } |
| 3088 | } |
| 3089 | return 0; |
| 3090 | } |
| 3091 | |
| 3092 | static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, |
| 3093 | u16 *tc_size, u16 *tc_offset) |
| 3094 | { |
| 3095 | struct hclge_rss_tc_mode_cmd *req; |
| 3096 | struct hclge_desc desc; |
| 3097 | int ret; |
| 3098 | int i; |
| 3099 | |
| 3100 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); |
| 3101 | req = (struct hclge_rss_tc_mode_cmd *)desc.data; |
| 3102 | |
| 3103 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 3104 | u16 mode = 0; |
| 3105 | |
| 3106 | hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); |
| 3107 | hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M, |
| 3108 | HCLGE_RSS_TC_SIZE_S, tc_size[i]); |
| 3109 | hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M, |
| 3110 | HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); |
| 3111 | |
| 3112 | req->rss_tc_mode[i] = cpu_to_le16(mode); |
| 3113 | } |
| 3114 | |
| 3115 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3116 | if (ret) { |
| 3117 | dev_err(&hdev->pdev->dev, |
| 3118 | "Configure rss tc mode fail, status = %d\n", ret); |
| 3119 | return ret; |
| 3120 | } |
| 3121 | |
| 3122 | return 0; |
| 3123 | } |
| 3124 | |
| 3125 | static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) |
| 3126 | { |
| 3127 | struct hclge_rss_input_tuple_cmd *req; |
| 3128 | struct hclge_desc desc; |
| 3129 | int ret; |
| 3130 | |
| 3131 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); |
| 3132 | |
| 3133 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; |
| 3134 | |
| 3135 | /* Get the tuple cfg from pf */ |
| 3136 | req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; |
| 3137 | req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; |
| 3138 | req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; |
| 3139 | req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; |
| 3140 | req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; |
| 3141 | req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; |
| 3142 | req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; |
| 3143 | req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; |
| 3144 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3145 | if (ret) { |
| 3146 | dev_err(&hdev->pdev->dev, |
| 3147 | "Configure rss input fail, status = %d\n", ret); |
| 3148 | return ret; |
| 3149 | } |
| 3150 | |
| 3151 | return 0; |
| 3152 | } |
| 3153 | |
| 3154 | static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, |
| 3155 | u8 *key, u8 *hfunc) |
| 3156 | { |
| 3157 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3158 | int i; |
| 3159 | |
| 3160 | /* Get hash algorithm */ |
| 3161 | if (hfunc) |
| 3162 | *hfunc = vport->rss_algo; |
| 3163 | |
| 3164 | /* Get the RSS Key required by the user */ |
| 3165 | if (key) |
| 3166 | memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); |
| 3167 | |
| 3168 | /* Get indirect table */ |
| 3169 | if (indir) |
| 3170 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) |
| 3171 | indir[i] = vport->rss_indirection_tbl[i]; |
| 3172 | |
| 3173 | return 0; |
| 3174 | } |
| 3175 | |
| 3176 | static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, |
| 3177 | const u8 *key, const u8 hfunc) |
| 3178 | { |
| 3179 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3180 | struct hclge_dev *hdev = vport->back; |
| 3181 | u8 hash_algo; |
| 3182 | int ret, i; |
| 3183 | |
| 3184 | /* Set the RSS Hash Key if specififed by the user */ |
| 3185 | if (key) { |
| 3186 | |
| 3187 | if (hfunc == ETH_RSS_HASH_TOP || |
| 3188 | hfunc == ETH_RSS_HASH_NO_CHANGE) |
| 3189 | hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; |
| 3190 | else |
| 3191 | return -EINVAL; |
| 3192 | ret = hclge_set_rss_algo_key(hdev, hash_algo, key); |
| 3193 | if (ret) |
| 3194 | return ret; |
| 3195 | |
| 3196 | /* Update the shadow RSS key with user specified qids */ |
| 3197 | memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); |
| 3198 | vport->rss_algo = hash_algo; |
| 3199 | } |
| 3200 | |
| 3201 | /* Update the shadow RSS table with user specified qids */ |
| 3202 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) |
| 3203 | vport->rss_indirection_tbl[i] = indir[i]; |
| 3204 | |
| 3205 | /* Update the hardware */ |
| 3206 | return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); |
| 3207 | } |
| 3208 | |
| 3209 | static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) |
| 3210 | { |
| 3211 | u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; |
| 3212 | |
| 3213 | if (nfc->data & RXH_L4_B_2_3) |
| 3214 | hash_sets |= HCLGE_D_PORT_BIT; |
| 3215 | else |
| 3216 | hash_sets &= ~HCLGE_D_PORT_BIT; |
| 3217 | |
| 3218 | if (nfc->data & RXH_IP_SRC) |
| 3219 | hash_sets |= HCLGE_S_IP_BIT; |
| 3220 | else |
| 3221 | hash_sets &= ~HCLGE_S_IP_BIT; |
| 3222 | |
| 3223 | if (nfc->data & RXH_IP_DST) |
| 3224 | hash_sets |= HCLGE_D_IP_BIT; |
| 3225 | else |
| 3226 | hash_sets &= ~HCLGE_D_IP_BIT; |
| 3227 | |
| 3228 | if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) |
| 3229 | hash_sets |= HCLGE_V_TAG_BIT; |
| 3230 | |
| 3231 | return hash_sets; |
| 3232 | } |
| 3233 | |
| 3234 | static int hclge_set_rss_tuple(struct hnae3_handle *handle, |
| 3235 | struct ethtool_rxnfc *nfc) |
| 3236 | { |
| 3237 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3238 | struct hclge_dev *hdev = vport->back; |
| 3239 | struct hclge_rss_input_tuple_cmd *req; |
| 3240 | struct hclge_desc desc; |
| 3241 | u8 tuple_sets; |
| 3242 | int ret; |
| 3243 | |
| 3244 | if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | |
| 3245 | RXH_L4_B_0_1 | RXH_L4_B_2_3)) |
| 3246 | return -EINVAL; |
| 3247 | |
| 3248 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; |
| 3249 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); |
| 3250 | |
| 3251 | req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; |
| 3252 | req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; |
| 3253 | req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; |
| 3254 | req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; |
| 3255 | req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; |
| 3256 | req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; |
| 3257 | req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; |
| 3258 | req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; |
| 3259 | |
| 3260 | tuple_sets = hclge_get_rss_hash_bits(nfc); |
| 3261 | switch (nfc->flow_type) { |
| 3262 | case TCP_V4_FLOW: |
| 3263 | req->ipv4_tcp_en = tuple_sets; |
| 3264 | break; |
| 3265 | case TCP_V6_FLOW: |
| 3266 | req->ipv6_tcp_en = tuple_sets; |
| 3267 | break; |
| 3268 | case UDP_V4_FLOW: |
| 3269 | req->ipv4_udp_en = tuple_sets; |
| 3270 | break; |
| 3271 | case UDP_V6_FLOW: |
| 3272 | req->ipv6_udp_en = tuple_sets; |
| 3273 | break; |
| 3274 | case SCTP_V4_FLOW: |
| 3275 | req->ipv4_sctp_en = tuple_sets; |
| 3276 | break; |
| 3277 | case SCTP_V6_FLOW: |
| 3278 | if ((nfc->data & RXH_L4_B_0_1) || |
| 3279 | (nfc->data & RXH_L4_B_2_3)) |
| 3280 | return -EINVAL; |
| 3281 | |
| 3282 | req->ipv6_sctp_en = tuple_sets; |
| 3283 | break; |
| 3284 | case IPV4_FLOW: |
| 3285 | req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3286 | break; |
| 3287 | case IPV6_FLOW: |
| 3288 | req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3289 | break; |
| 3290 | default: |
| 3291 | return -EINVAL; |
| 3292 | } |
| 3293 | |
| 3294 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3295 | if (ret) { |
| 3296 | dev_err(&hdev->pdev->dev, |
| 3297 | "Set rss tuple fail, status = %d\n", ret); |
| 3298 | return ret; |
| 3299 | } |
| 3300 | |
| 3301 | vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; |
| 3302 | vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; |
| 3303 | vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; |
| 3304 | vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; |
| 3305 | vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; |
| 3306 | vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; |
| 3307 | vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; |
| 3308 | vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; |
| 3309 | return 0; |
| 3310 | } |
| 3311 | |
| 3312 | static int hclge_get_rss_tuple(struct hnae3_handle *handle, |
| 3313 | struct ethtool_rxnfc *nfc) |
| 3314 | { |
| 3315 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3316 | u8 tuple_sets; |
| 3317 | |
| 3318 | nfc->data = 0; |
| 3319 | |
| 3320 | switch (nfc->flow_type) { |
| 3321 | case TCP_V4_FLOW: |
| 3322 | tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; |
| 3323 | break; |
| 3324 | case UDP_V4_FLOW: |
| 3325 | tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; |
| 3326 | break; |
| 3327 | case TCP_V6_FLOW: |
| 3328 | tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; |
| 3329 | break; |
| 3330 | case UDP_V6_FLOW: |
| 3331 | tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; |
| 3332 | break; |
| 3333 | case SCTP_V4_FLOW: |
| 3334 | tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; |
| 3335 | break; |
| 3336 | case SCTP_V6_FLOW: |
| 3337 | tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; |
| 3338 | break; |
| 3339 | case IPV4_FLOW: |
| 3340 | case IPV6_FLOW: |
| 3341 | tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; |
| 3342 | break; |
| 3343 | default: |
| 3344 | return -EINVAL; |
| 3345 | } |
| 3346 | |
| 3347 | if (!tuple_sets) |
| 3348 | return 0; |
| 3349 | |
| 3350 | if (tuple_sets & HCLGE_D_PORT_BIT) |
| 3351 | nfc->data |= RXH_L4_B_2_3; |
| 3352 | if (tuple_sets & HCLGE_S_PORT_BIT) |
| 3353 | nfc->data |= RXH_L4_B_0_1; |
| 3354 | if (tuple_sets & HCLGE_D_IP_BIT) |
| 3355 | nfc->data |= RXH_IP_DST; |
| 3356 | if (tuple_sets & HCLGE_S_IP_BIT) |
| 3357 | nfc->data |= RXH_IP_SRC; |
| 3358 | |
| 3359 | return 0; |
| 3360 | } |
| 3361 | |
| 3362 | static int hclge_get_tc_size(struct hnae3_handle *handle) |
| 3363 | { |
| 3364 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3365 | struct hclge_dev *hdev = vport->back; |
| 3366 | |
| 3367 | return hdev->rss_size_max; |
| 3368 | } |
| 3369 | |
| 3370 | int hclge_rss_init_hw(struct hclge_dev *hdev) |
| 3371 | { |
| 3372 | struct hclge_vport *vport = hdev->vport; |
| 3373 | u8 *rss_indir = vport[0].rss_indirection_tbl; |
| 3374 | u16 rss_size = vport[0].alloc_rss_size; |
| 3375 | u8 *key = vport[0].rss_hash_key; |
| 3376 | u8 hfunc = vport[0].rss_algo; |
| 3377 | u16 tc_offset[HCLGE_MAX_TC_NUM]; |
| 3378 | u16 tc_valid[HCLGE_MAX_TC_NUM]; |
| 3379 | u16 tc_size[HCLGE_MAX_TC_NUM]; |
| 3380 | u16 roundup_size; |
| 3381 | int i, ret; |
| 3382 | |
| 3383 | ret = hclge_set_rss_indir_table(hdev, rss_indir); |
| 3384 | if (ret) |
| 3385 | return ret; |
| 3386 | |
| 3387 | ret = hclge_set_rss_algo_key(hdev, hfunc, key); |
| 3388 | if (ret) |
| 3389 | return ret; |
| 3390 | |
| 3391 | ret = hclge_set_rss_input_tuple(hdev); |
| 3392 | if (ret) |
| 3393 | return ret; |
| 3394 | |
| 3395 | /* Each TC have the same queue size, and tc_size set to hardware is |
| 3396 | * the log2 of roundup power of two of rss_size, the acutal queue |
| 3397 | * size is limited by indirection table. |
| 3398 | */ |
| 3399 | if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { |
| 3400 | dev_err(&hdev->pdev->dev, |
| 3401 | "Configure rss tc size failed, invalid TC_SIZE = %d\n", |
| 3402 | rss_size); |
| 3403 | return -EINVAL; |
| 3404 | } |
| 3405 | |
| 3406 | roundup_size = roundup_pow_of_two(rss_size); |
| 3407 | roundup_size = ilog2(roundup_size); |
| 3408 | |
| 3409 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 3410 | tc_valid[i] = 0; |
| 3411 | |
| 3412 | if (!(hdev->hw_tc_map & BIT(i))) |
| 3413 | continue; |
| 3414 | |
| 3415 | tc_valid[i] = 1; |
| 3416 | tc_size[i] = roundup_size; |
| 3417 | tc_offset[i] = rss_size * i; |
| 3418 | } |
| 3419 | |
| 3420 | return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); |
| 3421 | } |
| 3422 | |
| 3423 | void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) |
| 3424 | { |
| 3425 | struct hclge_vport *vport = hdev->vport; |
| 3426 | int i, j; |
| 3427 | |
| 3428 | for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { |
| 3429 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) |
| 3430 | vport[j].rss_indirection_tbl[i] = |
| 3431 | i % vport[j].alloc_rss_size; |
| 3432 | } |
| 3433 | } |
| 3434 | |
| 3435 | static void hclge_rss_init_cfg(struct hclge_dev *hdev) |
| 3436 | { |
| 3437 | struct hclge_vport *vport = hdev->vport; |
| 3438 | int i; |
| 3439 | |
| 3440 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
| 3441 | vport[i].rss_tuple_sets.ipv4_tcp_en = |
| 3442 | HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3443 | vport[i].rss_tuple_sets.ipv4_udp_en = |
| 3444 | HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3445 | vport[i].rss_tuple_sets.ipv4_sctp_en = |
| 3446 | HCLGE_RSS_INPUT_TUPLE_SCTP; |
| 3447 | vport[i].rss_tuple_sets.ipv4_fragment_en = |
| 3448 | HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3449 | vport[i].rss_tuple_sets.ipv6_tcp_en = |
| 3450 | HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3451 | vport[i].rss_tuple_sets.ipv6_udp_en = |
| 3452 | HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3453 | vport[i].rss_tuple_sets.ipv6_sctp_en = |
| 3454 | HCLGE_RSS_INPUT_TUPLE_SCTP; |
| 3455 | vport[i].rss_tuple_sets.ipv6_fragment_en = |
| 3456 | HCLGE_RSS_INPUT_TUPLE_OTHER; |
| 3457 | |
| 3458 | vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; |
| 3459 | |
| 3460 | netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); |
| 3461 | } |
| 3462 | |
| 3463 | hclge_rss_indir_init_cfg(hdev); |
| 3464 | } |
| 3465 | |
| 3466 | int hclge_bind_ring_with_vector(struct hclge_vport *vport, |
| 3467 | int vector_id, bool en, |
| 3468 | struct hnae3_ring_chain_node *ring_chain) |
| 3469 | { |
| 3470 | struct hclge_dev *hdev = vport->back; |
| 3471 | struct hnae3_ring_chain_node *node; |
| 3472 | struct hclge_desc desc; |
| 3473 | struct hclge_ctrl_vector_chain_cmd *req |
| 3474 | = (struct hclge_ctrl_vector_chain_cmd *)desc.data; |
| 3475 | enum hclge_cmd_status status; |
| 3476 | enum hclge_opcode_type op; |
| 3477 | u16 tqp_type_and_id; |
| 3478 | int i; |
| 3479 | |
| 3480 | op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; |
| 3481 | hclge_cmd_setup_basic_desc(&desc, op, false); |
| 3482 | req->int_vector_id = vector_id; |
| 3483 | |
| 3484 | i = 0; |
| 3485 | for (node = ring_chain; node; node = node->next) { |
| 3486 | tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); |
| 3487 | hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, |
| 3488 | HCLGE_INT_TYPE_S, |
| 3489 | hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); |
| 3490 | hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, |
| 3491 | HCLGE_TQP_ID_S, node->tqp_index); |
| 3492 | hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, |
| 3493 | HCLGE_INT_GL_IDX_S, |
| 3494 | hnae3_get_field(node->int_gl_idx, |
| 3495 | HNAE3_RING_GL_IDX_M, |
| 3496 | HNAE3_RING_GL_IDX_S)); |
| 3497 | req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); |
| 3498 | if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { |
| 3499 | req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; |
| 3500 | req->vfid = vport->vport_id; |
| 3501 | |
| 3502 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3503 | if (status) { |
| 3504 | dev_err(&hdev->pdev->dev, |
| 3505 | "Map TQP fail, status is %d.\n", |
| 3506 | status); |
| 3507 | return -EIO; |
| 3508 | } |
| 3509 | i = 0; |
| 3510 | |
| 3511 | hclge_cmd_setup_basic_desc(&desc, |
| 3512 | op, |
| 3513 | false); |
| 3514 | req->int_vector_id = vector_id; |
| 3515 | } |
| 3516 | } |
| 3517 | |
| 3518 | if (i > 0) { |
| 3519 | req->int_cause_num = i; |
| 3520 | req->vfid = vport->vport_id; |
| 3521 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3522 | if (status) { |
| 3523 | dev_err(&hdev->pdev->dev, |
| 3524 | "Map TQP fail, status is %d.\n", status); |
| 3525 | return -EIO; |
| 3526 | } |
| 3527 | } |
| 3528 | |
| 3529 | return 0; |
| 3530 | } |
| 3531 | |
| 3532 | static int hclge_map_ring_to_vector(struct hnae3_handle *handle, |
| 3533 | int vector, |
| 3534 | struct hnae3_ring_chain_node *ring_chain) |
| 3535 | { |
| 3536 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3537 | struct hclge_dev *hdev = vport->back; |
| 3538 | int vector_id; |
| 3539 | |
| 3540 | vector_id = hclge_get_vector_index(hdev, vector); |
| 3541 | if (vector_id < 0) { |
| 3542 | dev_err(&hdev->pdev->dev, |
| 3543 | "Get vector index fail. vector_id =%d\n", vector_id); |
| 3544 | return vector_id; |
| 3545 | } |
| 3546 | |
| 3547 | return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); |
| 3548 | } |
| 3549 | |
| 3550 | static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, |
| 3551 | int vector, |
| 3552 | struct hnae3_ring_chain_node *ring_chain) |
| 3553 | { |
| 3554 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3555 | struct hclge_dev *hdev = vport->back; |
| 3556 | int vector_id, ret; |
| 3557 | |
| 3558 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
| 3559 | return 0; |
| 3560 | |
| 3561 | vector_id = hclge_get_vector_index(hdev, vector); |
| 3562 | if (vector_id < 0) { |
| 3563 | dev_err(&handle->pdev->dev, |
| 3564 | "Get vector index fail. ret =%d\n", vector_id); |
| 3565 | return vector_id; |
| 3566 | } |
| 3567 | |
| 3568 | ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); |
| 3569 | if (ret) |
| 3570 | dev_err(&handle->pdev->dev, |
| 3571 | "Unmap ring from vector fail. vectorid=%d, ret =%d\n", |
| 3572 | vector_id, |
| 3573 | ret); |
| 3574 | |
| 3575 | return ret; |
| 3576 | } |
| 3577 | |
| 3578 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, |
| 3579 | struct hclge_promisc_param *param) |
| 3580 | { |
| 3581 | struct hclge_promisc_cfg_cmd *req; |
| 3582 | struct hclge_desc desc; |
| 3583 | int ret; |
| 3584 | |
| 3585 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); |
| 3586 | |
| 3587 | req = (struct hclge_promisc_cfg_cmd *)desc.data; |
| 3588 | req->vf_id = param->vf_id; |
| 3589 | |
| 3590 | /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on |
| 3591 | * pdev revision(0x20), new revision support them. The |
| 3592 | * value of this two fields will not return error when driver |
| 3593 | * send command to fireware in revision(0x20). |
| 3594 | */ |
| 3595 | req->flag = (param->enable << HCLGE_PROMISC_EN_B) | |
| 3596 | HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B; |
| 3597 | |
| 3598 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3599 | if (ret) { |
| 3600 | dev_err(&hdev->pdev->dev, |
| 3601 | "Set promisc mode fail, status is %d.\n", ret); |
| 3602 | return ret; |
| 3603 | } |
| 3604 | return 0; |
| 3605 | } |
| 3606 | |
| 3607 | void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, |
| 3608 | bool en_mc, bool en_bc, int vport_id) |
| 3609 | { |
| 3610 | if (!param) |
| 3611 | return; |
| 3612 | |
| 3613 | memset(param, 0, sizeof(struct hclge_promisc_param)); |
| 3614 | if (en_uc) |
| 3615 | param->enable = HCLGE_PROMISC_EN_UC; |
| 3616 | if (en_mc) |
| 3617 | param->enable |= HCLGE_PROMISC_EN_MC; |
| 3618 | if (en_bc) |
| 3619 | param->enable |= HCLGE_PROMISC_EN_BC; |
| 3620 | param->vf_id = vport_id; |
| 3621 | } |
| 3622 | |
| 3623 | static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, |
| 3624 | bool en_mc_pmc) |
| 3625 | { |
| 3626 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3627 | struct hclge_dev *hdev = vport->back; |
| 3628 | struct hclge_promisc_param param; |
| 3629 | |
| 3630 | hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true, |
| 3631 | vport->vport_id); |
| 3632 | hclge_cmd_set_promisc_mode(hdev, ¶m); |
| 3633 | } |
| 3634 | |
| 3635 | static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) |
| 3636 | { |
| 3637 | struct hclge_desc desc; |
| 3638 | struct hclge_config_mac_mode_cmd *req = |
| 3639 | (struct hclge_config_mac_mode_cmd *)desc.data; |
| 3640 | u32 loop_en = 0; |
| 3641 | int ret; |
| 3642 | |
| 3643 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); |
| 3644 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); |
| 3645 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); |
| 3646 | hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); |
| 3647 | hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); |
| 3648 | hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); |
| 3649 | hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); |
| 3650 | hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); |
| 3651 | hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); |
| 3652 | hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); |
| 3653 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); |
| 3654 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); |
| 3655 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); |
| 3656 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); |
| 3657 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); |
| 3658 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); |
| 3659 | |
| 3660 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3661 | if (ret) |
| 3662 | dev_err(&hdev->pdev->dev, |
| 3663 | "mac enable fail, ret =%d.\n", ret); |
| 3664 | } |
| 3665 | |
| 3666 | static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en) |
| 3667 | { |
| 3668 | struct hclge_config_mac_mode_cmd *req; |
| 3669 | struct hclge_desc desc; |
| 3670 | u32 loop_en; |
| 3671 | int ret; |
| 3672 | |
| 3673 | req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; |
| 3674 | /* 1 Read out the MAC mode config at first */ |
| 3675 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); |
| 3676 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3677 | if (ret) { |
| 3678 | dev_err(&hdev->pdev->dev, |
| 3679 | "mac loopback get fail, ret =%d.\n", ret); |
| 3680 | return ret; |
| 3681 | } |
| 3682 | |
| 3683 | /* 2 Then setup the loopback flag */ |
| 3684 | loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); |
| 3685 | hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); |
| 3686 | |
| 3687 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); |
| 3688 | |
| 3689 | /* 3 Config mac work mode with loopback flag |
| 3690 | * and its original configure parameters |
| 3691 | */ |
| 3692 | hclge_cmd_reuse_desc(&desc, false); |
| 3693 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3694 | if (ret) |
| 3695 | dev_err(&hdev->pdev->dev, |
| 3696 | "mac loopback set fail, ret =%d.\n", ret); |
| 3697 | return ret; |
| 3698 | } |
| 3699 | |
| 3700 | static int hclge_set_loopback(struct hnae3_handle *handle, |
| 3701 | enum hnae3_loop loop_mode, bool en) |
| 3702 | { |
| 3703 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3704 | struct hclge_dev *hdev = vport->back; |
| 3705 | int ret; |
| 3706 | |
| 3707 | switch (loop_mode) { |
| 3708 | case HNAE3_MAC_INTER_LOOP_MAC: |
| 3709 | ret = hclge_set_mac_loopback(hdev, en); |
| 3710 | break; |
| 3711 | default: |
| 3712 | ret = -ENOTSUPP; |
| 3713 | dev_err(&hdev->pdev->dev, |
| 3714 | "loop_mode %d is not supported\n", loop_mode); |
| 3715 | break; |
| 3716 | } |
| 3717 | |
| 3718 | return ret; |
| 3719 | } |
| 3720 | |
| 3721 | static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, |
| 3722 | int stream_id, bool enable) |
| 3723 | { |
| 3724 | struct hclge_desc desc; |
| 3725 | struct hclge_cfg_com_tqp_queue_cmd *req = |
| 3726 | (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; |
| 3727 | int ret; |
| 3728 | |
| 3729 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); |
| 3730 | req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); |
| 3731 | req->stream_id = cpu_to_le16(stream_id); |
| 3732 | req->enable |= enable << HCLGE_TQP_ENABLE_B; |
| 3733 | |
| 3734 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3735 | if (ret) |
| 3736 | dev_err(&hdev->pdev->dev, |
| 3737 | "Tqp enable fail, status =%d.\n", ret); |
| 3738 | return ret; |
| 3739 | } |
| 3740 | |
| 3741 | static void hclge_reset_tqp_stats(struct hnae3_handle *handle) |
| 3742 | { |
| 3743 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3744 | struct hnae3_queue *queue; |
| 3745 | struct hclge_tqp *tqp; |
| 3746 | int i; |
| 3747 | |
| 3748 | for (i = 0; i < vport->alloc_tqps; i++) { |
| 3749 | queue = handle->kinfo.tqp[i]; |
| 3750 | tqp = container_of(queue, struct hclge_tqp, q); |
| 3751 | memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); |
| 3752 | } |
| 3753 | } |
| 3754 | |
| 3755 | static int hclge_ae_start(struct hnae3_handle *handle) |
| 3756 | { |
| 3757 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3758 | struct hclge_dev *hdev = vport->back; |
| 3759 | int i, ret; |
| 3760 | |
| 3761 | for (i = 0; i < vport->alloc_tqps; i++) |
| 3762 | hclge_tqp_enable(hdev, i, 0, true); |
| 3763 | |
| 3764 | /* mac enable */ |
| 3765 | hclge_cfg_mac_mode(hdev, true); |
| 3766 | clear_bit(HCLGE_STATE_DOWN, &hdev->state); |
| 3767 | mod_timer(&hdev->service_timer, jiffies + HZ); |
| 3768 | hdev->hw.mac.link = 0; |
| 3769 | |
| 3770 | /* reset tqp stats */ |
| 3771 | hclge_reset_tqp_stats(handle); |
| 3772 | |
| 3773 | ret = hclge_mac_start_phy(hdev); |
| 3774 | if (ret) |
| 3775 | return ret; |
| 3776 | |
| 3777 | return 0; |
| 3778 | } |
| 3779 | |
| 3780 | static void hclge_ae_stop(struct hnae3_handle *handle) |
| 3781 | { |
| 3782 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 3783 | struct hclge_dev *hdev = vport->back; |
| 3784 | int i; |
| 3785 | |
| 3786 | del_timer_sync(&hdev->service_timer); |
| 3787 | cancel_work_sync(&hdev->service_task); |
| 3788 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); |
| 3789 | |
| 3790 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { |
| 3791 | hclge_mac_stop_phy(hdev); |
| 3792 | return; |
| 3793 | } |
| 3794 | |
| 3795 | for (i = 0; i < vport->alloc_tqps; i++) |
| 3796 | hclge_tqp_enable(hdev, i, 0, false); |
| 3797 | |
| 3798 | /* Mac disable */ |
| 3799 | hclge_cfg_mac_mode(hdev, false); |
| 3800 | |
| 3801 | hclge_mac_stop_phy(hdev); |
| 3802 | |
| 3803 | /* reset tqp stats */ |
| 3804 | hclge_reset_tqp_stats(handle); |
| 3805 | del_timer_sync(&hdev->service_timer); |
| 3806 | cancel_work_sync(&hdev->service_task); |
| 3807 | hclge_update_link_status(hdev); |
| 3808 | } |
| 3809 | |
| 3810 | static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, |
| 3811 | u16 cmdq_resp, u8 resp_code, |
| 3812 | enum hclge_mac_vlan_tbl_opcode op) |
| 3813 | { |
| 3814 | struct hclge_dev *hdev = vport->back; |
| 3815 | int return_status = -EIO; |
| 3816 | |
| 3817 | if (cmdq_resp) { |
| 3818 | dev_err(&hdev->pdev->dev, |
| 3819 | "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", |
| 3820 | cmdq_resp); |
| 3821 | return -EIO; |
| 3822 | } |
| 3823 | |
| 3824 | if (op == HCLGE_MAC_VLAN_ADD) { |
| 3825 | if ((!resp_code) || (resp_code == 1)) { |
| 3826 | return_status = 0; |
| 3827 | } else if (resp_code == 2) { |
| 3828 | return_status = -ENOSPC; |
| 3829 | dev_err(&hdev->pdev->dev, |
| 3830 | "add mac addr failed for uc_overflow.\n"); |
| 3831 | } else if (resp_code == 3) { |
| 3832 | return_status = -ENOSPC; |
| 3833 | dev_err(&hdev->pdev->dev, |
| 3834 | "add mac addr failed for mc_overflow.\n"); |
| 3835 | } else { |
| 3836 | dev_err(&hdev->pdev->dev, |
| 3837 | "add mac addr failed for undefined, code=%d.\n", |
| 3838 | resp_code); |
| 3839 | } |
| 3840 | } else if (op == HCLGE_MAC_VLAN_REMOVE) { |
| 3841 | if (!resp_code) { |
| 3842 | return_status = 0; |
| 3843 | } else if (resp_code == 1) { |
| 3844 | return_status = -ENOENT; |
| 3845 | dev_dbg(&hdev->pdev->dev, |
| 3846 | "remove mac addr failed for miss.\n"); |
| 3847 | } else { |
| 3848 | dev_err(&hdev->pdev->dev, |
| 3849 | "remove mac addr failed for undefined, code=%d.\n", |
| 3850 | resp_code); |
| 3851 | } |
| 3852 | } else if (op == HCLGE_MAC_VLAN_LKUP) { |
| 3853 | if (!resp_code) { |
| 3854 | return_status = 0; |
| 3855 | } else if (resp_code == 1) { |
| 3856 | return_status = -ENOENT; |
| 3857 | dev_dbg(&hdev->pdev->dev, |
| 3858 | "lookup mac addr failed for miss.\n"); |
| 3859 | } else { |
| 3860 | dev_err(&hdev->pdev->dev, |
| 3861 | "lookup mac addr failed for undefined, code=%d.\n", |
| 3862 | resp_code); |
| 3863 | } |
| 3864 | } else { |
| 3865 | return_status = -EINVAL; |
| 3866 | dev_err(&hdev->pdev->dev, |
| 3867 | "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", |
| 3868 | op); |
| 3869 | } |
| 3870 | |
| 3871 | return return_status; |
| 3872 | } |
| 3873 | |
| 3874 | static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) |
| 3875 | { |
| 3876 | int word_num; |
| 3877 | int bit_num; |
| 3878 | |
| 3879 | if (vfid > 255 || vfid < 0) |
| 3880 | return -EIO; |
| 3881 | |
| 3882 | if (vfid >= 0 && vfid <= 191) { |
| 3883 | word_num = vfid / 32; |
| 3884 | bit_num = vfid % 32; |
| 3885 | if (clr) |
| 3886 | desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
| 3887 | else |
| 3888 | desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); |
| 3889 | } else { |
| 3890 | word_num = (vfid - 192) / 32; |
| 3891 | bit_num = vfid % 32; |
| 3892 | if (clr) |
| 3893 | desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
| 3894 | else |
| 3895 | desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); |
| 3896 | } |
| 3897 | |
| 3898 | return 0; |
| 3899 | } |
| 3900 | |
| 3901 | static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) |
| 3902 | { |
| 3903 | #define HCLGE_DESC_NUMBER 3 |
| 3904 | #define HCLGE_FUNC_NUMBER_PER_DESC 6 |
| 3905 | int i, j; |
| 3906 | |
| 3907 | for (i = 0; i < HCLGE_DESC_NUMBER; i++) |
| 3908 | for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) |
| 3909 | if (desc[i].data[j]) |
| 3910 | return false; |
| 3911 | |
| 3912 | return true; |
| 3913 | } |
| 3914 | |
| 3915 | static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, |
| 3916 | const u8 *addr) |
| 3917 | { |
| 3918 | const unsigned char *mac_addr = addr; |
| 3919 | u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | |
| 3920 | (mac_addr[0]) | (mac_addr[1] << 8); |
| 3921 | u32 low_val = mac_addr[4] | (mac_addr[5] << 8); |
| 3922 | |
| 3923 | new_req->mac_addr_hi32 = cpu_to_le32(high_val); |
| 3924 | new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); |
| 3925 | } |
| 3926 | |
| 3927 | static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, |
| 3928 | const u8 *addr) |
| 3929 | { |
| 3930 | u16 high_val = addr[1] | (addr[0] << 8); |
| 3931 | struct hclge_dev *hdev = vport->back; |
| 3932 | u32 rsh = 4 - hdev->mta_mac_sel_type; |
| 3933 | u16 ret_val = (high_val >> rsh) & 0xfff; |
| 3934 | |
| 3935 | return ret_val; |
| 3936 | } |
| 3937 | |
| 3938 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, |
| 3939 | enum hclge_mta_dmac_sel_type mta_mac_sel, |
| 3940 | bool enable) |
| 3941 | { |
| 3942 | struct hclge_mta_filter_mode_cmd *req; |
| 3943 | struct hclge_desc desc; |
| 3944 | int ret; |
| 3945 | |
| 3946 | req = (struct hclge_mta_filter_mode_cmd *)desc.data; |
| 3947 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); |
| 3948 | |
| 3949 | hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, |
| 3950 | enable); |
| 3951 | hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, |
| 3952 | HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); |
| 3953 | |
| 3954 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3955 | if (ret) { |
| 3956 | dev_err(&hdev->pdev->dev, |
| 3957 | "Config mat filter mode failed for cmd_send, ret =%d.\n", |
| 3958 | ret); |
| 3959 | return ret; |
| 3960 | } |
| 3961 | |
| 3962 | return 0; |
| 3963 | } |
| 3964 | |
| 3965 | int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, |
| 3966 | u8 func_id, |
| 3967 | bool enable) |
| 3968 | { |
| 3969 | struct hclge_cfg_func_mta_filter_cmd *req; |
| 3970 | struct hclge_desc desc; |
| 3971 | int ret; |
| 3972 | |
| 3973 | req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; |
| 3974 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); |
| 3975 | |
| 3976 | hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, |
| 3977 | enable); |
| 3978 | req->function_id = func_id; |
| 3979 | |
| 3980 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 3981 | if (ret) { |
| 3982 | dev_err(&hdev->pdev->dev, |
| 3983 | "Config func_id enable failed for cmd_send, ret =%d.\n", |
| 3984 | ret); |
| 3985 | return ret; |
| 3986 | } |
| 3987 | |
| 3988 | return 0; |
| 3989 | } |
| 3990 | |
| 3991 | static int hclge_set_mta_table_item(struct hclge_vport *vport, |
| 3992 | u16 idx, |
| 3993 | bool enable) |
| 3994 | { |
| 3995 | struct hclge_dev *hdev = vport->back; |
| 3996 | struct hclge_cfg_func_mta_item_cmd *req; |
| 3997 | struct hclge_desc desc; |
| 3998 | u16 item_idx = 0; |
| 3999 | int ret; |
| 4000 | |
| 4001 | req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; |
| 4002 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); |
| 4003 | hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); |
| 4004 | |
| 4005 | hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, |
| 4006 | HCLGE_CFG_MTA_ITEM_IDX_S, idx); |
| 4007 | req->item_idx = cpu_to_le16(item_idx); |
| 4008 | |
| 4009 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4010 | if (ret) { |
| 4011 | dev_err(&hdev->pdev->dev, |
| 4012 | "Config mta table item failed for cmd_send, ret =%d.\n", |
| 4013 | ret); |
| 4014 | return ret; |
| 4015 | } |
| 4016 | |
| 4017 | if (enable) |
| 4018 | set_bit(idx, vport->mta_shadow); |
| 4019 | else |
| 4020 | clear_bit(idx, vport->mta_shadow); |
| 4021 | |
| 4022 | return 0; |
| 4023 | } |
| 4024 | |
| 4025 | static int hclge_update_mta_status(struct hnae3_handle *handle) |
| 4026 | { |
| 4027 | unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)]; |
| 4028 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4029 | struct net_device *netdev = handle->kinfo.netdev; |
| 4030 | struct netdev_hw_addr *ha; |
| 4031 | u16 tbl_idx; |
| 4032 | |
| 4033 | memset(mta_status, 0, sizeof(mta_status)); |
| 4034 | |
| 4035 | /* update mta_status from mc addr list */ |
| 4036 | netdev_for_each_mc_addr(ha, netdev) { |
| 4037 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr); |
| 4038 | set_bit(tbl_idx, mta_status); |
| 4039 | } |
| 4040 | |
| 4041 | return hclge_update_mta_status_common(vport, mta_status, |
| 4042 | 0, HCLGE_MTA_TBL_SIZE, true); |
| 4043 | } |
| 4044 | |
| 4045 | int hclge_update_mta_status_common(struct hclge_vport *vport, |
| 4046 | unsigned long *status, |
| 4047 | u16 idx, |
| 4048 | u16 count, |
| 4049 | bool update_filter) |
| 4050 | { |
| 4051 | struct hclge_dev *hdev = vport->back; |
| 4052 | u16 update_max = idx + count; |
| 4053 | u16 check_max; |
| 4054 | int ret = 0; |
| 4055 | bool used; |
| 4056 | u16 i; |
| 4057 | |
| 4058 | /* setup mta check range */ |
| 4059 | if (update_filter) { |
| 4060 | i = 0; |
| 4061 | check_max = HCLGE_MTA_TBL_SIZE; |
| 4062 | } else { |
| 4063 | i = idx; |
| 4064 | check_max = update_max; |
| 4065 | } |
| 4066 | |
| 4067 | used = false; |
| 4068 | /* check and update all mta item */ |
| 4069 | for (; i < check_max; i++) { |
| 4070 | /* ignore unused item */ |
| 4071 | if (!test_bit(i, vport->mta_shadow)) |
| 4072 | continue; |
| 4073 | |
| 4074 | /* if i in update range then update it */ |
| 4075 | if (i >= idx && i < update_max) |
| 4076 | if (!test_bit(i - idx, status)) |
| 4077 | hclge_set_mta_table_item(vport, i, false); |
| 4078 | |
| 4079 | if (!used && test_bit(i, vport->mta_shadow)) |
| 4080 | used = true; |
| 4081 | } |
| 4082 | |
| 4083 | /* no longer use mta, disable it */ |
| 4084 | if (vport->accept_mta_mc && update_filter && !used) { |
| 4085 | ret = hclge_cfg_func_mta_filter(hdev, |
| 4086 | vport->vport_id, |
| 4087 | false); |
| 4088 | if (ret) |
| 4089 | dev_err(&hdev->pdev->dev, |
| 4090 | "disable func mta filter fail ret=%d\n", |
| 4091 | ret); |
| 4092 | else |
| 4093 | vport->accept_mta_mc = false; |
| 4094 | } |
| 4095 | |
| 4096 | return ret; |
| 4097 | } |
| 4098 | |
| 4099 | static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, |
| 4100 | struct hclge_mac_vlan_tbl_entry_cmd *req) |
| 4101 | { |
| 4102 | struct hclge_dev *hdev = vport->back; |
| 4103 | struct hclge_desc desc; |
| 4104 | u8 resp_code; |
| 4105 | u16 retval; |
| 4106 | int ret; |
| 4107 | |
| 4108 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); |
| 4109 | |
| 4110 | memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
| 4111 | |
| 4112 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4113 | if (ret) { |
| 4114 | dev_err(&hdev->pdev->dev, |
| 4115 | "del mac addr failed for cmd_send, ret =%d.\n", |
| 4116 | ret); |
| 4117 | return ret; |
| 4118 | } |
| 4119 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
| 4120 | retval = le16_to_cpu(desc.retval); |
| 4121 | |
| 4122 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
| 4123 | HCLGE_MAC_VLAN_REMOVE); |
| 4124 | } |
| 4125 | |
| 4126 | static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, |
| 4127 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
| 4128 | struct hclge_desc *desc, |
| 4129 | bool is_mc) |
| 4130 | { |
| 4131 | struct hclge_dev *hdev = vport->back; |
| 4132 | u8 resp_code; |
| 4133 | u16 retval; |
| 4134 | int ret; |
| 4135 | |
| 4136 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); |
| 4137 | if (is_mc) { |
| 4138 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 4139 | memcpy(desc[0].data, |
| 4140 | req, |
| 4141 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
| 4142 | hclge_cmd_setup_basic_desc(&desc[1], |
| 4143 | HCLGE_OPC_MAC_VLAN_ADD, |
| 4144 | true); |
| 4145 | desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 4146 | hclge_cmd_setup_basic_desc(&desc[2], |
| 4147 | HCLGE_OPC_MAC_VLAN_ADD, |
| 4148 | true); |
| 4149 | ret = hclge_cmd_send(&hdev->hw, desc, 3); |
| 4150 | } else { |
| 4151 | memcpy(desc[0].data, |
| 4152 | req, |
| 4153 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
| 4154 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
| 4155 | } |
| 4156 | if (ret) { |
| 4157 | dev_err(&hdev->pdev->dev, |
| 4158 | "lookup mac addr failed for cmd_send, ret =%d.\n", |
| 4159 | ret); |
| 4160 | return ret; |
| 4161 | } |
| 4162 | resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; |
| 4163 | retval = le16_to_cpu(desc[0].retval); |
| 4164 | |
| 4165 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
| 4166 | HCLGE_MAC_VLAN_LKUP); |
| 4167 | } |
| 4168 | |
| 4169 | static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, |
| 4170 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
| 4171 | struct hclge_desc *mc_desc) |
| 4172 | { |
| 4173 | struct hclge_dev *hdev = vport->back; |
| 4174 | int cfg_status; |
| 4175 | u8 resp_code; |
| 4176 | u16 retval; |
| 4177 | int ret; |
| 4178 | |
| 4179 | if (!mc_desc) { |
| 4180 | struct hclge_desc desc; |
| 4181 | |
| 4182 | hclge_cmd_setup_basic_desc(&desc, |
| 4183 | HCLGE_OPC_MAC_VLAN_ADD, |
| 4184 | false); |
| 4185 | memcpy(desc.data, req, |
| 4186 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
| 4187 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4188 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
| 4189 | retval = le16_to_cpu(desc.retval); |
| 4190 | |
| 4191 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, |
| 4192 | resp_code, |
| 4193 | HCLGE_MAC_VLAN_ADD); |
| 4194 | } else { |
| 4195 | hclge_cmd_reuse_desc(&mc_desc[0], false); |
| 4196 | mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 4197 | hclge_cmd_reuse_desc(&mc_desc[1], false); |
| 4198 | mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 4199 | hclge_cmd_reuse_desc(&mc_desc[2], false); |
| 4200 | mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); |
| 4201 | memcpy(mc_desc[0].data, req, |
| 4202 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
| 4203 | ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); |
| 4204 | resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; |
| 4205 | retval = le16_to_cpu(mc_desc[0].retval); |
| 4206 | |
| 4207 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, |
| 4208 | resp_code, |
| 4209 | HCLGE_MAC_VLAN_ADD); |
| 4210 | } |
| 4211 | |
| 4212 | if (ret) { |
| 4213 | dev_err(&hdev->pdev->dev, |
| 4214 | "add mac addr failed for cmd_send, ret =%d.\n", |
| 4215 | ret); |
| 4216 | return ret; |
| 4217 | } |
| 4218 | |
| 4219 | return cfg_status; |
| 4220 | } |
| 4221 | |
| 4222 | static int hclge_add_uc_addr(struct hnae3_handle *handle, |
| 4223 | const unsigned char *addr) |
| 4224 | { |
| 4225 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4226 | |
| 4227 | return hclge_add_uc_addr_common(vport, addr); |
| 4228 | } |
| 4229 | |
| 4230 | int hclge_add_uc_addr_common(struct hclge_vport *vport, |
| 4231 | const unsigned char *addr) |
| 4232 | { |
| 4233 | struct hclge_dev *hdev = vport->back; |
| 4234 | struct hclge_mac_vlan_tbl_entry_cmd req; |
| 4235 | struct hclge_desc desc; |
| 4236 | u16 egress_port = 0; |
| 4237 | int ret; |
| 4238 | |
| 4239 | /* mac addr check */ |
| 4240 | if (is_zero_ether_addr(addr) || |
| 4241 | is_broadcast_ether_addr(addr) || |
| 4242 | is_multicast_ether_addr(addr)) { |
| 4243 | dev_err(&hdev->pdev->dev, |
| 4244 | "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", |
| 4245 | addr, |
| 4246 | is_zero_ether_addr(addr), |
| 4247 | is_broadcast_ether_addr(addr), |
| 4248 | is_multicast_ether_addr(addr)); |
| 4249 | return -EINVAL; |
| 4250 | } |
| 4251 | |
| 4252 | memset(&req, 0, sizeof(req)); |
| 4253 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
| 4254 | |
| 4255 | hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, |
| 4256 | HCLGE_MAC_EPORT_VFID_S, vport->vport_id); |
| 4257 | |
| 4258 | req.egress_port = cpu_to_le16(egress_port); |
| 4259 | |
| 4260 | hclge_prepare_mac_addr(&req, addr); |
| 4261 | |
| 4262 | /* Lookup the mac address in the mac_vlan table, and add |
| 4263 | * it if the entry is inexistent. Repeated unicast entry |
| 4264 | * is not allowed in the mac vlan table. |
| 4265 | */ |
| 4266 | ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); |
| 4267 | if (ret == -ENOENT) |
| 4268 | return hclge_add_mac_vlan_tbl(vport, &req, NULL); |
| 4269 | |
| 4270 | /* check if we just hit the duplicate */ |
| 4271 | if (!ret) |
| 4272 | ret = -EINVAL; |
| 4273 | |
| 4274 | dev_err(&hdev->pdev->dev, |
| 4275 | "PF failed to add unicast entry(%pM) in the MAC table\n", |
| 4276 | addr); |
| 4277 | |
| 4278 | return ret; |
| 4279 | } |
| 4280 | |
| 4281 | static int hclge_rm_uc_addr(struct hnae3_handle *handle, |
| 4282 | const unsigned char *addr) |
| 4283 | { |
| 4284 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4285 | |
| 4286 | return hclge_rm_uc_addr_common(vport, addr); |
| 4287 | } |
| 4288 | |
| 4289 | int hclge_rm_uc_addr_common(struct hclge_vport *vport, |
| 4290 | const unsigned char *addr) |
| 4291 | { |
| 4292 | struct hclge_dev *hdev = vport->back; |
| 4293 | struct hclge_mac_vlan_tbl_entry_cmd req; |
| 4294 | int ret; |
| 4295 | |
| 4296 | /* mac addr check */ |
| 4297 | if (is_zero_ether_addr(addr) || |
| 4298 | is_broadcast_ether_addr(addr) || |
| 4299 | is_multicast_ether_addr(addr)) { |
| 4300 | dev_dbg(&hdev->pdev->dev, |
| 4301 | "Remove mac err! invalid mac:%pM.\n", |
| 4302 | addr); |
| 4303 | return -EINVAL; |
| 4304 | } |
| 4305 | |
| 4306 | memset(&req, 0, sizeof(req)); |
| 4307 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
| 4308 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); |
| 4309 | hclge_prepare_mac_addr(&req, addr); |
| 4310 | ret = hclge_remove_mac_vlan_tbl(vport, &req); |
| 4311 | |
| 4312 | return ret; |
| 4313 | } |
| 4314 | |
| 4315 | static int hclge_add_mc_addr(struct hnae3_handle *handle, |
| 4316 | const unsigned char *addr) |
| 4317 | { |
| 4318 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4319 | |
| 4320 | return hclge_add_mc_addr_common(vport, addr); |
| 4321 | } |
| 4322 | |
| 4323 | int hclge_add_mc_addr_common(struct hclge_vport *vport, |
| 4324 | const unsigned char *addr) |
| 4325 | { |
| 4326 | struct hclge_dev *hdev = vport->back; |
| 4327 | struct hclge_mac_vlan_tbl_entry_cmd req; |
| 4328 | struct hclge_desc desc[3]; |
| 4329 | u16 tbl_idx; |
| 4330 | int status; |
| 4331 | |
| 4332 | /* mac addr check */ |
| 4333 | if (!is_multicast_ether_addr(addr)) { |
| 4334 | dev_err(&hdev->pdev->dev, |
| 4335 | "Add mc mac err! invalid mac:%pM.\n", |
| 4336 | addr); |
| 4337 | return -EINVAL; |
| 4338 | } |
| 4339 | memset(&req, 0, sizeof(req)); |
| 4340 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
| 4341 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); |
| 4342 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); |
| 4343 | hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); |
| 4344 | hclge_prepare_mac_addr(&req, addr); |
| 4345 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); |
| 4346 | if (!status) { |
| 4347 | /* This mac addr exist, update VFID for it */ |
| 4348 | hclge_update_desc_vfid(desc, vport->vport_id, false); |
| 4349 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); |
| 4350 | } else { |
| 4351 | /* This mac addr do not exist, add new entry for it */ |
| 4352 | memset(desc[0].data, 0, sizeof(desc[0].data)); |
| 4353 | memset(desc[1].data, 0, sizeof(desc[0].data)); |
| 4354 | memset(desc[2].data, 0, sizeof(desc[0].data)); |
| 4355 | hclge_update_desc_vfid(desc, vport->vport_id, false); |
| 4356 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); |
| 4357 | } |
| 4358 | |
| 4359 | /* If mc mac vlan table is full, use MTA table */ |
| 4360 | if (status == -ENOSPC) { |
| 4361 | if (!vport->accept_mta_mc) { |
| 4362 | status = hclge_cfg_func_mta_filter(hdev, |
| 4363 | vport->vport_id, |
| 4364 | true); |
| 4365 | if (status) { |
| 4366 | dev_err(&hdev->pdev->dev, |
| 4367 | "set mta filter mode fail ret=%d\n", |
| 4368 | status); |
| 4369 | return status; |
| 4370 | } |
| 4371 | vport->accept_mta_mc = true; |
| 4372 | } |
| 4373 | |
| 4374 | /* Set MTA table for this MAC address */ |
| 4375 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); |
| 4376 | status = hclge_set_mta_table_item(vport, tbl_idx, true); |
| 4377 | } |
| 4378 | |
| 4379 | return status; |
| 4380 | } |
| 4381 | |
| 4382 | static int hclge_rm_mc_addr(struct hnae3_handle *handle, |
| 4383 | const unsigned char *addr) |
| 4384 | { |
| 4385 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4386 | |
| 4387 | return hclge_rm_mc_addr_common(vport, addr); |
| 4388 | } |
| 4389 | |
| 4390 | int hclge_rm_mc_addr_common(struct hclge_vport *vport, |
| 4391 | const unsigned char *addr) |
| 4392 | { |
| 4393 | struct hclge_dev *hdev = vport->back; |
| 4394 | struct hclge_mac_vlan_tbl_entry_cmd req; |
| 4395 | enum hclge_cmd_status status; |
| 4396 | struct hclge_desc desc[3]; |
| 4397 | |
| 4398 | /* mac addr check */ |
| 4399 | if (!is_multicast_ether_addr(addr)) { |
| 4400 | dev_dbg(&hdev->pdev->dev, |
| 4401 | "Remove mc mac err! invalid mac:%pM.\n", |
| 4402 | addr); |
| 4403 | return -EINVAL; |
| 4404 | } |
| 4405 | |
| 4406 | memset(&req, 0, sizeof(req)); |
| 4407 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
| 4408 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); |
| 4409 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); |
| 4410 | hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); |
| 4411 | hclge_prepare_mac_addr(&req, addr); |
| 4412 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); |
| 4413 | if (!status) { |
| 4414 | /* This mac addr exist, remove this handle's VFID for it */ |
| 4415 | hclge_update_desc_vfid(desc, vport->vport_id, true); |
| 4416 | |
| 4417 | if (hclge_is_all_function_id_zero(desc)) |
| 4418 | /* All the vfid is zero, so need to delete this entry */ |
| 4419 | status = hclge_remove_mac_vlan_tbl(vport, &req); |
| 4420 | else |
| 4421 | /* Not all the vfid is zero, update the vfid */ |
| 4422 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); |
| 4423 | |
| 4424 | } else { |
| 4425 | /* Maybe this mac address is in mta table, but it cannot be |
| 4426 | * deleted here because an entry of mta represents an address |
| 4427 | * range rather than a specific address. the delete action to |
| 4428 | * all entries will take effect in update_mta_status called by |
| 4429 | * hns3_nic_set_rx_mode. |
| 4430 | */ |
| 4431 | status = 0; |
| 4432 | } |
| 4433 | |
| 4434 | return status; |
| 4435 | } |
| 4436 | |
| 4437 | static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, |
| 4438 | u16 cmdq_resp, u8 resp_code) |
| 4439 | { |
| 4440 | #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 |
| 4441 | #define HCLGE_ETHERTYPE_ALREADY_ADD 1 |
| 4442 | #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 |
| 4443 | #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 |
| 4444 | |
| 4445 | int return_status; |
| 4446 | |
| 4447 | if (cmdq_resp) { |
| 4448 | dev_err(&hdev->pdev->dev, |
| 4449 | "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", |
| 4450 | cmdq_resp); |
| 4451 | return -EIO; |
| 4452 | } |
| 4453 | |
| 4454 | switch (resp_code) { |
| 4455 | case HCLGE_ETHERTYPE_SUCCESS_ADD: |
| 4456 | case HCLGE_ETHERTYPE_ALREADY_ADD: |
| 4457 | return_status = 0; |
| 4458 | break; |
| 4459 | case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: |
| 4460 | dev_err(&hdev->pdev->dev, |
| 4461 | "add mac ethertype failed for manager table overflow.\n"); |
| 4462 | return_status = -EIO; |
| 4463 | break; |
| 4464 | case HCLGE_ETHERTYPE_KEY_CONFLICT: |
| 4465 | dev_err(&hdev->pdev->dev, |
| 4466 | "add mac ethertype failed for key conflict.\n"); |
| 4467 | return_status = -EIO; |
| 4468 | break; |
| 4469 | default: |
| 4470 | dev_err(&hdev->pdev->dev, |
| 4471 | "add mac ethertype failed for undefined, code=%d.\n", |
| 4472 | resp_code); |
| 4473 | return_status = -EIO; |
| 4474 | } |
| 4475 | |
| 4476 | return return_status; |
| 4477 | } |
| 4478 | |
| 4479 | static int hclge_add_mgr_tbl(struct hclge_dev *hdev, |
| 4480 | const struct hclge_mac_mgr_tbl_entry_cmd *req) |
| 4481 | { |
| 4482 | struct hclge_desc desc; |
| 4483 | u8 resp_code; |
| 4484 | u16 retval; |
| 4485 | int ret; |
| 4486 | |
| 4487 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); |
| 4488 | memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); |
| 4489 | |
| 4490 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4491 | if (ret) { |
| 4492 | dev_err(&hdev->pdev->dev, |
| 4493 | "add mac ethertype failed for cmd_send, ret =%d.\n", |
| 4494 | ret); |
| 4495 | return ret; |
| 4496 | } |
| 4497 | |
| 4498 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
| 4499 | retval = le16_to_cpu(desc.retval); |
| 4500 | |
| 4501 | return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); |
| 4502 | } |
| 4503 | |
| 4504 | static int init_mgr_tbl(struct hclge_dev *hdev) |
| 4505 | { |
| 4506 | int ret; |
| 4507 | int i; |
| 4508 | |
| 4509 | for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { |
| 4510 | ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); |
| 4511 | if (ret) { |
| 4512 | dev_err(&hdev->pdev->dev, |
| 4513 | "add mac ethertype failed, ret =%d.\n", |
| 4514 | ret); |
| 4515 | return ret; |
| 4516 | } |
| 4517 | } |
| 4518 | |
| 4519 | return 0; |
| 4520 | } |
| 4521 | |
| 4522 | static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) |
| 4523 | { |
| 4524 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4525 | struct hclge_dev *hdev = vport->back; |
| 4526 | |
| 4527 | ether_addr_copy(p, hdev->hw.mac.mac_addr); |
| 4528 | } |
| 4529 | |
| 4530 | static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, |
| 4531 | bool is_first) |
| 4532 | { |
| 4533 | const unsigned char *new_addr = (const unsigned char *)p; |
| 4534 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4535 | struct hclge_dev *hdev = vport->back; |
| 4536 | int ret; |
| 4537 | |
| 4538 | /* mac addr check */ |
| 4539 | if (is_zero_ether_addr(new_addr) || |
| 4540 | is_broadcast_ether_addr(new_addr) || |
| 4541 | is_multicast_ether_addr(new_addr)) { |
| 4542 | dev_err(&hdev->pdev->dev, |
| 4543 | "Change uc mac err! invalid mac:%p.\n", |
| 4544 | new_addr); |
| 4545 | return -EINVAL; |
| 4546 | } |
| 4547 | |
| 4548 | if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) |
| 4549 | dev_warn(&hdev->pdev->dev, |
| 4550 | "remove old uc mac address fail.\n"); |
| 4551 | |
| 4552 | ret = hclge_add_uc_addr(handle, new_addr); |
| 4553 | if (ret) { |
| 4554 | dev_err(&hdev->pdev->dev, |
| 4555 | "add uc mac address fail, ret =%d.\n", |
| 4556 | ret); |
| 4557 | |
| 4558 | if (!is_first && |
| 4559 | hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) |
| 4560 | dev_err(&hdev->pdev->dev, |
| 4561 | "restore uc mac address fail.\n"); |
| 4562 | |
| 4563 | return -EIO; |
| 4564 | } |
| 4565 | |
| 4566 | ret = hclge_pause_addr_cfg(hdev, new_addr); |
| 4567 | if (ret) { |
| 4568 | dev_err(&hdev->pdev->dev, |
| 4569 | "configure mac pause address fail, ret =%d.\n", |
| 4570 | ret); |
| 4571 | return -EIO; |
| 4572 | } |
| 4573 | |
| 4574 | ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); |
| 4575 | |
| 4576 | return 0; |
| 4577 | } |
| 4578 | |
| 4579 | static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, |
| 4580 | bool filter_en) |
| 4581 | { |
| 4582 | struct hclge_vlan_filter_ctrl_cmd *req; |
| 4583 | struct hclge_desc desc; |
| 4584 | int ret; |
| 4585 | |
| 4586 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); |
| 4587 | |
| 4588 | req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; |
| 4589 | req->vlan_type = vlan_type; |
| 4590 | req->vlan_fe = filter_en; |
| 4591 | |
| 4592 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4593 | if (ret) { |
| 4594 | dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", |
| 4595 | ret); |
| 4596 | return ret; |
| 4597 | } |
| 4598 | |
| 4599 | return 0; |
| 4600 | } |
| 4601 | |
| 4602 | #define HCLGE_FILTER_TYPE_VF 0 |
| 4603 | #define HCLGE_FILTER_TYPE_PORT 1 |
| 4604 | |
| 4605 | static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) |
| 4606 | { |
| 4607 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4608 | struct hclge_dev *hdev = vport->back; |
| 4609 | |
| 4610 | hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); |
| 4611 | } |
| 4612 | |
| 4613 | static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, |
| 4614 | bool is_kill, u16 vlan, u8 qos, |
| 4615 | __be16 proto) |
| 4616 | { |
| 4617 | #define HCLGE_MAX_VF_BYTES 16 |
| 4618 | struct hclge_vlan_filter_vf_cfg_cmd *req0; |
| 4619 | struct hclge_vlan_filter_vf_cfg_cmd *req1; |
| 4620 | struct hclge_desc desc[2]; |
| 4621 | u8 vf_byte_val; |
| 4622 | u8 vf_byte_off; |
| 4623 | int ret; |
| 4624 | |
| 4625 | hclge_cmd_setup_basic_desc(&desc[0], |
| 4626 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); |
| 4627 | hclge_cmd_setup_basic_desc(&desc[1], |
| 4628 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); |
| 4629 | |
| 4630 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
| 4631 | |
| 4632 | vf_byte_off = vfid / 8; |
| 4633 | vf_byte_val = 1 << (vfid % 8); |
| 4634 | |
| 4635 | req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; |
| 4636 | req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; |
| 4637 | |
| 4638 | req0->vlan_id = cpu_to_le16(vlan); |
| 4639 | req0->vlan_cfg = is_kill; |
| 4640 | |
| 4641 | if (vf_byte_off < HCLGE_MAX_VF_BYTES) |
| 4642 | req0->vf_bitmap[vf_byte_off] = vf_byte_val; |
| 4643 | else |
| 4644 | req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; |
| 4645 | |
| 4646 | ret = hclge_cmd_send(&hdev->hw, desc, 2); |
| 4647 | if (ret) { |
| 4648 | dev_err(&hdev->pdev->dev, |
| 4649 | "Send vf vlan command fail, ret =%d.\n", |
| 4650 | ret); |
| 4651 | return ret; |
| 4652 | } |
| 4653 | |
| 4654 | if (!is_kill) { |
| 4655 | #define HCLGE_VF_VLAN_NO_ENTRY 2 |
| 4656 | if (!req0->resp_code || req0->resp_code == 1) |
| 4657 | return 0; |
| 4658 | |
| 4659 | if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { |
| 4660 | dev_warn(&hdev->pdev->dev, |
| 4661 | "vf vlan table is full, vf vlan filter is disabled\n"); |
| 4662 | return 0; |
| 4663 | } |
| 4664 | |
| 4665 | dev_err(&hdev->pdev->dev, |
| 4666 | "Add vf vlan filter fail, ret =%d.\n", |
| 4667 | req0->resp_code); |
| 4668 | } else { |
| 4669 | if (!req0->resp_code) |
| 4670 | return 0; |
| 4671 | |
| 4672 | dev_err(&hdev->pdev->dev, |
| 4673 | "Kill vf vlan filter fail, ret =%d.\n", |
| 4674 | req0->resp_code); |
| 4675 | } |
| 4676 | |
| 4677 | return -EIO; |
| 4678 | } |
| 4679 | |
| 4680 | static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, |
| 4681 | u16 vlan_id, bool is_kill) |
| 4682 | { |
| 4683 | struct hclge_vlan_filter_pf_cfg_cmd *req; |
| 4684 | struct hclge_desc desc; |
| 4685 | u8 vlan_offset_byte_val; |
| 4686 | u8 vlan_offset_byte; |
| 4687 | u8 vlan_offset_160; |
| 4688 | int ret; |
| 4689 | |
| 4690 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); |
| 4691 | |
| 4692 | vlan_offset_160 = vlan_id / 160; |
| 4693 | vlan_offset_byte = (vlan_id % 160) / 8; |
| 4694 | vlan_offset_byte_val = 1 << (vlan_id % 8); |
| 4695 | |
| 4696 | req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; |
| 4697 | req->vlan_offset = vlan_offset_160; |
| 4698 | req->vlan_cfg = is_kill; |
| 4699 | req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; |
| 4700 | |
| 4701 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4702 | if (ret) |
| 4703 | dev_err(&hdev->pdev->dev, |
| 4704 | "port vlan command, send fail, ret =%d.\n", ret); |
| 4705 | return ret; |
| 4706 | } |
| 4707 | |
| 4708 | static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, |
| 4709 | u16 vport_id, u16 vlan_id, u8 qos, |
| 4710 | bool is_kill) |
| 4711 | { |
| 4712 | u16 vport_idx, vport_num = 0; |
| 4713 | int ret; |
| 4714 | |
| 4715 | ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, |
| 4716 | 0, proto); |
| 4717 | if (ret) { |
| 4718 | dev_err(&hdev->pdev->dev, |
| 4719 | "Set %d vport vlan filter config fail, ret =%d.\n", |
| 4720 | vport_id, ret); |
| 4721 | return ret; |
| 4722 | } |
| 4723 | |
| 4724 | /* vlan 0 may be added twice when 8021q module is enabled */ |
| 4725 | if (!is_kill && !vlan_id && |
| 4726 | test_bit(vport_id, hdev->vlan_table[vlan_id])) |
| 4727 | return 0; |
| 4728 | |
| 4729 | if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { |
| 4730 | dev_err(&hdev->pdev->dev, |
| 4731 | "Add port vlan failed, vport %d is already in vlan %d\n", |
| 4732 | vport_id, vlan_id); |
| 4733 | return -EINVAL; |
| 4734 | } |
| 4735 | |
| 4736 | if (is_kill && |
| 4737 | !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { |
| 4738 | dev_err(&hdev->pdev->dev, |
| 4739 | "Delete port vlan failed, vport %d is not in vlan %d\n", |
| 4740 | vport_id, vlan_id); |
| 4741 | return -EINVAL; |
| 4742 | } |
| 4743 | |
| 4744 | for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID) |
| 4745 | vport_num++; |
| 4746 | |
| 4747 | if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) |
| 4748 | ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, |
| 4749 | is_kill); |
| 4750 | |
| 4751 | return ret; |
| 4752 | } |
| 4753 | |
| 4754 | int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, |
| 4755 | u16 vlan_id, bool is_kill) |
| 4756 | { |
| 4757 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4758 | struct hclge_dev *hdev = vport->back; |
| 4759 | |
| 4760 | return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, |
| 4761 | 0, is_kill); |
| 4762 | } |
| 4763 | |
| 4764 | static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, |
| 4765 | u16 vlan, u8 qos, __be16 proto) |
| 4766 | { |
| 4767 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4768 | struct hclge_dev *hdev = vport->back; |
| 4769 | |
| 4770 | if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) |
| 4771 | return -EINVAL; |
| 4772 | if (proto != htons(ETH_P_8021Q)) |
| 4773 | return -EPROTONOSUPPORT; |
| 4774 | |
| 4775 | return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); |
| 4776 | } |
| 4777 | |
| 4778 | static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) |
| 4779 | { |
| 4780 | struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; |
| 4781 | struct hclge_vport_vtag_tx_cfg_cmd *req; |
| 4782 | struct hclge_dev *hdev = vport->back; |
| 4783 | struct hclge_desc desc; |
| 4784 | int status; |
| 4785 | |
| 4786 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); |
| 4787 | |
| 4788 | req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; |
| 4789 | req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); |
| 4790 | req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); |
| 4791 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, |
| 4792 | vcfg->accept_tag1 ? 1 : 0); |
| 4793 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, |
| 4794 | vcfg->accept_untag1 ? 1 : 0); |
| 4795 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, |
| 4796 | vcfg->accept_tag2 ? 1 : 0); |
| 4797 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, |
| 4798 | vcfg->accept_untag2 ? 1 : 0); |
| 4799 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, |
| 4800 | vcfg->insert_tag1_en ? 1 : 0); |
| 4801 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, |
| 4802 | vcfg->insert_tag2_en ? 1 : 0); |
| 4803 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); |
| 4804 | |
| 4805 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; |
| 4806 | req->vf_bitmap[req->vf_offset] = |
| 4807 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); |
| 4808 | |
| 4809 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4810 | if (status) |
| 4811 | dev_err(&hdev->pdev->dev, |
| 4812 | "Send port txvlan cfg command fail, ret =%d\n", |
| 4813 | status); |
| 4814 | |
| 4815 | return status; |
| 4816 | } |
| 4817 | |
| 4818 | static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) |
| 4819 | { |
| 4820 | struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; |
| 4821 | struct hclge_vport_vtag_rx_cfg_cmd *req; |
| 4822 | struct hclge_dev *hdev = vport->back; |
| 4823 | struct hclge_desc desc; |
| 4824 | int status; |
| 4825 | |
| 4826 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); |
| 4827 | |
| 4828 | req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; |
| 4829 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, |
| 4830 | vcfg->strip_tag1_en ? 1 : 0); |
| 4831 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, |
| 4832 | vcfg->strip_tag2_en ? 1 : 0); |
| 4833 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, |
| 4834 | vcfg->vlan1_vlan_prionly ? 1 : 0); |
| 4835 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, |
| 4836 | vcfg->vlan2_vlan_prionly ? 1 : 0); |
| 4837 | |
| 4838 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; |
| 4839 | req->vf_bitmap[req->vf_offset] = |
| 4840 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); |
| 4841 | |
| 4842 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4843 | if (status) |
| 4844 | dev_err(&hdev->pdev->dev, |
| 4845 | "Send port rxvlan cfg command fail, ret =%d\n", |
| 4846 | status); |
| 4847 | |
| 4848 | return status; |
| 4849 | } |
| 4850 | |
| 4851 | static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) |
| 4852 | { |
| 4853 | struct hclge_rx_vlan_type_cfg_cmd *rx_req; |
| 4854 | struct hclge_tx_vlan_type_cfg_cmd *tx_req; |
| 4855 | struct hclge_desc desc; |
| 4856 | int status; |
| 4857 | |
| 4858 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); |
| 4859 | rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; |
| 4860 | rx_req->ot_fst_vlan_type = |
| 4861 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); |
| 4862 | rx_req->ot_sec_vlan_type = |
| 4863 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); |
| 4864 | rx_req->in_fst_vlan_type = |
| 4865 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); |
| 4866 | rx_req->in_sec_vlan_type = |
| 4867 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); |
| 4868 | |
| 4869 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4870 | if (status) { |
| 4871 | dev_err(&hdev->pdev->dev, |
| 4872 | "Send rxvlan protocol type command fail, ret =%d\n", |
| 4873 | status); |
| 4874 | return status; |
| 4875 | } |
| 4876 | |
| 4877 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); |
| 4878 | |
| 4879 | tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; |
| 4880 | tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); |
| 4881 | tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); |
| 4882 | |
| 4883 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4884 | if (status) |
| 4885 | dev_err(&hdev->pdev->dev, |
| 4886 | "Send txvlan protocol type command fail, ret =%d\n", |
| 4887 | status); |
| 4888 | |
| 4889 | return status; |
| 4890 | } |
| 4891 | |
| 4892 | static int hclge_init_vlan_config(struct hclge_dev *hdev) |
| 4893 | { |
| 4894 | #define HCLGE_DEF_VLAN_TYPE 0x8100 |
| 4895 | |
| 4896 | struct hnae3_handle *handle; |
| 4897 | struct hclge_vport *vport; |
| 4898 | int ret; |
| 4899 | int i; |
| 4900 | |
| 4901 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); |
| 4902 | if (ret) |
| 4903 | return ret; |
| 4904 | |
| 4905 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); |
| 4906 | if (ret) |
| 4907 | return ret; |
| 4908 | |
| 4909 | hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; |
| 4910 | hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; |
| 4911 | hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; |
| 4912 | hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; |
| 4913 | hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; |
| 4914 | hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; |
| 4915 | |
| 4916 | ret = hclge_set_vlan_protocol_type(hdev); |
| 4917 | if (ret) |
| 4918 | return ret; |
| 4919 | |
| 4920 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
| 4921 | vport = &hdev->vport[i]; |
| 4922 | vport->txvlan_cfg.accept_tag1 = true; |
| 4923 | vport->txvlan_cfg.accept_untag1 = true; |
| 4924 | |
| 4925 | /* accept_tag2 and accept_untag2 are not supported on |
| 4926 | * pdev revision(0x20), new revision support them. The |
| 4927 | * value of this two fields will not return error when driver |
| 4928 | * send command to fireware in revision(0x20). |
| 4929 | * This two fields can not configured by user. |
| 4930 | */ |
| 4931 | vport->txvlan_cfg.accept_tag2 = true; |
| 4932 | vport->txvlan_cfg.accept_untag2 = true; |
| 4933 | |
| 4934 | vport->txvlan_cfg.insert_tag1_en = false; |
| 4935 | vport->txvlan_cfg.insert_tag2_en = false; |
| 4936 | vport->txvlan_cfg.default_tag1 = 0; |
| 4937 | vport->txvlan_cfg.default_tag2 = 0; |
| 4938 | |
| 4939 | ret = hclge_set_vlan_tx_offload_cfg(vport); |
| 4940 | if (ret) |
| 4941 | return ret; |
| 4942 | |
| 4943 | vport->rxvlan_cfg.strip_tag1_en = false; |
| 4944 | vport->rxvlan_cfg.strip_tag2_en = true; |
| 4945 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; |
| 4946 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; |
| 4947 | |
| 4948 | ret = hclge_set_vlan_rx_offload_cfg(vport); |
| 4949 | if (ret) |
| 4950 | return ret; |
| 4951 | } |
| 4952 | |
| 4953 | handle = &hdev->vport[0].nic; |
| 4954 | return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); |
| 4955 | } |
| 4956 | |
| 4957 | int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) |
| 4958 | { |
| 4959 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 4960 | |
| 4961 | vport->rxvlan_cfg.strip_tag1_en = false; |
| 4962 | vport->rxvlan_cfg.strip_tag2_en = enable; |
| 4963 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; |
| 4964 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; |
| 4965 | |
| 4966 | return hclge_set_vlan_rx_offload_cfg(vport); |
| 4967 | } |
| 4968 | |
| 4969 | static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) |
| 4970 | { |
| 4971 | struct hclge_config_max_frm_size_cmd *req; |
| 4972 | struct hclge_desc desc; |
| 4973 | int max_frm_size; |
| 4974 | int ret; |
| 4975 | |
| 4976 | max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
| 4977 | |
| 4978 | if (max_frm_size < HCLGE_MAC_MIN_FRAME || |
| 4979 | max_frm_size > HCLGE_MAC_MAX_FRAME) |
| 4980 | return -EINVAL; |
| 4981 | |
| 4982 | max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); |
| 4983 | |
| 4984 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); |
| 4985 | |
| 4986 | req = (struct hclge_config_max_frm_size_cmd *)desc.data; |
| 4987 | req->max_frm_size = cpu_to_le16(max_frm_size); |
| 4988 | req->min_frm_size = HCLGE_MAC_MIN_FRAME; |
| 4989 | |
| 4990 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 4991 | if (ret) { |
| 4992 | dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); |
| 4993 | return ret; |
| 4994 | } |
| 4995 | |
| 4996 | hdev->mps = max_frm_size; |
| 4997 | |
| 4998 | return 0; |
| 4999 | } |
| 5000 | |
| 5001 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) |
| 5002 | { |
| 5003 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5004 | struct hclge_dev *hdev = vport->back; |
| 5005 | int ret; |
| 5006 | |
| 5007 | ret = hclge_set_mac_mtu(hdev, new_mtu); |
| 5008 | if (ret) { |
| 5009 | dev_err(&hdev->pdev->dev, |
| 5010 | "Change mtu fail, ret =%d\n", ret); |
| 5011 | return ret; |
| 5012 | } |
| 5013 | |
| 5014 | ret = hclge_buffer_alloc(hdev); |
| 5015 | if (ret) |
| 5016 | dev_err(&hdev->pdev->dev, |
| 5017 | "Allocate buffer fail, ret =%d\n", ret); |
| 5018 | |
| 5019 | return ret; |
| 5020 | } |
| 5021 | |
| 5022 | static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, |
| 5023 | bool enable) |
| 5024 | { |
| 5025 | struct hclge_reset_tqp_queue_cmd *req; |
| 5026 | struct hclge_desc desc; |
| 5027 | int ret; |
| 5028 | |
| 5029 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); |
| 5030 | |
| 5031 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
| 5032 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
| 5033 | hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); |
| 5034 | |
| 5035 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 5036 | if (ret) { |
| 5037 | dev_err(&hdev->pdev->dev, |
| 5038 | "Send tqp reset cmd error, status =%d\n", ret); |
| 5039 | return ret; |
| 5040 | } |
| 5041 | |
| 5042 | return 0; |
| 5043 | } |
| 5044 | |
| 5045 | static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) |
| 5046 | { |
| 5047 | struct hclge_reset_tqp_queue_cmd *req; |
| 5048 | struct hclge_desc desc; |
| 5049 | int ret; |
| 5050 | |
| 5051 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); |
| 5052 | |
| 5053 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
| 5054 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
| 5055 | |
| 5056 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 5057 | if (ret) { |
| 5058 | dev_err(&hdev->pdev->dev, |
| 5059 | "Get reset status error, status =%d\n", ret); |
| 5060 | return ret; |
| 5061 | } |
| 5062 | |
| 5063 | return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); |
| 5064 | } |
| 5065 | |
| 5066 | static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, |
| 5067 | u16 queue_id) |
| 5068 | { |
| 5069 | struct hnae3_queue *queue; |
| 5070 | struct hclge_tqp *tqp; |
| 5071 | |
| 5072 | queue = handle->kinfo.tqp[queue_id]; |
| 5073 | tqp = container_of(queue, struct hclge_tqp, q); |
| 5074 | |
| 5075 | return tqp->index; |
| 5076 | } |
| 5077 | |
| 5078 | void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) |
| 5079 | { |
| 5080 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5081 | struct hclge_dev *hdev = vport->back; |
| 5082 | int reset_try_times = 0; |
| 5083 | int reset_status; |
| 5084 | u16 queue_gid; |
| 5085 | int ret; |
| 5086 | |
| 5087 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
| 5088 | return; |
| 5089 | |
| 5090 | queue_gid = hclge_covert_handle_qid_global(handle, queue_id); |
| 5091 | |
| 5092 | ret = hclge_tqp_enable(hdev, queue_id, 0, false); |
| 5093 | if (ret) { |
| 5094 | dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); |
| 5095 | return; |
| 5096 | } |
| 5097 | |
| 5098 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); |
| 5099 | if (ret) { |
| 5100 | dev_warn(&hdev->pdev->dev, |
| 5101 | "Send reset tqp cmd fail, ret = %d\n", ret); |
| 5102 | return; |
| 5103 | } |
| 5104 | |
| 5105 | reset_try_times = 0; |
| 5106 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { |
| 5107 | /* Wait for tqp hw reset */ |
| 5108 | msleep(20); |
| 5109 | reset_status = hclge_get_reset_status(hdev, queue_gid); |
| 5110 | if (reset_status) |
| 5111 | break; |
| 5112 | } |
| 5113 | |
| 5114 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { |
| 5115 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); |
| 5116 | return; |
| 5117 | } |
| 5118 | |
| 5119 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); |
| 5120 | if (ret) { |
| 5121 | dev_warn(&hdev->pdev->dev, |
| 5122 | "Deassert the soft reset fail, ret = %d\n", ret); |
| 5123 | return; |
| 5124 | } |
| 5125 | } |
| 5126 | |
| 5127 | void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) |
| 5128 | { |
| 5129 | struct hclge_dev *hdev = vport->back; |
| 5130 | int reset_try_times = 0; |
| 5131 | int reset_status; |
| 5132 | u16 queue_gid; |
| 5133 | int ret; |
| 5134 | |
| 5135 | queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); |
| 5136 | |
| 5137 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); |
| 5138 | if (ret) { |
| 5139 | dev_warn(&hdev->pdev->dev, |
| 5140 | "Send reset tqp cmd fail, ret = %d\n", ret); |
| 5141 | return; |
| 5142 | } |
| 5143 | |
| 5144 | reset_try_times = 0; |
| 5145 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { |
| 5146 | /* Wait for tqp hw reset */ |
| 5147 | msleep(20); |
| 5148 | reset_status = hclge_get_reset_status(hdev, queue_gid); |
| 5149 | if (reset_status) |
| 5150 | break; |
| 5151 | } |
| 5152 | |
| 5153 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { |
| 5154 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); |
| 5155 | return; |
| 5156 | } |
| 5157 | |
| 5158 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); |
| 5159 | if (ret) |
| 5160 | dev_warn(&hdev->pdev->dev, |
| 5161 | "Deassert the soft reset fail, ret = %d\n", ret); |
| 5162 | } |
| 5163 | |
| 5164 | static u32 hclge_get_fw_version(struct hnae3_handle *handle) |
| 5165 | { |
| 5166 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5167 | struct hclge_dev *hdev = vport->back; |
| 5168 | |
| 5169 | return hdev->fw_version; |
| 5170 | } |
| 5171 | |
| 5172 | static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, |
| 5173 | u32 *flowctrl_adv) |
| 5174 | { |
| 5175 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5176 | struct hclge_dev *hdev = vport->back; |
| 5177 | struct phy_device *phydev = hdev->hw.mac.phydev; |
| 5178 | |
| 5179 | if (!phydev) |
| 5180 | return; |
| 5181 | |
| 5182 | *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | |
| 5183 | (phydev->advertising & ADVERTISED_Asym_Pause); |
| 5184 | } |
| 5185 | |
| 5186 | static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) |
| 5187 | { |
| 5188 | struct phy_device *phydev = hdev->hw.mac.phydev; |
| 5189 | |
| 5190 | if (!phydev) |
| 5191 | return; |
| 5192 | |
| 5193 | phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); |
| 5194 | |
| 5195 | if (rx_en) |
| 5196 | phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; |
| 5197 | |
| 5198 | if (tx_en) |
| 5199 | phydev->advertising ^= ADVERTISED_Asym_Pause; |
| 5200 | } |
| 5201 | |
| 5202 | static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) |
| 5203 | { |
| 5204 | int ret; |
| 5205 | |
| 5206 | if (rx_en && tx_en) |
| 5207 | hdev->fc_mode_last_time = HCLGE_FC_FULL; |
| 5208 | else if (rx_en && !tx_en) |
| 5209 | hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; |
| 5210 | else if (!rx_en && tx_en) |
| 5211 | hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; |
| 5212 | else |
| 5213 | hdev->fc_mode_last_time = HCLGE_FC_NONE; |
| 5214 | |
| 5215 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) |
| 5216 | return 0; |
| 5217 | |
| 5218 | ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); |
| 5219 | if (ret) { |
| 5220 | dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", |
| 5221 | ret); |
| 5222 | return ret; |
| 5223 | } |
| 5224 | |
| 5225 | hdev->tm_info.fc_mode = hdev->fc_mode_last_time; |
| 5226 | |
| 5227 | return 0; |
| 5228 | } |
| 5229 | |
| 5230 | int hclge_cfg_flowctrl(struct hclge_dev *hdev) |
| 5231 | { |
| 5232 | struct phy_device *phydev = hdev->hw.mac.phydev; |
| 5233 | u16 remote_advertising = 0; |
| 5234 | u16 local_advertising = 0; |
| 5235 | u32 rx_pause, tx_pause; |
| 5236 | u8 flowctl; |
| 5237 | |
| 5238 | if (!phydev->link || !phydev->autoneg) |
| 5239 | return 0; |
| 5240 | |
| 5241 | if (phydev->advertising & ADVERTISED_Pause) |
| 5242 | local_advertising = ADVERTISE_PAUSE_CAP; |
| 5243 | |
| 5244 | if (phydev->advertising & ADVERTISED_Asym_Pause) |
| 5245 | local_advertising |= ADVERTISE_PAUSE_ASYM; |
| 5246 | |
| 5247 | if (phydev->pause) |
| 5248 | remote_advertising = LPA_PAUSE_CAP; |
| 5249 | |
| 5250 | if (phydev->asym_pause) |
| 5251 | remote_advertising |= LPA_PAUSE_ASYM; |
| 5252 | |
| 5253 | flowctl = mii_resolve_flowctrl_fdx(local_advertising, |
| 5254 | remote_advertising); |
| 5255 | tx_pause = flowctl & FLOW_CTRL_TX; |
| 5256 | rx_pause = flowctl & FLOW_CTRL_RX; |
| 5257 | |
| 5258 | if (phydev->duplex == HCLGE_MAC_HALF) { |
| 5259 | tx_pause = 0; |
| 5260 | rx_pause = 0; |
| 5261 | } |
| 5262 | |
| 5263 | return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); |
| 5264 | } |
| 5265 | |
| 5266 | static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, |
| 5267 | u32 *rx_en, u32 *tx_en) |
| 5268 | { |
| 5269 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5270 | struct hclge_dev *hdev = vport->back; |
| 5271 | |
| 5272 | *auto_neg = hclge_get_autoneg(handle); |
| 5273 | |
| 5274 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { |
| 5275 | *rx_en = 0; |
| 5276 | *tx_en = 0; |
| 5277 | return; |
| 5278 | } |
| 5279 | |
| 5280 | if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { |
| 5281 | *rx_en = 1; |
| 5282 | *tx_en = 0; |
| 5283 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { |
| 5284 | *tx_en = 1; |
| 5285 | *rx_en = 0; |
| 5286 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { |
| 5287 | *rx_en = 1; |
| 5288 | *tx_en = 1; |
| 5289 | } else { |
| 5290 | *rx_en = 0; |
| 5291 | *tx_en = 0; |
| 5292 | } |
| 5293 | } |
| 5294 | |
| 5295 | static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, |
| 5296 | u32 rx_en, u32 tx_en) |
| 5297 | { |
| 5298 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5299 | struct hclge_dev *hdev = vport->back; |
| 5300 | struct phy_device *phydev = hdev->hw.mac.phydev; |
| 5301 | u32 fc_autoneg; |
| 5302 | |
| 5303 | fc_autoneg = hclge_get_autoneg(handle); |
| 5304 | if (auto_neg != fc_autoneg) { |
| 5305 | dev_info(&hdev->pdev->dev, |
| 5306 | "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); |
| 5307 | return -EOPNOTSUPP; |
| 5308 | } |
| 5309 | |
| 5310 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { |
| 5311 | dev_info(&hdev->pdev->dev, |
| 5312 | "Priority flow control enabled. Cannot set link flow control.\n"); |
| 5313 | return -EOPNOTSUPP; |
| 5314 | } |
| 5315 | |
| 5316 | hclge_set_flowctrl_adv(hdev, rx_en, tx_en); |
| 5317 | |
| 5318 | if (!fc_autoneg) |
| 5319 | return hclge_cfg_pauseparam(hdev, rx_en, tx_en); |
| 5320 | |
| 5321 | /* Only support flow control negotiation for netdev with |
| 5322 | * phy attached for now. |
| 5323 | */ |
| 5324 | if (!phydev) |
| 5325 | return -EOPNOTSUPP; |
| 5326 | |
| 5327 | return phy_start_aneg(phydev); |
| 5328 | } |
| 5329 | |
| 5330 | static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, |
| 5331 | u8 *auto_neg, u32 *speed, u8 *duplex) |
| 5332 | { |
| 5333 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5334 | struct hclge_dev *hdev = vport->back; |
| 5335 | |
| 5336 | if (speed) |
| 5337 | *speed = hdev->hw.mac.speed; |
| 5338 | if (duplex) |
| 5339 | *duplex = hdev->hw.mac.duplex; |
| 5340 | if (auto_neg) |
| 5341 | *auto_neg = hdev->hw.mac.autoneg; |
| 5342 | } |
| 5343 | |
| 5344 | static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) |
| 5345 | { |
| 5346 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5347 | struct hclge_dev *hdev = vport->back; |
| 5348 | |
| 5349 | if (media_type) |
| 5350 | *media_type = hdev->hw.mac.media_type; |
| 5351 | } |
| 5352 | |
| 5353 | static void hclge_get_mdix_mode(struct hnae3_handle *handle, |
| 5354 | u8 *tp_mdix_ctrl, u8 *tp_mdix) |
| 5355 | { |
| 5356 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5357 | struct hclge_dev *hdev = vport->back; |
| 5358 | struct phy_device *phydev = hdev->hw.mac.phydev; |
| 5359 | int mdix_ctrl, mdix, retval, is_resolved; |
| 5360 | |
| 5361 | if (!phydev) { |
| 5362 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; |
| 5363 | *tp_mdix = ETH_TP_MDI_INVALID; |
| 5364 | return; |
| 5365 | } |
| 5366 | |
| 5367 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); |
| 5368 | |
| 5369 | retval = phy_read(phydev, HCLGE_PHY_CSC_REG); |
| 5370 | mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, |
| 5371 | HCLGE_PHY_MDIX_CTRL_S); |
| 5372 | |
| 5373 | retval = phy_read(phydev, HCLGE_PHY_CSS_REG); |
| 5374 | mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); |
| 5375 | is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); |
| 5376 | |
| 5377 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); |
| 5378 | |
| 5379 | switch (mdix_ctrl) { |
| 5380 | case 0x0: |
| 5381 | *tp_mdix_ctrl = ETH_TP_MDI; |
| 5382 | break; |
| 5383 | case 0x1: |
| 5384 | *tp_mdix_ctrl = ETH_TP_MDI_X; |
| 5385 | break; |
| 5386 | case 0x3: |
| 5387 | *tp_mdix_ctrl = ETH_TP_MDI_AUTO; |
| 5388 | break; |
| 5389 | default: |
| 5390 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; |
| 5391 | break; |
| 5392 | } |
| 5393 | |
| 5394 | if (!is_resolved) |
| 5395 | *tp_mdix = ETH_TP_MDI_INVALID; |
| 5396 | else if (mdix) |
| 5397 | *tp_mdix = ETH_TP_MDI_X; |
| 5398 | else |
| 5399 | *tp_mdix = ETH_TP_MDI; |
| 5400 | } |
| 5401 | |
| 5402 | static int hclge_init_client_instance(struct hnae3_client *client, |
| 5403 | struct hnae3_ae_dev *ae_dev) |
| 5404 | { |
| 5405 | struct hclge_dev *hdev = ae_dev->priv; |
| 5406 | struct hclge_vport *vport; |
| 5407 | int i, ret; |
| 5408 | |
| 5409 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
| 5410 | vport = &hdev->vport[i]; |
| 5411 | |
| 5412 | switch (client->type) { |
| 5413 | case HNAE3_CLIENT_KNIC: |
| 5414 | |
| 5415 | hdev->nic_client = client; |
| 5416 | vport->nic.client = client; |
| 5417 | ret = client->ops->init_instance(&vport->nic); |
| 5418 | if (ret) |
| 5419 | return ret; |
| 5420 | |
| 5421 | if (hdev->roce_client && |
| 5422 | hnae3_dev_roce_supported(hdev)) { |
| 5423 | struct hnae3_client *rc = hdev->roce_client; |
| 5424 | |
| 5425 | ret = hclge_init_roce_base_info(vport); |
| 5426 | if (ret) |
| 5427 | return ret; |
| 5428 | |
| 5429 | ret = rc->ops->init_instance(&vport->roce); |
| 5430 | if (ret) |
| 5431 | return ret; |
| 5432 | } |
| 5433 | |
| 5434 | break; |
| 5435 | case HNAE3_CLIENT_UNIC: |
| 5436 | hdev->nic_client = client; |
| 5437 | vport->nic.client = client; |
| 5438 | |
| 5439 | ret = client->ops->init_instance(&vport->nic); |
| 5440 | if (ret) |
| 5441 | return ret; |
| 5442 | |
| 5443 | break; |
| 5444 | case HNAE3_CLIENT_ROCE: |
| 5445 | if (hnae3_dev_roce_supported(hdev)) { |
| 5446 | hdev->roce_client = client; |
| 5447 | vport->roce.client = client; |
| 5448 | } |
| 5449 | |
| 5450 | if (hdev->roce_client && hdev->nic_client) { |
| 5451 | ret = hclge_init_roce_base_info(vport); |
| 5452 | if (ret) |
| 5453 | return ret; |
| 5454 | |
| 5455 | ret = client->ops->init_instance(&vport->roce); |
| 5456 | if (ret) |
| 5457 | return ret; |
| 5458 | } |
| 5459 | } |
| 5460 | } |
| 5461 | |
| 5462 | return 0; |
| 5463 | } |
| 5464 | |
| 5465 | static void hclge_uninit_client_instance(struct hnae3_client *client, |
| 5466 | struct hnae3_ae_dev *ae_dev) |
| 5467 | { |
| 5468 | struct hclge_dev *hdev = ae_dev->priv; |
| 5469 | struct hclge_vport *vport; |
| 5470 | int i; |
| 5471 | |
| 5472 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
| 5473 | vport = &hdev->vport[i]; |
| 5474 | if (hdev->roce_client) { |
| 5475 | hdev->roce_client->ops->uninit_instance(&vport->roce, |
| 5476 | 0); |
| 5477 | hdev->roce_client = NULL; |
| 5478 | vport->roce.client = NULL; |
| 5479 | } |
| 5480 | if (client->type == HNAE3_CLIENT_ROCE) |
| 5481 | return; |
| 5482 | if (client->ops->uninit_instance) { |
| 5483 | client->ops->uninit_instance(&vport->nic, 0); |
| 5484 | hdev->nic_client = NULL; |
| 5485 | vport->nic.client = NULL; |
| 5486 | } |
| 5487 | } |
| 5488 | } |
| 5489 | |
| 5490 | static int hclge_pci_init(struct hclge_dev *hdev) |
| 5491 | { |
| 5492 | struct pci_dev *pdev = hdev->pdev; |
| 5493 | struct hclge_hw *hw; |
| 5494 | int ret; |
| 5495 | |
| 5496 | ret = pci_enable_device(pdev); |
| 5497 | if (ret) { |
| 5498 | dev_err(&pdev->dev, "failed to enable PCI device\n"); |
| 5499 | return ret; |
| 5500 | } |
| 5501 | |
| 5502 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
| 5503 | if (ret) { |
| 5504 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
| 5505 | if (ret) { |
| 5506 | dev_err(&pdev->dev, |
| 5507 | "can't set consistent PCI DMA"); |
| 5508 | goto err_disable_device; |
| 5509 | } |
| 5510 | dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); |
| 5511 | } |
| 5512 | |
| 5513 | ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); |
| 5514 | if (ret) { |
| 5515 | dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); |
| 5516 | goto err_disable_device; |
| 5517 | } |
| 5518 | |
| 5519 | pci_set_master(pdev); |
| 5520 | hw = &hdev->hw; |
| 5521 | hw->io_base = pcim_iomap(pdev, 2, 0); |
| 5522 | if (!hw->io_base) { |
| 5523 | dev_err(&pdev->dev, "Can't map configuration register space\n"); |
| 5524 | ret = -ENOMEM; |
| 5525 | goto err_clr_master; |
| 5526 | } |
| 5527 | |
| 5528 | hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); |
| 5529 | |
| 5530 | return 0; |
| 5531 | err_clr_master: |
| 5532 | pci_clear_master(pdev); |
| 5533 | pci_release_regions(pdev); |
| 5534 | err_disable_device: |
| 5535 | pci_disable_device(pdev); |
| 5536 | |
| 5537 | return ret; |
| 5538 | } |
| 5539 | |
| 5540 | static void hclge_pci_uninit(struct hclge_dev *hdev) |
| 5541 | { |
| 5542 | struct pci_dev *pdev = hdev->pdev; |
| 5543 | |
| 5544 | pcim_iounmap(pdev, hdev->hw.io_base); |
| 5545 | pci_free_irq_vectors(pdev); |
| 5546 | pci_clear_master(pdev); |
| 5547 | pci_release_mem_regions(pdev); |
| 5548 | pci_disable_device(pdev); |
| 5549 | } |
| 5550 | |
| 5551 | static void hclge_state_init(struct hclge_dev *hdev) |
| 5552 | { |
| 5553 | set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); |
| 5554 | set_bit(HCLGE_STATE_DOWN, &hdev->state); |
| 5555 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); |
| 5556 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); |
| 5557 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); |
| 5558 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); |
| 5559 | } |
| 5560 | |
| 5561 | static void hclge_state_uninit(struct hclge_dev *hdev) |
| 5562 | { |
| 5563 | set_bit(HCLGE_STATE_DOWN, &hdev->state); |
| 5564 | |
| 5565 | if (hdev->service_timer.function) |
| 5566 | del_timer_sync(&hdev->service_timer); |
| 5567 | if (hdev->service_task.func) |
| 5568 | cancel_work_sync(&hdev->service_task); |
| 5569 | if (hdev->rst_service_task.func) |
| 5570 | cancel_work_sync(&hdev->rst_service_task); |
| 5571 | if (hdev->mbx_service_task.func) |
| 5572 | cancel_work_sync(&hdev->mbx_service_task); |
| 5573 | } |
| 5574 | |
| 5575 | static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) |
| 5576 | { |
| 5577 | struct pci_dev *pdev = ae_dev->pdev; |
| 5578 | struct hclge_dev *hdev; |
| 5579 | int ret; |
| 5580 | |
| 5581 | hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); |
| 5582 | if (!hdev) { |
| 5583 | ret = -ENOMEM; |
| 5584 | goto out; |
| 5585 | } |
| 5586 | |
| 5587 | hdev->pdev = pdev; |
| 5588 | hdev->ae_dev = ae_dev; |
| 5589 | hdev->reset_type = HNAE3_NONE_RESET; |
| 5590 | hdev->reset_request = 0; |
| 5591 | hdev->reset_pending = 0; |
| 5592 | ae_dev->priv = hdev; |
| 5593 | |
| 5594 | ret = hclge_pci_init(hdev); |
| 5595 | if (ret) { |
| 5596 | dev_err(&pdev->dev, "PCI init failed\n"); |
| 5597 | goto out; |
| 5598 | } |
| 5599 | |
| 5600 | /* Firmware command queue initialize */ |
| 5601 | ret = hclge_cmd_queue_init(hdev); |
| 5602 | if (ret) { |
| 5603 | dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); |
| 5604 | goto err_pci_uninit; |
| 5605 | } |
| 5606 | |
| 5607 | /* Firmware command initialize */ |
| 5608 | ret = hclge_cmd_init(hdev); |
| 5609 | if (ret) |
| 5610 | goto err_cmd_uninit; |
| 5611 | |
| 5612 | ret = hclge_get_cap(hdev); |
| 5613 | if (ret) { |
| 5614 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", |
| 5615 | ret); |
| 5616 | goto err_cmd_uninit; |
| 5617 | } |
| 5618 | |
| 5619 | ret = hclge_configure(hdev); |
| 5620 | if (ret) { |
| 5621 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); |
| 5622 | goto err_cmd_uninit; |
| 5623 | } |
| 5624 | |
| 5625 | ret = hclge_init_msi(hdev); |
| 5626 | if (ret) { |
| 5627 | dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); |
| 5628 | goto err_cmd_uninit; |
| 5629 | } |
| 5630 | |
| 5631 | ret = hclge_misc_irq_init(hdev); |
| 5632 | if (ret) { |
| 5633 | dev_err(&pdev->dev, |
| 5634 | "Misc IRQ(vector0) init error, ret = %d.\n", |
| 5635 | ret); |
| 5636 | goto err_msi_uninit; |
| 5637 | } |
| 5638 | |
| 5639 | ret = hclge_alloc_tqps(hdev); |
| 5640 | if (ret) { |
| 5641 | dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); |
| 5642 | goto err_msi_irq_uninit; |
| 5643 | } |
| 5644 | |
| 5645 | ret = hclge_alloc_vport(hdev); |
| 5646 | if (ret) { |
| 5647 | dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); |
| 5648 | goto err_msi_irq_uninit; |
| 5649 | } |
| 5650 | |
| 5651 | ret = hclge_map_tqp(hdev); |
| 5652 | if (ret) { |
| 5653 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); |
| 5654 | goto err_msi_irq_uninit; |
| 5655 | } |
| 5656 | |
| 5657 | if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { |
| 5658 | ret = hclge_mac_mdio_config(hdev); |
| 5659 | if (ret) { |
| 5660 | dev_err(&hdev->pdev->dev, |
| 5661 | "mdio config fail ret=%d\n", ret); |
| 5662 | goto err_msi_irq_uninit; |
| 5663 | } |
| 5664 | } |
| 5665 | |
| 5666 | ret = hclge_mac_init(hdev); |
| 5667 | if (ret) { |
| 5668 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); |
| 5669 | goto err_mdiobus_unreg; |
| 5670 | } |
| 5671 | |
| 5672 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); |
| 5673 | if (ret) { |
| 5674 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); |
| 5675 | goto err_mdiobus_unreg; |
| 5676 | } |
| 5677 | |
| 5678 | ret = hclge_init_vlan_config(hdev); |
| 5679 | if (ret) { |
| 5680 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); |
| 5681 | goto err_mdiobus_unreg; |
| 5682 | } |
| 5683 | |
| 5684 | ret = hclge_tm_schd_init(hdev); |
| 5685 | if (ret) { |
| 5686 | dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); |
| 5687 | goto err_mdiobus_unreg; |
| 5688 | } |
| 5689 | |
| 5690 | hclge_rss_init_cfg(hdev); |
| 5691 | ret = hclge_rss_init_hw(hdev); |
| 5692 | if (ret) { |
| 5693 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); |
| 5694 | goto err_mdiobus_unreg; |
| 5695 | } |
| 5696 | |
| 5697 | ret = init_mgr_tbl(hdev); |
| 5698 | if (ret) { |
| 5699 | dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); |
| 5700 | goto err_mdiobus_unreg; |
| 5701 | } |
| 5702 | |
| 5703 | hclge_dcb_ops_set(hdev); |
| 5704 | |
| 5705 | timer_setup(&hdev->service_timer, hclge_service_timer, 0); |
| 5706 | INIT_WORK(&hdev->service_task, hclge_service_task); |
| 5707 | INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); |
| 5708 | INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); |
| 5709 | |
| 5710 | hclge_clear_all_event_cause(hdev); |
| 5711 | |
| 5712 | /* Enable MISC vector(vector0) */ |
| 5713 | hclge_enable_vector(&hdev->misc_vector, true); |
| 5714 | |
| 5715 | hclge_state_init(hdev); |
| 5716 | |
| 5717 | pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); |
| 5718 | return 0; |
| 5719 | |
| 5720 | err_mdiobus_unreg: |
| 5721 | if (hdev->hw.mac.phydev) |
| 5722 | mdiobus_unregister(hdev->hw.mac.mdio_bus); |
| 5723 | err_msi_irq_uninit: |
| 5724 | hclge_misc_irq_uninit(hdev); |
| 5725 | err_msi_uninit: |
| 5726 | pci_free_irq_vectors(pdev); |
| 5727 | err_cmd_uninit: |
| 5728 | hclge_destroy_cmd_queue(&hdev->hw); |
| 5729 | err_pci_uninit: |
| 5730 | pcim_iounmap(pdev, hdev->hw.io_base); |
| 5731 | pci_clear_master(pdev); |
| 5732 | pci_release_regions(pdev); |
| 5733 | pci_disable_device(pdev); |
| 5734 | out: |
| 5735 | return ret; |
| 5736 | } |
| 5737 | |
| 5738 | static void hclge_stats_clear(struct hclge_dev *hdev) |
| 5739 | { |
| 5740 | memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); |
| 5741 | } |
| 5742 | |
| 5743 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) |
| 5744 | { |
| 5745 | struct hclge_dev *hdev = ae_dev->priv; |
| 5746 | struct pci_dev *pdev = ae_dev->pdev; |
| 5747 | int ret; |
| 5748 | |
| 5749 | set_bit(HCLGE_STATE_DOWN, &hdev->state); |
| 5750 | |
| 5751 | hclge_stats_clear(hdev); |
| 5752 | memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); |
| 5753 | |
| 5754 | ret = hclge_cmd_init(hdev); |
| 5755 | if (ret) { |
| 5756 | dev_err(&pdev->dev, "Cmd queue init failed\n"); |
| 5757 | return ret; |
| 5758 | } |
| 5759 | |
| 5760 | ret = hclge_get_cap(hdev); |
| 5761 | if (ret) { |
| 5762 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", |
| 5763 | ret); |
| 5764 | return ret; |
| 5765 | } |
| 5766 | |
| 5767 | ret = hclge_configure(hdev); |
| 5768 | if (ret) { |
| 5769 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); |
| 5770 | return ret; |
| 5771 | } |
| 5772 | |
| 5773 | ret = hclge_map_tqp(hdev); |
| 5774 | if (ret) { |
| 5775 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); |
| 5776 | return ret; |
| 5777 | } |
| 5778 | |
| 5779 | ret = hclge_mac_init(hdev); |
| 5780 | if (ret) { |
| 5781 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); |
| 5782 | return ret; |
| 5783 | } |
| 5784 | |
| 5785 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); |
| 5786 | if (ret) { |
| 5787 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); |
| 5788 | return ret; |
| 5789 | } |
| 5790 | |
| 5791 | ret = hclge_init_vlan_config(hdev); |
| 5792 | if (ret) { |
| 5793 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); |
| 5794 | return ret; |
| 5795 | } |
| 5796 | |
| 5797 | ret = hclge_tm_init_hw(hdev); |
| 5798 | if (ret) { |
| 5799 | dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); |
| 5800 | return ret; |
| 5801 | } |
| 5802 | |
| 5803 | ret = hclge_rss_init_hw(hdev); |
| 5804 | if (ret) { |
| 5805 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); |
| 5806 | return ret; |
| 5807 | } |
| 5808 | |
| 5809 | dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", |
| 5810 | HCLGE_DRIVER_NAME); |
| 5811 | |
| 5812 | return 0; |
| 5813 | } |
| 5814 | |
| 5815 | static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) |
| 5816 | { |
| 5817 | struct hclge_dev *hdev = ae_dev->priv; |
| 5818 | struct hclge_mac *mac = &hdev->hw.mac; |
| 5819 | |
| 5820 | hclge_state_uninit(hdev); |
| 5821 | |
| 5822 | if (mac->phydev) |
| 5823 | mdiobus_unregister(mac->mdio_bus); |
| 5824 | |
| 5825 | /* Disable MISC vector(vector0) */ |
| 5826 | hclge_enable_vector(&hdev->misc_vector, false); |
| 5827 | synchronize_irq(hdev->misc_vector.vector_irq); |
| 5828 | |
| 5829 | hclge_destroy_cmd_queue(&hdev->hw); |
| 5830 | hclge_misc_irq_uninit(hdev); |
| 5831 | hclge_pci_uninit(hdev); |
| 5832 | ae_dev->priv = NULL; |
| 5833 | } |
| 5834 | |
| 5835 | static u32 hclge_get_max_channels(struct hnae3_handle *handle) |
| 5836 | { |
| 5837 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; |
| 5838 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5839 | struct hclge_dev *hdev = vport->back; |
| 5840 | |
| 5841 | return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); |
| 5842 | } |
| 5843 | |
| 5844 | static void hclge_get_channels(struct hnae3_handle *handle, |
| 5845 | struct ethtool_channels *ch) |
| 5846 | { |
| 5847 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5848 | |
| 5849 | ch->max_combined = hclge_get_max_channels(handle); |
| 5850 | ch->other_count = 1; |
| 5851 | ch->max_other = 1; |
| 5852 | ch->combined_count = vport->alloc_tqps; |
| 5853 | } |
| 5854 | |
| 5855 | static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, |
| 5856 | u16 *free_tqps, u16 *max_rss_size) |
| 5857 | { |
| 5858 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5859 | struct hclge_dev *hdev = vport->back; |
| 5860 | u16 temp_tqps = 0; |
| 5861 | int i; |
| 5862 | |
| 5863 | for (i = 0; i < hdev->num_tqps; i++) { |
| 5864 | if (!hdev->htqp[i].alloced) |
| 5865 | temp_tqps++; |
| 5866 | } |
| 5867 | *free_tqps = temp_tqps; |
| 5868 | *max_rss_size = hdev->rss_size_max; |
| 5869 | } |
| 5870 | |
| 5871 | static void hclge_release_tqp(struct hclge_vport *vport) |
| 5872 | { |
| 5873 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; |
| 5874 | struct hclge_dev *hdev = vport->back; |
| 5875 | int i; |
| 5876 | |
| 5877 | for (i = 0; i < kinfo->num_tqps; i++) { |
| 5878 | struct hclge_tqp *tqp = |
| 5879 | container_of(kinfo->tqp[i], struct hclge_tqp, q); |
| 5880 | |
| 5881 | tqp->q.handle = NULL; |
| 5882 | tqp->q.tqp_index = 0; |
| 5883 | tqp->alloced = false; |
| 5884 | } |
| 5885 | |
| 5886 | devm_kfree(&hdev->pdev->dev, kinfo->tqp); |
| 5887 | kinfo->tqp = NULL; |
| 5888 | } |
| 5889 | |
| 5890 | static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) |
| 5891 | { |
| 5892 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 5893 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; |
| 5894 | struct hclge_dev *hdev = vport->back; |
| 5895 | int cur_rss_size = kinfo->rss_size; |
| 5896 | int cur_tqps = kinfo->num_tqps; |
| 5897 | u16 tc_offset[HCLGE_MAX_TC_NUM]; |
| 5898 | u16 tc_valid[HCLGE_MAX_TC_NUM]; |
| 5899 | u16 tc_size[HCLGE_MAX_TC_NUM]; |
| 5900 | u16 roundup_size; |
| 5901 | u32 *rss_indir; |
| 5902 | int ret, i; |
| 5903 | |
| 5904 | hclge_release_tqp(vport); |
| 5905 | |
| 5906 | ret = hclge_knic_setup(vport, new_tqps_num); |
| 5907 | if (ret) { |
| 5908 | dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); |
| 5909 | return ret; |
| 5910 | } |
| 5911 | |
| 5912 | ret = hclge_map_tqp_to_vport(hdev, vport); |
| 5913 | if (ret) { |
| 5914 | dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); |
| 5915 | return ret; |
| 5916 | } |
| 5917 | |
| 5918 | ret = hclge_tm_schd_init(hdev); |
| 5919 | if (ret) { |
| 5920 | dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); |
| 5921 | return ret; |
| 5922 | } |
| 5923 | |
| 5924 | roundup_size = roundup_pow_of_two(kinfo->rss_size); |
| 5925 | roundup_size = ilog2(roundup_size); |
| 5926 | /* Set the RSS TC mode according to the new RSS size */ |
| 5927 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
| 5928 | tc_valid[i] = 0; |
| 5929 | |
| 5930 | if (!(hdev->hw_tc_map & BIT(i))) |
| 5931 | continue; |
| 5932 | |
| 5933 | tc_valid[i] = 1; |
| 5934 | tc_size[i] = roundup_size; |
| 5935 | tc_offset[i] = kinfo->rss_size * i; |
| 5936 | } |
| 5937 | ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); |
| 5938 | if (ret) |
| 5939 | return ret; |
| 5940 | |
| 5941 | /* Reinitializes the rss indirect table according to the new RSS size */ |
| 5942 | rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); |
| 5943 | if (!rss_indir) |
| 5944 | return -ENOMEM; |
| 5945 | |
| 5946 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) |
| 5947 | rss_indir[i] = i % kinfo->rss_size; |
| 5948 | |
| 5949 | ret = hclge_set_rss(handle, rss_indir, NULL, 0); |
| 5950 | if (ret) |
| 5951 | dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", |
| 5952 | ret); |
| 5953 | |
| 5954 | kfree(rss_indir); |
| 5955 | |
| 5956 | if (!ret) |
| 5957 | dev_info(&hdev->pdev->dev, |
| 5958 | "Channels changed, rss_size from %d to %d, tqps from %d to %d", |
| 5959 | cur_rss_size, kinfo->rss_size, |
| 5960 | cur_tqps, kinfo->rss_size * kinfo->num_tc); |
| 5961 | |
| 5962 | return ret; |
| 5963 | } |
| 5964 | |
| 5965 | static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, |
| 5966 | u32 *regs_num_64_bit) |
| 5967 | { |
| 5968 | struct hclge_desc desc; |
| 5969 | u32 total_num; |
| 5970 | int ret; |
| 5971 | |
| 5972 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); |
| 5973 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 5974 | if (ret) { |
| 5975 | dev_err(&hdev->pdev->dev, |
| 5976 | "Query register number cmd failed, ret = %d.\n", ret); |
| 5977 | return ret; |
| 5978 | } |
| 5979 | |
| 5980 | *regs_num_32_bit = le32_to_cpu(desc.data[0]); |
| 5981 | *regs_num_64_bit = le32_to_cpu(desc.data[1]); |
| 5982 | |
| 5983 | total_num = *regs_num_32_bit + *regs_num_64_bit; |
| 5984 | if (!total_num) |
| 5985 | return -EINVAL; |
| 5986 | |
| 5987 | return 0; |
| 5988 | } |
| 5989 | |
| 5990 | static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, |
| 5991 | void *data) |
| 5992 | { |
| 5993 | #define HCLGE_32_BIT_REG_RTN_DATANUM 8 |
| 5994 | |
| 5995 | struct hclge_desc *desc; |
| 5996 | u32 *reg_val = data; |
| 5997 | __le32 *desc_data; |
| 5998 | int cmd_num; |
| 5999 | int i, k, n; |
| 6000 | int ret; |
| 6001 | |
| 6002 | if (regs_num == 0) |
| 6003 | return 0; |
| 6004 | |
| 6005 | cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); |
| 6006 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); |
| 6007 | if (!desc) |
| 6008 | return -ENOMEM; |
| 6009 | |
| 6010 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); |
| 6011 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); |
| 6012 | if (ret) { |
| 6013 | dev_err(&hdev->pdev->dev, |
| 6014 | "Query 32 bit register cmd failed, ret = %d.\n", ret); |
| 6015 | kfree(desc); |
| 6016 | return ret; |
| 6017 | } |
| 6018 | |
| 6019 | for (i = 0; i < cmd_num; i++) { |
| 6020 | if (i == 0) { |
| 6021 | desc_data = (__le32 *)(&desc[i].data[0]); |
| 6022 | n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; |
| 6023 | } else { |
| 6024 | desc_data = (__le32 *)(&desc[i]); |
| 6025 | n = HCLGE_32_BIT_REG_RTN_DATANUM; |
| 6026 | } |
| 6027 | for (k = 0; k < n; k++) { |
| 6028 | *reg_val++ = le32_to_cpu(*desc_data++); |
| 6029 | |
| 6030 | regs_num--; |
| 6031 | if (!regs_num) |
| 6032 | break; |
| 6033 | } |
| 6034 | } |
| 6035 | |
| 6036 | kfree(desc); |
| 6037 | return 0; |
| 6038 | } |
| 6039 | |
| 6040 | static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, |
| 6041 | void *data) |
| 6042 | { |
| 6043 | #define HCLGE_64_BIT_REG_RTN_DATANUM 4 |
| 6044 | |
| 6045 | struct hclge_desc *desc; |
| 6046 | u64 *reg_val = data; |
| 6047 | __le64 *desc_data; |
| 6048 | int cmd_num; |
| 6049 | int i, k, n; |
| 6050 | int ret; |
| 6051 | |
| 6052 | if (regs_num == 0) |
| 6053 | return 0; |
| 6054 | |
| 6055 | cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); |
| 6056 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); |
| 6057 | if (!desc) |
| 6058 | return -ENOMEM; |
| 6059 | |
| 6060 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); |
| 6061 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); |
| 6062 | if (ret) { |
| 6063 | dev_err(&hdev->pdev->dev, |
| 6064 | "Query 64 bit register cmd failed, ret = %d.\n", ret); |
| 6065 | kfree(desc); |
| 6066 | return ret; |
| 6067 | } |
| 6068 | |
| 6069 | for (i = 0; i < cmd_num; i++) { |
| 6070 | if (i == 0) { |
| 6071 | desc_data = (__le64 *)(&desc[i].data[0]); |
| 6072 | n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; |
| 6073 | } else { |
| 6074 | desc_data = (__le64 *)(&desc[i]); |
| 6075 | n = HCLGE_64_BIT_REG_RTN_DATANUM; |
| 6076 | } |
| 6077 | for (k = 0; k < n; k++) { |
| 6078 | *reg_val++ = le64_to_cpu(*desc_data++); |
| 6079 | |
| 6080 | regs_num--; |
| 6081 | if (!regs_num) |
| 6082 | break; |
| 6083 | } |
| 6084 | } |
| 6085 | |
| 6086 | kfree(desc); |
| 6087 | return 0; |
| 6088 | } |
| 6089 | |
| 6090 | static int hclge_get_regs_len(struct hnae3_handle *handle) |
| 6091 | { |
| 6092 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 6093 | struct hclge_dev *hdev = vport->back; |
| 6094 | u32 regs_num_32_bit, regs_num_64_bit; |
| 6095 | int ret; |
| 6096 | |
| 6097 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); |
| 6098 | if (ret) { |
| 6099 | dev_err(&hdev->pdev->dev, |
| 6100 | "Get register number failed, ret = %d.\n", ret); |
| 6101 | return -EOPNOTSUPP; |
| 6102 | } |
| 6103 | |
| 6104 | return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); |
| 6105 | } |
| 6106 | |
| 6107 | static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, |
| 6108 | void *data) |
| 6109 | { |
| 6110 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 6111 | struct hclge_dev *hdev = vport->back; |
| 6112 | u32 regs_num_32_bit, regs_num_64_bit; |
| 6113 | int ret; |
| 6114 | |
| 6115 | *version = hdev->fw_version; |
| 6116 | |
| 6117 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); |
| 6118 | if (ret) { |
| 6119 | dev_err(&hdev->pdev->dev, |
| 6120 | "Get register number failed, ret = %d.\n", ret); |
| 6121 | return; |
| 6122 | } |
| 6123 | |
| 6124 | ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); |
| 6125 | if (ret) { |
| 6126 | dev_err(&hdev->pdev->dev, |
| 6127 | "Get 32 bit register failed, ret = %d.\n", ret); |
| 6128 | return; |
| 6129 | } |
| 6130 | |
| 6131 | data = (u32 *)data + regs_num_32_bit; |
| 6132 | ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, |
| 6133 | data); |
| 6134 | if (ret) |
| 6135 | dev_err(&hdev->pdev->dev, |
| 6136 | "Get 64 bit register failed, ret = %d.\n", ret); |
| 6137 | } |
| 6138 | |
| 6139 | static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) |
| 6140 | { |
| 6141 | struct hclge_set_led_state_cmd *req; |
| 6142 | struct hclge_desc desc; |
| 6143 | int ret; |
| 6144 | |
| 6145 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); |
| 6146 | |
| 6147 | req = (struct hclge_set_led_state_cmd *)desc.data; |
| 6148 | hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, |
| 6149 | HCLGE_LED_LOCATE_STATE_S, locate_led_status); |
| 6150 | |
| 6151 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
| 6152 | if (ret) |
| 6153 | dev_err(&hdev->pdev->dev, |
| 6154 | "Send set led state cmd error, ret =%d\n", ret); |
| 6155 | |
| 6156 | return ret; |
| 6157 | } |
| 6158 | |
| 6159 | enum hclge_led_status { |
| 6160 | HCLGE_LED_OFF, |
| 6161 | HCLGE_LED_ON, |
| 6162 | HCLGE_LED_NO_CHANGE = 0xFF, |
| 6163 | }; |
| 6164 | |
| 6165 | static int hclge_set_led_id(struct hnae3_handle *handle, |
| 6166 | enum ethtool_phys_id_state status) |
| 6167 | { |
| 6168 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 6169 | struct hclge_dev *hdev = vport->back; |
| 6170 | |
| 6171 | switch (status) { |
| 6172 | case ETHTOOL_ID_ACTIVE: |
| 6173 | return hclge_set_led_status(hdev, HCLGE_LED_ON); |
| 6174 | case ETHTOOL_ID_INACTIVE: |
| 6175 | return hclge_set_led_status(hdev, HCLGE_LED_OFF); |
| 6176 | default: |
| 6177 | return -EINVAL; |
| 6178 | } |
| 6179 | } |
| 6180 | |
| 6181 | static void hclge_get_link_mode(struct hnae3_handle *handle, |
| 6182 | unsigned long *supported, |
| 6183 | unsigned long *advertising) |
| 6184 | { |
| 6185 | unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); |
| 6186 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 6187 | struct hclge_dev *hdev = vport->back; |
| 6188 | unsigned int idx = 0; |
| 6189 | |
| 6190 | for (; idx < size; idx++) { |
| 6191 | supported[idx] = hdev->hw.mac.supported[idx]; |
| 6192 | advertising[idx] = hdev->hw.mac.advertising[idx]; |
| 6193 | } |
| 6194 | } |
| 6195 | |
| 6196 | static void hclge_get_port_type(struct hnae3_handle *handle, |
| 6197 | u8 *port_type) |
| 6198 | { |
| 6199 | struct hclge_vport *vport = hclge_get_vport(handle); |
| 6200 | struct hclge_dev *hdev = vport->back; |
| 6201 | u8 media_type = hdev->hw.mac.media_type; |
| 6202 | |
| 6203 | switch (media_type) { |
| 6204 | case HNAE3_MEDIA_TYPE_FIBER: |
| 6205 | *port_type = PORT_FIBRE; |
| 6206 | break; |
| 6207 | case HNAE3_MEDIA_TYPE_COPPER: |
| 6208 | *port_type = PORT_TP; |
| 6209 | break; |
| 6210 | case HNAE3_MEDIA_TYPE_UNKNOWN: |
| 6211 | default: |
| 6212 | *port_type = PORT_OTHER; |
| 6213 | break; |
| 6214 | } |
| 6215 | } |
| 6216 | |
| 6217 | static const struct hnae3_ae_ops hclge_ops = { |
| 6218 | .init_ae_dev = hclge_init_ae_dev, |
| 6219 | .uninit_ae_dev = hclge_uninit_ae_dev, |
| 6220 | .init_client_instance = hclge_init_client_instance, |
| 6221 | .uninit_client_instance = hclge_uninit_client_instance, |
| 6222 | .map_ring_to_vector = hclge_map_ring_to_vector, |
| 6223 | .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, |
| 6224 | .get_vector = hclge_get_vector, |
| 6225 | .put_vector = hclge_put_vector, |
| 6226 | .set_promisc_mode = hclge_set_promisc_mode, |
| 6227 | .set_loopback = hclge_set_loopback, |
| 6228 | .start = hclge_ae_start, |
| 6229 | .stop = hclge_ae_stop, |
| 6230 | .get_status = hclge_get_status, |
| 6231 | .get_ksettings_an_result = hclge_get_ksettings_an_result, |
| 6232 | .update_speed_duplex_h = hclge_update_speed_duplex_h, |
| 6233 | .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, |
| 6234 | .get_media_type = hclge_get_media_type, |
| 6235 | .get_rss_key_size = hclge_get_rss_key_size, |
| 6236 | .get_rss_indir_size = hclge_get_rss_indir_size, |
| 6237 | .get_rss = hclge_get_rss, |
| 6238 | .set_rss = hclge_set_rss, |
| 6239 | .set_rss_tuple = hclge_set_rss_tuple, |
| 6240 | .get_rss_tuple = hclge_get_rss_tuple, |
| 6241 | .get_tc_size = hclge_get_tc_size, |
| 6242 | .get_mac_addr = hclge_get_mac_addr, |
| 6243 | .set_mac_addr = hclge_set_mac_addr, |
| 6244 | .add_uc_addr = hclge_add_uc_addr, |
| 6245 | .rm_uc_addr = hclge_rm_uc_addr, |
| 6246 | .add_mc_addr = hclge_add_mc_addr, |
| 6247 | .rm_mc_addr = hclge_rm_mc_addr, |
| 6248 | .update_mta_status = hclge_update_mta_status, |
| 6249 | .set_autoneg = hclge_set_autoneg, |
| 6250 | .get_autoneg = hclge_get_autoneg, |
| 6251 | .get_pauseparam = hclge_get_pauseparam, |
| 6252 | .set_pauseparam = hclge_set_pauseparam, |
| 6253 | .set_mtu = hclge_set_mtu, |
| 6254 | .reset_queue = hclge_reset_tqp, |
| 6255 | .get_stats = hclge_get_stats, |
| 6256 | .update_stats = hclge_update_stats, |
| 6257 | .get_strings = hclge_get_strings, |
| 6258 | .get_sset_count = hclge_get_sset_count, |
| 6259 | .get_fw_version = hclge_get_fw_version, |
| 6260 | .get_mdix_mode = hclge_get_mdix_mode, |
| 6261 | .enable_vlan_filter = hclge_enable_vlan_filter, |
| 6262 | .set_vlan_filter = hclge_set_vlan_filter, |
| 6263 | .set_vf_vlan_filter = hclge_set_vf_vlan_filter, |
| 6264 | .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, |
| 6265 | .reset_event = hclge_reset_event, |
| 6266 | .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, |
| 6267 | .set_channels = hclge_set_channels, |
| 6268 | .get_channels = hclge_get_channels, |
| 6269 | .get_flowctrl_adv = hclge_get_flowctrl_adv, |
| 6270 | .get_regs_len = hclge_get_regs_len, |
| 6271 | .get_regs = hclge_get_regs, |
| 6272 | .set_led_id = hclge_set_led_id, |
| 6273 | .get_link_mode = hclge_get_link_mode, |
| 6274 | .get_port_type = hclge_get_port_type, |
| 6275 | }; |
| 6276 | |
| 6277 | static struct hnae3_ae_algo ae_algo = { |
| 6278 | .ops = &hclge_ops, |
| 6279 | .pdev_id_table = ae_algo_pci_tbl, |
| 6280 | }; |
| 6281 | |
| 6282 | static int hclge_init(void) |
| 6283 | { |
| 6284 | pr_info("%s is initializing\n", HCLGE_NAME); |
| 6285 | |
| 6286 | hnae3_register_ae_algo(&ae_algo); |
| 6287 | |
| 6288 | return 0; |
| 6289 | } |
| 6290 | |
| 6291 | static void hclge_exit(void) |
| 6292 | { |
| 6293 | hnae3_unregister_ae_algo(&ae_algo); |
| 6294 | } |
| 6295 | module_init(hclge_init); |
| 6296 | module_exit(hclge_exit); |
| 6297 | |
| 6298 | MODULE_LICENSE("GPL"); |
| 6299 | MODULE_AUTHOR("Huawei Tech. Co., Ltd."); |
| 6300 | MODULE_DESCRIPTION("HCLGE Driver"); |
| 6301 | MODULE_VERSION(HCLGE_MOD_VERSION); |