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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / net / ethernet / freescale / gianfar.c
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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* drivers/net/ethernet/freescale/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 *
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
15 *
16 * Gianfar: AKA Lambda Draconis, "Dragon"
17 * RA 11 31 24.2
18 * Dec +69 19 52
19 * V 3.84
20 * B-V +1.62
21 *
22 * Theory of operation
23 *
24 * The driver is initialized through of_device. Configuration information
25 * is therefore conveyed through an OF-style device tree.
26 *
27 * The Gianfar Ethernet Controller uses a ring of buffer
28 * descriptors. The beginning is indicated by a register
29 * pointing to the physical address of the start of the ring.
30 * The end is determined by a "wrap" bit being set in the
31 * last descriptor of the ring.
32 *
33 * When a packet is received, the RXF bit in the
34 * IEVENT register is set, triggering an interrupt when the
35 * corresponding bit in the IMASK register is also set (if
36 * interrupt coalescing is active, then the interrupt may not
37 * happen immediately, but will wait until either a set number
38 * of frames or amount of time have passed). In NAPI, the
39 * interrupt handler will signal there is work to be done, and
40 * exit. This method will start at the last known empty
41 * descriptor, and process every subsequent descriptor until there
42 * are none left with data (NAPI will stop after a set number of
43 * packets to give time to other tasks, but will eventually
44 * process all the packets). The data arrives inside a
45 * pre-allocated skb, and so after the skb is passed up to the
46 * stack, a new skb must be allocated, and the address field in
47 * the buffer descriptor must be updated to indicate this new
48 * skb.
49 *
50 * When the kernel requests that a packet be transmitted, the
51 * driver starts where it left off last time, and points the
52 * descriptor at the buffer which was passed in. The driver
53 * then informs the DMA engine that there are packets ready to
54 * be transmitted. Once the controller is finished transmitting
55 * the packet, an interrupt may be triggered (under the same
56 * conditions as for reception, but depending on the TXF bit).
57 * The driver then cleans up the buffer.
58 */
59
60#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61
62#include <linux/kernel.h>
63#include <linux/platform_device.h>
64#include <linux/string.h>
65#include <linux/errno.h>
66#include <linux/unistd.h>
67#include <linux/slab.h>
68#include <linux/interrupt.h>
69#include <linux/delay.h>
70#include <linux/netdevice.h>
71#include <linux/etherdevice.h>
72#include <linux/skbuff.h>
73#include <linux/if_vlan.h>
74#include <linux/spinlock.h>
75#include <linux/mm.h>
76#include <linux/of_address.h>
77#include <linux/of_irq.h>
78#include <linux/of_mdio.h>
79#include <linux/ip.h>
80#include <linux/tcp.h>
81#include <linux/udp.h>
82#include <linux/in.h>
83#include <linux/net_tstamp.h>
84
85#include <asm/io.h>
86#ifdef CONFIG_PPC
87#include <asm/reg.h>
88#include <asm/mpc85xx.h>
89#endif
90#include <asm/irq.h>
91#include <linux/uaccess.h>
92#include <linux/module.h>
93#include <linux/dma-mapping.h>
94#include <linux/crc32.h>
95#include <linux/mii.h>
96#include <linux/phy.h>
97#include <linux/phy_fixed.h>
98#include <linux/of.h>
99#include <linux/of_net.h>
100
101#include "gianfar.h"
102
103#define TX_TIMEOUT (5*HZ)
104
105MODULE_AUTHOR("Freescale Semiconductor, Inc");
106MODULE_DESCRIPTION("Gianfar Ethernet Driver");
107MODULE_LICENSE("GPL");
108
109static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
110 dma_addr_t buf)
111{
112 u32 lstatus;
113
114 bdp->bufPtr = cpu_to_be32(buf);
115
116 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
117 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
118 lstatus |= BD_LFLAG(RXBD_WRAP);
119
120 gfar_wmb();
121
122 bdp->lstatus = cpu_to_be32(lstatus);
123}
124
125static void gfar_init_tx_rx_base(struct gfar_private *priv)
126{
127 struct gfar __iomem *regs = priv->gfargrp[0].regs;
128 u32 __iomem *baddr;
129 int i;
130
131 baddr = &regs->tbase0;
132 for (i = 0; i < priv->num_tx_queues; i++) {
133 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
134 baddr += 2;
135 }
136
137 baddr = &regs->rbase0;
138 for (i = 0; i < priv->num_rx_queues; i++) {
139 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
140 baddr += 2;
141 }
142}
143
144static void gfar_init_rqprm(struct gfar_private *priv)
145{
146 struct gfar __iomem *regs = priv->gfargrp[0].regs;
147 u32 __iomem *baddr;
148 int i;
149
150 baddr = &regs->rqprm0;
151 for (i = 0; i < priv->num_rx_queues; i++) {
152 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
153 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
154 baddr++;
155 }
156}
157
158static void gfar_rx_offload_en(struct gfar_private *priv)
159{
160 /* set this when rx hw offload (TOE) functions are being used */
161 priv->uses_rxfcb = 0;
162
163 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
164 priv->uses_rxfcb = 1;
165
166 if (priv->hwts_rx_en || priv->rx_filer_enable)
167 priv->uses_rxfcb = 1;
168}
169
170static void gfar_mac_rx_config(struct gfar_private *priv)
171{
172 struct gfar __iomem *regs = priv->gfargrp[0].regs;
173 u32 rctrl = 0;
174
175 if (priv->rx_filer_enable) {
176 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
177 /* Program the RIR0 reg with the required distribution */
178 gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
179 }
180
181 /* Restore PROMISC mode */
182 if (priv->ndev->flags & IFF_PROMISC)
183 rctrl |= RCTRL_PROM;
184
185 if (priv->ndev->features & NETIF_F_RXCSUM)
186 rctrl |= RCTRL_CHECKSUMMING;
187
188 if (priv->extended_hash)
189 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
190
191 if (priv->padding) {
192 rctrl &= ~RCTRL_PAL_MASK;
193 rctrl |= RCTRL_PADDING(priv->padding);
194 }
195
196 /* Enable HW time stamping if requested from user space */
197 if (priv->hwts_rx_en)
198 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
199
200 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
201 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
202
203 /* Clear the LFC bit */
204 gfar_write(&regs->rctrl, rctrl);
205 /* Init flow control threshold values */
206 gfar_init_rqprm(priv);
207 gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
208 rctrl |= RCTRL_LFC;
209
210 /* Init rctrl based on our settings */
211 gfar_write(&regs->rctrl, rctrl);
212}
213
214static void gfar_mac_tx_config(struct gfar_private *priv)
215{
216 struct gfar __iomem *regs = priv->gfargrp[0].regs;
217 u32 tctrl = 0;
218
219 if (priv->ndev->features & NETIF_F_IP_CSUM)
220 tctrl |= TCTRL_INIT_CSUM;
221
222 if (priv->prio_sched_en)
223 tctrl |= TCTRL_TXSCHED_PRIO;
224 else {
225 tctrl |= TCTRL_TXSCHED_WRRS;
226 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
227 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
228 }
229
230 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
231 tctrl |= TCTRL_VLINS;
232
233 gfar_write(&regs->tctrl, tctrl);
234}
235
236static void gfar_configure_coalescing(struct gfar_private *priv,
237 unsigned long tx_mask, unsigned long rx_mask)
238{
239 struct gfar __iomem *regs = priv->gfargrp[0].regs;
240 u32 __iomem *baddr;
241
242 if (priv->mode == MQ_MG_MODE) {
243 int i = 0;
244
245 baddr = &regs->txic0;
246 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
247 gfar_write(baddr + i, 0);
248 if (likely(priv->tx_queue[i]->txcoalescing))
249 gfar_write(baddr + i, priv->tx_queue[i]->txic);
250 }
251
252 baddr = &regs->rxic0;
253 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
254 gfar_write(baddr + i, 0);
255 if (likely(priv->rx_queue[i]->rxcoalescing))
256 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
257 }
258 } else {
259 /* Backward compatible case -- even if we enable
260 * multiple queues, there's only single reg to program
261 */
262 gfar_write(&regs->txic, 0);
263 if (likely(priv->tx_queue[0]->txcoalescing))
264 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
265
266 gfar_write(&regs->rxic, 0);
267 if (unlikely(priv->rx_queue[0]->rxcoalescing))
268 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
269 }
270}
271
272static void gfar_configure_coalescing_all(struct gfar_private *priv)
273{
274 gfar_configure_coalescing(priv, 0xFF, 0xFF);
275}
276
277static void gfar_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
278{
279 struct gfar_private *priv = netdev_priv(dev);
280 int i;
281
282 for (i = 0; i < priv->num_rx_queues; i++) {
283 stats->rx_packets += priv->rx_queue[i]->stats.rx_packets;
284 stats->rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
285 stats->rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
286 }
287
288 for (i = 0; i < priv->num_tx_queues; i++) {
289 stats->tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
290 stats->tx_packets += priv->tx_queue[i]->stats.tx_packets;
291 }
292
293 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
294 struct rmon_mib __iomem *rmon = &priv->gfargrp[0].regs->rmon;
295 unsigned long flags;
296 u32 rdrp, car, car_before;
297 u64 rdrp_offset;
298
299 spin_lock_irqsave(&priv->rmon_overflow.lock, flags);
300 car = gfar_read(&rmon->car1) & CAR1_C1RDR;
301 do {
302 car_before = car;
303 rdrp = gfar_read(&rmon->rdrp);
304 car = gfar_read(&rmon->car1) & CAR1_C1RDR;
305 } while (car != car_before);
306 if (car) {
307 priv->rmon_overflow.rdrp++;
308 gfar_write(&rmon->car1, car);
309 }
310 rdrp_offset = priv->rmon_overflow.rdrp;
311 spin_unlock_irqrestore(&priv->rmon_overflow.lock, flags);
312
313 stats->rx_missed_errors = rdrp + (rdrp_offset << 16);
314 }
315}
316
317/* Set the appropriate hash bit for the given addr */
318/* The algorithm works like so:
319 * 1) Take the Destination Address (ie the multicast address), and
320 * do a CRC on it (little endian), and reverse the bits of the
321 * result.
322 * 2) Use the 8 most significant bits as a hash into a 256-entry
323 * table. The table is controlled through 8 32-bit registers:
324 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
325 * gaddr7. This means that the 3 most significant bits in the
326 * hash index which gaddr register to use, and the 5 other bits
327 * indicate which bit (assuming an IBM numbering scheme, which
328 * for PowerPC (tm) is usually the case) in the register holds
329 * the entry.
330 */
331static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
332{
333 u32 tempval;
334 struct gfar_private *priv = netdev_priv(dev);
335 u32 result = ether_crc(ETH_ALEN, addr);
336 int width = priv->hash_width;
337 u8 whichbit = (result >> (32 - width)) & 0x1f;
338 u8 whichreg = result >> (32 - width + 5);
339 u32 value = (1 << (31-whichbit));
340
341 tempval = gfar_read(priv->hash_regs[whichreg]);
342 tempval |= value;
343 gfar_write(priv->hash_regs[whichreg], tempval);
344}
345
346/* There are multiple MAC Address register pairs on some controllers
347 * This function sets the numth pair to a given address
348 */
349static void gfar_set_mac_for_addr(struct net_device *dev, int num,
350 const u8 *addr)
351{
352 struct gfar_private *priv = netdev_priv(dev);
353 struct gfar __iomem *regs = priv->gfargrp[0].regs;
354 u32 tempval;
355 u32 __iomem *macptr = &regs->macstnaddr1;
356
357 macptr += num*2;
358
359 /* For a station address of 0x12345678ABCD in transmission
360 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
361 * MACnADDR2 is set to 0x34120000.
362 */
363 tempval = (addr[5] << 24) | (addr[4] << 16) |
364 (addr[3] << 8) | addr[2];
365
366 gfar_write(macptr, tempval);
367
368 tempval = (addr[1] << 24) | (addr[0] << 16);
369
370 gfar_write(macptr+1, tempval);
371}
372
373static int gfar_set_mac_addr(struct net_device *dev, void *p)
374{
375 int ret;
376
377 ret = eth_mac_addr(dev, p);
378 if (ret)
379 return ret;
380
381 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
382
383 return 0;
384}
385
386static void gfar_ints_disable(struct gfar_private *priv)
387{
388 int i;
389 for (i = 0; i < priv->num_grps; i++) {
390 struct gfar __iomem *regs = priv->gfargrp[i].regs;
391 /* Clear IEVENT */
392 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
393
394 /* Initialize IMASK */
395 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
396 }
397}
398
399static void gfar_ints_enable(struct gfar_private *priv)
400{
401 int i;
402 for (i = 0; i < priv->num_grps; i++) {
403 struct gfar __iomem *regs = priv->gfargrp[i].regs;
404 /* Unmask the interrupts we look for */
405 gfar_write(&regs->imask,
406 IMASK_DEFAULT | priv->rmon_overflow.imask);
407 }
408}
409
410static int gfar_alloc_tx_queues(struct gfar_private *priv)
411{
412 int i;
413
414 for (i = 0; i < priv->num_tx_queues; i++) {
415 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
416 GFP_KERNEL);
417 if (!priv->tx_queue[i])
418 return -ENOMEM;
419
420 priv->tx_queue[i]->tx_skbuff = NULL;
421 priv->tx_queue[i]->qindex = i;
422 priv->tx_queue[i]->dev = priv->ndev;
423 spin_lock_init(&(priv->tx_queue[i]->txlock));
424 }
425 return 0;
426}
427
428static int gfar_alloc_rx_queues(struct gfar_private *priv)
429{
430 int i;
431
432 for (i = 0; i < priv->num_rx_queues; i++) {
433 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
434 GFP_KERNEL);
435 if (!priv->rx_queue[i])
436 return -ENOMEM;
437
438 priv->rx_queue[i]->qindex = i;
439 priv->rx_queue[i]->ndev = priv->ndev;
440 }
441 return 0;
442}
443
444static void gfar_free_tx_queues(struct gfar_private *priv)
445{
446 int i;
447
448 for (i = 0; i < priv->num_tx_queues; i++)
449 kfree(priv->tx_queue[i]);
450}
451
452static void gfar_free_rx_queues(struct gfar_private *priv)
453{
454 int i;
455
456 for (i = 0; i < priv->num_rx_queues; i++)
457 kfree(priv->rx_queue[i]);
458}
459
460static void unmap_group_regs(struct gfar_private *priv)
461{
462 int i;
463
464 for (i = 0; i < MAXGROUPS; i++)
465 if (priv->gfargrp[i].regs)
466 iounmap(priv->gfargrp[i].regs);
467}
468
469static void free_gfar_dev(struct gfar_private *priv)
470{
471 int i, j;
472
473 for (i = 0; i < priv->num_grps; i++)
474 for (j = 0; j < GFAR_NUM_IRQS; j++) {
475 kfree(priv->gfargrp[i].irqinfo[j]);
476 priv->gfargrp[i].irqinfo[j] = NULL;
477 }
478
479 free_netdev(priv->ndev);
480}
481
482static void disable_napi(struct gfar_private *priv)
483{
484 int i;
485
486 for (i = 0; i < priv->num_grps; i++) {
487 napi_disable(&priv->gfargrp[i].napi_rx);
488 napi_disable(&priv->gfargrp[i].napi_tx);
489 }
490}
491
492static void enable_napi(struct gfar_private *priv)
493{
494 int i;
495
496 for (i = 0; i < priv->num_grps; i++) {
497 napi_enable(&priv->gfargrp[i].napi_rx);
498 napi_enable(&priv->gfargrp[i].napi_tx);
499 }
500}
501
502static int gfar_parse_group(struct device_node *np,
503 struct gfar_private *priv, const char *model)
504{
505 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
506 int i;
507
508 for (i = 0; i < GFAR_NUM_IRQS; i++) {
509 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
510 GFP_KERNEL);
511 if (!grp->irqinfo[i])
512 return -ENOMEM;
513 }
514
515 grp->regs = of_iomap(np, 0);
516 if (!grp->regs)
517 return -ENOMEM;
518
519 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
520
521 /* If we aren't the FEC we have multiple interrupts */
522 if (model && strcasecmp(model, "FEC")) {
523 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
524 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
525 if (!gfar_irq(grp, TX)->irq ||
526 !gfar_irq(grp, RX)->irq ||
527 !gfar_irq(grp, ER)->irq)
528 return -EINVAL;
529 }
530
531 grp->priv = priv;
532 spin_lock_init(&grp->grplock);
533 if (priv->mode == MQ_MG_MODE) {
534 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
535 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
536 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
537 } else {
538 grp->rx_bit_map = 0xFF;
539 grp->tx_bit_map = 0xFF;
540 }
541
542 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
543 * right to left, so we need to revert the 8 bits to get the q index
544 */
545 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
546 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
547
548 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
549 * also assign queues to groups
550 */
551 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
552 if (!grp->rx_queue)
553 grp->rx_queue = priv->rx_queue[i];
554 grp->num_rx_queues++;
555 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
556 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
557 priv->rx_queue[i]->grp = grp;
558 }
559
560 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
561 if (!grp->tx_queue)
562 grp->tx_queue = priv->tx_queue[i];
563 grp->num_tx_queues++;
564 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
565 priv->tqueue |= (TQUEUE_EN0 >> i);
566 priv->tx_queue[i]->grp = grp;
567 }
568
569 priv->num_grps++;
570
571 return 0;
572}
573
574static int gfar_of_group_count(struct device_node *np)
575{
576 struct device_node *child;
577 int num = 0;
578
579 for_each_available_child_of_node(np, child)
580 if (of_node_name_eq(child, "queue-group"))
581 num++;
582
583 return num;
584}
585
586/* Reads the controller's registers to determine what interface
587 * connects it to the PHY.
588 */
589static phy_interface_t gfar_get_interface(struct net_device *dev)
590{
591 struct gfar_private *priv = netdev_priv(dev);
592 struct gfar __iomem *regs = priv->gfargrp[0].regs;
593 u32 ecntrl;
594
595 ecntrl = gfar_read(&regs->ecntrl);
596
597 if (ecntrl & ECNTRL_SGMII_MODE)
598 return PHY_INTERFACE_MODE_SGMII;
599
600 if (ecntrl & ECNTRL_TBI_MODE) {
601 if (ecntrl & ECNTRL_REDUCED_MODE)
602 return PHY_INTERFACE_MODE_RTBI;
603 else
604 return PHY_INTERFACE_MODE_TBI;
605 }
606
607 if (ecntrl & ECNTRL_REDUCED_MODE) {
608 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
609 return PHY_INTERFACE_MODE_RMII;
610 }
611 else {
612 phy_interface_t interface = priv->interface;
613
614 /* This isn't autodetected right now, so it must
615 * be set by the device tree or platform code.
616 */
617 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
618 return PHY_INTERFACE_MODE_RGMII_ID;
619
620 return PHY_INTERFACE_MODE_RGMII;
621 }
622 }
623
624 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
625 return PHY_INTERFACE_MODE_GMII;
626
627 return PHY_INTERFACE_MODE_MII;
628}
629
630static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
631{
632 const char *model;
633 int err = 0, i;
634 phy_interface_t interface;
635 struct net_device *dev = NULL;
636 struct gfar_private *priv = NULL;
637 struct device_node *np = ofdev->dev.of_node;
638 struct device_node *child = NULL;
639 u32 stash_len = 0;
640 u32 stash_idx = 0;
641 unsigned int num_tx_qs, num_rx_qs;
642 unsigned short mode;
643
644 if (!np)
645 return -ENODEV;
646
647 if (of_device_is_compatible(np, "fsl,etsec2"))
648 mode = MQ_MG_MODE;
649 else
650 mode = SQ_SG_MODE;
651
652 if (mode == SQ_SG_MODE) {
653 num_tx_qs = 1;
654 num_rx_qs = 1;
655 } else { /* MQ_MG_MODE */
656 /* get the actual number of supported groups */
657 unsigned int num_grps = gfar_of_group_count(np);
658
659 if (num_grps == 0 || num_grps > MAXGROUPS) {
660 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
661 num_grps);
662 pr_err("Cannot do alloc_etherdev, aborting\n");
663 return -EINVAL;
664 }
665
666 num_tx_qs = num_grps; /* one txq per int group */
667 num_rx_qs = num_grps; /* one rxq per int group */
668 }
669
670 if (num_tx_qs > MAX_TX_QS) {
671 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
672 num_tx_qs, MAX_TX_QS);
673 pr_err("Cannot do alloc_etherdev, aborting\n");
674 return -EINVAL;
675 }
676
677 if (num_rx_qs > MAX_RX_QS) {
678 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
679 num_rx_qs, MAX_RX_QS);
680 pr_err("Cannot do alloc_etherdev, aborting\n");
681 return -EINVAL;
682 }
683
684 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
685 dev = *pdev;
686 if (NULL == dev)
687 return -ENOMEM;
688
689 priv = netdev_priv(dev);
690 priv->ndev = dev;
691
692 priv->mode = mode;
693
694 priv->num_tx_queues = num_tx_qs;
695 netif_set_real_num_rx_queues(dev, num_rx_qs);
696 priv->num_rx_queues = num_rx_qs;
697
698 err = gfar_alloc_tx_queues(priv);
699 if (err)
700 goto tx_alloc_failed;
701
702 err = gfar_alloc_rx_queues(priv);
703 if (err)
704 goto rx_alloc_failed;
705
706 err = of_property_read_string(np, "model", &model);
707 if (err) {
708 pr_err("Device model property missing, aborting\n");
709 goto rx_alloc_failed;
710 }
711
712 /* Init Rx queue filer rule set linked list */
713 INIT_LIST_HEAD(&priv->rx_list.list);
714 priv->rx_list.count = 0;
715 mutex_init(&priv->rx_queue_access);
716
717 for (i = 0; i < MAXGROUPS; i++)
718 priv->gfargrp[i].regs = NULL;
719
720 /* Parse and initialize group specific information */
721 if (priv->mode == MQ_MG_MODE) {
722 for_each_available_child_of_node(np, child) {
723 if (!of_node_name_eq(child, "queue-group"))
724 continue;
725
726 err = gfar_parse_group(child, priv, model);
727 if (err) {
728 of_node_put(child);
729 goto err_grp_init;
730 }
731 }
732 } else { /* SQ_SG_MODE */
733 err = gfar_parse_group(np, priv, model);
734 if (err)
735 goto err_grp_init;
736 }
737
738 if (of_property_read_bool(np, "bd-stash")) {
739 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
740 priv->bd_stash_en = 1;
741 }
742
743 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
744
745 if (err == 0)
746 priv->rx_stash_size = stash_len;
747
748 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
749
750 if (err == 0)
751 priv->rx_stash_index = stash_idx;
752
753 if (stash_len || stash_idx)
754 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
755
756 err = of_get_ethdev_address(np, dev);
757 if (err == -EPROBE_DEFER)
758 goto err_grp_init;
759 if (err) {
760 eth_hw_addr_random(dev);
761 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr);
762 }
763
764 if (model && !strcasecmp(model, "TSEC"))
765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
766 FSL_GIANFAR_DEV_HAS_COALESCE |
767 FSL_GIANFAR_DEV_HAS_RMON |
768 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
769
770 if (model && !strcasecmp(model, "eTSEC"))
771 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
772 FSL_GIANFAR_DEV_HAS_COALESCE |
773 FSL_GIANFAR_DEV_HAS_RMON |
774 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
775 FSL_GIANFAR_DEV_HAS_CSUM |
776 FSL_GIANFAR_DEV_HAS_VLAN |
777 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
778 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
779 FSL_GIANFAR_DEV_HAS_TIMER |
780 FSL_GIANFAR_DEV_HAS_RX_FILER;
781
782 /* Use PHY connection type from the DT node if one is specified there.
783 * rgmii-id really needs to be specified. Other types can be
784 * detected by hardware
785 */
786 err = of_get_phy_mode(np, &interface);
787 if (!err)
788 priv->interface = interface;
789 else
790 priv->interface = gfar_get_interface(dev);
791
792 if (of_property_read_bool(np, "fsl,magic-packet"))
793 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
794
795 if (of_property_read_bool(np, "fsl,wake-on-filer"))
796 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
797
798 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
799
800 /* In the case of a fixed PHY, the DT node associated
801 * to the PHY is the Ethernet MAC DT node.
802 */
803 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
804 err = of_phy_register_fixed_link(np);
805 if (err)
806 goto err_grp_init;
807
808 priv->phy_node = of_node_get(np);
809 }
810
811 /* Find the TBI PHY. If it's not there, we don't support SGMII */
812 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
813
814 return 0;
815
816err_grp_init:
817 unmap_group_regs(priv);
818rx_alloc_failed:
819 gfar_free_rx_queues(priv);
820tx_alloc_failed:
821 gfar_free_tx_queues(priv);
822 free_gfar_dev(priv);
823 return err;
824}
825
826static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
827 u32 class)
828{
829 u32 rqfpr = FPR_FILER_MASK;
830 u32 rqfcr = 0x0;
831
832 rqfar--;
833 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
834 priv->ftp_rqfpr[rqfar] = rqfpr;
835 priv->ftp_rqfcr[rqfar] = rqfcr;
836 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
837
838 rqfar--;
839 rqfcr = RQFCR_CMP_NOMATCH;
840 priv->ftp_rqfpr[rqfar] = rqfpr;
841 priv->ftp_rqfcr[rqfar] = rqfcr;
842 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
843
844 rqfar--;
845 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
846 rqfpr = class;
847 priv->ftp_rqfcr[rqfar] = rqfcr;
848 priv->ftp_rqfpr[rqfar] = rqfpr;
849 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
850
851 rqfar--;
852 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
853 rqfpr = class;
854 priv->ftp_rqfcr[rqfar] = rqfcr;
855 priv->ftp_rqfpr[rqfar] = rqfpr;
856 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
857
858 return rqfar;
859}
860
861static void gfar_init_filer_table(struct gfar_private *priv)
862{
863 int i = 0x0;
864 u32 rqfar = MAX_FILER_IDX;
865 u32 rqfcr = 0x0;
866 u32 rqfpr = FPR_FILER_MASK;
867
868 /* Default rule */
869 rqfcr = RQFCR_CMP_MATCH;
870 priv->ftp_rqfcr[rqfar] = rqfcr;
871 priv->ftp_rqfpr[rqfar] = rqfpr;
872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
873
874 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
875 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
876 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
877 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
878 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
879 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
880
881 /* cur_filer_idx indicated the first non-masked rule */
882 priv->cur_filer_idx = rqfar;
883
884 /* Rest are masked rules */
885 rqfcr = RQFCR_CMP_NOMATCH;
886 for (i = 0; i < rqfar; i++) {
887 priv->ftp_rqfcr[i] = rqfcr;
888 priv->ftp_rqfpr[i] = rqfpr;
889 gfar_write_filer(priv, i, rqfcr, rqfpr);
890 }
891}
892
893#ifdef CONFIG_PPC
894static void __gfar_detect_errata_83xx(struct gfar_private *priv)
895{
896 unsigned int pvr = mfspr(SPRN_PVR);
897 unsigned int svr = mfspr(SPRN_SVR);
898 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
899 unsigned int rev = svr & 0xffff;
900
901 /* MPC8313 Rev 2.0 and higher; All MPC837x */
902 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
903 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
904 priv->errata |= GFAR_ERRATA_74;
905
906 /* MPC8313 and MPC837x all rev */
907 if ((pvr == 0x80850010 && mod == 0x80b0) ||
908 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
909 priv->errata |= GFAR_ERRATA_76;
910
911 /* MPC8313 Rev < 2.0 */
912 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
913 priv->errata |= GFAR_ERRATA_12;
914}
915
916static void __gfar_detect_errata_85xx(struct gfar_private *priv)
917{
918 unsigned int svr = mfspr(SPRN_SVR);
919
920 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
921 priv->errata |= GFAR_ERRATA_12;
922 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
923 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
924 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
925 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
926 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
927}
928#endif
929
930static void gfar_detect_errata(struct gfar_private *priv)
931{
932 struct device *dev = &priv->ofdev->dev;
933
934 /* no plans to fix */
935 priv->errata |= GFAR_ERRATA_A002;
936
937#ifdef CONFIG_PPC
938 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
939 __gfar_detect_errata_85xx(priv);
940 else /* non-mpc85xx parts, i.e. e300 core based */
941 __gfar_detect_errata_83xx(priv);
942#endif
943
944 if (priv->errata)
945 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
946 priv->errata);
947}
948
949static void gfar_init_addr_hash_table(struct gfar_private *priv)
950{
951 struct gfar __iomem *regs = priv->gfargrp[0].regs;
952
953 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
954 priv->extended_hash = 1;
955 priv->hash_width = 9;
956
957 priv->hash_regs[0] = &regs->igaddr0;
958 priv->hash_regs[1] = &regs->igaddr1;
959 priv->hash_regs[2] = &regs->igaddr2;
960 priv->hash_regs[3] = &regs->igaddr3;
961 priv->hash_regs[4] = &regs->igaddr4;
962 priv->hash_regs[5] = &regs->igaddr5;
963 priv->hash_regs[6] = &regs->igaddr6;
964 priv->hash_regs[7] = &regs->igaddr7;
965 priv->hash_regs[8] = &regs->gaddr0;
966 priv->hash_regs[9] = &regs->gaddr1;
967 priv->hash_regs[10] = &regs->gaddr2;
968 priv->hash_regs[11] = &regs->gaddr3;
969 priv->hash_regs[12] = &regs->gaddr4;
970 priv->hash_regs[13] = &regs->gaddr5;
971 priv->hash_regs[14] = &regs->gaddr6;
972 priv->hash_regs[15] = &regs->gaddr7;
973
974 } else {
975 priv->extended_hash = 0;
976 priv->hash_width = 8;
977
978 priv->hash_regs[0] = &regs->gaddr0;
979 priv->hash_regs[1] = &regs->gaddr1;
980 priv->hash_regs[2] = &regs->gaddr2;
981 priv->hash_regs[3] = &regs->gaddr3;
982 priv->hash_regs[4] = &regs->gaddr4;
983 priv->hash_regs[5] = &regs->gaddr5;
984 priv->hash_regs[6] = &regs->gaddr6;
985 priv->hash_regs[7] = &regs->gaddr7;
986 }
987}
988
989static int __gfar_is_rx_idle(struct gfar_private *priv)
990{
991 u32 res;
992
993 /* Normaly TSEC should not hang on GRS commands, so we should
994 * actually wait for IEVENT_GRSC flag.
995 */
996 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
997 return 0;
998
999 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1000 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1001 * and the Rx can be safely reset.
1002 */
1003 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1004 res &= 0x7f807f80;
1005 if ((res & 0xffff) == (res >> 16))
1006 return 1;
1007
1008 return 0;
1009}
1010
1011/* Halt the receive and transmit queues */
1012static void gfar_halt_nodisable(struct gfar_private *priv)
1013{
1014 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1015 u32 tempval;
1016 unsigned int timeout;
1017 int stopped;
1018
1019 gfar_ints_disable(priv);
1020
1021 if (gfar_is_dma_stopped(priv))
1022 return;
1023
1024 /* Stop the DMA, and wait for it to stop */
1025 tempval = gfar_read(&regs->dmactrl);
1026 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1027 gfar_write(&regs->dmactrl, tempval);
1028
1029retry:
1030 timeout = 1000;
1031 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1032 cpu_relax();
1033 timeout--;
1034 }
1035
1036 if (!timeout)
1037 stopped = gfar_is_dma_stopped(priv);
1038
1039 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1040 !__gfar_is_rx_idle(priv))
1041 goto retry;
1042}
1043
1044/* Halt the receive and transmit queues */
1045static void gfar_halt(struct gfar_private *priv)
1046{
1047 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1048 u32 tempval;
1049
1050 /* Dissable the Rx/Tx hw queues */
1051 gfar_write(&regs->rqueue, 0);
1052 gfar_write(&regs->tqueue, 0);
1053
1054 mdelay(10);
1055
1056 gfar_halt_nodisable(priv);
1057
1058 /* Disable Rx/Tx DMA */
1059 tempval = gfar_read(&regs->maccfg1);
1060 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1061 gfar_write(&regs->maccfg1, tempval);
1062}
1063
1064static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1065{
1066 struct txbd8 *txbdp;
1067 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1068 int i, j;
1069
1070 txbdp = tx_queue->tx_bd_base;
1071
1072 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1073 if (!tx_queue->tx_skbuff[i])
1074 continue;
1075
1076 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1077 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1078 txbdp->lstatus = 0;
1079 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1080 j++) {
1081 txbdp++;
1082 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1083 be16_to_cpu(txbdp->length),
1084 DMA_TO_DEVICE);
1085 }
1086 txbdp++;
1087 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1088 tx_queue->tx_skbuff[i] = NULL;
1089 }
1090 kfree(tx_queue->tx_skbuff);
1091 tx_queue->tx_skbuff = NULL;
1092}
1093
1094static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1095{
1096 int i;
1097
1098 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1099
1100 dev_kfree_skb(rx_queue->skb);
1101
1102 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1103 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1104
1105 rxbdp->lstatus = 0;
1106 rxbdp->bufPtr = 0;
1107 rxbdp++;
1108
1109 if (!rxb->page)
1110 continue;
1111
1112 dma_unmap_page(rx_queue->dev, rxb->dma,
1113 PAGE_SIZE, DMA_FROM_DEVICE);
1114 __free_page(rxb->page);
1115
1116 rxb->page = NULL;
1117 }
1118
1119 kfree(rx_queue->rx_buff);
1120 rx_queue->rx_buff = NULL;
1121}
1122
1123/* If there are any tx skbs or rx skbs still around, free them.
1124 * Then free tx_skbuff and rx_skbuff
1125 */
1126static void free_skb_resources(struct gfar_private *priv)
1127{
1128 struct gfar_priv_tx_q *tx_queue = NULL;
1129 struct gfar_priv_rx_q *rx_queue = NULL;
1130 int i;
1131
1132 /* Go through all the buffer descriptors and free their data buffers */
1133 for (i = 0; i < priv->num_tx_queues; i++) {
1134 struct netdev_queue *txq;
1135
1136 tx_queue = priv->tx_queue[i];
1137 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1138 if (tx_queue->tx_skbuff)
1139 free_skb_tx_queue(tx_queue);
1140 netdev_tx_reset_queue(txq);
1141 }
1142
1143 for (i = 0; i < priv->num_rx_queues; i++) {
1144 rx_queue = priv->rx_queue[i];
1145 if (rx_queue->rx_buff)
1146 free_skb_rx_queue(rx_queue);
1147 }
1148
1149 dma_free_coherent(priv->dev,
1150 sizeof(struct txbd8) * priv->total_tx_ring_size +
1151 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1152 priv->tx_queue[0]->tx_bd_base,
1153 priv->tx_queue[0]->tx_bd_dma_base);
1154}
1155
1156void stop_gfar(struct net_device *dev)
1157{
1158 struct gfar_private *priv = netdev_priv(dev);
1159
1160 netif_tx_stop_all_queues(dev);
1161
1162 smp_mb__before_atomic();
1163 set_bit(GFAR_DOWN, &priv->state);
1164 smp_mb__after_atomic();
1165
1166 disable_napi(priv);
1167
1168 /* disable ints and gracefully shut down Rx/Tx DMA */
1169 gfar_halt(priv);
1170
1171 phy_stop(dev->phydev);
1172
1173 free_skb_resources(priv);
1174}
1175
1176static void gfar_start(struct gfar_private *priv)
1177{
1178 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1179 u32 tempval;
1180 int i = 0;
1181
1182 /* Enable Rx/Tx hw queues */
1183 gfar_write(&regs->rqueue, priv->rqueue);
1184 gfar_write(&regs->tqueue, priv->tqueue);
1185
1186 /* Initialize DMACTRL to have WWR and WOP */
1187 tempval = gfar_read(&regs->dmactrl);
1188 tempval |= DMACTRL_INIT_SETTINGS;
1189 gfar_write(&regs->dmactrl, tempval);
1190
1191 /* Make sure we aren't stopped */
1192 tempval = gfar_read(&regs->dmactrl);
1193 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1194 gfar_write(&regs->dmactrl, tempval);
1195
1196 for (i = 0; i < priv->num_grps; i++) {
1197 regs = priv->gfargrp[i].regs;
1198 /* Clear THLT/RHLT, so that the DMA starts polling now */
1199 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1200 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1201 }
1202
1203 /* Enable Rx/Tx DMA */
1204 tempval = gfar_read(&regs->maccfg1);
1205 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1206 gfar_write(&regs->maccfg1, tempval);
1207
1208 gfar_ints_enable(priv);
1209
1210 netif_trans_update(priv->ndev); /* prevent tx timeout */
1211}
1212
1213static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1214{
1215 struct page *page;
1216 dma_addr_t addr;
1217
1218 page = dev_alloc_page();
1219 if (unlikely(!page))
1220 return false;
1221
1222 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1223 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1224 __free_page(page);
1225
1226 return false;
1227 }
1228
1229 rxb->dma = addr;
1230 rxb->page = page;
1231 rxb->page_offset = 0;
1232
1233 return true;
1234}
1235
1236static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1237{
1238 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1239 struct gfar_extra_stats *estats = &priv->extra_stats;
1240
1241 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1242 atomic64_inc(&estats->rx_alloc_err);
1243}
1244
1245static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1246 int alloc_cnt)
1247{
1248 struct rxbd8 *bdp;
1249 struct gfar_rx_buff *rxb;
1250 int i;
1251
1252 i = rx_queue->next_to_use;
1253 bdp = &rx_queue->rx_bd_base[i];
1254 rxb = &rx_queue->rx_buff[i];
1255
1256 while (alloc_cnt--) {
1257 /* try reuse page */
1258 if (unlikely(!rxb->page)) {
1259 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1260 gfar_rx_alloc_err(rx_queue);
1261 break;
1262 }
1263 }
1264
1265 /* Setup the new RxBD */
1266 gfar_init_rxbdp(rx_queue, bdp,
1267 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1268
1269 /* Update to the next pointer */
1270 bdp++;
1271 rxb++;
1272
1273 if (unlikely(++i == rx_queue->rx_ring_size)) {
1274 i = 0;
1275 bdp = rx_queue->rx_bd_base;
1276 rxb = rx_queue->rx_buff;
1277 }
1278 }
1279
1280 rx_queue->next_to_use = i;
1281 rx_queue->next_to_alloc = i;
1282}
1283
1284static void gfar_init_bds(struct net_device *ndev)
1285{
1286 struct gfar_private *priv = netdev_priv(ndev);
1287 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1288 struct gfar_priv_tx_q *tx_queue = NULL;
1289 struct gfar_priv_rx_q *rx_queue = NULL;
1290 struct txbd8 *txbdp;
1291 u32 __iomem *rfbptr;
1292 int i, j;
1293
1294 for (i = 0; i < priv->num_tx_queues; i++) {
1295 tx_queue = priv->tx_queue[i];
1296 /* Initialize some variables in our dev structure */
1297 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1298 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1299 tx_queue->cur_tx = tx_queue->tx_bd_base;
1300 tx_queue->skb_curtx = 0;
1301 tx_queue->skb_dirtytx = 0;
1302
1303 /* Initialize Transmit Descriptor Ring */
1304 txbdp = tx_queue->tx_bd_base;
1305 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1306 txbdp->lstatus = 0;
1307 txbdp->bufPtr = 0;
1308 txbdp++;
1309 }
1310
1311 /* Set the last descriptor in the ring to indicate wrap */
1312 txbdp--;
1313 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1314 TXBD_WRAP);
1315 }
1316
1317 rfbptr = &regs->rfbptr0;
1318 for (i = 0; i < priv->num_rx_queues; i++) {
1319 rx_queue = priv->rx_queue[i];
1320
1321 rx_queue->next_to_clean = 0;
1322 rx_queue->next_to_use = 0;
1323 rx_queue->next_to_alloc = 0;
1324
1325 /* make sure next_to_clean != next_to_use after this
1326 * by leaving at least 1 unused descriptor
1327 */
1328 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1329
1330 rx_queue->rfbptr = rfbptr;
1331 rfbptr += 2;
1332 }
1333}
1334
1335static int gfar_alloc_skb_resources(struct net_device *ndev)
1336{
1337 void *vaddr;
1338 dma_addr_t addr;
1339 int i, j;
1340 struct gfar_private *priv = netdev_priv(ndev);
1341 struct device *dev = priv->dev;
1342 struct gfar_priv_tx_q *tx_queue = NULL;
1343 struct gfar_priv_rx_q *rx_queue = NULL;
1344
1345 priv->total_tx_ring_size = 0;
1346 for (i = 0; i < priv->num_tx_queues; i++)
1347 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1348
1349 priv->total_rx_ring_size = 0;
1350 for (i = 0; i < priv->num_rx_queues; i++)
1351 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1352
1353 /* Allocate memory for the buffer descriptors */
1354 vaddr = dma_alloc_coherent(dev,
1355 (priv->total_tx_ring_size *
1356 sizeof(struct txbd8)) +
1357 (priv->total_rx_ring_size *
1358 sizeof(struct rxbd8)),
1359 &addr, GFP_KERNEL);
1360 if (!vaddr)
1361 return -ENOMEM;
1362
1363 for (i = 0; i < priv->num_tx_queues; i++) {
1364 tx_queue = priv->tx_queue[i];
1365 tx_queue->tx_bd_base = vaddr;
1366 tx_queue->tx_bd_dma_base = addr;
1367 tx_queue->dev = ndev;
1368 /* enet DMA only understands physical addresses */
1369 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1370 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1371 }
1372
1373 /* Start the rx descriptor ring where the tx ring leaves off */
1374 for (i = 0; i < priv->num_rx_queues; i++) {
1375 rx_queue = priv->rx_queue[i];
1376 rx_queue->rx_bd_base = vaddr;
1377 rx_queue->rx_bd_dma_base = addr;
1378 rx_queue->ndev = ndev;
1379 rx_queue->dev = dev;
1380 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1381 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1382 }
1383
1384 /* Setup the skbuff rings */
1385 for (i = 0; i < priv->num_tx_queues; i++) {
1386 tx_queue = priv->tx_queue[i];
1387 tx_queue->tx_skbuff =
1388 kmalloc_array(tx_queue->tx_ring_size,
1389 sizeof(*tx_queue->tx_skbuff),
1390 GFP_KERNEL);
1391 if (!tx_queue->tx_skbuff)
1392 goto cleanup;
1393
1394 for (j = 0; j < tx_queue->tx_ring_size; j++)
1395 tx_queue->tx_skbuff[j] = NULL;
1396 }
1397
1398 for (i = 0; i < priv->num_rx_queues; i++) {
1399 rx_queue = priv->rx_queue[i];
1400 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1401 sizeof(*rx_queue->rx_buff),
1402 GFP_KERNEL);
1403 if (!rx_queue->rx_buff)
1404 goto cleanup;
1405 }
1406
1407 gfar_init_bds(ndev);
1408
1409 return 0;
1410
1411cleanup:
1412 free_skb_resources(priv);
1413 return -ENOMEM;
1414}
1415
1416/* Bring the controller up and running */
1417int startup_gfar(struct net_device *ndev)
1418{
1419 struct gfar_private *priv = netdev_priv(ndev);
1420 int err;
1421
1422 gfar_mac_reset(priv);
1423
1424 err = gfar_alloc_skb_resources(ndev);
1425 if (err)
1426 return err;
1427
1428 gfar_init_tx_rx_base(priv);
1429
1430 smp_mb__before_atomic();
1431 clear_bit(GFAR_DOWN, &priv->state);
1432 smp_mb__after_atomic();
1433
1434 /* Start Rx/Tx DMA and enable the interrupts */
1435 gfar_start(priv);
1436
1437 /* force link state update after mac reset */
1438 priv->oldlink = 0;
1439 priv->oldspeed = 0;
1440 priv->oldduplex = -1;
1441
1442 phy_start(ndev->phydev);
1443
1444 enable_napi(priv);
1445
1446 netif_tx_wake_all_queues(ndev);
1447
1448 return 0;
1449}
1450
1451static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1452{
1453 struct net_device *ndev = priv->ndev;
1454 struct phy_device *phydev = ndev->phydev;
1455 u32 val = 0;
1456
1457 if (!phydev->duplex)
1458 return val;
1459
1460 if (!priv->pause_aneg_en) {
1461 if (priv->tx_pause_en)
1462 val |= MACCFG1_TX_FLOW;
1463 if (priv->rx_pause_en)
1464 val |= MACCFG1_RX_FLOW;
1465 } else {
1466 u16 lcl_adv, rmt_adv;
1467 u8 flowctrl;
1468 /* get link partner capabilities */
1469 rmt_adv = 0;
1470 if (phydev->pause)
1471 rmt_adv = LPA_PAUSE_CAP;
1472 if (phydev->asym_pause)
1473 rmt_adv |= LPA_PAUSE_ASYM;
1474
1475 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1476 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1477 if (flowctrl & FLOW_CTRL_TX)
1478 val |= MACCFG1_TX_FLOW;
1479 if (flowctrl & FLOW_CTRL_RX)
1480 val |= MACCFG1_RX_FLOW;
1481 }
1482
1483 return val;
1484}
1485
1486static noinline void gfar_update_link_state(struct gfar_private *priv)
1487{
1488 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1489 struct net_device *ndev = priv->ndev;
1490 struct phy_device *phydev = ndev->phydev;
1491 struct gfar_priv_rx_q *rx_queue = NULL;
1492 int i;
1493
1494 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1495 return;
1496
1497 if (phydev->link) {
1498 u32 tempval1 = gfar_read(&regs->maccfg1);
1499 u32 tempval = gfar_read(&regs->maccfg2);
1500 u32 ecntrl = gfar_read(&regs->ecntrl);
1501 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1502
1503 if (phydev->duplex != priv->oldduplex) {
1504 if (!(phydev->duplex))
1505 tempval &= ~(MACCFG2_FULL_DUPLEX);
1506 else
1507 tempval |= MACCFG2_FULL_DUPLEX;
1508
1509 priv->oldduplex = phydev->duplex;
1510 }
1511
1512 if (phydev->speed != priv->oldspeed) {
1513 switch (phydev->speed) {
1514 case 1000:
1515 tempval =
1516 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1517
1518 ecntrl &= ~(ECNTRL_R100);
1519 break;
1520 case 100:
1521 case 10:
1522 tempval =
1523 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1524
1525 /* Reduced mode distinguishes
1526 * between 10 and 100
1527 */
1528 if (phydev->speed == SPEED_100)
1529 ecntrl |= ECNTRL_R100;
1530 else
1531 ecntrl &= ~(ECNTRL_R100);
1532 break;
1533 default:
1534 netif_warn(priv, link, priv->ndev,
1535 "Ack! Speed (%d) is not 10/100/1000!\n",
1536 phydev->speed);
1537 break;
1538 }
1539
1540 priv->oldspeed = phydev->speed;
1541 }
1542
1543 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1544 tempval1 |= gfar_get_flowctrl_cfg(priv);
1545
1546 /* Turn last free buffer recording on */
1547 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1548 for (i = 0; i < priv->num_rx_queues; i++) {
1549 u32 bdp_dma;
1550
1551 rx_queue = priv->rx_queue[i];
1552 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1553 gfar_write(rx_queue->rfbptr, bdp_dma);
1554 }
1555
1556 priv->tx_actual_en = 1;
1557 }
1558
1559 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1560 priv->tx_actual_en = 0;
1561
1562 gfar_write(&regs->maccfg1, tempval1);
1563 gfar_write(&regs->maccfg2, tempval);
1564 gfar_write(&regs->ecntrl, ecntrl);
1565
1566 if (!priv->oldlink)
1567 priv->oldlink = 1;
1568
1569 } else if (priv->oldlink) {
1570 priv->oldlink = 0;
1571 priv->oldspeed = 0;
1572 priv->oldduplex = -1;
1573 }
1574
1575 if (netif_msg_link(priv))
1576 phy_print_status(phydev);
1577}
1578
1579/* Called every time the controller might need to be made
1580 * aware of new link state. The PHY code conveys this
1581 * information through variables in the phydev structure, and this
1582 * function converts those variables into the appropriate
1583 * register values, and can bring down the device if needed.
1584 */
1585static void adjust_link(struct net_device *dev)
1586{
1587 struct gfar_private *priv = netdev_priv(dev);
1588 struct phy_device *phydev = dev->phydev;
1589
1590 if (unlikely(phydev->link != priv->oldlink ||
1591 (phydev->link && (phydev->duplex != priv->oldduplex ||
1592 phydev->speed != priv->oldspeed))))
1593 gfar_update_link_state(priv);
1594}
1595
1596/* Initialize TBI PHY interface for communicating with the
1597 * SERDES lynx PHY on the chip. We communicate with this PHY
1598 * through the MDIO bus on each controller, treating it as a
1599 * "normal" PHY at the address found in the TBIPA register. We assume
1600 * that the TBIPA register is valid. Either the MDIO bus code will set
1601 * it to a value that doesn't conflict with other PHYs on the bus, or the
1602 * value doesn't matter, as there are no other PHYs on the bus.
1603 */
1604static void gfar_configure_serdes(struct net_device *dev)
1605{
1606 struct gfar_private *priv = netdev_priv(dev);
1607 struct phy_device *tbiphy;
1608
1609 if (!priv->tbi_node) {
1610 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1611 "device tree specify a tbi-handle\n");
1612 return;
1613 }
1614
1615 tbiphy = of_phy_find_device(priv->tbi_node);
1616 if (!tbiphy) {
1617 dev_err(&dev->dev, "error: Could not get TBI device\n");
1618 return;
1619 }
1620
1621 /* If the link is already up, we must already be ok, and don't need to
1622 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1623 * everything for us? Resetting it takes the link down and requires
1624 * several seconds for it to come back.
1625 */
1626 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1627 put_device(&tbiphy->mdio.dev);
1628 return;
1629 }
1630
1631 /* Single clk mode, mii mode off(for serdes communication) */
1632 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1633
1634 phy_write(tbiphy, MII_ADVERTISE,
1635 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1636 ADVERTISE_1000XPSE_ASYM);
1637
1638 phy_write(tbiphy, MII_BMCR,
1639 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1640 BMCR_SPEED1000);
1641
1642 put_device(&tbiphy->mdio.dev);
1643}
1644
1645/* Initializes driver's PHY state, and attaches to the PHY.
1646 * Returns 0 on success.
1647 */
1648static int init_phy(struct net_device *dev)
1649{
1650 struct gfar_private *priv = netdev_priv(dev);
1651 phy_interface_t interface = priv->interface;
1652 struct phy_device *phydev;
1653 struct ethtool_keee edata;
1654
1655 priv->oldlink = 0;
1656 priv->oldspeed = 0;
1657 priv->oldduplex = -1;
1658
1659 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1660 interface);
1661 if (!phydev) {
1662 dev_err(&dev->dev, "could not attach to PHY\n");
1663 return -ENODEV;
1664 }
1665
1666 if (interface == PHY_INTERFACE_MODE_SGMII)
1667 gfar_configure_serdes(dev);
1668
1669 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT))
1670 phy_set_max_speed(phydev, SPEED_100);
1671
1672 /* Add support for flow control */
1673 phy_support_asym_pause(phydev);
1674
1675 /* disable EEE autoneg, EEE not supported by eTSEC */
1676 memset(&edata, 0, sizeof(struct ethtool_keee));
1677 phy_ethtool_set_eee(phydev, &edata);
1678
1679 return 0;
1680}
1681
1682static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1683{
1684 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1685
1686 memset(fcb, 0, GMAC_FCB_LEN);
1687
1688 return fcb;
1689}
1690
1691static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1692 int fcb_length)
1693{
1694 /* If we're here, it's a IP packet with a TCP or UDP
1695 * payload. We set it to checksum, using a pseudo-header
1696 * we provide
1697 */
1698 u8 flags = TXFCB_DEFAULT;
1699
1700 /* Tell the controller what the protocol is
1701 * And provide the already calculated phcs
1702 */
1703 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1704 flags |= TXFCB_UDP;
1705 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1706 } else
1707 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1708
1709 /* l3os is the distance between the start of the
1710 * frame (skb->data) and the start of the IP hdr.
1711 * l4os is the distance between the start of the
1712 * l3 hdr and the l4 hdr
1713 */
1714 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1715 fcb->l4os = skb_network_header_len(skb);
1716
1717 fcb->flags = flags;
1718}
1719
1720static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1721{
1722 fcb->flags |= TXFCB_VLN;
1723 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1724}
1725
1726static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1727 struct txbd8 *base, int ring_size)
1728{
1729 struct txbd8 *new_bd = bdp + stride;
1730
1731 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1732}
1733
1734static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1735 int ring_size)
1736{
1737 return skip_txbd(bdp, 1, base, ring_size);
1738}
1739
1740/* eTSEC12: csum generation not supported for some fcb offsets */
1741static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1742 unsigned long fcb_addr)
1743{
1744 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1745 (fcb_addr % 0x20) > 0x18);
1746}
1747
1748/* eTSEC76: csum generation for frames larger than 2500 may
1749 * cause excess delays before start of transmission
1750 */
1751static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1752 unsigned int len)
1753{
1754 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1755 (len > 2500));
1756}
1757
1758/* This is called by the kernel when a frame is ready for transmission.
1759 * It is pointed to by the dev->hard_start_xmit function pointer
1760 */
1761static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1762{
1763 struct gfar_private *priv = netdev_priv(dev);
1764 struct gfar_priv_tx_q *tx_queue = NULL;
1765 struct netdev_queue *txq;
1766 struct gfar __iomem *regs = NULL;
1767 struct txfcb *fcb = NULL;
1768 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1769 u32 lstatus;
1770 skb_frag_t *frag;
1771 int i, rq = 0;
1772 int do_tstamp, do_csum, do_vlan;
1773 u32 bufaddr;
1774 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1775
1776 rq = skb->queue_mapping;
1777 tx_queue = priv->tx_queue[rq];
1778 txq = netdev_get_tx_queue(dev, rq);
1779 base = tx_queue->tx_bd_base;
1780 regs = tx_queue->grp->regs;
1781
1782 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1783 do_vlan = skb_vlan_tag_present(skb);
1784 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1785 priv->hwts_tx_en;
1786
1787 if (do_csum || do_vlan)
1788 fcb_len = GMAC_FCB_LEN;
1789
1790 /* check if time stamp should be generated */
1791 if (unlikely(do_tstamp))
1792 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1793
1794 /* make space for additional header when fcb is needed */
1795 if (fcb_len) {
1796 if (unlikely(skb_cow_head(skb, fcb_len))) {
1797 dev->stats.tx_errors++;
1798 dev_kfree_skb_any(skb);
1799 return NETDEV_TX_OK;
1800 }
1801 }
1802
1803 /* total number of fragments in the SKB */
1804 nr_frags = skb_shinfo(skb)->nr_frags;
1805
1806 /* calculate the required number of TxBDs for this skb */
1807 if (unlikely(do_tstamp))
1808 nr_txbds = nr_frags + 2;
1809 else
1810 nr_txbds = nr_frags + 1;
1811
1812 /* check if there is space to queue this packet */
1813 if (nr_txbds > tx_queue->num_txbdfree) {
1814 /* no space, stop the queue */
1815 netif_tx_stop_queue(txq);
1816 dev->stats.tx_fifo_errors++;
1817 return NETDEV_TX_BUSY;
1818 }
1819
1820 /* Update transmit stats */
1821 bytes_sent = skb->len;
1822 tx_queue->stats.tx_bytes += bytes_sent;
1823 /* keep Tx bytes on wire for BQL accounting */
1824 GFAR_CB(skb)->bytes_sent = bytes_sent;
1825 tx_queue->stats.tx_packets++;
1826
1827 txbdp = txbdp_start = tx_queue->cur_tx;
1828 lstatus = be32_to_cpu(txbdp->lstatus);
1829
1830 /* Add TxPAL between FCB and frame if required */
1831 if (unlikely(do_tstamp)) {
1832 skb_push(skb, GMAC_TXPAL_LEN);
1833 memset(skb->data, 0, GMAC_TXPAL_LEN);
1834 }
1835
1836 /* Add TxFCB if required */
1837 if (fcb_len) {
1838 fcb = gfar_add_fcb(skb);
1839 lstatus |= BD_LFLAG(TXBD_TOE);
1840 }
1841
1842 /* Set up checksumming */
1843 if (do_csum) {
1844 gfar_tx_checksum(skb, fcb, fcb_len);
1845
1846 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1847 unlikely(gfar_csum_errata_76(priv, skb->len))) {
1848 __skb_pull(skb, GMAC_FCB_LEN);
1849 skb_checksum_help(skb);
1850 if (do_vlan || do_tstamp) {
1851 /* put back a new fcb for vlan/tstamp TOE */
1852 fcb = gfar_add_fcb(skb);
1853 } else {
1854 /* Tx TOE not used */
1855 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1856 fcb = NULL;
1857 }
1858 }
1859 }
1860
1861 if (do_vlan)
1862 gfar_tx_vlan(skb, fcb);
1863
1864 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1865 DMA_TO_DEVICE);
1866 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1867 goto dma_map_err;
1868
1869 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1870
1871 /* Time stamp insertion requires one additional TxBD */
1872 if (unlikely(do_tstamp))
1873 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1874 tx_queue->tx_ring_size);
1875
1876 if (likely(!nr_frags)) {
1877 if (likely(!do_tstamp))
1878 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1879 } else {
1880 u32 lstatus_start = lstatus;
1881
1882 /* Place the fragment addresses and lengths into the TxBDs */
1883 frag = &skb_shinfo(skb)->frags[0];
1884 for (i = 0; i < nr_frags; i++, frag++) {
1885 unsigned int size;
1886
1887 /* Point at the next BD, wrapping as needed */
1888 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1889
1890 size = skb_frag_size(frag);
1891
1892 lstatus = be32_to_cpu(txbdp->lstatus) | size |
1893 BD_LFLAG(TXBD_READY);
1894
1895 /* Handle the last BD specially */
1896 if (i == nr_frags - 1)
1897 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1898
1899 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1900 size, DMA_TO_DEVICE);
1901 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1902 goto dma_map_err;
1903
1904 /* set the TxBD length and buffer pointer */
1905 txbdp->bufPtr = cpu_to_be32(bufaddr);
1906 txbdp->lstatus = cpu_to_be32(lstatus);
1907 }
1908
1909 lstatus = lstatus_start;
1910 }
1911
1912 /* If time stamping is requested one additional TxBD must be set up. The
1913 * first TxBD points to the FCB and must have a data length of
1914 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
1915 * the full frame length.
1916 */
1917 if (unlikely(do_tstamp)) {
1918 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1919
1920 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1921 bufaddr += fcb_len;
1922
1923 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1924 (skb_headlen(skb) - fcb_len);
1925 if (!nr_frags)
1926 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1927
1928 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1929 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1930 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1931
1932 /* Setup tx hardware time stamping */
1933 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1934 fcb->ptp = 1;
1935 } else {
1936 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1937 }
1938
1939 skb_tx_timestamp(skb);
1940 netdev_tx_sent_queue(txq, bytes_sent);
1941
1942 gfar_wmb();
1943
1944 txbdp_start->lstatus = cpu_to_be32(lstatus);
1945
1946 gfar_wmb(); /* force lstatus write before tx_skbuff */
1947
1948 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1949
1950 /* Update the current skb pointer to the next entry we will use
1951 * (wrapping if necessary)
1952 */
1953 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1954 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1955
1956 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1957
1958 /* We can work in parallel with gfar_clean_tx_ring(), except
1959 * when modifying num_txbdfree. Note that we didn't grab the lock
1960 * when we were reading the num_txbdfree and checking for available
1961 * space, that's because outside of this function it can only grow.
1962 */
1963 spin_lock_bh(&tx_queue->txlock);
1964 /* reduce TxBD free count */
1965 tx_queue->num_txbdfree -= (nr_txbds);
1966 spin_unlock_bh(&tx_queue->txlock);
1967
1968 /* If the next BD still needs to be cleaned up, then the bds
1969 * are full. We need to tell the kernel to stop sending us stuff.
1970 */
1971 if (!tx_queue->num_txbdfree) {
1972 netif_tx_stop_queue(txq);
1973
1974 dev->stats.tx_fifo_errors++;
1975 }
1976
1977 /* Tell the DMA to go go go */
1978 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1979
1980 return NETDEV_TX_OK;
1981
1982dma_map_err:
1983 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
1984 if (do_tstamp)
1985 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1986 for (i = 0; i < nr_frags; i++) {
1987 lstatus = be32_to_cpu(txbdp->lstatus);
1988 if (!(lstatus & BD_LFLAG(TXBD_READY)))
1989 break;
1990
1991 lstatus &= ~BD_LFLAG(TXBD_READY);
1992 txbdp->lstatus = cpu_to_be32(lstatus);
1993 bufaddr = be32_to_cpu(txbdp->bufPtr);
1994 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
1995 DMA_TO_DEVICE);
1996 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1997 }
1998 gfar_wmb();
1999 dev_kfree_skb_any(skb);
2000 return NETDEV_TX_OK;
2001}
2002
2003/* Changes the mac address if the controller is not running. */
2004static int gfar_set_mac_address(struct net_device *dev)
2005{
2006 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2007
2008 return 0;
2009}
2010
2011static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2012{
2013 struct gfar_private *priv = netdev_priv(dev);
2014
2015 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2016 cpu_relax();
2017
2018 if (dev->flags & IFF_UP)
2019 stop_gfar(dev);
2020
2021 WRITE_ONCE(dev->mtu, new_mtu);
2022
2023 if (dev->flags & IFF_UP)
2024 startup_gfar(dev);
2025
2026 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2027
2028 return 0;
2029}
2030
2031static void reset_gfar(struct net_device *ndev)
2032{
2033 struct gfar_private *priv = netdev_priv(ndev);
2034
2035 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2036 cpu_relax();
2037
2038 stop_gfar(ndev);
2039 startup_gfar(ndev);
2040
2041 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2042}
2043
2044/* gfar_reset_task gets scheduled when a packet has not been
2045 * transmitted after a set amount of time.
2046 * For now, assume that clearing out all the structures, and
2047 * starting over will fix the problem.
2048 */
2049static void gfar_reset_task(struct work_struct *work)
2050{
2051 struct gfar_private *priv = container_of(work, struct gfar_private,
2052 reset_task);
2053 reset_gfar(priv->ndev);
2054}
2055
2056static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2057{
2058 struct gfar_private *priv = netdev_priv(dev);
2059
2060 dev->stats.tx_errors++;
2061 schedule_work(&priv->reset_task);
2062}
2063
2064static int gfar_hwtstamp_set(struct net_device *netdev,
2065 struct kernel_hwtstamp_config *config,
2066 struct netlink_ext_ack *extack)
2067{
2068 struct gfar_private *priv = netdev_priv(netdev);
2069
2070 switch (config->tx_type) {
2071 case HWTSTAMP_TX_OFF:
2072 priv->hwts_tx_en = 0;
2073 break;
2074 case HWTSTAMP_TX_ON:
2075 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2076 return -ERANGE;
2077 priv->hwts_tx_en = 1;
2078 break;
2079 default:
2080 return -ERANGE;
2081 }
2082
2083 switch (config->rx_filter) {
2084 case HWTSTAMP_FILTER_NONE:
2085 if (priv->hwts_rx_en) {
2086 priv->hwts_rx_en = 0;
2087 reset_gfar(netdev);
2088 }
2089 break;
2090 default:
2091 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2092 return -ERANGE;
2093 if (!priv->hwts_rx_en) {
2094 priv->hwts_rx_en = 1;
2095 reset_gfar(netdev);
2096 }
2097 config->rx_filter = HWTSTAMP_FILTER_ALL;
2098 break;
2099 }
2100
2101 return 0;
2102}
2103
2104static int gfar_hwtstamp_get(struct net_device *netdev,
2105 struct kernel_hwtstamp_config *config)
2106{
2107 struct gfar_private *priv = netdev_priv(netdev);
2108
2109 config->tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2110 config->rx_filter = priv->hwts_rx_en ? HWTSTAMP_FILTER_ALL :
2111 HWTSTAMP_FILTER_NONE;
2112
2113 return 0;
2114}
2115
2116/* Interrupt Handler for Transmit complete */
2117static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2118{
2119 struct net_device *dev = tx_queue->dev;
2120 struct netdev_queue *txq;
2121 struct gfar_private *priv = netdev_priv(dev);
2122 struct txbd8 *bdp, *next = NULL;
2123 struct txbd8 *lbdp = NULL;
2124 struct txbd8 *base = tx_queue->tx_bd_base;
2125 struct sk_buff *skb;
2126 int skb_dirtytx;
2127 int tx_ring_size = tx_queue->tx_ring_size;
2128 int frags = 0, nr_txbds = 0;
2129 int i;
2130 int howmany = 0;
2131 int tqi = tx_queue->qindex;
2132 unsigned int bytes_sent = 0;
2133 u32 lstatus;
2134 size_t buflen;
2135
2136 txq = netdev_get_tx_queue(dev, tqi);
2137 bdp = tx_queue->dirty_tx;
2138 skb_dirtytx = tx_queue->skb_dirtytx;
2139
2140 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2141 bool do_tstamp;
2142
2143 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2144 priv->hwts_tx_en;
2145
2146 frags = skb_shinfo(skb)->nr_frags;
2147
2148 /* When time stamping, one additional TxBD must be freed.
2149 * Also, we need to dma_unmap_single() the TxPAL.
2150 */
2151 if (unlikely(do_tstamp))
2152 nr_txbds = frags + 2;
2153 else
2154 nr_txbds = frags + 1;
2155
2156 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2157
2158 lstatus = be32_to_cpu(lbdp->lstatus);
2159
2160 /* Only clean completed frames */
2161 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2162 (lstatus & BD_LENGTH_MASK))
2163 break;
2164
2165 if (unlikely(do_tstamp)) {
2166 next = next_txbd(bdp, base, tx_ring_size);
2167 buflen = be16_to_cpu(next->length) +
2168 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2169 } else
2170 buflen = be16_to_cpu(bdp->length);
2171
2172 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2173 buflen, DMA_TO_DEVICE);
2174
2175 if (unlikely(do_tstamp)) {
2176 struct skb_shared_hwtstamps shhwtstamps;
2177 __be64 *ns;
2178
2179 ns = (__be64 *)(((uintptr_t)skb->data + 0x10) & ~0x7UL);
2180
2181 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2182 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2183 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2184 skb_tstamp_tx(skb, &shhwtstamps);
2185 gfar_clear_txbd_status(bdp);
2186 bdp = next;
2187 }
2188
2189 gfar_clear_txbd_status(bdp);
2190 bdp = next_txbd(bdp, base, tx_ring_size);
2191
2192 for (i = 0; i < frags; i++) {
2193 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2194 be16_to_cpu(bdp->length),
2195 DMA_TO_DEVICE);
2196 gfar_clear_txbd_status(bdp);
2197 bdp = next_txbd(bdp, base, tx_ring_size);
2198 }
2199
2200 bytes_sent += GFAR_CB(skb)->bytes_sent;
2201
2202 dev_kfree_skb_any(skb);
2203
2204 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2205
2206 skb_dirtytx = (skb_dirtytx + 1) &
2207 TX_RING_MOD_MASK(tx_ring_size);
2208
2209 howmany++;
2210 spin_lock(&tx_queue->txlock);
2211 tx_queue->num_txbdfree += nr_txbds;
2212 spin_unlock(&tx_queue->txlock);
2213 }
2214
2215 /* If we freed a buffer, we can restart transmission, if necessary */
2216 if (tx_queue->num_txbdfree &&
2217 netif_tx_queue_stopped(txq) &&
2218 !(test_bit(GFAR_DOWN, &priv->state)))
2219 netif_wake_subqueue(priv->ndev, tqi);
2220
2221 /* Update dirty indicators */
2222 tx_queue->skb_dirtytx = skb_dirtytx;
2223 tx_queue->dirty_tx = bdp;
2224
2225 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2226}
2227
2228static void count_errors(u32 lstatus, struct net_device *ndev)
2229{
2230 struct gfar_private *priv = netdev_priv(ndev);
2231 struct net_device_stats *stats = &ndev->stats;
2232 struct gfar_extra_stats *estats = &priv->extra_stats;
2233
2234 /* If the packet was truncated, none of the other errors matter */
2235 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2236 stats->rx_length_errors++;
2237
2238 atomic64_inc(&estats->rx_trunc);
2239
2240 return;
2241 }
2242 /* Count the errors, if there were any */
2243 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2244 stats->rx_length_errors++;
2245
2246 if (lstatus & BD_LFLAG(RXBD_LARGE))
2247 atomic64_inc(&estats->rx_large);
2248 else
2249 atomic64_inc(&estats->rx_short);
2250 }
2251 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2252 stats->rx_frame_errors++;
2253 atomic64_inc(&estats->rx_nonoctet);
2254 }
2255 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2256 atomic64_inc(&estats->rx_crcerr);
2257 stats->rx_crc_errors++;
2258 }
2259 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2260 atomic64_inc(&estats->rx_overrun);
2261 stats->rx_over_errors++;
2262 }
2263}
2264
2265static irqreturn_t gfar_receive(int irq, void *grp_id)
2266{
2267 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2268 unsigned long flags;
2269 u32 imask, ievent;
2270
2271 ievent = gfar_read(&grp->regs->ievent);
2272
2273 if (unlikely(ievent & IEVENT_FGPI)) {
2274 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2275 return IRQ_HANDLED;
2276 }
2277
2278 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2279 spin_lock_irqsave(&grp->grplock, flags);
2280 imask = gfar_read(&grp->regs->imask);
2281 imask &= IMASK_RX_DISABLED | grp->priv->rmon_overflow.imask;
2282 gfar_write(&grp->regs->imask, imask);
2283 spin_unlock_irqrestore(&grp->grplock, flags);
2284 __napi_schedule(&grp->napi_rx);
2285 } else {
2286 /* Clear IEVENT, so interrupts aren't called again
2287 * because of the packets that have already arrived.
2288 */
2289 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2290 }
2291
2292 return IRQ_HANDLED;
2293}
2294
2295/* Interrupt Handler for Transmit complete */
2296static irqreturn_t gfar_transmit(int irq, void *grp_id)
2297{
2298 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2299 unsigned long flags;
2300 u32 imask;
2301
2302 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2303 spin_lock_irqsave(&grp->grplock, flags);
2304 imask = gfar_read(&grp->regs->imask);
2305 imask &= IMASK_TX_DISABLED | grp->priv->rmon_overflow.imask;
2306 gfar_write(&grp->regs->imask, imask);
2307 spin_unlock_irqrestore(&grp->grplock, flags);
2308 __napi_schedule(&grp->napi_tx);
2309 } else {
2310 /* Clear IEVENT, so interrupts aren't called again
2311 * because of the packets that have already arrived.
2312 */
2313 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2314 }
2315
2316 return IRQ_HANDLED;
2317}
2318
2319static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2320 struct sk_buff *skb, bool first)
2321{
2322 int size = lstatus & BD_LENGTH_MASK;
2323 struct page *page = rxb->page;
2324
2325 if (likely(first)) {
2326 skb_put(skb, size);
2327 } else {
2328 /* the last fragments' length contains the full frame length */
2329 if (lstatus & BD_LFLAG(RXBD_LAST))
2330 size -= skb->len;
2331
2332 WARN(size < 0, "gianfar: rx fragment size underflow");
2333 if (size < 0)
2334 return false;
2335
2336 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2337 rxb->page_offset + RXBUF_ALIGNMENT,
2338 size, GFAR_RXB_TRUESIZE);
2339 }
2340
2341 /* try reuse page */
2342 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2343 return false;
2344
2345 /* change offset to the other half */
2346 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2347
2348 page_ref_inc(page);
2349
2350 return true;
2351}
2352
2353static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2354 struct gfar_rx_buff *old_rxb)
2355{
2356 struct gfar_rx_buff *new_rxb;
2357 u16 nta = rxq->next_to_alloc;
2358
2359 new_rxb = &rxq->rx_buff[nta];
2360
2361 /* find next buf that can reuse a page */
2362 nta++;
2363 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2364
2365 /* copy page reference */
2366 *new_rxb = *old_rxb;
2367
2368 /* sync for use by the device */
2369 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2370 old_rxb->page_offset,
2371 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2372}
2373
2374static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2375 u32 lstatus, struct sk_buff *skb)
2376{
2377 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2378 struct page *page = rxb->page;
2379 bool first = false;
2380
2381 if (likely(!skb)) {
2382 void *buff_addr = page_address(page) + rxb->page_offset;
2383
2384 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2385 if (unlikely(!skb)) {
2386 gfar_rx_alloc_err(rx_queue);
2387 return NULL;
2388 }
2389 skb_reserve(skb, RXBUF_ALIGNMENT);
2390 first = true;
2391 }
2392
2393 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2394 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2395
2396 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2397 /* reuse the free half of the page */
2398 gfar_reuse_rx_page(rx_queue, rxb);
2399 } else {
2400 /* page cannot be reused, unmap it */
2401 dma_unmap_page(rx_queue->dev, rxb->dma,
2402 PAGE_SIZE, DMA_FROM_DEVICE);
2403 }
2404
2405 /* clear rxb content */
2406 rxb->page = NULL;
2407
2408 return skb;
2409}
2410
2411static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2412{
2413 /* If valid headers were found, and valid sums
2414 * were verified, then we tell the kernel that no
2415 * checksumming is necessary. Otherwise, it is [FIXME]
2416 */
2417 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2418 (RXFCB_CIP | RXFCB_CTU))
2419 skb->ip_summed = CHECKSUM_UNNECESSARY;
2420 else
2421 skb_checksum_none_assert(skb);
2422}
2423
2424/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2425static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2426{
2427 struct gfar_private *priv = netdev_priv(ndev);
2428 struct rxfcb *fcb = NULL;
2429
2430 /* fcb is at the beginning if exists */
2431 fcb = (struct rxfcb *)skb->data;
2432
2433 /* Remove the FCB from the skb
2434 * Remove the padded bytes, if there are any
2435 */
2436 if (priv->uses_rxfcb)
2437 skb_pull(skb, GMAC_FCB_LEN);
2438
2439 /* Get receive timestamp from the skb */
2440 if (priv->hwts_rx_en) {
2441 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2442 __be64 *ns = (__be64 *)skb->data;
2443
2444 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2445 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2446 }
2447
2448 if (priv->padding)
2449 skb_pull(skb, priv->padding);
2450
2451 /* Trim off the FCS */
2452 pskb_trim(skb, skb->len - ETH_FCS_LEN);
2453
2454 if (ndev->features & NETIF_F_RXCSUM)
2455 gfar_rx_checksum(skb, fcb);
2456
2457 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2458 * Even if vlan rx accel is disabled, on some chips
2459 * RXFCB_VLN is pseudo randomly set.
2460 */
2461 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2462 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2463 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2464 be16_to_cpu(fcb->vlctl));
2465}
2466
2467/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2468 * until the budget/quota has been reached. Returns the number
2469 * of frames handled
2470 */
2471static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2472 int rx_work_limit)
2473{
2474 struct net_device *ndev = rx_queue->ndev;
2475 struct gfar_private *priv = netdev_priv(ndev);
2476 struct rxbd8 *bdp;
2477 int i, howmany = 0;
2478 struct sk_buff *skb = rx_queue->skb;
2479 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2480 unsigned int total_bytes = 0, total_pkts = 0;
2481
2482 /* Get the first full descriptor */
2483 i = rx_queue->next_to_clean;
2484
2485 while (rx_work_limit--) {
2486 u32 lstatus;
2487
2488 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2489 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2490 cleaned_cnt = 0;
2491 }
2492
2493 bdp = &rx_queue->rx_bd_base[i];
2494 lstatus = be32_to_cpu(bdp->lstatus);
2495 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2496 break;
2497
2498 /* lost RXBD_LAST descriptor due to overrun */
2499 if (skb &&
2500 (lstatus & BD_LFLAG(RXBD_FIRST))) {
2501 /* discard faulty buffer */
2502 dev_kfree_skb(skb);
2503 skb = NULL;
2504 rx_queue->stats.rx_dropped++;
2505
2506 /* can continue normally */
2507 }
2508
2509 /* order rx buffer descriptor reads */
2510 rmb();
2511
2512 /* fetch next to clean buffer from the ring */
2513 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2514 if (unlikely(!skb))
2515 break;
2516
2517 cleaned_cnt++;
2518 howmany++;
2519
2520 if (unlikely(++i == rx_queue->rx_ring_size))
2521 i = 0;
2522
2523 rx_queue->next_to_clean = i;
2524
2525 /* fetch next buffer if not the last in frame */
2526 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2527 continue;
2528
2529 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2530 count_errors(lstatus, ndev);
2531
2532 /* discard faulty buffer */
2533 dev_kfree_skb(skb);
2534 skb = NULL;
2535 rx_queue->stats.rx_dropped++;
2536 continue;
2537 }
2538
2539 gfar_process_frame(ndev, skb);
2540
2541 /* Increment the number of packets */
2542 total_pkts++;
2543 total_bytes += skb->len;
2544
2545 skb_record_rx_queue(skb, rx_queue->qindex);
2546
2547 skb->protocol = eth_type_trans(skb, ndev);
2548
2549 /* Send the packet up the stack */
2550 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2551
2552 skb = NULL;
2553 }
2554
2555 /* Store incomplete frames for completion */
2556 rx_queue->skb = skb;
2557
2558 rx_queue->stats.rx_packets += total_pkts;
2559 rx_queue->stats.rx_bytes += total_bytes;
2560
2561 if (cleaned_cnt)
2562 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2563
2564 /* Update Last Free RxBD pointer for LFC */
2565 if (unlikely(priv->tx_actual_en)) {
2566 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2567
2568 gfar_write(rx_queue->rfbptr, bdp_dma);
2569 }
2570
2571 return howmany;
2572}
2573
2574static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2575{
2576 struct gfar_priv_grp *gfargrp =
2577 container_of(napi, struct gfar_priv_grp, napi_rx);
2578 struct gfar __iomem *regs = gfargrp->regs;
2579 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2580 int work_done = 0;
2581
2582 /* Clear IEVENT, so interrupts aren't called again
2583 * because of the packets that have already arrived
2584 */
2585 gfar_write(&regs->ievent, IEVENT_RX_MASK);
2586
2587 work_done = gfar_clean_rx_ring(rx_queue, budget);
2588
2589 if (work_done < budget) {
2590 u32 imask;
2591 napi_complete_done(napi, work_done);
2592 /* Clear the halt bit in RSTAT */
2593 gfar_write(&regs->rstat, gfargrp->rstat);
2594
2595 spin_lock_irq(&gfargrp->grplock);
2596 imask = gfar_read(&regs->imask);
2597 imask |= IMASK_RX_DEFAULT;
2598 gfar_write(&regs->imask, imask);
2599 spin_unlock_irq(&gfargrp->grplock);
2600 }
2601
2602 return work_done;
2603}
2604
2605static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2606{
2607 struct gfar_priv_grp *gfargrp =
2608 container_of(napi, struct gfar_priv_grp, napi_tx);
2609 struct gfar __iomem *regs = gfargrp->regs;
2610 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2611 u32 imask;
2612
2613 /* Clear IEVENT, so interrupts aren't called again
2614 * because of the packets that have already arrived
2615 */
2616 gfar_write(&regs->ievent, IEVENT_TX_MASK);
2617
2618 /* run Tx cleanup to completion */
2619 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2620 gfar_clean_tx_ring(tx_queue);
2621
2622 napi_complete(napi);
2623
2624 spin_lock_irq(&gfargrp->grplock);
2625 imask = gfar_read(&regs->imask);
2626 imask |= IMASK_TX_DEFAULT;
2627 gfar_write(&regs->imask, imask);
2628 spin_unlock_irq(&gfargrp->grplock);
2629
2630 return 0;
2631}
2632
2633/* GFAR error interrupt handler */
2634static irqreturn_t gfar_error(int irq, void *grp_id)
2635{
2636 struct gfar_priv_grp *gfargrp = grp_id;
2637 struct gfar __iomem *regs = gfargrp->regs;
2638 struct gfar_private *priv= gfargrp->priv;
2639 struct net_device *dev = priv->ndev;
2640
2641 /* Save ievent for future reference */
2642 u32 events = gfar_read(&regs->ievent);
2643
2644 /* Clear IEVENT */
2645 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
2646
2647 /* Magic Packet is not an error. */
2648 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2649 (events & IEVENT_MAG))
2650 events &= ~IEVENT_MAG;
2651
2652 /* Hmm... */
2653 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2654 netdev_dbg(dev,
2655 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2656 events, gfar_read(&regs->imask));
2657
2658 /* Update the error counters */
2659 if (events & IEVENT_TXE) {
2660 dev->stats.tx_errors++;
2661
2662 if (events & IEVENT_LC)
2663 dev->stats.tx_window_errors++;
2664 if (events & IEVENT_CRL)
2665 dev->stats.tx_aborted_errors++;
2666 if (events & IEVENT_XFUN) {
2667 netif_dbg(priv, tx_err, dev,
2668 "TX FIFO underrun, packet dropped\n");
2669 dev->stats.tx_dropped++;
2670 atomic64_inc(&priv->extra_stats.tx_underrun);
2671
2672 schedule_work(&priv->reset_task);
2673 }
2674 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2675 }
2676 if (events & IEVENT_MSRO) {
2677 struct rmon_mib __iomem *rmon = &regs->rmon;
2678 u32 car;
2679
2680 spin_lock(&priv->rmon_overflow.lock);
2681 car = gfar_read(&rmon->car1) & CAR1_C1RDR;
2682 if (car) {
2683 priv->rmon_overflow.rdrp++;
2684 gfar_write(&rmon->car1, car);
2685 }
2686 spin_unlock(&priv->rmon_overflow.lock);
2687 }
2688 if (events & IEVENT_BSY) {
2689 dev->stats.rx_over_errors++;
2690 atomic64_inc(&priv->extra_stats.rx_bsy);
2691
2692 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2693 gfar_read(&regs->rstat));
2694 }
2695 if (events & IEVENT_BABR) {
2696 dev->stats.rx_errors++;
2697 atomic64_inc(&priv->extra_stats.rx_babr);
2698
2699 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2700 }
2701 if (events & IEVENT_EBERR) {
2702 atomic64_inc(&priv->extra_stats.eberr);
2703 netif_dbg(priv, rx_err, dev, "bus error\n");
2704 }
2705 if (events & IEVENT_RXC)
2706 netif_dbg(priv, rx_status, dev, "control frame\n");
2707
2708 if (events & IEVENT_BABT) {
2709 atomic64_inc(&priv->extra_stats.tx_babt);
2710 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2711 }
2712 return IRQ_HANDLED;
2713}
2714
2715/* The interrupt handler for devices with one interrupt */
2716static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2717{
2718 struct gfar_priv_grp *gfargrp = grp_id;
2719
2720 /* Save ievent for future reference */
2721 u32 events = gfar_read(&gfargrp->regs->ievent);
2722
2723 /* Check for reception */
2724 if (events & IEVENT_RX_MASK)
2725 gfar_receive(irq, grp_id);
2726
2727 /* Check for transmit completion */
2728 if (events & IEVENT_TX_MASK)
2729 gfar_transmit(irq, grp_id);
2730
2731 /* Check for errors */
2732 if (events & IEVENT_ERR_MASK)
2733 gfar_error(irq, grp_id);
2734
2735 return IRQ_HANDLED;
2736}
2737
2738#ifdef CONFIG_NET_POLL_CONTROLLER
2739/* Polling 'interrupt' - used by things like netconsole to send skbs
2740 * without having to re-enable interrupts. It's not called while
2741 * the interrupt routine is executing.
2742 */
2743static void gfar_netpoll(struct net_device *dev)
2744{
2745 struct gfar_private *priv = netdev_priv(dev);
2746 int i;
2747
2748 /* If the device has multiple interrupts, run tx/rx */
2749 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2750 for (i = 0; i < priv->num_grps; i++) {
2751 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2752
2753 disable_irq(gfar_irq(grp, TX)->irq);
2754 disable_irq(gfar_irq(grp, RX)->irq);
2755 disable_irq(gfar_irq(grp, ER)->irq);
2756 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2757 enable_irq(gfar_irq(grp, ER)->irq);
2758 enable_irq(gfar_irq(grp, RX)->irq);
2759 enable_irq(gfar_irq(grp, TX)->irq);
2760 }
2761 } else {
2762 for (i = 0; i < priv->num_grps; i++) {
2763 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2764
2765 disable_irq(gfar_irq(grp, TX)->irq);
2766 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2767 enable_irq(gfar_irq(grp, TX)->irq);
2768 }
2769 }
2770}
2771#endif
2772
2773static void free_grp_irqs(struct gfar_priv_grp *grp)
2774{
2775 free_irq(gfar_irq(grp, TX)->irq, grp);
2776 free_irq(gfar_irq(grp, RX)->irq, grp);
2777 free_irq(gfar_irq(grp, ER)->irq, grp);
2778}
2779
2780static int register_grp_irqs(struct gfar_priv_grp *grp)
2781{
2782 struct gfar_private *priv = grp->priv;
2783 struct net_device *dev = priv->ndev;
2784 int err;
2785
2786 /* If the device has multiple interrupts, register for
2787 * them. Otherwise, only register for the one
2788 */
2789 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2790 /* Install our interrupt handlers for Error,
2791 * Transmit, and Receive
2792 */
2793 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2794 gfar_irq(grp, ER)->name, grp);
2795 if (err < 0) {
2796 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2797 gfar_irq(grp, ER)->irq);
2798
2799 goto err_irq_fail;
2800 }
2801 enable_irq_wake(gfar_irq(grp, ER)->irq);
2802
2803 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2804 gfar_irq(grp, TX)->name, grp);
2805 if (err < 0) {
2806 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2807 gfar_irq(grp, TX)->irq);
2808 goto tx_irq_fail;
2809 }
2810 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2811 gfar_irq(grp, RX)->name, grp);
2812 if (err < 0) {
2813 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2814 gfar_irq(grp, RX)->irq);
2815 goto rx_irq_fail;
2816 }
2817 enable_irq_wake(gfar_irq(grp, RX)->irq);
2818
2819 } else {
2820 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2821 gfar_irq(grp, TX)->name, grp);
2822 if (err < 0) {
2823 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2824 gfar_irq(grp, TX)->irq);
2825 goto err_irq_fail;
2826 }
2827 enable_irq_wake(gfar_irq(grp, TX)->irq);
2828 }
2829
2830 return 0;
2831
2832rx_irq_fail:
2833 free_irq(gfar_irq(grp, TX)->irq, grp);
2834tx_irq_fail:
2835 free_irq(gfar_irq(grp, ER)->irq, grp);
2836err_irq_fail:
2837 return err;
2838
2839}
2840
2841static void gfar_free_irq(struct gfar_private *priv)
2842{
2843 int i;
2844
2845 /* Free the IRQs */
2846 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2847 for (i = 0; i < priv->num_grps; i++)
2848 free_grp_irqs(&priv->gfargrp[i]);
2849 } else {
2850 for (i = 0; i < priv->num_grps; i++)
2851 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2852 &priv->gfargrp[i]);
2853 }
2854}
2855
2856static int gfar_request_irq(struct gfar_private *priv)
2857{
2858 int err, i, j;
2859
2860 for (i = 0; i < priv->num_grps; i++) {
2861 err = register_grp_irqs(&priv->gfargrp[i]);
2862 if (err) {
2863 for (j = 0; j < i; j++)
2864 free_grp_irqs(&priv->gfargrp[j]);
2865 return err;
2866 }
2867 }
2868
2869 return 0;
2870}
2871
2872/* Called when something needs to use the ethernet device
2873 * Returns 0 for success.
2874 */
2875static int gfar_enet_open(struct net_device *dev)
2876{
2877 struct gfar_private *priv = netdev_priv(dev);
2878 int err;
2879
2880 err = init_phy(dev);
2881 if (err)
2882 return err;
2883
2884 err = gfar_request_irq(priv);
2885 if (err)
2886 return err;
2887
2888 err = startup_gfar(dev);
2889 if (err)
2890 return err;
2891
2892 return err;
2893}
2894
2895/* Stops the kernel queue, and halts the controller */
2896static int gfar_close(struct net_device *dev)
2897{
2898 struct gfar_private *priv = netdev_priv(dev);
2899
2900 cancel_work_sync(&priv->reset_task);
2901 stop_gfar(dev);
2902
2903 /* Disconnect from the PHY */
2904 phy_disconnect(dev->phydev);
2905
2906 gfar_free_irq(priv);
2907
2908 return 0;
2909}
2910
2911/* Clears each of the exact match registers to zero, so they
2912 * don't interfere with normal reception
2913 */
2914static void gfar_clear_exact_match(struct net_device *dev)
2915{
2916 int idx;
2917 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2918
2919 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
2920 gfar_set_mac_for_addr(dev, idx, zero_arr);
2921}
2922
2923/* Update the hash table based on the current list of multicast
2924 * addresses we subscribe to. Also, change the promiscuity of
2925 * the device based on the flags (this function is called
2926 * whenever dev->flags is changed
2927 */
2928static void gfar_set_multi(struct net_device *dev)
2929{
2930 struct netdev_hw_addr *ha;
2931 struct gfar_private *priv = netdev_priv(dev);
2932 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2933 u32 tempval;
2934
2935 if (dev->flags & IFF_PROMISC) {
2936 /* Set RCTRL to PROM */
2937 tempval = gfar_read(&regs->rctrl);
2938 tempval |= RCTRL_PROM;
2939 gfar_write(&regs->rctrl, tempval);
2940 } else {
2941 /* Set RCTRL to not PROM */
2942 tempval = gfar_read(&regs->rctrl);
2943 tempval &= ~(RCTRL_PROM);
2944 gfar_write(&regs->rctrl, tempval);
2945 }
2946
2947 if (dev->flags & IFF_ALLMULTI) {
2948 /* Set the hash to rx all multicast frames */
2949 gfar_write(&regs->igaddr0, 0xffffffff);
2950 gfar_write(&regs->igaddr1, 0xffffffff);
2951 gfar_write(&regs->igaddr2, 0xffffffff);
2952 gfar_write(&regs->igaddr3, 0xffffffff);
2953 gfar_write(&regs->igaddr4, 0xffffffff);
2954 gfar_write(&regs->igaddr5, 0xffffffff);
2955 gfar_write(&regs->igaddr6, 0xffffffff);
2956 gfar_write(&regs->igaddr7, 0xffffffff);
2957 gfar_write(&regs->gaddr0, 0xffffffff);
2958 gfar_write(&regs->gaddr1, 0xffffffff);
2959 gfar_write(&regs->gaddr2, 0xffffffff);
2960 gfar_write(&regs->gaddr3, 0xffffffff);
2961 gfar_write(&regs->gaddr4, 0xffffffff);
2962 gfar_write(&regs->gaddr5, 0xffffffff);
2963 gfar_write(&regs->gaddr6, 0xffffffff);
2964 gfar_write(&regs->gaddr7, 0xffffffff);
2965 } else {
2966 int em_num;
2967 int idx;
2968
2969 /* zero out the hash */
2970 gfar_write(&regs->igaddr0, 0x0);
2971 gfar_write(&regs->igaddr1, 0x0);
2972 gfar_write(&regs->igaddr2, 0x0);
2973 gfar_write(&regs->igaddr3, 0x0);
2974 gfar_write(&regs->igaddr4, 0x0);
2975 gfar_write(&regs->igaddr5, 0x0);
2976 gfar_write(&regs->igaddr6, 0x0);
2977 gfar_write(&regs->igaddr7, 0x0);
2978 gfar_write(&regs->gaddr0, 0x0);
2979 gfar_write(&regs->gaddr1, 0x0);
2980 gfar_write(&regs->gaddr2, 0x0);
2981 gfar_write(&regs->gaddr3, 0x0);
2982 gfar_write(&regs->gaddr4, 0x0);
2983 gfar_write(&regs->gaddr5, 0x0);
2984 gfar_write(&regs->gaddr6, 0x0);
2985 gfar_write(&regs->gaddr7, 0x0);
2986
2987 /* If we have extended hash tables, we need to
2988 * clear the exact match registers to prepare for
2989 * setting them
2990 */
2991 if (priv->extended_hash) {
2992 em_num = GFAR_EM_NUM + 1;
2993 gfar_clear_exact_match(dev);
2994 idx = 1;
2995 } else {
2996 idx = 0;
2997 em_num = 0;
2998 }
2999
3000 if (netdev_mc_empty(dev))
3001 return;
3002
3003 /* Parse the list, and set the appropriate bits */
3004 netdev_for_each_mc_addr(ha, dev) {
3005 if (idx < em_num) {
3006 gfar_set_mac_for_addr(dev, idx, ha->addr);
3007 idx++;
3008 } else
3009 gfar_set_hash_for_addr(dev, ha->addr);
3010 }
3011 }
3012}
3013
3014void gfar_mac_reset(struct gfar_private *priv)
3015{
3016 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3017 u32 tempval;
3018
3019 /* Reset MAC layer */
3020 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
3021
3022 /* We need to delay at least 3 TX clocks */
3023 udelay(3);
3024
3025 /* the soft reset bit is not self-resetting, so we need to
3026 * clear it before resuming normal operation
3027 */
3028 gfar_write(&regs->maccfg1, 0);
3029
3030 udelay(3);
3031
3032 gfar_rx_offload_en(priv);
3033
3034 /* Initialize the max receive frame/buffer lengths */
3035 gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3036 gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
3037
3038 /* Initialize the Minimum Frame Length Register */
3039 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
3040
3041 /* Initialize MACCFG2. */
3042 tempval = MACCFG2_INIT_SETTINGS;
3043
3044 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
3045 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
3046 * and by checking RxBD[LG] and discarding larger than MAXFRM.
3047 */
3048 if (gfar_has_errata(priv, GFAR_ERRATA_74))
3049 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3050
3051 gfar_write(&regs->maccfg2, tempval);
3052
3053 /* Clear mac addr hash registers */
3054 gfar_write(&regs->igaddr0, 0);
3055 gfar_write(&regs->igaddr1, 0);
3056 gfar_write(&regs->igaddr2, 0);
3057 gfar_write(&regs->igaddr3, 0);
3058 gfar_write(&regs->igaddr4, 0);
3059 gfar_write(&regs->igaddr5, 0);
3060 gfar_write(&regs->igaddr6, 0);
3061 gfar_write(&regs->igaddr7, 0);
3062
3063 gfar_write(&regs->gaddr0, 0);
3064 gfar_write(&regs->gaddr1, 0);
3065 gfar_write(&regs->gaddr2, 0);
3066 gfar_write(&regs->gaddr3, 0);
3067 gfar_write(&regs->gaddr4, 0);
3068 gfar_write(&regs->gaddr5, 0);
3069 gfar_write(&regs->gaddr6, 0);
3070 gfar_write(&regs->gaddr7, 0);
3071
3072 if (priv->extended_hash)
3073 gfar_clear_exact_match(priv->ndev);
3074
3075 gfar_mac_rx_config(priv);
3076
3077 gfar_mac_tx_config(priv);
3078
3079 gfar_set_mac_address(priv->ndev);
3080
3081 gfar_set_multi(priv->ndev);
3082
3083 /* clear ievent and imask before configuring coalescing */
3084 gfar_ints_disable(priv);
3085
3086 /* Configure the coalescing support */
3087 gfar_configure_coalescing_all(priv);
3088}
3089
3090static void gfar_hw_init(struct gfar_private *priv)
3091{
3092 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3093 u32 attrs;
3094
3095 /* Stop the DMA engine now, in case it was running before
3096 * (The firmware could have used it, and left it running).
3097 */
3098 gfar_halt(priv);
3099
3100 gfar_mac_reset(priv);
3101
3102 /* Zero out the rmon mib registers if it has them */
3103 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3104 memset_io(&regs->rmon, 0, offsetof(struct rmon_mib, car1));
3105
3106 /* Mask off the CAM interrupts */
3107 gfar_write(&regs->rmon.cam1, 0xffffffff);
3108 gfar_write(&regs->rmon.cam2, 0xffffffff);
3109 /* Clear the CAR registers (w1c style) */
3110 gfar_write(&regs->rmon.car1, 0xffffffff);
3111 gfar_write(&regs->rmon.car2, 0xffffffff);
3112 }
3113
3114 /* Initialize ECNTRL */
3115 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
3116
3117 /* Set the extraction length and index */
3118 attrs = ATTRELI_EL(priv->rx_stash_size) |
3119 ATTRELI_EI(priv->rx_stash_index);
3120
3121 gfar_write(&regs->attreli, attrs);
3122
3123 /* Start with defaults, and add stashing
3124 * depending on driver parameters
3125 */
3126 attrs = ATTR_INIT_SETTINGS;
3127
3128 if (priv->bd_stash_en)
3129 attrs |= ATTR_BDSTASH;
3130
3131 if (priv->rx_stash_size != 0)
3132 attrs |= ATTR_BUFSTASH;
3133
3134 gfar_write(&regs->attr, attrs);
3135
3136 /* FIFO configs */
3137 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3138 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3139 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3140
3141 /* Program the interrupt steering regs, only for MG devices */
3142 if (priv->num_grps > 1)
3143 gfar_write_isrg(priv);
3144}
3145
3146static const struct net_device_ops gfar_netdev_ops = {
3147 .ndo_open = gfar_enet_open,
3148 .ndo_start_xmit = gfar_start_xmit,
3149 .ndo_stop = gfar_close,
3150 .ndo_change_mtu = gfar_change_mtu,
3151 .ndo_set_features = gfar_set_features,
3152 .ndo_set_rx_mode = gfar_set_multi,
3153 .ndo_tx_timeout = gfar_timeout,
3154 .ndo_eth_ioctl = phy_do_ioctl_running,
3155 .ndo_get_stats64 = gfar_get_stats64,
3156 .ndo_change_carrier = fixed_phy_change_carrier,
3157 .ndo_set_mac_address = gfar_set_mac_addr,
3158 .ndo_validate_addr = eth_validate_addr,
3159#ifdef CONFIG_NET_POLL_CONTROLLER
3160 .ndo_poll_controller = gfar_netpoll,
3161#endif
3162 .ndo_hwtstamp_get = gfar_hwtstamp_get,
3163 .ndo_hwtstamp_set = gfar_hwtstamp_set,
3164};
3165
3166/* Set up the ethernet device structure, private data,
3167 * and anything else we need before we start
3168 */
3169static int gfar_probe(struct platform_device *ofdev)
3170{
3171 struct device_node *np = ofdev->dev.of_node;
3172 struct net_device *dev = NULL;
3173 struct gfar_private *priv = NULL;
3174 int err = 0, i;
3175
3176 err = gfar_of_init(ofdev, &dev);
3177
3178 if (err)
3179 return err;
3180
3181 priv = netdev_priv(dev);
3182 priv->ndev = dev;
3183 priv->ofdev = ofdev;
3184 priv->dev = &ofdev->dev;
3185 SET_NETDEV_DEV(dev, &ofdev->dev);
3186
3187 INIT_WORK(&priv->reset_task, gfar_reset_task);
3188
3189 platform_set_drvdata(ofdev, priv);
3190
3191 gfar_detect_errata(priv);
3192
3193 /* Set the dev->base_addr to the gfar reg region */
3194 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3195
3196 /* Fill in the dev structure */
3197 dev->watchdog_timeo = TX_TIMEOUT;
3198 /* MTU range: 50 - 9586 */
3199 dev->mtu = 1500;
3200 dev->min_mtu = 50;
3201 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3202 dev->netdev_ops = &gfar_netdev_ops;
3203 dev->ethtool_ops = &gfar_ethtool_ops;
3204
3205 /* Register for napi ...We are registering NAPI for each grp */
3206 for (i = 0; i < priv->num_grps; i++) {
3207 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3208 gfar_poll_rx_sq);
3209 netif_napi_add_tx_weight(dev, &priv->gfargrp[i].napi_tx,
3210 gfar_poll_tx_sq, 2);
3211 }
3212
3213 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3214 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3215 NETIF_F_RXCSUM;
3216 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3217 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3218 }
3219
3220 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3221 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3222 NETIF_F_HW_VLAN_CTAG_RX;
3223 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3224 }
3225
3226 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3227
3228 gfar_init_addr_hash_table(priv);
3229
3230 /* Insert receive time stamps into padding alignment bytes, and
3231 * plus 2 bytes padding to ensure the cpu alignment.
3232 */
3233 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3234 priv->padding = 8 + DEFAULT_PADDING;
3235
3236 if (dev->features & NETIF_F_IP_CSUM ||
3237 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3238 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
3239
3240 /* Initializing some of the rx/tx queue level parameters */
3241 for (i = 0; i < priv->num_tx_queues; i++) {
3242 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3243 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3244 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3245 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3246 }
3247
3248 for (i = 0; i < priv->num_rx_queues; i++) {
3249 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3250 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3251 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3252 }
3253
3254 /* Always enable rx filer if available */
3255 priv->rx_filer_enable =
3256 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3257 /* Enable most messages by default */
3258 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3259 /* use pritority h/w tx queue scheduling for single queue devices */
3260 if (priv->num_tx_queues == 1)
3261 priv->prio_sched_en = 1;
3262
3263 set_bit(GFAR_DOWN, &priv->state);
3264
3265 gfar_hw_init(priv);
3266
3267 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3268 struct rmon_mib __iomem *rmon = &priv->gfargrp[0].regs->rmon;
3269
3270 spin_lock_init(&priv->rmon_overflow.lock);
3271 priv->rmon_overflow.imask = IMASK_MSRO;
3272 gfar_write(&rmon->cam1, gfar_read(&rmon->cam1) & ~CAM1_M1RDR);
3273 }
3274
3275 /* Carrier starts down, phylib will bring it up */
3276 netif_carrier_off(dev);
3277
3278 err = register_netdev(dev);
3279
3280 if (err) {
3281 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3282 goto register_fail;
3283 }
3284
3285 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3286 priv->wol_supported |= GFAR_WOL_MAGIC;
3287
3288 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3289 priv->rx_filer_enable)
3290 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3291
3292 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3293
3294 /* fill out IRQ number and name fields */
3295 for (i = 0; i < priv->num_grps; i++) {
3296 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3297 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3298 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3299 dev->name, "_g", '0' + i, "_tx");
3300 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3301 dev->name, "_g", '0' + i, "_rx");
3302 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3303 dev->name, "_g", '0' + i, "_er");
3304 } else
3305 strcpy(gfar_irq(grp, TX)->name, dev->name);
3306 }
3307
3308 /* Initialize the filer table */
3309 gfar_init_filer_table(priv);
3310
3311 /* Print out the device info */
3312 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3313
3314 /* Even more device info helps when determining which kernel
3315 * provided which set of benchmarks.
3316 */
3317 netdev_info(dev, "Running with NAPI enabled\n");
3318 for (i = 0; i < priv->num_rx_queues; i++)
3319 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3320 i, priv->rx_queue[i]->rx_ring_size);
3321 for (i = 0; i < priv->num_tx_queues; i++)
3322 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3323 i, priv->tx_queue[i]->tx_ring_size);
3324
3325 return 0;
3326
3327register_fail:
3328 if (of_phy_is_fixed_link(np))
3329 of_phy_deregister_fixed_link(np);
3330 unmap_group_regs(priv);
3331 gfar_free_rx_queues(priv);
3332 gfar_free_tx_queues(priv);
3333 of_node_put(priv->phy_node);
3334 of_node_put(priv->tbi_node);
3335 free_gfar_dev(priv);
3336 return err;
3337}
3338
3339static void gfar_remove(struct platform_device *ofdev)
3340{
3341 struct gfar_private *priv = platform_get_drvdata(ofdev);
3342 struct device_node *np = ofdev->dev.of_node;
3343
3344 of_node_put(priv->phy_node);
3345 of_node_put(priv->tbi_node);
3346
3347 unregister_netdev(priv->ndev);
3348
3349 if (of_phy_is_fixed_link(np))
3350 of_phy_deregister_fixed_link(np);
3351
3352 unmap_group_regs(priv);
3353 gfar_free_rx_queues(priv);
3354 gfar_free_tx_queues(priv);
3355 free_gfar_dev(priv);
3356}
3357
3358#ifdef CONFIG_PM
3359
3360static void __gfar_filer_disable(struct gfar_private *priv)
3361{
3362 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3363 u32 temp;
3364
3365 temp = gfar_read(&regs->rctrl);
3366 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3367 gfar_write(&regs->rctrl, temp);
3368}
3369
3370static void __gfar_filer_enable(struct gfar_private *priv)
3371{
3372 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3373 u32 temp;
3374
3375 temp = gfar_read(&regs->rctrl);
3376 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3377 gfar_write(&regs->rctrl, temp);
3378}
3379
3380/* Filer rules implementing wol capabilities */
3381static void gfar_filer_config_wol(struct gfar_private *priv)
3382{
3383 unsigned int i;
3384 u32 rqfcr;
3385
3386 __gfar_filer_disable(priv);
3387
3388 /* clear the filer table, reject any packet by default */
3389 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3390 for (i = 0; i <= MAX_FILER_IDX; i++)
3391 gfar_write_filer(priv, i, rqfcr, 0);
3392
3393 i = 0;
3394 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3395 /* unicast packet, accept it */
3396 struct net_device *ndev = priv->ndev;
3397 /* get the default rx queue index */
3398 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3399 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3400 (ndev->dev_addr[1] << 8) |
3401 ndev->dev_addr[2];
3402
3403 rqfcr = (qindex << 10) | RQFCR_AND |
3404 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3405
3406 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3407
3408 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3409 (ndev->dev_addr[4] << 8) |
3410 ndev->dev_addr[5];
3411 rqfcr = (qindex << 10) | RQFCR_GPI |
3412 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3413 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3414 }
3415
3416 __gfar_filer_enable(priv);
3417}
3418
3419static void gfar_filer_restore_table(struct gfar_private *priv)
3420{
3421 u32 rqfcr, rqfpr;
3422 unsigned int i;
3423
3424 __gfar_filer_disable(priv);
3425
3426 for (i = 0; i <= MAX_FILER_IDX; i++) {
3427 rqfcr = priv->ftp_rqfcr[i];
3428 rqfpr = priv->ftp_rqfpr[i];
3429 gfar_write_filer(priv, i, rqfcr, rqfpr);
3430 }
3431
3432 __gfar_filer_enable(priv);
3433}
3434
3435/* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
3436static void gfar_start_wol_filer(struct gfar_private *priv)
3437{
3438 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3439 u32 tempval;
3440 int i = 0;
3441
3442 /* Enable Rx hw queues */
3443 gfar_write(&regs->rqueue, priv->rqueue);
3444
3445 /* Initialize DMACTRL to have WWR and WOP */
3446 tempval = gfar_read(&regs->dmactrl);
3447 tempval |= DMACTRL_INIT_SETTINGS;
3448 gfar_write(&regs->dmactrl, tempval);
3449
3450 /* Make sure we aren't stopped */
3451 tempval = gfar_read(&regs->dmactrl);
3452 tempval &= ~DMACTRL_GRS;
3453 gfar_write(&regs->dmactrl, tempval);
3454
3455 for (i = 0; i < priv->num_grps; i++) {
3456 regs = priv->gfargrp[i].regs;
3457 /* Clear RHLT, so that the DMA starts polling now */
3458 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
3459 /* enable the Filer General Purpose Interrupt */
3460 gfar_write(&regs->imask, IMASK_FGPI);
3461 }
3462
3463 /* Enable Rx DMA */
3464 tempval = gfar_read(&regs->maccfg1);
3465 tempval |= MACCFG1_RX_EN;
3466 gfar_write(&regs->maccfg1, tempval);
3467}
3468
3469static int gfar_suspend(struct device *dev)
3470{
3471 struct gfar_private *priv = dev_get_drvdata(dev);
3472 struct net_device *ndev = priv->ndev;
3473 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3474 u32 tempval;
3475 u16 wol = priv->wol_opts;
3476
3477 if (!netif_running(ndev))
3478 return 0;
3479
3480 disable_napi(priv);
3481 netif_tx_lock(ndev);
3482 netif_device_detach(ndev);
3483 netif_tx_unlock(ndev);
3484
3485 gfar_halt(priv);
3486
3487 if (wol & GFAR_WOL_MAGIC) {
3488 /* Enable interrupt on Magic Packet */
3489 gfar_write(&regs->imask, IMASK_MAG);
3490
3491 /* Enable Magic Packet mode */
3492 tempval = gfar_read(&regs->maccfg2);
3493 tempval |= MACCFG2_MPEN;
3494 gfar_write(&regs->maccfg2, tempval);
3495
3496 /* re-enable the Rx block */
3497 tempval = gfar_read(&regs->maccfg1);
3498 tempval |= MACCFG1_RX_EN;
3499 gfar_write(&regs->maccfg1, tempval);
3500
3501 } else if (wol & GFAR_WOL_FILER_UCAST) {
3502 gfar_filer_config_wol(priv);
3503 gfar_start_wol_filer(priv);
3504
3505 } else {
3506 phy_stop(ndev->phydev);
3507 }
3508
3509 return 0;
3510}
3511
3512static int gfar_resume(struct device *dev)
3513{
3514 struct gfar_private *priv = dev_get_drvdata(dev);
3515 struct net_device *ndev = priv->ndev;
3516 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3517 u32 tempval;
3518 u16 wol = priv->wol_opts;
3519
3520 if (!netif_running(ndev))
3521 return 0;
3522
3523 if (wol & GFAR_WOL_MAGIC) {
3524 /* Disable Magic Packet mode */
3525 tempval = gfar_read(&regs->maccfg2);
3526 tempval &= ~MACCFG2_MPEN;
3527 gfar_write(&regs->maccfg2, tempval);
3528
3529 } else if (wol & GFAR_WOL_FILER_UCAST) {
3530 /* need to stop rx only, tx is already down */
3531 gfar_halt(priv);
3532 gfar_filer_restore_table(priv);
3533
3534 } else {
3535 phy_start(ndev->phydev);
3536 }
3537
3538 gfar_start(priv);
3539
3540 netif_device_attach(ndev);
3541 enable_napi(priv);
3542
3543 return 0;
3544}
3545
3546static int gfar_restore(struct device *dev)
3547{
3548 struct gfar_private *priv = dev_get_drvdata(dev);
3549 struct net_device *ndev = priv->ndev;
3550
3551 if (!netif_running(ndev)) {
3552 netif_device_attach(ndev);
3553
3554 return 0;
3555 }
3556
3557 gfar_init_bds(ndev);
3558
3559 gfar_mac_reset(priv);
3560
3561 gfar_init_tx_rx_base(priv);
3562
3563 gfar_start(priv);
3564
3565 priv->oldlink = 0;
3566 priv->oldspeed = 0;
3567 priv->oldduplex = -1;
3568
3569 if (ndev->phydev)
3570 phy_start(ndev->phydev);
3571
3572 netif_device_attach(ndev);
3573 enable_napi(priv);
3574
3575 return 0;
3576}
3577
3578static const struct dev_pm_ops gfar_pm_ops = {
3579 .suspend = gfar_suspend,
3580 .resume = gfar_resume,
3581 .freeze = gfar_suspend,
3582 .thaw = gfar_resume,
3583 .restore = gfar_restore,
3584};
3585
3586#define GFAR_PM_OPS (&gfar_pm_ops)
3587
3588#else
3589
3590#define GFAR_PM_OPS NULL
3591
3592#endif
3593
3594static const struct of_device_id gfar_match[] =
3595{
3596 {
3597 .type = "network",
3598 .compatible = "gianfar",
3599 },
3600 {
3601 .compatible = "fsl,etsec2",
3602 },
3603 {},
3604};
3605MODULE_DEVICE_TABLE(of, gfar_match);
3606
3607/* Structure for a device driver */
3608static struct platform_driver gfar_driver = {
3609 .driver = {
3610 .name = "fsl-gianfar",
3611 .pm = GFAR_PM_OPS,
3612 .of_match_table = gfar_match,
3613 },
3614 .probe = gfar_probe,
3615 .remove = gfar_remove,
3616};
3617
3618module_platform_driver(gfar_driver);
Linux 6.x block layer and io_uring tree(s)