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gianfar: Implement MAC reset and reconfig procedure
[linux-block.git] / drivers / net / ethernet / freescale / gianfar.c
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1/* drivers/net/ethernet/freescale/gianfar.c
2 *
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 *
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
67#include <linux/kernel.h>
68#include <linux/string.h>
69#include <linux/errno.h>
70#include <linux/unistd.h>
71#include <linux/slab.h>
72#include <linux/interrupt.h>
73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
77#include <linux/if_vlan.h>
78#include <linux/spinlock.h>
79#include <linux/mm.h>
80#include <linux/of_address.h>
81#include <linux/of_irq.h>
82#include <linux/of_mdio.h>
83#include <linux/of_platform.h>
84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
87#include <linux/in.h>
88#include <linux/net_tstamp.h>
89
90#include <asm/io.h>
91#include <asm/reg.h>
92#include <asm/mpc85xx.h>
93#include <asm/irq.h>
94#include <asm/uaccess.h>
95#include <linux/module.h>
96#include <linux/dma-mapping.h>
97#include <linux/crc32.h>
98#include <linux/mii.h>
99#include <linux/phy.h>
100#include <linux/phy_fixed.h>
101#include <linux/of.h>
102#include <linux/of_net.h>
103
104#include "gianfar.h"
105
106#define TX_TIMEOUT (1*HZ)
107
108const char gfar_driver_version[] = "1.3";
109
110static int gfar_enet_open(struct net_device *dev);
111static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
112static void gfar_reset_task(struct work_struct *work);
113static void gfar_timeout(struct net_device *dev);
114static int gfar_close(struct net_device *dev);
115struct sk_buff *gfar_new_skb(struct net_device *dev);
116static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
117 struct sk_buff *skb);
118static int gfar_set_mac_address(struct net_device *dev);
119static int gfar_change_mtu(struct net_device *dev, int new_mtu);
120static irqreturn_t gfar_error(int irq, void *dev_id);
121static irqreturn_t gfar_transmit(int irq, void *dev_id);
122static irqreturn_t gfar_interrupt(int irq, void *dev_id);
123static void adjust_link(struct net_device *dev);
124static int init_phy(struct net_device *dev);
125static int gfar_probe(struct platform_device *ofdev);
126static int gfar_remove(struct platform_device *ofdev);
127static void free_skb_resources(struct gfar_private *priv);
128static void gfar_set_multi(struct net_device *dev);
129static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
130static void gfar_configure_serdes(struct net_device *dev);
131static int gfar_poll(struct napi_struct *napi, int budget);
132static int gfar_poll_sq(struct napi_struct *napi, int budget);
133#ifdef CONFIG_NET_POLL_CONTROLLER
134static void gfar_netpoll(struct net_device *dev);
135#endif
136int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
138static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull, struct napi_struct *napi);
140static void gfar_halt_nodisable(struct gfar_private *priv);
141static void gfar_clear_exact_match(struct net_device *dev);
142static void gfar_set_mac_for_addr(struct net_device *dev, int num,
143 const u8 *addr);
144static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146MODULE_AUTHOR("Freescale Semiconductor, Inc");
147MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148MODULE_LICENSE("GPL");
149
150static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
151 dma_addr_t buf)
152{
153 u32 lstatus;
154
155 bdp->bufPtr = buf;
156
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
160
161 eieio();
162
163 bdp->lstatus = lstatus;
164}
165
166static int gfar_init_bds(struct net_device *ndev)
167{
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
171 struct txbd8 *txbdp;
172 struct rxbd8 *rxbdp;
173 int i, j;
174
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
183
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
187 txbdp->lstatus = 0;
188 txbdp->bufPtr = 0;
189 txbdp++;
190 }
191
192 /* Set the last descriptor in the ring to indicate wrap */
193 txbdp--;
194 txbdp->status |= TXBD_WRAP;
195 }
196
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
202
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
205
206 if (skb) {
207 gfar_init_rxbdp(rx_queue, rxbdp,
208 rxbdp->bufPtr);
209 } else {
210 skb = gfar_new_skb(ndev);
211 if (!skb) {
212 netdev_err(ndev, "Can't allocate RX buffers\n");
213 return -ENOMEM;
214 }
215 rx_queue->rx_skbuff[j] = skb;
216
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
218 }
219
220 rxbdp++;
221 }
222
223 }
224
225 return 0;
226}
227
228static int gfar_alloc_skb_resources(struct net_device *ndev)
229{
230 void *vaddr;
231 dma_addr_t addr;
232 int i, j, k;
233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = priv->dev;
235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
237
238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
241
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
245
246 /* Allocate memory for the buffer descriptors */
247 vaddr = dma_alloc_coherent(dev,
248 (priv->total_tx_ring_size *
249 sizeof(struct txbd8)) +
250 (priv->total_rx_ring_size *
251 sizeof(struct rxbd8)),
252 &addr, GFP_KERNEL);
253 if (!vaddr)
254 return -ENOMEM;
255
256 for (i = 0; i < priv->num_tx_queues; i++) {
257 tx_queue = priv->tx_queue[i];
258 tx_queue->tx_bd_base = vaddr;
259 tx_queue->tx_bd_dma_base = addr;
260 tx_queue->dev = ndev;
261 /* enet DMA only understands physical addresses */
262 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
263 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
264 }
265
266 /* Start the rx descriptor ring where the tx ring leaves off */
267 for (i = 0; i < priv->num_rx_queues; i++) {
268 rx_queue = priv->rx_queue[i];
269 rx_queue->rx_bd_base = vaddr;
270 rx_queue->rx_bd_dma_base = addr;
271 rx_queue->dev = ndev;
272 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
273 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
274 }
275
276 /* Setup the skbuff rings */
277 for (i = 0; i < priv->num_tx_queues; i++) {
278 tx_queue = priv->tx_queue[i];
279 tx_queue->tx_skbuff =
280 kmalloc_array(tx_queue->tx_ring_size,
281 sizeof(*tx_queue->tx_skbuff),
282 GFP_KERNEL);
283 if (!tx_queue->tx_skbuff)
284 goto cleanup;
285
286 for (k = 0; k < tx_queue->tx_ring_size; k++)
287 tx_queue->tx_skbuff[k] = NULL;
288 }
289
290 for (i = 0; i < priv->num_rx_queues; i++) {
291 rx_queue = priv->rx_queue[i];
292 rx_queue->rx_skbuff =
293 kmalloc_array(rx_queue->rx_ring_size,
294 sizeof(*rx_queue->rx_skbuff),
295 GFP_KERNEL);
296 if (!rx_queue->rx_skbuff)
297 goto cleanup;
298
299 for (j = 0; j < rx_queue->rx_ring_size; j++)
300 rx_queue->rx_skbuff[j] = NULL;
301 }
302
303 if (gfar_init_bds(ndev))
304 goto cleanup;
305
306 return 0;
307
308cleanup:
309 free_skb_resources(priv);
310 return -ENOMEM;
311}
312
313static void gfar_init_tx_rx_base(struct gfar_private *priv)
314{
315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
316 u32 __iomem *baddr;
317 int i;
318
319 baddr = &regs->tbase0;
320 for (i = 0; i < priv->num_tx_queues; i++) {
321 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
322 baddr += 2;
323 }
324
325 baddr = &regs->rbase0;
326 for (i = 0; i < priv->num_rx_queues; i++) {
327 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
328 baddr += 2;
329 }
330}
331
332static void gfar_mac_rx_config(struct gfar_private *priv)
333{
334 struct gfar __iomem *regs = priv->gfargrp[0].regs;
335 u32 rctrl = 0;
336
337 /* set this when rx hw offload (TOE) functions are being used */
338 priv->uses_rxfcb = 0;
339
340 if (priv->rx_filer_enable) {
341 rctrl |= RCTRL_FILREN;
342 /* Program the RIR0 reg with the required distribution */
343 gfar_write(&regs->rir0, DEFAULT_RIR0);
344 }
345
346 /* Restore PROMISC mode */
347 if (priv->ndev->flags & IFF_PROMISC)
348 rctrl |= RCTRL_PROM;
349
350 if (priv->ndev->features & NETIF_F_RXCSUM) {
351 rctrl |= RCTRL_CHECKSUMMING;
352 priv->uses_rxfcb = 1;
353 }
354
355 if (priv->extended_hash) {
356 rctrl |= RCTRL_EXTHASH;
357 rctrl |= RCTRL_EMEN;
358 }
359
360 if (priv->padding) {
361 rctrl &= ~RCTRL_PAL_MASK;
362 rctrl |= RCTRL_PADDING(priv->padding);
363 }
364
365 /* Enable HW time stamping if requested from user space */
366 if (priv->hwts_rx_en) {
367 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
368 priv->uses_rxfcb = 1;
369 }
370
371 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
372 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
373 priv->uses_rxfcb = 1;
374 }
375
376 /* Init rctrl based on our settings */
377 gfar_write(&regs->rctrl, rctrl);
378}
379
380static void gfar_mac_tx_config(struct gfar_private *priv)
381{
382 struct gfar __iomem *regs = priv->gfargrp[0].regs;
383 u32 tctrl = 0;
384
385 if (priv->ndev->features & NETIF_F_IP_CSUM)
386 tctrl |= TCTRL_INIT_CSUM;
387
388 if (priv->prio_sched_en)
389 tctrl |= TCTRL_TXSCHED_PRIO;
390 else {
391 tctrl |= TCTRL_TXSCHED_WRRS;
392 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
393 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
394 }
395
396 gfar_write(&regs->tctrl, tctrl);
397}
398
399static struct net_device_stats *gfar_get_stats(struct net_device *dev)
400{
401 struct gfar_private *priv = netdev_priv(dev);
402 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
403 unsigned long tx_packets = 0, tx_bytes = 0;
404 int i;
405
406 for (i = 0; i < priv->num_rx_queues; i++) {
407 rx_packets += priv->rx_queue[i]->stats.rx_packets;
408 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
409 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
410 }
411
412 dev->stats.rx_packets = rx_packets;
413 dev->stats.rx_bytes = rx_bytes;
414 dev->stats.rx_dropped = rx_dropped;
415
416 for (i = 0; i < priv->num_tx_queues; i++) {
417 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
418 tx_packets += priv->tx_queue[i]->stats.tx_packets;
419 }
420
421 dev->stats.tx_bytes = tx_bytes;
422 dev->stats.tx_packets = tx_packets;
423
424 return &dev->stats;
425}
426
427static const struct net_device_ops gfar_netdev_ops = {
428 .ndo_open = gfar_enet_open,
429 .ndo_start_xmit = gfar_start_xmit,
430 .ndo_stop = gfar_close,
431 .ndo_change_mtu = gfar_change_mtu,
432 .ndo_set_features = gfar_set_features,
433 .ndo_set_rx_mode = gfar_set_multi,
434 .ndo_tx_timeout = gfar_timeout,
435 .ndo_do_ioctl = gfar_ioctl,
436 .ndo_get_stats = gfar_get_stats,
437 .ndo_set_mac_address = eth_mac_addr,
438 .ndo_validate_addr = eth_validate_addr,
439#ifdef CONFIG_NET_POLL_CONTROLLER
440 .ndo_poll_controller = gfar_netpoll,
441#endif
442};
443
444static void gfar_ints_disable(struct gfar_private *priv)
445{
446 int i;
447 for (i = 0; i < priv->num_grps; i++) {
448 struct gfar __iomem *regs = priv->gfargrp[i].regs;
449 /* Clear IEVENT */
450 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
451
452 /* Initialize IMASK */
453 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
454 }
455}
456
457static void gfar_ints_enable(struct gfar_private *priv)
458{
459 int i;
460 for (i = 0; i < priv->num_grps; i++) {
461 struct gfar __iomem *regs = priv->gfargrp[i].regs;
462 /* Unmask the interrupts we look for */
463 gfar_write(&regs->imask, IMASK_DEFAULT);
464 }
465}
466
467void lock_rx_qs(struct gfar_private *priv)
468{
469 int i;
470
471 for (i = 0; i < priv->num_rx_queues; i++)
472 spin_lock(&priv->rx_queue[i]->rxlock);
473}
474
475void lock_tx_qs(struct gfar_private *priv)
476{
477 int i;
478
479 for (i = 0; i < priv->num_tx_queues; i++)
480 spin_lock(&priv->tx_queue[i]->txlock);
481}
482
483void unlock_rx_qs(struct gfar_private *priv)
484{
485 int i;
486
487 for (i = 0; i < priv->num_rx_queues; i++)
488 spin_unlock(&priv->rx_queue[i]->rxlock);
489}
490
491void unlock_tx_qs(struct gfar_private *priv)
492{
493 int i;
494
495 for (i = 0; i < priv->num_tx_queues; i++)
496 spin_unlock(&priv->tx_queue[i]->txlock);
497}
498
499static int gfar_alloc_tx_queues(struct gfar_private *priv)
500{
501 int i;
502
503 for (i = 0; i < priv->num_tx_queues; i++) {
504 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
505 GFP_KERNEL);
506 if (!priv->tx_queue[i])
507 return -ENOMEM;
508
509 priv->tx_queue[i]->tx_skbuff = NULL;
510 priv->tx_queue[i]->qindex = i;
511 priv->tx_queue[i]->dev = priv->ndev;
512 spin_lock_init(&(priv->tx_queue[i]->txlock));
513 }
514 return 0;
515}
516
517static int gfar_alloc_rx_queues(struct gfar_private *priv)
518{
519 int i;
520
521 for (i = 0; i < priv->num_rx_queues; i++) {
522 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
523 GFP_KERNEL);
524 if (!priv->rx_queue[i])
525 return -ENOMEM;
526
527 priv->rx_queue[i]->rx_skbuff = NULL;
528 priv->rx_queue[i]->qindex = i;
529 priv->rx_queue[i]->dev = priv->ndev;
530 spin_lock_init(&(priv->rx_queue[i]->rxlock));
531 }
532 return 0;
533}
534
535static void gfar_free_tx_queues(struct gfar_private *priv)
536{
537 int i;
538
539 for (i = 0; i < priv->num_tx_queues; i++)
540 kfree(priv->tx_queue[i]);
541}
542
543static void gfar_free_rx_queues(struct gfar_private *priv)
544{
545 int i;
546
547 for (i = 0; i < priv->num_rx_queues; i++)
548 kfree(priv->rx_queue[i]);
549}
550
551static void unmap_group_regs(struct gfar_private *priv)
552{
553 int i;
554
555 for (i = 0; i < MAXGROUPS; i++)
556 if (priv->gfargrp[i].regs)
557 iounmap(priv->gfargrp[i].regs);
558}
559
560static void free_gfar_dev(struct gfar_private *priv)
561{
562 int i, j;
563
564 for (i = 0; i < priv->num_grps; i++)
565 for (j = 0; j < GFAR_NUM_IRQS; j++) {
566 kfree(priv->gfargrp[i].irqinfo[j]);
567 priv->gfargrp[i].irqinfo[j] = NULL;
568 }
569
570 free_netdev(priv->ndev);
571}
572
573static void disable_napi(struct gfar_private *priv)
574{
575 int i;
576
577 for (i = 0; i < priv->num_grps; i++)
578 napi_disable(&priv->gfargrp[i].napi);
579}
580
581static void enable_napi(struct gfar_private *priv)
582{
583 int i;
584
585 for (i = 0; i < priv->num_grps; i++)
586 napi_enable(&priv->gfargrp[i].napi);
587}
588
589static int gfar_parse_group(struct device_node *np,
590 struct gfar_private *priv, const char *model)
591{
592 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
593 u32 *queue_mask;
594 int i;
595
596 for (i = 0; i < GFAR_NUM_IRQS; i++) {
597 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
598 GFP_KERNEL);
599 if (!grp->irqinfo[i])
600 return -ENOMEM;
601 }
602
603 grp->regs = of_iomap(np, 0);
604 if (!grp->regs)
605 return -ENOMEM;
606
607 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
608
609 /* If we aren't the FEC we have multiple interrupts */
610 if (model && strcasecmp(model, "FEC")) {
611 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
612 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
613 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
614 gfar_irq(grp, RX)->irq == NO_IRQ ||
615 gfar_irq(grp, ER)->irq == NO_IRQ)
616 return -EINVAL;
617 }
618
619 grp->priv = priv;
620 spin_lock_init(&grp->grplock);
621 if (priv->mode == MQ_MG_MODE) {
622 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
623 grp->rx_bit_map = queue_mask ?
624 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
625 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
626 grp->tx_bit_map = queue_mask ?
627 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
628 } else {
629 grp->rx_bit_map = 0xFF;
630 grp->tx_bit_map = 0xFF;
631 }
632
633 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
634 * right to left, so we need to revert the 8 bits to get the q index
635 */
636 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
637 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
638
639 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
640 * also assign queues to groups
641 */
642 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
643 grp->num_rx_queues++;
644 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
645 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
646 priv->rx_queue[i]->grp = grp;
647 }
648
649 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
650 grp->num_tx_queues++;
651 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
652 priv->tqueue |= (TQUEUE_EN0 >> i);
653 priv->tx_queue[i]->grp = grp;
654 }
655
656 priv->num_grps++;
657
658 return 0;
659}
660
661static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
662{
663 const char *model;
664 const char *ctype;
665 const void *mac_addr;
666 int err = 0, i;
667 struct net_device *dev = NULL;
668 struct gfar_private *priv = NULL;
669 struct device_node *np = ofdev->dev.of_node;
670 struct device_node *child = NULL;
671 const u32 *stash;
672 const u32 *stash_len;
673 const u32 *stash_idx;
674 unsigned int num_tx_qs, num_rx_qs;
675 u32 *tx_queues, *rx_queues;
676
677 if (!np || !of_device_is_available(np))
678 return -ENODEV;
679
680 /* parse the num of tx and rx queues */
681 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
682 num_tx_qs = tx_queues ? *tx_queues : 1;
683
684 if (num_tx_qs > MAX_TX_QS) {
685 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
686 num_tx_qs, MAX_TX_QS);
687 pr_err("Cannot do alloc_etherdev, aborting\n");
688 return -EINVAL;
689 }
690
691 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
692 num_rx_qs = rx_queues ? *rx_queues : 1;
693
694 if (num_rx_qs > MAX_RX_QS) {
695 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
696 num_rx_qs, MAX_RX_QS);
697 pr_err("Cannot do alloc_etherdev, aborting\n");
698 return -EINVAL;
699 }
700
701 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
702 dev = *pdev;
703 if (NULL == dev)
704 return -ENOMEM;
705
706 priv = netdev_priv(dev);
707 priv->ndev = dev;
708
709 priv->num_tx_queues = num_tx_qs;
710 netif_set_real_num_rx_queues(dev, num_rx_qs);
711 priv->num_rx_queues = num_rx_qs;
712
713 err = gfar_alloc_tx_queues(priv);
714 if (err)
715 goto tx_alloc_failed;
716
717 err = gfar_alloc_rx_queues(priv);
718 if (err)
719 goto rx_alloc_failed;
720
721 /* Init Rx queue filer rule set linked list */
722 INIT_LIST_HEAD(&priv->rx_list.list);
723 priv->rx_list.count = 0;
724 mutex_init(&priv->rx_queue_access);
725
726 model = of_get_property(np, "model", NULL);
727
728 for (i = 0; i < MAXGROUPS; i++)
729 priv->gfargrp[i].regs = NULL;
730
731 /* Parse and initialize group specific information */
732 if (of_device_is_compatible(np, "fsl,etsec2")) {
733 priv->mode = MQ_MG_MODE;
734 for_each_child_of_node(np, child) {
735 err = gfar_parse_group(child, priv, model);
736 if (err)
737 goto err_grp_init;
738 }
739 } else {
740 priv->mode = SQ_SG_MODE;
741 err = gfar_parse_group(np, priv, model);
742 if (err)
743 goto err_grp_init;
744 }
745
746 stash = of_get_property(np, "bd-stash", NULL);
747
748 if (stash) {
749 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
750 priv->bd_stash_en = 1;
751 }
752
753 stash_len = of_get_property(np, "rx-stash-len", NULL);
754
755 if (stash_len)
756 priv->rx_stash_size = *stash_len;
757
758 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
759
760 if (stash_idx)
761 priv->rx_stash_index = *stash_idx;
762
763 if (stash_len || stash_idx)
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
765
766 mac_addr = of_get_mac_address(np);
767
768 if (mac_addr)
769 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
770
771 if (model && !strcasecmp(model, "TSEC"))
772 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
773 FSL_GIANFAR_DEV_HAS_COALESCE |
774 FSL_GIANFAR_DEV_HAS_RMON |
775 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
776
777 if (model && !strcasecmp(model, "eTSEC"))
778 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
779 FSL_GIANFAR_DEV_HAS_COALESCE |
780 FSL_GIANFAR_DEV_HAS_RMON |
781 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
782 FSL_GIANFAR_DEV_HAS_CSUM |
783 FSL_GIANFAR_DEV_HAS_VLAN |
784 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
785 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
786 FSL_GIANFAR_DEV_HAS_TIMER;
787
788 ctype = of_get_property(np, "phy-connection-type", NULL);
789
790 /* We only care about rgmii-id. The rest are autodetected */
791 if (ctype && !strcmp(ctype, "rgmii-id"))
792 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
793 else
794 priv->interface = PHY_INTERFACE_MODE_MII;
795
796 if (of_get_property(np, "fsl,magic-packet", NULL))
797 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
798
799 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
800
801 /* Find the TBI PHY. If it's not there, we don't support SGMII */
802 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
803
804 return 0;
805
806err_grp_init:
807 unmap_group_regs(priv);
808rx_alloc_failed:
809 gfar_free_rx_queues(priv);
810tx_alloc_failed:
811 gfar_free_tx_queues(priv);
812 free_gfar_dev(priv);
813 return err;
814}
815
816static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
817{
818 struct hwtstamp_config config;
819 struct gfar_private *priv = netdev_priv(netdev);
820
821 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
822 return -EFAULT;
823
824 /* reserved for future extensions */
825 if (config.flags)
826 return -EINVAL;
827
828 switch (config.tx_type) {
829 case HWTSTAMP_TX_OFF:
830 priv->hwts_tx_en = 0;
831 break;
832 case HWTSTAMP_TX_ON:
833 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
834 return -ERANGE;
835 priv->hwts_tx_en = 1;
836 break;
837 default:
838 return -ERANGE;
839 }
840
841 switch (config.rx_filter) {
842 case HWTSTAMP_FILTER_NONE:
843 if (priv->hwts_rx_en) {
844 stop_gfar(netdev);
845 priv->hwts_rx_en = 0;
846 startup_gfar(netdev);
847 }
848 break;
849 default:
850 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
851 return -ERANGE;
852 if (!priv->hwts_rx_en) {
853 stop_gfar(netdev);
854 priv->hwts_rx_en = 1;
855 startup_gfar(netdev);
856 }
857 config.rx_filter = HWTSTAMP_FILTER_ALL;
858 break;
859 }
860
861 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
862 -EFAULT : 0;
863}
864
865static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
866{
867 struct hwtstamp_config config;
868 struct gfar_private *priv = netdev_priv(netdev);
869
870 config.flags = 0;
871 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
872 config.rx_filter = (priv->hwts_rx_en ?
873 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
874
875 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
876 -EFAULT : 0;
877}
878
879static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
880{
881 struct gfar_private *priv = netdev_priv(dev);
882
883 if (!netif_running(dev))
884 return -EINVAL;
885
886 if (cmd == SIOCSHWTSTAMP)
887 return gfar_hwtstamp_set(dev, rq);
888 if (cmd == SIOCGHWTSTAMP)
889 return gfar_hwtstamp_get(dev, rq);
890
891 if (!priv->phydev)
892 return -ENODEV;
893
894 return phy_mii_ioctl(priv->phydev, rq, cmd);
895}
896
897static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
898 u32 class)
899{
900 u32 rqfpr = FPR_FILER_MASK;
901 u32 rqfcr = 0x0;
902
903 rqfar--;
904 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
905 priv->ftp_rqfpr[rqfar] = rqfpr;
906 priv->ftp_rqfcr[rqfar] = rqfcr;
907 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
908
909 rqfar--;
910 rqfcr = RQFCR_CMP_NOMATCH;
911 priv->ftp_rqfpr[rqfar] = rqfpr;
912 priv->ftp_rqfcr[rqfar] = rqfcr;
913 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
914
915 rqfar--;
916 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
917 rqfpr = class;
918 priv->ftp_rqfcr[rqfar] = rqfcr;
919 priv->ftp_rqfpr[rqfar] = rqfpr;
920 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
921
922 rqfar--;
923 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
924 rqfpr = class;
925 priv->ftp_rqfcr[rqfar] = rqfcr;
926 priv->ftp_rqfpr[rqfar] = rqfpr;
927 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
928
929 return rqfar;
930}
931
932static void gfar_init_filer_table(struct gfar_private *priv)
933{
934 int i = 0x0;
935 u32 rqfar = MAX_FILER_IDX;
936 u32 rqfcr = 0x0;
937 u32 rqfpr = FPR_FILER_MASK;
938
939 /* Default rule */
940 rqfcr = RQFCR_CMP_MATCH;
941 priv->ftp_rqfcr[rqfar] = rqfcr;
942 priv->ftp_rqfpr[rqfar] = rqfpr;
943 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
944
945 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
946 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
947 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
948 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
949 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
950 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
951
952 /* cur_filer_idx indicated the first non-masked rule */
953 priv->cur_filer_idx = rqfar;
954
955 /* Rest are masked rules */
956 rqfcr = RQFCR_CMP_NOMATCH;
957 for (i = 0; i < rqfar; i++) {
958 priv->ftp_rqfcr[i] = rqfcr;
959 priv->ftp_rqfpr[i] = rqfpr;
960 gfar_write_filer(priv, i, rqfcr, rqfpr);
961 }
962}
963
964static void __gfar_detect_errata_83xx(struct gfar_private *priv)
965{
966 unsigned int pvr = mfspr(SPRN_PVR);
967 unsigned int svr = mfspr(SPRN_SVR);
968 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
969 unsigned int rev = svr & 0xffff;
970
971 /* MPC8313 Rev 2.0 and higher; All MPC837x */
972 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
973 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
974 priv->errata |= GFAR_ERRATA_74;
975
976 /* MPC8313 and MPC837x all rev */
977 if ((pvr == 0x80850010 && mod == 0x80b0) ||
978 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
979 priv->errata |= GFAR_ERRATA_76;
980
981 /* MPC8313 Rev < 2.0 */
982 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
983 priv->errata |= GFAR_ERRATA_12;
984}
985
986static void __gfar_detect_errata_85xx(struct gfar_private *priv)
987{
988 unsigned int svr = mfspr(SPRN_SVR);
989
990 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
991 priv->errata |= GFAR_ERRATA_12;
992 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
993 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
994 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
995}
996
997static void gfar_detect_errata(struct gfar_private *priv)
998{
999 struct device *dev = &priv->ofdev->dev;
1000
1001 /* no plans to fix */
1002 priv->errata |= GFAR_ERRATA_A002;
1003
1004 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1005 __gfar_detect_errata_85xx(priv);
1006 else /* non-mpc85xx parts, i.e. e300 core based */
1007 __gfar_detect_errata_83xx(priv);
1008
1009 if (priv->errata)
1010 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1011 priv->errata);
1012}
1013
1014static void gfar_mac_reset(struct gfar_private *priv)
1015{
1016 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1017 u32 tempval;
1018
1019 /* Reset MAC layer */
1020 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1021
1022 /* We need to delay at least 3 TX clocks */
1023 udelay(3);
1024
1025 /* the soft reset bit is not self-resetting, so we need to
1026 * clear it before resuming normal operation
1027 */
1028 gfar_write(&regs->maccfg1, 0);
1029
1030 udelay(3);
1031
1032 /* Initialize the max receive buffer length */
1033 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1034
1035 /* Initialize the Minimum Frame Length Register */
1036 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1037
1038 /* Initialize MACCFG2. */
1039 tempval = MACCFG2_INIT_SETTINGS;
1040 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1041 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1042 gfar_write(&regs->maccfg2, tempval);
1043
1044 /* Clear mac addr hash registers */
1045 gfar_write(&regs->igaddr0, 0);
1046 gfar_write(&regs->igaddr1, 0);
1047 gfar_write(&regs->igaddr2, 0);
1048 gfar_write(&regs->igaddr3, 0);
1049 gfar_write(&regs->igaddr4, 0);
1050 gfar_write(&regs->igaddr5, 0);
1051 gfar_write(&regs->igaddr6, 0);
1052 gfar_write(&regs->igaddr7, 0);
1053
1054 gfar_write(&regs->gaddr0, 0);
1055 gfar_write(&regs->gaddr1, 0);
1056 gfar_write(&regs->gaddr2, 0);
1057 gfar_write(&regs->gaddr3, 0);
1058 gfar_write(&regs->gaddr4, 0);
1059 gfar_write(&regs->gaddr5, 0);
1060 gfar_write(&regs->gaddr6, 0);
1061 gfar_write(&regs->gaddr7, 0);
1062
1063 if (priv->extended_hash)
1064 gfar_clear_exact_match(priv->ndev);
1065
1066 gfar_mac_rx_config(priv);
1067
1068 gfar_mac_tx_config(priv);
1069
1070 gfar_set_mac_address(priv->ndev);
1071
1072 gfar_set_multi(priv->ndev);
1073
1074 /* clear ievent and imask before configuring coalescing */
1075 gfar_ints_disable(priv);
1076
1077 /* Configure the coalescing support */
1078 gfar_configure_coalescing_all(priv);
1079}
1080
1081static void gfar_hw_init(struct gfar_private *priv)
1082{
1083 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1084 u32 attrs;
1085
1086 /* Stop the DMA engine now, in case it was running before
1087 * (The firmware could have used it, and left it running).
1088 */
1089 gfar_halt(priv);
1090
1091 gfar_mac_reset(priv);
1092
1093 /* Zero out the rmon mib registers if it has them */
1094 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1095 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1096
1097 /* Mask off the CAM interrupts */
1098 gfar_write(&regs->rmon.cam1, 0xffffffff);
1099 gfar_write(&regs->rmon.cam2, 0xffffffff);
1100 }
1101
1102 /* Initialize ECNTRL */
1103 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1104
1105 /* Set the extraction length and index */
1106 attrs = ATTRELI_EL(priv->rx_stash_size) |
1107 ATTRELI_EI(priv->rx_stash_index);
1108
1109 gfar_write(&regs->attreli, attrs);
1110
1111 /* Start with defaults, and add stashing
1112 * depending on driver parameters
1113 */
1114 attrs = ATTR_INIT_SETTINGS;
1115
1116 if (priv->bd_stash_en)
1117 attrs |= ATTR_BDSTASH;
1118
1119 if (priv->rx_stash_size != 0)
1120 attrs |= ATTR_BUFSTASH;
1121
1122 gfar_write(&regs->attr, attrs);
1123
1124 /* FIFO configs */
1125 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1126 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1127 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1128
1129 /* Program the interrupt steering regs, only for MG devices */
1130 if (priv->num_grps > 1)
1131 gfar_write_isrg(priv);
1132}
1133
1134static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
1135{
1136 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1137
1138 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1139 priv->extended_hash = 1;
1140 priv->hash_width = 9;
1141
1142 priv->hash_regs[0] = &regs->igaddr0;
1143 priv->hash_regs[1] = &regs->igaddr1;
1144 priv->hash_regs[2] = &regs->igaddr2;
1145 priv->hash_regs[3] = &regs->igaddr3;
1146 priv->hash_regs[4] = &regs->igaddr4;
1147 priv->hash_regs[5] = &regs->igaddr5;
1148 priv->hash_regs[6] = &regs->igaddr6;
1149 priv->hash_regs[7] = &regs->igaddr7;
1150 priv->hash_regs[8] = &regs->gaddr0;
1151 priv->hash_regs[9] = &regs->gaddr1;
1152 priv->hash_regs[10] = &regs->gaddr2;
1153 priv->hash_regs[11] = &regs->gaddr3;
1154 priv->hash_regs[12] = &regs->gaddr4;
1155 priv->hash_regs[13] = &regs->gaddr5;
1156 priv->hash_regs[14] = &regs->gaddr6;
1157 priv->hash_regs[15] = &regs->gaddr7;
1158
1159 } else {
1160 priv->extended_hash = 0;
1161 priv->hash_width = 8;
1162
1163 priv->hash_regs[0] = &regs->gaddr0;
1164 priv->hash_regs[1] = &regs->gaddr1;
1165 priv->hash_regs[2] = &regs->gaddr2;
1166 priv->hash_regs[3] = &regs->gaddr3;
1167 priv->hash_regs[4] = &regs->gaddr4;
1168 priv->hash_regs[5] = &regs->gaddr5;
1169 priv->hash_regs[6] = &regs->gaddr6;
1170 priv->hash_regs[7] = &regs->gaddr7;
1171 }
1172}
1173
1174/* Set up the ethernet device structure, private data,
1175 * and anything else we need before we start
1176 */
1177static int gfar_probe(struct platform_device *ofdev)
1178{
1179 struct net_device *dev = NULL;
1180 struct gfar_private *priv = NULL;
1181 int err = 0, i;
1182
1183 err = gfar_of_init(ofdev, &dev);
1184
1185 if (err)
1186 return err;
1187
1188 priv = netdev_priv(dev);
1189 priv->ndev = dev;
1190 priv->ofdev = ofdev;
1191 priv->dev = &ofdev->dev;
1192 SET_NETDEV_DEV(dev, &ofdev->dev);
1193
1194 spin_lock_init(&priv->bflock);
1195 INIT_WORK(&priv->reset_task, gfar_reset_task);
1196
1197 platform_set_drvdata(ofdev, priv);
1198
1199 gfar_detect_errata(priv);
1200
1201 /* Set the dev->base_addr to the gfar reg region */
1202 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1203
1204 /* Fill in the dev structure */
1205 dev->watchdog_timeo = TX_TIMEOUT;
1206 dev->mtu = 1500;
1207 dev->netdev_ops = &gfar_netdev_ops;
1208 dev->ethtool_ops = &gfar_ethtool_ops;
1209
1210 /* Register for napi ...We are registering NAPI for each grp */
1211 if (priv->mode == SQ_SG_MODE)
1212 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1213 GFAR_DEV_WEIGHT);
1214 else
1215 for (i = 0; i < priv->num_grps; i++)
1216 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1217 GFAR_DEV_WEIGHT);
1218
1219 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1220 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1221 NETIF_F_RXCSUM;
1222 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1223 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1224 }
1225
1226 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1227 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1228 NETIF_F_HW_VLAN_CTAG_RX;
1229 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1230 }
1231
1232 gfar_init_addr_hash_table(priv);
1233
1234 /* Insert receive time stamps into padding alignment bytes */
1235 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1236 priv->padding = 8;
1237
1238 if (dev->features & NETIF_F_IP_CSUM ||
1239 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1240 dev->needed_headroom = GMAC_FCB_LEN;
1241
1242 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1243
1244 /* Initializing some of the rx/tx queue level parameters */
1245 for (i = 0; i < priv->num_tx_queues; i++) {
1246 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1247 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1248 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1249 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1250 }
1251
1252 for (i = 0; i < priv->num_rx_queues; i++) {
1253 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1254 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1255 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1256 }
1257
1258 /* always enable rx filer */
1259 priv->rx_filer_enable = 1;
1260 /* Enable most messages by default */
1261 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1262 /* use pritority h/w tx queue scheduling for single queue devices */
1263 if (priv->num_tx_queues == 1)
1264 priv->prio_sched_en = 1;
1265
1266 gfar_hw_init(priv);
1267
1268 err = register_netdev(dev);
1269
1270 if (err) {
1271 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1272 goto register_fail;
1273 }
1274
1275 /* Carrier starts down, phylib will bring it up */
1276 netif_carrier_off(dev);
1277
1278 device_init_wakeup(&dev->dev,
1279 priv->device_flags &
1280 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1281
1282 /* fill out IRQ number and name fields */
1283 for (i = 0; i < priv->num_grps; i++) {
1284 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1285 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1286 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1287 dev->name, "_g", '0' + i, "_tx");
1288 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1289 dev->name, "_g", '0' + i, "_rx");
1290 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1291 dev->name, "_g", '0' + i, "_er");
1292 } else
1293 strcpy(gfar_irq(grp, TX)->name, dev->name);
1294 }
1295
1296 /* Initialize the filer table */
1297 gfar_init_filer_table(priv);
1298
1299 /* Print out the device info */
1300 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1301
1302 /* Even more device info helps when determining which kernel
1303 * provided which set of benchmarks.
1304 */
1305 netdev_info(dev, "Running with NAPI enabled\n");
1306 for (i = 0; i < priv->num_rx_queues; i++)
1307 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1308 i, priv->rx_queue[i]->rx_ring_size);
1309 for (i = 0; i < priv->num_tx_queues; i++)
1310 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1311 i, priv->tx_queue[i]->tx_ring_size);
1312
1313 return 0;
1314
1315register_fail:
1316 unmap_group_regs(priv);
1317 gfar_free_rx_queues(priv);
1318 gfar_free_tx_queues(priv);
1319 if (priv->phy_node)
1320 of_node_put(priv->phy_node);
1321 if (priv->tbi_node)
1322 of_node_put(priv->tbi_node);
1323 free_gfar_dev(priv);
1324 return err;
1325}
1326
1327static int gfar_remove(struct platform_device *ofdev)
1328{
1329 struct gfar_private *priv = platform_get_drvdata(ofdev);
1330
1331 if (priv->phy_node)
1332 of_node_put(priv->phy_node);
1333 if (priv->tbi_node)
1334 of_node_put(priv->tbi_node);
1335
1336 unregister_netdev(priv->ndev);
1337 unmap_group_regs(priv);
1338 gfar_free_rx_queues(priv);
1339 gfar_free_tx_queues(priv);
1340 free_gfar_dev(priv);
1341
1342 return 0;
1343}
1344
1345#ifdef CONFIG_PM
1346
1347static int gfar_suspend(struct device *dev)
1348{
1349 struct gfar_private *priv = dev_get_drvdata(dev);
1350 struct net_device *ndev = priv->ndev;
1351 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1352 unsigned long flags;
1353 u32 tempval;
1354
1355 int magic_packet = priv->wol_en &&
1356 (priv->device_flags &
1357 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1358
1359 netif_device_detach(ndev);
1360
1361 if (netif_running(ndev)) {
1362
1363 local_irq_save(flags);
1364 lock_tx_qs(priv);
1365 lock_rx_qs(priv);
1366
1367 gfar_halt_nodisable(priv);
1368
1369 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1370 tempval = gfar_read(&regs->maccfg1);
1371
1372 tempval &= ~MACCFG1_TX_EN;
1373
1374 if (!magic_packet)
1375 tempval &= ~MACCFG1_RX_EN;
1376
1377 gfar_write(&regs->maccfg1, tempval);
1378
1379 unlock_rx_qs(priv);
1380 unlock_tx_qs(priv);
1381 local_irq_restore(flags);
1382
1383 disable_napi(priv);
1384
1385 if (magic_packet) {
1386 /* Enable interrupt on Magic Packet */
1387 gfar_write(&regs->imask, IMASK_MAG);
1388
1389 /* Enable Magic Packet mode */
1390 tempval = gfar_read(&regs->maccfg2);
1391 tempval |= MACCFG2_MPEN;
1392 gfar_write(&regs->maccfg2, tempval);
1393 } else {
1394 phy_stop(priv->phydev);
1395 }
1396 }
1397
1398 return 0;
1399}
1400
1401static int gfar_resume(struct device *dev)
1402{
1403 struct gfar_private *priv = dev_get_drvdata(dev);
1404 struct net_device *ndev = priv->ndev;
1405 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1406 unsigned long flags;
1407 u32 tempval;
1408 int magic_packet = priv->wol_en &&
1409 (priv->device_flags &
1410 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1411
1412 if (!netif_running(ndev)) {
1413 netif_device_attach(ndev);
1414 return 0;
1415 }
1416
1417 if (!magic_packet && priv->phydev)
1418 phy_start(priv->phydev);
1419
1420 /* Disable Magic Packet mode, in case something
1421 * else woke us up.
1422 */
1423 local_irq_save(flags);
1424 lock_tx_qs(priv);
1425 lock_rx_qs(priv);
1426
1427 tempval = gfar_read(&regs->maccfg2);
1428 tempval &= ~MACCFG2_MPEN;
1429 gfar_write(&regs->maccfg2, tempval);
1430
1431 gfar_start(priv);
1432
1433 unlock_rx_qs(priv);
1434 unlock_tx_qs(priv);
1435 local_irq_restore(flags);
1436
1437 netif_device_attach(ndev);
1438
1439 enable_napi(priv);
1440
1441 return 0;
1442}
1443
1444static int gfar_restore(struct device *dev)
1445{
1446 struct gfar_private *priv = dev_get_drvdata(dev);
1447 struct net_device *ndev = priv->ndev;
1448
1449 if (!netif_running(ndev)) {
1450 netif_device_attach(ndev);
1451
1452 return 0;
1453 }
1454
1455 if (gfar_init_bds(ndev)) {
1456 free_skb_resources(priv);
1457 return -ENOMEM;
1458 }
1459
1460 gfar_mac_reset(priv);
1461
1462 gfar_init_tx_rx_base(priv);
1463
1464 gfar_start(priv);
1465
1466 priv->oldlink = 0;
1467 priv->oldspeed = 0;
1468 priv->oldduplex = -1;
1469
1470 if (priv->phydev)
1471 phy_start(priv->phydev);
1472
1473 netif_device_attach(ndev);
1474 enable_napi(priv);
1475
1476 return 0;
1477}
1478
1479static struct dev_pm_ops gfar_pm_ops = {
1480 .suspend = gfar_suspend,
1481 .resume = gfar_resume,
1482 .freeze = gfar_suspend,
1483 .thaw = gfar_resume,
1484 .restore = gfar_restore,
1485};
1486
1487#define GFAR_PM_OPS (&gfar_pm_ops)
1488
1489#else
1490
1491#define GFAR_PM_OPS NULL
1492
1493#endif
1494
1495/* Reads the controller's registers to determine what interface
1496 * connects it to the PHY.
1497 */
1498static phy_interface_t gfar_get_interface(struct net_device *dev)
1499{
1500 struct gfar_private *priv = netdev_priv(dev);
1501 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1502 u32 ecntrl;
1503
1504 ecntrl = gfar_read(&regs->ecntrl);
1505
1506 if (ecntrl & ECNTRL_SGMII_MODE)
1507 return PHY_INTERFACE_MODE_SGMII;
1508
1509 if (ecntrl & ECNTRL_TBI_MODE) {
1510 if (ecntrl & ECNTRL_REDUCED_MODE)
1511 return PHY_INTERFACE_MODE_RTBI;
1512 else
1513 return PHY_INTERFACE_MODE_TBI;
1514 }
1515
1516 if (ecntrl & ECNTRL_REDUCED_MODE) {
1517 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1518 return PHY_INTERFACE_MODE_RMII;
1519 }
1520 else {
1521 phy_interface_t interface = priv->interface;
1522
1523 /* This isn't autodetected right now, so it must
1524 * be set by the device tree or platform code.
1525 */
1526 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1527 return PHY_INTERFACE_MODE_RGMII_ID;
1528
1529 return PHY_INTERFACE_MODE_RGMII;
1530 }
1531 }
1532
1533 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1534 return PHY_INTERFACE_MODE_GMII;
1535
1536 return PHY_INTERFACE_MODE_MII;
1537}
1538
1539
1540/* Initializes driver's PHY state, and attaches to the PHY.
1541 * Returns 0 on success.
1542 */
1543static int init_phy(struct net_device *dev)
1544{
1545 struct gfar_private *priv = netdev_priv(dev);
1546 uint gigabit_support =
1547 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1548 GFAR_SUPPORTED_GBIT : 0;
1549 phy_interface_t interface;
1550
1551 priv->oldlink = 0;
1552 priv->oldspeed = 0;
1553 priv->oldduplex = -1;
1554
1555 interface = gfar_get_interface(dev);
1556
1557 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1558 interface);
1559 if (!priv->phydev)
1560 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1561 interface);
1562 if (!priv->phydev) {
1563 dev_err(&dev->dev, "could not attach to PHY\n");
1564 return -ENODEV;
1565 }
1566
1567 if (interface == PHY_INTERFACE_MODE_SGMII)
1568 gfar_configure_serdes(dev);
1569
1570 /* Remove any features not supported by the controller */
1571 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1572 priv->phydev->advertising = priv->phydev->supported;
1573
1574 return 0;
1575}
1576
1577/* Initialize TBI PHY interface for communicating with the
1578 * SERDES lynx PHY on the chip. We communicate with this PHY
1579 * through the MDIO bus on each controller, treating it as a
1580 * "normal" PHY at the address found in the TBIPA register. We assume
1581 * that the TBIPA register is valid. Either the MDIO bus code will set
1582 * it to a value that doesn't conflict with other PHYs on the bus, or the
1583 * value doesn't matter, as there are no other PHYs on the bus.
1584 */
1585static void gfar_configure_serdes(struct net_device *dev)
1586{
1587 struct gfar_private *priv = netdev_priv(dev);
1588 struct phy_device *tbiphy;
1589
1590 if (!priv->tbi_node) {
1591 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1592 "device tree specify a tbi-handle\n");
1593 return;
1594 }
1595
1596 tbiphy = of_phy_find_device(priv->tbi_node);
1597 if (!tbiphy) {
1598 dev_err(&dev->dev, "error: Could not get TBI device\n");
1599 return;
1600 }
1601
1602 /* If the link is already up, we must already be ok, and don't need to
1603 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1604 * everything for us? Resetting it takes the link down and requires
1605 * several seconds for it to come back.
1606 */
1607 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1608 return;
1609
1610 /* Single clk mode, mii mode off(for serdes communication) */
1611 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1612
1613 phy_write(tbiphy, MII_ADVERTISE,
1614 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1615 ADVERTISE_1000XPSE_ASYM);
1616
1617 phy_write(tbiphy, MII_BMCR,
1618 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1619 BMCR_SPEED1000);
1620}
1621
1622static int __gfar_is_rx_idle(struct gfar_private *priv)
1623{
1624 u32 res;
1625
1626 /* Normaly TSEC should not hang on GRS commands, so we should
1627 * actually wait for IEVENT_GRSC flag.
1628 */
1629 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1630 return 0;
1631
1632 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1633 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1634 * and the Rx can be safely reset.
1635 */
1636 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1637 res &= 0x7f807f80;
1638 if ((res & 0xffff) == (res >> 16))
1639 return 1;
1640
1641 return 0;
1642}
1643
1644/* Halt the receive and transmit queues */
1645static void gfar_halt_nodisable(struct gfar_private *priv)
1646{
1647 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1648 u32 tempval;
1649
1650 gfar_ints_disable(priv);
1651
1652 /* Stop the DMA, and wait for it to stop */
1653 tempval = gfar_read(&regs->dmactrl);
1654 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1655 (DMACTRL_GRS | DMACTRL_GTS)) {
1656 int ret;
1657
1658 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1659 gfar_write(&regs->dmactrl, tempval);
1660
1661 do {
1662 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1663 (IEVENT_GRSC | IEVENT_GTSC)) ==
1664 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1665 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1666 ret = __gfar_is_rx_idle(priv);
1667 } while (!ret);
1668 }
1669}
1670
1671/* Halt the receive and transmit queues */
1672void gfar_halt(struct gfar_private *priv)
1673{
1674 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1675 u32 tempval;
1676
1677 /* Dissable the Rx/Tx hw queues */
1678 gfar_write(&regs->rqueue, 0);
1679 gfar_write(&regs->tqueue, 0);
1680
1681 mdelay(10);
1682
1683 gfar_halt_nodisable(priv);
1684
1685 /* Disable Rx/Tx DMA */
1686 tempval = gfar_read(&regs->maccfg1);
1687 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1688 gfar_write(&regs->maccfg1, tempval);
1689}
1690
1691static void free_grp_irqs(struct gfar_priv_grp *grp)
1692{
1693 free_irq(gfar_irq(grp, TX)->irq, grp);
1694 free_irq(gfar_irq(grp, RX)->irq, grp);
1695 free_irq(gfar_irq(grp, ER)->irq, grp);
1696}
1697
1698void stop_gfar(struct net_device *dev)
1699{
1700 struct gfar_private *priv = netdev_priv(dev);
1701 unsigned long flags;
1702 int i;
1703
1704 phy_stop(priv->phydev);
1705
1706
1707 /* Lock it down */
1708 local_irq_save(flags);
1709 lock_tx_qs(priv);
1710 lock_rx_qs(priv);
1711
1712 gfar_halt(priv);
1713
1714 unlock_rx_qs(priv);
1715 unlock_tx_qs(priv);
1716 local_irq_restore(flags);
1717
1718 /* Free the IRQs */
1719 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1720 for (i = 0; i < priv->num_grps; i++)
1721 free_grp_irqs(&priv->gfargrp[i]);
1722 } else {
1723 for (i = 0; i < priv->num_grps; i++)
1724 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1725 &priv->gfargrp[i]);
1726 }
1727
1728 free_skb_resources(priv);
1729}
1730
1731static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1732{
1733 struct txbd8 *txbdp;
1734 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1735 int i, j;
1736
1737 txbdp = tx_queue->tx_bd_base;
1738
1739 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1740 if (!tx_queue->tx_skbuff[i])
1741 continue;
1742
1743 dma_unmap_single(priv->dev, txbdp->bufPtr,
1744 txbdp->length, DMA_TO_DEVICE);
1745 txbdp->lstatus = 0;
1746 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1747 j++) {
1748 txbdp++;
1749 dma_unmap_page(priv->dev, txbdp->bufPtr,
1750 txbdp->length, DMA_TO_DEVICE);
1751 }
1752 txbdp++;
1753 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1754 tx_queue->tx_skbuff[i] = NULL;
1755 }
1756 kfree(tx_queue->tx_skbuff);
1757 tx_queue->tx_skbuff = NULL;
1758}
1759
1760static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1761{
1762 struct rxbd8 *rxbdp;
1763 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1764 int i;
1765
1766 rxbdp = rx_queue->rx_bd_base;
1767
1768 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1769 if (rx_queue->rx_skbuff[i]) {
1770 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1771 priv->rx_buffer_size,
1772 DMA_FROM_DEVICE);
1773 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1774 rx_queue->rx_skbuff[i] = NULL;
1775 }
1776 rxbdp->lstatus = 0;
1777 rxbdp->bufPtr = 0;
1778 rxbdp++;
1779 }
1780 kfree(rx_queue->rx_skbuff);
1781 rx_queue->rx_skbuff = NULL;
1782}
1783
1784/* If there are any tx skbs or rx skbs still around, free them.
1785 * Then free tx_skbuff and rx_skbuff
1786 */
1787static void free_skb_resources(struct gfar_private *priv)
1788{
1789 struct gfar_priv_tx_q *tx_queue = NULL;
1790 struct gfar_priv_rx_q *rx_queue = NULL;
1791 int i;
1792
1793 /* Go through all the buffer descriptors and free their data buffers */
1794 for (i = 0; i < priv->num_tx_queues; i++) {
1795 struct netdev_queue *txq;
1796
1797 tx_queue = priv->tx_queue[i];
1798 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1799 if (tx_queue->tx_skbuff)
1800 free_skb_tx_queue(tx_queue);
1801 netdev_tx_reset_queue(txq);
1802 }
1803
1804 for (i = 0; i < priv->num_rx_queues; i++) {
1805 rx_queue = priv->rx_queue[i];
1806 if (rx_queue->rx_skbuff)
1807 free_skb_rx_queue(rx_queue);
1808 }
1809
1810 dma_free_coherent(priv->dev,
1811 sizeof(struct txbd8) * priv->total_tx_ring_size +
1812 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1813 priv->tx_queue[0]->tx_bd_base,
1814 priv->tx_queue[0]->tx_bd_dma_base);
1815}
1816
1817void gfar_start(struct gfar_private *priv)
1818{
1819 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1820 u32 tempval;
1821 int i = 0;
1822
1823 /* Enable Rx/Tx hw queues */
1824 gfar_write(&regs->rqueue, priv->rqueue);
1825 gfar_write(&regs->tqueue, priv->tqueue);
1826
1827 /* Initialize DMACTRL to have WWR and WOP */
1828 tempval = gfar_read(&regs->dmactrl);
1829 tempval |= DMACTRL_INIT_SETTINGS;
1830 gfar_write(&regs->dmactrl, tempval);
1831
1832 /* Make sure we aren't stopped */
1833 tempval = gfar_read(&regs->dmactrl);
1834 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1835 gfar_write(&regs->dmactrl, tempval);
1836
1837 for (i = 0; i < priv->num_grps; i++) {
1838 regs = priv->gfargrp[i].regs;
1839 /* Clear THLT/RHLT, so that the DMA starts polling now */
1840 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1841 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1842 }
1843
1844 /* Enable Rx/Tx DMA */
1845 tempval = gfar_read(&regs->maccfg1);
1846 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1847 gfar_write(&regs->maccfg1, tempval);
1848
1849 gfar_ints_enable(priv);
1850
1851 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1852}
1853
1854static void gfar_configure_coalescing(struct gfar_private *priv,
1855 unsigned long tx_mask, unsigned long rx_mask)
1856{
1857 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1858 u32 __iomem *baddr;
1859
1860 if (priv->mode == MQ_MG_MODE) {
1861 int i = 0;
1862
1863 baddr = &regs->txic0;
1864 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1865 gfar_write(baddr + i, 0);
1866 if (likely(priv->tx_queue[i]->txcoalescing))
1867 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1868 }
1869
1870 baddr = &regs->rxic0;
1871 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1872 gfar_write(baddr + i, 0);
1873 if (likely(priv->rx_queue[i]->rxcoalescing))
1874 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1875 }
1876 } else {
1877 /* Backward compatible case -- even if we enable
1878 * multiple queues, there's only single reg to program
1879 */
1880 gfar_write(&regs->txic, 0);
1881 if (likely(priv->tx_queue[0]->txcoalescing))
1882 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1883
1884 gfar_write(&regs->rxic, 0);
1885 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1886 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1887 }
1888}
1889
1890void gfar_configure_coalescing_all(struct gfar_private *priv)
1891{
1892 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1893}
1894
1895static int register_grp_irqs(struct gfar_priv_grp *grp)
1896{
1897 struct gfar_private *priv = grp->priv;
1898 struct net_device *dev = priv->ndev;
1899 int err;
1900
1901 /* If the device has multiple interrupts, register for
1902 * them. Otherwise, only register for the one
1903 */
1904 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1905 /* Install our interrupt handlers for Error,
1906 * Transmit, and Receive
1907 */
1908 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1909 gfar_irq(grp, ER)->name, grp);
1910 if (err < 0) {
1911 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1912 gfar_irq(grp, ER)->irq);
1913
1914 goto err_irq_fail;
1915 }
1916 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1917 gfar_irq(grp, TX)->name, grp);
1918 if (err < 0) {
1919 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1920 gfar_irq(grp, TX)->irq);
1921 goto tx_irq_fail;
1922 }
1923 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1924 gfar_irq(grp, RX)->name, grp);
1925 if (err < 0) {
1926 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1927 gfar_irq(grp, RX)->irq);
1928 goto rx_irq_fail;
1929 }
1930 } else {
1931 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1932 gfar_irq(grp, TX)->name, grp);
1933 if (err < 0) {
1934 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1935 gfar_irq(grp, TX)->irq);
1936 goto err_irq_fail;
1937 }
1938 }
1939
1940 return 0;
1941
1942rx_irq_fail:
1943 free_irq(gfar_irq(grp, TX)->irq, grp);
1944tx_irq_fail:
1945 free_irq(gfar_irq(grp, ER)->irq, grp);
1946err_irq_fail:
1947 return err;
1948
1949}
1950
1951/* Bring the controller up and running */
1952int startup_gfar(struct net_device *ndev)
1953{
1954 struct gfar_private *priv = netdev_priv(ndev);
1955 int err, i, j;
1956
1957 gfar_mac_reset(priv);
1958
1959 err = gfar_alloc_skb_resources(ndev);
1960 if (err)
1961 return err;
1962
1963 gfar_init_tx_rx_base(priv);
1964
1965 for (i = 0; i < priv->num_grps; i++) {
1966 err = register_grp_irqs(&priv->gfargrp[i]);
1967 if (err) {
1968 for (j = 0; j < i; j++)
1969 free_grp_irqs(&priv->gfargrp[j]);
1970 goto irq_fail;
1971 }
1972 }
1973
1974 /* Start the controller */
1975 gfar_start(priv);
1976
1977 phy_start(priv->phydev);
1978
1979 return 0;
1980
1981irq_fail:
1982 free_skb_resources(priv);
1983 return err;
1984}
1985
1986/* Called when something needs to use the ethernet device
1987 * Returns 0 for success.
1988 */
1989static int gfar_enet_open(struct net_device *dev)
1990{
1991 struct gfar_private *priv = netdev_priv(dev);
1992 int err;
1993
1994 enable_napi(priv);
1995
1996 err = init_phy(dev);
1997
1998 if (err) {
1999 disable_napi(priv);
2000 return err;
2001 }
2002
2003 err = startup_gfar(dev);
2004 if (err) {
2005 disable_napi(priv);
2006 return err;
2007 }
2008
2009 netif_tx_start_all_queues(dev);
2010
2011 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2012
2013 return err;
2014}
2015
2016static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2017{
2018 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2019
2020 memset(fcb, 0, GMAC_FCB_LEN);
2021
2022 return fcb;
2023}
2024
2025static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2026 int fcb_length)
2027{
2028 /* If we're here, it's a IP packet with a TCP or UDP
2029 * payload. We set it to checksum, using a pseudo-header
2030 * we provide
2031 */
2032 u8 flags = TXFCB_DEFAULT;
2033
2034 /* Tell the controller what the protocol is
2035 * And provide the already calculated phcs
2036 */
2037 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2038 flags |= TXFCB_UDP;
2039 fcb->phcs = udp_hdr(skb)->check;
2040 } else
2041 fcb->phcs = tcp_hdr(skb)->check;
2042
2043 /* l3os is the distance between the start of the
2044 * frame (skb->data) and the start of the IP hdr.
2045 * l4os is the distance between the start of the
2046 * l3 hdr and the l4 hdr
2047 */
2048 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2049 fcb->l4os = skb_network_header_len(skb);
2050
2051 fcb->flags = flags;
2052}
2053
2054void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2055{
2056 fcb->flags |= TXFCB_VLN;
2057 fcb->vlctl = vlan_tx_tag_get(skb);
2058}
2059
2060static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2061 struct txbd8 *base, int ring_size)
2062{
2063 struct txbd8 *new_bd = bdp + stride;
2064
2065 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2066}
2067
2068static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2069 int ring_size)
2070{
2071 return skip_txbd(bdp, 1, base, ring_size);
2072}
2073
2074/* eTSEC12: csum generation not supported for some fcb offsets */
2075static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2076 unsigned long fcb_addr)
2077{
2078 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2079 (fcb_addr % 0x20) > 0x18);
2080}
2081
2082/* eTSEC76: csum generation for frames larger than 2500 may
2083 * cause excess delays before start of transmission
2084 */
2085static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2086 unsigned int len)
2087{
2088 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2089 (len > 2500));
2090}
2091
2092/* This is called by the kernel when a frame is ready for transmission.
2093 * It is pointed to by the dev->hard_start_xmit function pointer
2094 */
2095static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2096{
2097 struct gfar_private *priv = netdev_priv(dev);
2098 struct gfar_priv_tx_q *tx_queue = NULL;
2099 struct netdev_queue *txq;
2100 struct gfar __iomem *regs = NULL;
2101 struct txfcb *fcb = NULL;
2102 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2103 u32 lstatus;
2104 int i, rq = 0;
2105 int do_tstamp, do_csum, do_vlan;
2106 u32 bufaddr;
2107 unsigned long flags;
2108 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2109
2110 rq = skb->queue_mapping;
2111 tx_queue = priv->tx_queue[rq];
2112 txq = netdev_get_tx_queue(dev, rq);
2113 base = tx_queue->tx_bd_base;
2114 regs = tx_queue->grp->regs;
2115
2116 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2117 do_vlan = vlan_tx_tag_present(skb);
2118 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2119 priv->hwts_tx_en;
2120
2121 if (do_csum || do_vlan)
2122 fcb_len = GMAC_FCB_LEN;
2123
2124 /* check if time stamp should be generated */
2125 if (unlikely(do_tstamp))
2126 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2127
2128 /* make space for additional header when fcb is needed */
2129 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2130 struct sk_buff *skb_new;
2131
2132 skb_new = skb_realloc_headroom(skb, fcb_len);
2133 if (!skb_new) {
2134 dev->stats.tx_errors++;
2135 kfree_skb(skb);
2136 return NETDEV_TX_OK;
2137 }
2138
2139 if (skb->sk)
2140 skb_set_owner_w(skb_new, skb->sk);
2141 consume_skb(skb);
2142 skb = skb_new;
2143 }
2144
2145 /* total number of fragments in the SKB */
2146 nr_frags = skb_shinfo(skb)->nr_frags;
2147
2148 /* calculate the required number of TxBDs for this skb */
2149 if (unlikely(do_tstamp))
2150 nr_txbds = nr_frags + 2;
2151 else
2152 nr_txbds = nr_frags + 1;
2153
2154 /* check if there is space to queue this packet */
2155 if (nr_txbds > tx_queue->num_txbdfree) {
2156 /* no space, stop the queue */
2157 netif_tx_stop_queue(txq);
2158 dev->stats.tx_fifo_errors++;
2159 return NETDEV_TX_BUSY;
2160 }
2161
2162 /* Update transmit stats */
2163 bytes_sent = skb->len;
2164 tx_queue->stats.tx_bytes += bytes_sent;
2165 /* keep Tx bytes on wire for BQL accounting */
2166 GFAR_CB(skb)->bytes_sent = bytes_sent;
2167 tx_queue->stats.tx_packets++;
2168
2169 txbdp = txbdp_start = tx_queue->cur_tx;
2170 lstatus = txbdp->lstatus;
2171
2172 /* Time stamp insertion requires one additional TxBD */
2173 if (unlikely(do_tstamp))
2174 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2175 tx_queue->tx_ring_size);
2176
2177 if (nr_frags == 0) {
2178 if (unlikely(do_tstamp))
2179 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2180 TXBD_INTERRUPT);
2181 else
2182 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2183 } else {
2184 /* Place the fragment addresses and lengths into the TxBDs */
2185 for (i = 0; i < nr_frags; i++) {
2186 unsigned int frag_len;
2187 /* Point at the next BD, wrapping as needed */
2188 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2189
2190 frag_len = skb_shinfo(skb)->frags[i].size;
2191
2192 lstatus = txbdp->lstatus | frag_len |
2193 BD_LFLAG(TXBD_READY);
2194
2195 /* Handle the last BD specially */
2196 if (i == nr_frags - 1)
2197 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2198
2199 bufaddr = skb_frag_dma_map(priv->dev,
2200 &skb_shinfo(skb)->frags[i],
2201 0,
2202 frag_len,
2203 DMA_TO_DEVICE);
2204
2205 /* set the TxBD length and buffer pointer */
2206 txbdp->bufPtr = bufaddr;
2207 txbdp->lstatus = lstatus;
2208 }
2209
2210 lstatus = txbdp_start->lstatus;
2211 }
2212
2213 /* Add TxPAL between FCB and frame if required */
2214 if (unlikely(do_tstamp)) {
2215 skb_push(skb, GMAC_TXPAL_LEN);
2216 memset(skb->data, 0, GMAC_TXPAL_LEN);
2217 }
2218
2219 /* Add TxFCB if required */
2220 if (fcb_len) {
2221 fcb = gfar_add_fcb(skb);
2222 lstatus |= BD_LFLAG(TXBD_TOE);
2223 }
2224
2225 /* Set up checksumming */
2226 if (do_csum) {
2227 gfar_tx_checksum(skb, fcb, fcb_len);
2228
2229 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2230 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2231 __skb_pull(skb, GMAC_FCB_LEN);
2232 skb_checksum_help(skb);
2233 if (do_vlan || do_tstamp) {
2234 /* put back a new fcb for vlan/tstamp TOE */
2235 fcb = gfar_add_fcb(skb);
2236 } else {
2237 /* Tx TOE not used */
2238 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2239 fcb = NULL;
2240 }
2241 }
2242 }
2243
2244 if (do_vlan)
2245 gfar_tx_vlan(skb, fcb);
2246
2247 /* Setup tx hardware time stamping if requested */
2248 if (unlikely(do_tstamp)) {
2249 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2250 fcb->ptp = 1;
2251 }
2252
2253 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2254 skb_headlen(skb), DMA_TO_DEVICE);
2255
2256 /* If time stamping is requested one additional TxBD must be set up. The
2257 * first TxBD points to the FCB and must have a data length of
2258 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2259 * the full frame length.
2260 */
2261 if (unlikely(do_tstamp)) {
2262 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2263 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2264 (skb_headlen(skb) - fcb_len);
2265 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2266 } else {
2267 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2268 }
2269
2270 netdev_tx_sent_queue(txq, bytes_sent);
2271
2272 /* We can work in parallel with gfar_clean_tx_ring(), except
2273 * when modifying num_txbdfree. Note that we didn't grab the lock
2274 * when we were reading the num_txbdfree and checking for available
2275 * space, that's because outside of this function it can only grow,
2276 * and once we've got needed space, it cannot suddenly disappear.
2277 *
2278 * The lock also protects us from gfar_error(), which can modify
2279 * regs->tstat and thus retrigger the transfers, which is why we
2280 * also must grab the lock before setting ready bit for the first
2281 * to be transmitted BD.
2282 */
2283 spin_lock_irqsave(&tx_queue->txlock, flags);
2284
2285 /* The powerpc-specific eieio() is used, as wmb() has too strong
2286 * semantics (it requires synchronization between cacheable and
2287 * uncacheable mappings, which eieio doesn't provide and which we
2288 * don't need), thus requiring a more expensive sync instruction. At
2289 * some point, the set of architecture-independent barrier functions
2290 * should be expanded to include weaker barriers.
2291 */
2292 eieio();
2293
2294 txbdp_start->lstatus = lstatus;
2295
2296 eieio(); /* force lstatus write before tx_skbuff */
2297
2298 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2299
2300 /* Update the current skb pointer to the next entry we will use
2301 * (wrapping if necessary)
2302 */
2303 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2304 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2305
2306 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2307
2308 /* reduce TxBD free count */
2309 tx_queue->num_txbdfree -= (nr_txbds);
2310
2311 /* If the next BD still needs to be cleaned up, then the bds
2312 * are full. We need to tell the kernel to stop sending us stuff.
2313 */
2314 if (!tx_queue->num_txbdfree) {
2315 netif_tx_stop_queue(txq);
2316
2317 dev->stats.tx_fifo_errors++;
2318 }
2319
2320 /* Tell the DMA to go go go */
2321 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2322
2323 /* Unlock priv */
2324 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2325
2326 return NETDEV_TX_OK;
2327}
2328
2329/* Stops the kernel queue, and halts the controller */
2330static int gfar_close(struct net_device *dev)
2331{
2332 struct gfar_private *priv = netdev_priv(dev);
2333
2334 disable_napi(priv);
2335
2336 cancel_work_sync(&priv->reset_task);
2337 stop_gfar(dev);
2338
2339 /* Disconnect from the PHY */
2340 phy_disconnect(priv->phydev);
2341 priv->phydev = NULL;
2342
2343 netif_tx_stop_all_queues(dev);
2344
2345 return 0;
2346}
2347
2348/* Changes the mac address if the controller is not running. */
2349static int gfar_set_mac_address(struct net_device *dev)
2350{
2351 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2352
2353 return 0;
2354}
2355
2356/* Check if rx parser should be activated */
2357void gfar_check_rx_parser_mode(struct gfar_private *priv)
2358{
2359 struct gfar __iomem *regs;
2360 u32 tempval;
2361
2362 regs = priv->gfargrp[0].regs;
2363
2364 tempval = gfar_read(&regs->rctrl);
2365 /* If parse is no longer required, then disable parser */
2366 if (tempval & RCTRL_REQ_PARSER) {
2367 tempval |= RCTRL_PRSDEP_INIT;
2368 priv->uses_rxfcb = 1;
2369 } else {
2370 tempval &= ~RCTRL_PRSDEP_INIT;
2371 priv->uses_rxfcb = 0;
2372 }
2373 gfar_write(&regs->rctrl, tempval);
2374}
2375
2376/* Enables and disables VLAN insertion/extraction */
2377void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2378{
2379 struct gfar_private *priv = netdev_priv(dev);
2380 struct gfar __iomem *regs = NULL;
2381 unsigned long flags;
2382 u32 tempval;
2383
2384 regs = priv->gfargrp[0].regs;
2385 local_irq_save(flags);
2386 lock_rx_qs(priv);
2387
2388 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2389 /* Enable VLAN tag insertion */
2390 tempval = gfar_read(&regs->tctrl);
2391 tempval |= TCTRL_VLINS;
2392 gfar_write(&regs->tctrl, tempval);
2393 } else {
2394 /* Disable VLAN tag insertion */
2395 tempval = gfar_read(&regs->tctrl);
2396 tempval &= ~TCTRL_VLINS;
2397 gfar_write(&regs->tctrl, tempval);
2398 }
2399
2400 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2401 /* Enable VLAN tag extraction */
2402 tempval = gfar_read(&regs->rctrl);
2403 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2404 gfar_write(&regs->rctrl, tempval);
2405 priv->uses_rxfcb = 1;
2406 } else {
2407 /* Disable VLAN tag extraction */
2408 tempval = gfar_read(&regs->rctrl);
2409 tempval &= ~RCTRL_VLEX;
2410 gfar_write(&regs->rctrl, tempval);
2411
2412 gfar_check_rx_parser_mode(priv);
2413 }
2414
2415 gfar_change_mtu(dev, dev->mtu);
2416
2417 unlock_rx_qs(priv);
2418 local_irq_restore(flags);
2419}
2420
2421static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2422{
2423 int tempsize, tempval;
2424 struct gfar_private *priv = netdev_priv(dev);
2425 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2426 int oldsize = priv->rx_buffer_size;
2427 int frame_size = new_mtu + ETH_HLEN;
2428
2429 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2430 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2431 return -EINVAL;
2432 }
2433
2434 if (priv->uses_rxfcb)
2435 frame_size += GMAC_FCB_LEN;
2436
2437 frame_size += priv->padding;
2438
2439 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2440 INCREMENTAL_BUFFER_SIZE;
2441
2442 /* Only stop and start the controller if it isn't already
2443 * stopped, and we changed something
2444 */
2445 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2446 stop_gfar(dev);
2447
2448 priv->rx_buffer_size = tempsize;
2449
2450 dev->mtu = new_mtu;
2451
2452 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2453 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2454
2455 /* If the mtu is larger than the max size for standard
2456 * ethernet frames (ie, a jumbo frame), then set maccfg2
2457 * to allow huge frames, and to check the length
2458 */
2459 tempval = gfar_read(&regs->maccfg2);
2460
2461 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2462 gfar_has_errata(priv, GFAR_ERRATA_74))
2463 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2464 else
2465 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2466
2467 gfar_write(&regs->maccfg2, tempval);
2468
2469 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2470 startup_gfar(dev);
2471
2472 return 0;
2473}
2474
2475/* gfar_reset_task gets scheduled when a packet has not been
2476 * transmitted after a set amount of time.
2477 * For now, assume that clearing out all the structures, and
2478 * starting over will fix the problem.
2479 */
2480static void gfar_reset_task(struct work_struct *work)
2481{
2482 struct gfar_private *priv = container_of(work, struct gfar_private,
2483 reset_task);
2484 struct net_device *dev = priv->ndev;
2485
2486 if (dev->flags & IFF_UP) {
2487 netif_tx_stop_all_queues(dev);
2488 stop_gfar(dev);
2489 startup_gfar(dev);
2490 netif_tx_start_all_queues(dev);
2491 }
2492
2493 netif_tx_schedule_all(dev);
2494}
2495
2496static void gfar_timeout(struct net_device *dev)
2497{
2498 struct gfar_private *priv = netdev_priv(dev);
2499
2500 dev->stats.tx_errors++;
2501 schedule_work(&priv->reset_task);
2502}
2503
2504static void gfar_align_skb(struct sk_buff *skb)
2505{
2506 /* We need the data buffer to be aligned properly. We will reserve
2507 * as many bytes as needed to align the data properly
2508 */
2509 skb_reserve(skb, RXBUF_ALIGNMENT -
2510 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2511}
2512
2513/* Interrupt Handler for Transmit complete */
2514static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2515{
2516 struct net_device *dev = tx_queue->dev;
2517 struct netdev_queue *txq;
2518 struct gfar_private *priv = netdev_priv(dev);
2519 struct txbd8 *bdp, *next = NULL;
2520 struct txbd8 *lbdp = NULL;
2521 struct txbd8 *base = tx_queue->tx_bd_base;
2522 struct sk_buff *skb;
2523 int skb_dirtytx;
2524 int tx_ring_size = tx_queue->tx_ring_size;
2525 int frags = 0, nr_txbds = 0;
2526 int i;
2527 int howmany = 0;
2528 int tqi = tx_queue->qindex;
2529 unsigned int bytes_sent = 0;
2530 u32 lstatus;
2531 size_t buflen;
2532
2533 txq = netdev_get_tx_queue(dev, tqi);
2534 bdp = tx_queue->dirty_tx;
2535 skb_dirtytx = tx_queue->skb_dirtytx;
2536
2537 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2538 unsigned long flags;
2539
2540 frags = skb_shinfo(skb)->nr_frags;
2541
2542 /* When time stamping, one additional TxBD must be freed.
2543 * Also, we need to dma_unmap_single() the TxPAL.
2544 */
2545 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2546 nr_txbds = frags + 2;
2547 else
2548 nr_txbds = frags + 1;
2549
2550 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2551
2552 lstatus = lbdp->lstatus;
2553
2554 /* Only clean completed frames */
2555 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2556 (lstatus & BD_LENGTH_MASK))
2557 break;
2558
2559 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2560 next = next_txbd(bdp, base, tx_ring_size);
2561 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2562 } else
2563 buflen = bdp->length;
2564
2565 dma_unmap_single(priv->dev, bdp->bufPtr,
2566 buflen, DMA_TO_DEVICE);
2567
2568 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2569 struct skb_shared_hwtstamps shhwtstamps;
2570 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2571
2572 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2573 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2574 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2575 skb_tstamp_tx(skb, &shhwtstamps);
2576 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2577 bdp = next;
2578 }
2579
2580 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2581 bdp = next_txbd(bdp, base, tx_ring_size);
2582
2583 for (i = 0; i < frags; i++) {
2584 dma_unmap_page(priv->dev, bdp->bufPtr,
2585 bdp->length, DMA_TO_DEVICE);
2586 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2587 bdp = next_txbd(bdp, base, tx_ring_size);
2588 }
2589
2590 bytes_sent += GFAR_CB(skb)->bytes_sent;
2591
2592 dev_kfree_skb_any(skb);
2593
2594 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2595
2596 skb_dirtytx = (skb_dirtytx + 1) &
2597 TX_RING_MOD_MASK(tx_ring_size);
2598
2599 howmany++;
2600 spin_lock_irqsave(&tx_queue->txlock, flags);
2601 tx_queue->num_txbdfree += nr_txbds;
2602 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2603 }
2604
2605 /* If we freed a buffer, we can restart transmission, if necessary */
2606 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2607 netif_wake_subqueue(dev, tqi);
2608
2609 /* Update dirty indicators */
2610 tx_queue->skb_dirtytx = skb_dirtytx;
2611 tx_queue->dirty_tx = bdp;
2612
2613 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2614}
2615
2616static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2617{
2618 unsigned long flags;
2619
2620 spin_lock_irqsave(&gfargrp->grplock, flags);
2621 if (napi_schedule_prep(&gfargrp->napi)) {
2622 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2623 __napi_schedule(&gfargrp->napi);
2624 } else {
2625 /* Clear IEVENT, so interrupts aren't called again
2626 * because of the packets that have already arrived.
2627 */
2628 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2629 }
2630 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2631
2632}
2633
2634/* Interrupt Handler for Transmit complete */
2635static irqreturn_t gfar_transmit(int irq, void *grp_id)
2636{
2637 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2638 return IRQ_HANDLED;
2639}
2640
2641static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2642 struct sk_buff *skb)
2643{
2644 struct net_device *dev = rx_queue->dev;
2645 struct gfar_private *priv = netdev_priv(dev);
2646 dma_addr_t buf;
2647
2648 buf = dma_map_single(priv->dev, skb->data,
2649 priv->rx_buffer_size, DMA_FROM_DEVICE);
2650 gfar_init_rxbdp(rx_queue, bdp, buf);
2651}
2652
2653static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2654{
2655 struct gfar_private *priv = netdev_priv(dev);
2656 struct sk_buff *skb;
2657
2658 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2659 if (!skb)
2660 return NULL;
2661
2662 gfar_align_skb(skb);
2663
2664 return skb;
2665}
2666
2667struct sk_buff *gfar_new_skb(struct net_device *dev)
2668{
2669 return gfar_alloc_skb(dev);
2670}
2671
2672static inline void count_errors(unsigned short status, struct net_device *dev)
2673{
2674 struct gfar_private *priv = netdev_priv(dev);
2675 struct net_device_stats *stats = &dev->stats;
2676 struct gfar_extra_stats *estats = &priv->extra_stats;
2677
2678 /* If the packet was truncated, none of the other errors matter */
2679 if (status & RXBD_TRUNCATED) {
2680 stats->rx_length_errors++;
2681
2682 atomic64_inc(&estats->rx_trunc);
2683
2684 return;
2685 }
2686 /* Count the errors, if there were any */
2687 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2688 stats->rx_length_errors++;
2689
2690 if (status & RXBD_LARGE)
2691 atomic64_inc(&estats->rx_large);
2692 else
2693 atomic64_inc(&estats->rx_short);
2694 }
2695 if (status & RXBD_NONOCTET) {
2696 stats->rx_frame_errors++;
2697 atomic64_inc(&estats->rx_nonoctet);
2698 }
2699 if (status & RXBD_CRCERR) {
2700 atomic64_inc(&estats->rx_crcerr);
2701 stats->rx_crc_errors++;
2702 }
2703 if (status & RXBD_OVERRUN) {
2704 atomic64_inc(&estats->rx_overrun);
2705 stats->rx_crc_errors++;
2706 }
2707}
2708
2709irqreturn_t gfar_receive(int irq, void *grp_id)
2710{
2711 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2712 return IRQ_HANDLED;
2713}
2714
2715static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2716{
2717 /* If valid headers were found, and valid sums
2718 * were verified, then we tell the kernel that no
2719 * checksumming is necessary. Otherwise, it is [FIXME]
2720 */
2721 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2722 skb->ip_summed = CHECKSUM_UNNECESSARY;
2723 else
2724 skb_checksum_none_assert(skb);
2725}
2726
2727
2728/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2729static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2730 int amount_pull, struct napi_struct *napi)
2731{
2732 struct gfar_private *priv = netdev_priv(dev);
2733 struct rxfcb *fcb = NULL;
2734
2735 /* fcb is at the beginning if exists */
2736 fcb = (struct rxfcb *)skb->data;
2737
2738 /* Remove the FCB from the skb
2739 * Remove the padded bytes, if there are any
2740 */
2741 if (amount_pull) {
2742 skb_record_rx_queue(skb, fcb->rq);
2743 skb_pull(skb, amount_pull);
2744 }
2745
2746 /* Get receive timestamp from the skb */
2747 if (priv->hwts_rx_en) {
2748 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2749 u64 *ns = (u64 *) skb->data;
2750
2751 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2752 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2753 }
2754
2755 if (priv->padding)
2756 skb_pull(skb, priv->padding);
2757
2758 if (dev->features & NETIF_F_RXCSUM)
2759 gfar_rx_checksum(skb, fcb);
2760
2761 /* Tell the skb what kind of packet this is */
2762 skb->protocol = eth_type_trans(skb, dev);
2763
2764 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2765 * Even if vlan rx accel is disabled, on some chips
2766 * RXFCB_VLN is pseudo randomly set.
2767 */
2768 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2769 fcb->flags & RXFCB_VLN)
2770 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2771
2772 /* Send the packet up the stack */
2773 napi_gro_receive(napi, skb);
2774
2775}
2776
2777/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2778 * until the budget/quota has been reached. Returns the number
2779 * of frames handled
2780 */
2781int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2782{
2783 struct net_device *dev = rx_queue->dev;
2784 struct rxbd8 *bdp, *base;
2785 struct sk_buff *skb;
2786 int pkt_len;
2787 int amount_pull;
2788 int howmany = 0;
2789 struct gfar_private *priv = netdev_priv(dev);
2790
2791 /* Get the first full descriptor */
2792 bdp = rx_queue->cur_rx;
2793 base = rx_queue->rx_bd_base;
2794
2795 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2796
2797 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2798 struct sk_buff *newskb;
2799
2800 rmb();
2801
2802 /* Add another skb for the future */
2803 newskb = gfar_new_skb(dev);
2804
2805 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2806
2807 dma_unmap_single(priv->dev, bdp->bufPtr,
2808 priv->rx_buffer_size, DMA_FROM_DEVICE);
2809
2810 if (unlikely(!(bdp->status & RXBD_ERR) &&
2811 bdp->length > priv->rx_buffer_size))
2812 bdp->status = RXBD_LARGE;
2813
2814 /* We drop the frame if we failed to allocate a new buffer */
2815 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2816 bdp->status & RXBD_ERR)) {
2817 count_errors(bdp->status, dev);
2818
2819 if (unlikely(!newskb))
2820 newskb = skb;
2821 else if (skb)
2822 dev_kfree_skb(skb);
2823 } else {
2824 /* Increment the number of packets */
2825 rx_queue->stats.rx_packets++;
2826 howmany++;
2827
2828 if (likely(skb)) {
2829 pkt_len = bdp->length - ETH_FCS_LEN;
2830 /* Remove the FCS from the packet length */
2831 skb_put(skb, pkt_len);
2832 rx_queue->stats.rx_bytes += pkt_len;
2833 skb_record_rx_queue(skb, rx_queue->qindex);
2834 gfar_process_frame(dev, skb, amount_pull,
2835 &rx_queue->grp->napi);
2836
2837 } else {
2838 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2839 rx_queue->stats.rx_dropped++;
2840 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2841 }
2842
2843 }
2844
2845 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2846
2847 /* Setup the new bdp */
2848 gfar_new_rxbdp(rx_queue, bdp, newskb);
2849
2850 /* Update to the next pointer */
2851 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2852
2853 /* update to point at the next skb */
2854 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2855 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2856 }
2857
2858 /* Update the current rxbd pointer to be the next one */
2859 rx_queue->cur_rx = bdp;
2860
2861 return howmany;
2862}
2863
2864static int gfar_poll_sq(struct napi_struct *napi, int budget)
2865{
2866 struct gfar_priv_grp *gfargrp =
2867 container_of(napi, struct gfar_priv_grp, napi);
2868 struct gfar __iomem *regs = gfargrp->regs;
2869 struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2870 struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2871 int work_done = 0;
2872
2873 /* Clear IEVENT, so interrupts aren't called again
2874 * because of the packets that have already arrived
2875 */
2876 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2877
2878 /* run Tx cleanup to completion */
2879 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2880 gfar_clean_tx_ring(tx_queue);
2881
2882 work_done = gfar_clean_rx_ring(rx_queue, budget);
2883
2884 if (work_done < budget) {
2885 napi_complete(napi);
2886 /* Clear the halt bit in RSTAT */
2887 gfar_write(&regs->rstat, gfargrp->rstat);
2888
2889 gfar_write(&regs->imask, IMASK_DEFAULT);
2890
2891 /* If we are coalescing interrupts, update the timer
2892 * Otherwise, clear it
2893 */
2894 gfar_write(&regs->txic, 0);
2895 if (likely(tx_queue->txcoalescing))
2896 gfar_write(&regs->txic, tx_queue->txic);
2897
2898 gfar_write(&regs->rxic, 0);
2899 if (unlikely(rx_queue->rxcoalescing))
2900 gfar_write(&regs->rxic, rx_queue->rxic);
2901 }
2902
2903 return work_done;
2904}
2905
2906static int gfar_poll(struct napi_struct *napi, int budget)
2907{
2908 struct gfar_priv_grp *gfargrp =
2909 container_of(napi, struct gfar_priv_grp, napi);
2910 struct gfar_private *priv = gfargrp->priv;
2911 struct gfar __iomem *regs = gfargrp->regs;
2912 struct gfar_priv_tx_q *tx_queue = NULL;
2913 struct gfar_priv_rx_q *rx_queue = NULL;
2914 int work_done = 0, work_done_per_q = 0;
2915 int i, budget_per_q = 0;
2916 int has_tx_work = 0;
2917 unsigned long rstat_rxf;
2918 int num_act_queues;
2919
2920 /* Clear IEVENT, so interrupts aren't called again
2921 * because of the packets that have already arrived
2922 */
2923 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2924
2925 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2926
2927 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2928 if (num_act_queues)
2929 budget_per_q = budget/num_act_queues;
2930
2931 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2932 tx_queue = priv->tx_queue[i];
2933 /* run Tx cleanup to completion */
2934 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2935 gfar_clean_tx_ring(tx_queue);
2936 has_tx_work = 1;
2937 }
2938 }
2939
2940 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2941 /* skip queue if not active */
2942 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2943 continue;
2944
2945 rx_queue = priv->rx_queue[i];
2946 work_done_per_q =
2947 gfar_clean_rx_ring(rx_queue, budget_per_q);
2948 work_done += work_done_per_q;
2949
2950 /* finished processing this queue */
2951 if (work_done_per_q < budget_per_q) {
2952 /* clear active queue hw indication */
2953 gfar_write(&regs->rstat,
2954 RSTAT_CLEAR_RXF0 >> i);
2955 num_act_queues--;
2956
2957 if (!num_act_queues)
2958 break;
2959 }
2960 }
2961
2962 if (!num_act_queues && !has_tx_work) {
2963
2964 napi_complete(napi);
2965
2966 /* Clear the halt bit in RSTAT */
2967 gfar_write(&regs->rstat, gfargrp->rstat);
2968
2969 gfar_write(&regs->imask, IMASK_DEFAULT);
2970
2971 /* If we are coalescing interrupts, update the timer
2972 * Otherwise, clear it
2973 */
2974 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2975 gfargrp->tx_bit_map);
2976 }
2977
2978 return work_done;
2979}
2980
2981#ifdef CONFIG_NET_POLL_CONTROLLER
2982/* Polling 'interrupt' - used by things like netconsole to send skbs
2983 * without having to re-enable interrupts. It's not called while
2984 * the interrupt routine is executing.
2985 */
2986static void gfar_netpoll(struct net_device *dev)
2987{
2988 struct gfar_private *priv = netdev_priv(dev);
2989 int i;
2990
2991 /* If the device has multiple interrupts, run tx/rx */
2992 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2993 for (i = 0; i < priv->num_grps; i++) {
2994 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2995
2996 disable_irq(gfar_irq(grp, TX)->irq);
2997 disable_irq(gfar_irq(grp, RX)->irq);
2998 disable_irq(gfar_irq(grp, ER)->irq);
2999 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3000 enable_irq(gfar_irq(grp, ER)->irq);
3001 enable_irq(gfar_irq(grp, RX)->irq);
3002 enable_irq(gfar_irq(grp, TX)->irq);
3003 }
3004 } else {
3005 for (i = 0; i < priv->num_grps; i++) {
3006 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3007
3008 disable_irq(gfar_irq(grp, TX)->irq);
3009 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3010 enable_irq(gfar_irq(grp, TX)->irq);
3011 }
3012 }
3013}
3014#endif
3015
3016/* The interrupt handler for devices with one interrupt */
3017static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3018{
3019 struct gfar_priv_grp *gfargrp = grp_id;
3020
3021 /* Save ievent for future reference */
3022 u32 events = gfar_read(&gfargrp->regs->ievent);
3023
3024 /* Check for reception */
3025 if (events & IEVENT_RX_MASK)
3026 gfar_receive(irq, grp_id);
3027
3028 /* Check for transmit completion */
3029 if (events & IEVENT_TX_MASK)
3030 gfar_transmit(irq, grp_id);
3031
3032 /* Check for errors */
3033 if (events & IEVENT_ERR_MASK)
3034 gfar_error(irq, grp_id);
3035
3036 return IRQ_HANDLED;
3037}
3038
3039static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3040{
3041 struct phy_device *phydev = priv->phydev;
3042 u32 val = 0;
3043
3044 if (!phydev->duplex)
3045 return val;
3046
3047 if (!priv->pause_aneg_en) {
3048 if (priv->tx_pause_en)
3049 val |= MACCFG1_TX_FLOW;
3050 if (priv->rx_pause_en)
3051 val |= MACCFG1_RX_FLOW;
3052 } else {
3053 u16 lcl_adv, rmt_adv;
3054 u8 flowctrl;
3055 /* get link partner capabilities */
3056 rmt_adv = 0;
3057 if (phydev->pause)
3058 rmt_adv = LPA_PAUSE_CAP;
3059 if (phydev->asym_pause)
3060 rmt_adv |= LPA_PAUSE_ASYM;
3061
3062 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3063
3064 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3065 if (flowctrl & FLOW_CTRL_TX)
3066 val |= MACCFG1_TX_FLOW;
3067 if (flowctrl & FLOW_CTRL_RX)
3068 val |= MACCFG1_RX_FLOW;
3069 }
3070
3071 return val;
3072}
3073
3074/* Called every time the controller might need to be made
3075 * aware of new link state. The PHY code conveys this
3076 * information through variables in the phydev structure, and this
3077 * function converts those variables into the appropriate
3078 * register values, and can bring down the device if needed.
3079 */
3080static void adjust_link(struct net_device *dev)
3081{
3082 struct gfar_private *priv = netdev_priv(dev);
3083 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3084 unsigned long flags;
3085 struct phy_device *phydev = priv->phydev;
3086 int new_state = 0;
3087
3088 local_irq_save(flags);
3089 lock_tx_qs(priv);
3090
3091 if (phydev->link) {
3092 u32 tempval1 = gfar_read(&regs->maccfg1);
3093 u32 tempval = gfar_read(&regs->maccfg2);
3094 u32 ecntrl = gfar_read(&regs->ecntrl);
3095
3096 /* Now we make sure that we can be in full duplex mode.
3097 * If not, we operate in half-duplex mode.
3098 */
3099 if (phydev->duplex != priv->oldduplex) {
3100 new_state = 1;
3101 if (!(phydev->duplex))
3102 tempval &= ~(MACCFG2_FULL_DUPLEX);
3103 else
3104 tempval |= MACCFG2_FULL_DUPLEX;
3105
3106 priv->oldduplex = phydev->duplex;
3107 }
3108
3109 if (phydev->speed != priv->oldspeed) {
3110 new_state = 1;
3111 switch (phydev->speed) {
3112 case 1000:
3113 tempval =
3114 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3115
3116 ecntrl &= ~(ECNTRL_R100);
3117 break;
3118 case 100:
3119 case 10:
3120 tempval =
3121 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3122
3123 /* Reduced mode distinguishes
3124 * between 10 and 100
3125 */
3126 if (phydev->speed == SPEED_100)
3127 ecntrl |= ECNTRL_R100;
3128 else
3129 ecntrl &= ~(ECNTRL_R100);
3130 break;
3131 default:
3132 netif_warn(priv, link, dev,
3133 "Ack! Speed (%d) is not 10/100/1000!\n",
3134 phydev->speed);
3135 break;
3136 }
3137
3138 priv->oldspeed = phydev->speed;
3139 }
3140
3141 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3142 tempval1 |= gfar_get_flowctrl_cfg(priv);
3143
3144 gfar_write(&regs->maccfg1, tempval1);
3145 gfar_write(&regs->maccfg2, tempval);
3146 gfar_write(&regs->ecntrl, ecntrl);
3147
3148 if (!priv->oldlink) {
3149 new_state = 1;
3150 priv->oldlink = 1;
3151 }
3152 } else if (priv->oldlink) {
3153 new_state = 1;
3154 priv->oldlink = 0;
3155 priv->oldspeed = 0;
3156 priv->oldduplex = -1;
3157 }
3158
3159 if (new_state && netif_msg_link(priv))
3160 phy_print_status(phydev);
3161 unlock_tx_qs(priv);
3162 local_irq_restore(flags);
3163}
3164
3165/* Update the hash table based on the current list of multicast
3166 * addresses we subscribe to. Also, change the promiscuity of
3167 * the device based on the flags (this function is called
3168 * whenever dev->flags is changed
3169 */
3170static void gfar_set_multi(struct net_device *dev)
3171{
3172 struct netdev_hw_addr *ha;
3173 struct gfar_private *priv = netdev_priv(dev);
3174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3175 u32 tempval;
3176
3177 if (dev->flags & IFF_PROMISC) {
3178 /* Set RCTRL to PROM */
3179 tempval = gfar_read(&regs->rctrl);
3180 tempval |= RCTRL_PROM;
3181 gfar_write(&regs->rctrl, tempval);
3182 } else {
3183 /* Set RCTRL to not PROM */
3184 tempval = gfar_read(&regs->rctrl);
3185 tempval &= ~(RCTRL_PROM);
3186 gfar_write(&regs->rctrl, tempval);
3187 }
3188
3189 if (dev->flags & IFF_ALLMULTI) {
3190 /* Set the hash to rx all multicast frames */
3191 gfar_write(&regs->igaddr0, 0xffffffff);
3192 gfar_write(&regs->igaddr1, 0xffffffff);
3193 gfar_write(&regs->igaddr2, 0xffffffff);
3194 gfar_write(&regs->igaddr3, 0xffffffff);
3195 gfar_write(&regs->igaddr4, 0xffffffff);
3196 gfar_write(&regs->igaddr5, 0xffffffff);
3197 gfar_write(&regs->igaddr6, 0xffffffff);
3198 gfar_write(&regs->igaddr7, 0xffffffff);
3199 gfar_write(&regs->gaddr0, 0xffffffff);
3200 gfar_write(&regs->gaddr1, 0xffffffff);
3201 gfar_write(&regs->gaddr2, 0xffffffff);
3202 gfar_write(&regs->gaddr3, 0xffffffff);
3203 gfar_write(&regs->gaddr4, 0xffffffff);
3204 gfar_write(&regs->gaddr5, 0xffffffff);
3205 gfar_write(&regs->gaddr6, 0xffffffff);
3206 gfar_write(&regs->gaddr7, 0xffffffff);
3207 } else {
3208 int em_num;
3209 int idx;
3210
3211 /* zero out the hash */
3212 gfar_write(&regs->igaddr0, 0x0);
3213 gfar_write(&regs->igaddr1, 0x0);
3214 gfar_write(&regs->igaddr2, 0x0);
3215 gfar_write(&regs->igaddr3, 0x0);
3216 gfar_write(&regs->igaddr4, 0x0);
3217 gfar_write(&regs->igaddr5, 0x0);
3218 gfar_write(&regs->igaddr6, 0x0);
3219 gfar_write(&regs->igaddr7, 0x0);
3220 gfar_write(&regs->gaddr0, 0x0);
3221 gfar_write(&regs->gaddr1, 0x0);
3222 gfar_write(&regs->gaddr2, 0x0);
3223 gfar_write(&regs->gaddr3, 0x0);
3224 gfar_write(&regs->gaddr4, 0x0);
3225 gfar_write(&regs->gaddr5, 0x0);
3226 gfar_write(&regs->gaddr6, 0x0);
3227 gfar_write(&regs->gaddr7, 0x0);
3228
3229 /* If we have extended hash tables, we need to
3230 * clear the exact match registers to prepare for
3231 * setting them
3232 */
3233 if (priv->extended_hash) {
3234 em_num = GFAR_EM_NUM + 1;
3235 gfar_clear_exact_match(dev);
3236 idx = 1;
3237 } else {
3238 idx = 0;
3239 em_num = 0;
3240 }
3241
3242 if (netdev_mc_empty(dev))
3243 return;
3244
3245 /* Parse the list, and set the appropriate bits */
3246 netdev_for_each_mc_addr(ha, dev) {
3247 if (idx < em_num) {
3248 gfar_set_mac_for_addr(dev, idx, ha->addr);
3249 idx++;
3250 } else
3251 gfar_set_hash_for_addr(dev, ha->addr);
3252 }
3253 }
3254}
3255
3256
3257/* Clears each of the exact match registers to zero, so they
3258 * don't interfere with normal reception
3259 */
3260static void gfar_clear_exact_match(struct net_device *dev)
3261{
3262 int idx;
3263 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3264
3265 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3266 gfar_set_mac_for_addr(dev, idx, zero_arr);
3267}
3268
3269/* Set the appropriate hash bit for the given addr */
3270/* The algorithm works like so:
3271 * 1) Take the Destination Address (ie the multicast address), and
3272 * do a CRC on it (little endian), and reverse the bits of the
3273 * result.
3274 * 2) Use the 8 most significant bits as a hash into a 256-entry
3275 * table. The table is controlled through 8 32-bit registers:
3276 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3277 * gaddr7. This means that the 3 most significant bits in the
3278 * hash index which gaddr register to use, and the 5 other bits
3279 * indicate which bit (assuming an IBM numbering scheme, which
3280 * for PowerPC (tm) is usually the case) in the register holds
3281 * the entry.
3282 */
3283static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3284{
3285 u32 tempval;
3286 struct gfar_private *priv = netdev_priv(dev);
3287 u32 result = ether_crc(ETH_ALEN, addr);
3288 int width = priv->hash_width;
3289 u8 whichbit = (result >> (32 - width)) & 0x1f;
3290 u8 whichreg = result >> (32 - width + 5);
3291 u32 value = (1 << (31-whichbit));
3292
3293 tempval = gfar_read(priv->hash_regs[whichreg]);
3294 tempval |= value;
3295 gfar_write(priv->hash_regs[whichreg], tempval);
3296}
3297
3298
3299/* There are multiple MAC Address register pairs on some controllers
3300 * This function sets the numth pair to a given address
3301 */
3302static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3303 const u8 *addr)
3304{
3305 struct gfar_private *priv = netdev_priv(dev);
3306 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3307 int idx;
3308 char tmpbuf[ETH_ALEN];
3309 u32 tempval;
3310 u32 __iomem *macptr = &regs->macstnaddr1;
3311
3312 macptr += num*2;
3313
3314 /* Now copy it into the mac registers backwards, cuz
3315 * little endian is silly
3316 */
3317 for (idx = 0; idx < ETH_ALEN; idx++)
3318 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3319
3320 gfar_write(macptr, *((u32 *) (tmpbuf)));
3321
3322 tempval = *((u32 *) (tmpbuf + 4));
3323
3324 gfar_write(macptr+1, tempval);
3325}
3326
3327/* GFAR error interrupt handler */
3328static irqreturn_t gfar_error(int irq, void *grp_id)
3329{
3330 struct gfar_priv_grp *gfargrp = grp_id;
3331 struct gfar __iomem *regs = gfargrp->regs;
3332 struct gfar_private *priv= gfargrp->priv;
3333 struct net_device *dev = priv->ndev;
3334
3335 /* Save ievent for future reference */
3336 u32 events = gfar_read(&regs->ievent);
3337
3338 /* Clear IEVENT */
3339 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3340
3341 /* Magic Packet is not an error. */
3342 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3343 (events & IEVENT_MAG))
3344 events &= ~IEVENT_MAG;
3345
3346 /* Hmm... */
3347 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3348 netdev_dbg(dev,
3349 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3350 events, gfar_read(&regs->imask));
3351
3352 /* Update the error counters */
3353 if (events & IEVENT_TXE) {
3354 dev->stats.tx_errors++;
3355
3356 if (events & IEVENT_LC)
3357 dev->stats.tx_window_errors++;
3358 if (events & IEVENT_CRL)
3359 dev->stats.tx_aborted_errors++;
3360 if (events & IEVENT_XFUN) {
3361 unsigned long flags;
3362
3363 netif_dbg(priv, tx_err, dev,
3364 "TX FIFO underrun, packet dropped\n");
3365 dev->stats.tx_dropped++;
3366 atomic64_inc(&priv->extra_stats.tx_underrun);
3367
3368 local_irq_save(flags);
3369 lock_tx_qs(priv);
3370
3371 /* Reactivate the Tx Queues */
3372 gfar_write(&regs->tstat, gfargrp->tstat);
3373
3374 unlock_tx_qs(priv);
3375 local_irq_restore(flags);
3376 }
3377 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3378 }
3379 if (events & IEVENT_BSY) {
3380 dev->stats.rx_errors++;
3381 atomic64_inc(&priv->extra_stats.rx_bsy);
3382
3383 gfar_receive(irq, grp_id);
3384
3385 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3386 gfar_read(&regs->rstat));
3387 }
3388 if (events & IEVENT_BABR) {
3389 dev->stats.rx_errors++;
3390 atomic64_inc(&priv->extra_stats.rx_babr);
3391
3392 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3393 }
3394 if (events & IEVENT_EBERR) {
3395 atomic64_inc(&priv->extra_stats.eberr);
3396 netif_dbg(priv, rx_err, dev, "bus error\n");
3397 }
3398 if (events & IEVENT_RXC)
3399 netif_dbg(priv, rx_status, dev, "control frame\n");
3400
3401 if (events & IEVENT_BABT) {
3402 atomic64_inc(&priv->extra_stats.tx_babt);
3403 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3404 }
3405 return IRQ_HANDLED;
3406}
3407
3408static struct of_device_id gfar_match[] =
3409{
3410 {
3411 .type = "network",
3412 .compatible = "gianfar",
3413 },
3414 {
3415 .compatible = "fsl,etsec2",
3416 },
3417 {},
3418};
3419MODULE_DEVICE_TABLE(of, gfar_match);
3420
3421/* Structure for a device driver */
3422static struct platform_driver gfar_driver = {
3423 .driver = {
3424 .name = "fsl-gianfar",
3425 .owner = THIS_MODULE,
3426 .pm = GFAR_PM_OPS,
3427 .of_match_table = gfar_match,
3428 },
3429 .probe = gfar_probe,
3430 .remove = gfar_remove,
3431};
3432
3433module_platform_driver(gfar_driver);
Linux 6.x block layer and io_uring tree(s)