| 1 | /* |
| 2 | * drivers/mtd/nand/cs553x_nand.c |
| 3 | * |
| 4 | * (C) 2005, 2006 Red Hat Inc. |
| 5 | * |
| 6 | * Author: David Woodhouse <dwmw2@infradead.org> |
| 7 | * Tom Sylla <tom.sylla@amd.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * Overview: |
| 14 | * This is a device driver for the NAND flash controller found on |
| 15 | * the AMD CS5535/CS5536 companion chipsets for the Geode processor. |
| 16 | * mtd-id for command line partitioning is cs553x_nand_cs[0-3] |
| 17 | * where 0-3 reflects the chip select for NAND. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/mtd/mtd.h> |
| 27 | #include <linux/mtd/nand.h> |
| 28 | #include <linux/mtd/nand_ecc.h> |
| 29 | #include <linux/mtd/partitions.h> |
| 30 | |
| 31 | #include <asm/msr.h> |
| 32 | #include <asm/io.h> |
| 33 | |
| 34 | #define NR_CS553X_CONTROLLERS 4 |
| 35 | |
| 36 | #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */ |
| 37 | #define CAP_CS5535 0x2df000ULL |
| 38 | #define CAP_CS5536 0x5df500ULL |
| 39 | |
| 40 | /* NAND Timing MSRs */ |
| 41 | #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */ |
| 42 | #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */ |
| 43 | #define MSR_NANDF_RSVD 0x5140001d /* Reserved */ |
| 44 | |
| 45 | /* NAND BAR MSRs */ |
| 46 | #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */ |
| 47 | #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */ |
| 48 | #define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */ |
| 49 | #define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */ |
| 50 | /* Each made up of... */ |
| 51 | #define FLSH_LBAR_EN (1ULL<<32) |
| 52 | #define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */ |
| 53 | #define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */ |
| 54 | /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */ |
| 55 | /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */ |
| 56 | |
| 57 | /* Pin function selection MSR (IDE vs. flash on the IDE pins) */ |
| 58 | #define MSR_DIVIL_BALL_OPTS 0x51400015 |
| 59 | #define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */ |
| 60 | |
| 61 | /* Registers within the NAND flash controller BAR -- memory mapped */ |
| 62 | #define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */ |
| 63 | #define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */ |
| 64 | #define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */ |
| 65 | #define MM_NAND_STS 0x810 |
| 66 | #define MM_NAND_ECC_LSB 0x811 |
| 67 | #define MM_NAND_ECC_MSB 0x812 |
| 68 | #define MM_NAND_ECC_COL 0x813 |
| 69 | #define MM_NAND_LAC 0x814 |
| 70 | #define MM_NAND_ECC_CTL 0x815 |
| 71 | |
| 72 | /* Registers within the NAND flash controller BAR -- I/O mapped */ |
| 73 | #define IO_NAND_DATA 0x00 /* 0 to 3, in fact */ |
| 74 | #define IO_NAND_CTL 0x04 |
| 75 | #define IO_NAND_IO 0x05 |
| 76 | #define IO_NAND_STS 0x06 |
| 77 | #define IO_NAND_ECC_CTL 0x08 |
| 78 | #define IO_NAND_ECC_LSB 0x09 |
| 79 | #define IO_NAND_ECC_MSB 0x0a |
| 80 | #define IO_NAND_ECC_COL 0x0b |
| 81 | #define IO_NAND_LAC 0x0c |
| 82 | |
| 83 | #define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */ |
| 84 | #define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */ |
| 85 | #define CS_NAND_CTL_ALE (1<<2) |
| 86 | #define CS_NAND_CTL_CLE (1<<1) |
| 87 | #define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */ |
| 88 | |
| 89 | #define CS_NAND_STS_FLASH_RDY (1<<3) |
| 90 | #define CS_NAND_CTLR_BUSY (1<<2) |
| 91 | #define CS_NAND_CMD_COMP (1<<1) |
| 92 | #define CS_NAND_DIST_ST (1<<0) |
| 93 | |
| 94 | #define CS_NAND_ECC_PARITY (1<<2) |
| 95 | #define CS_NAND_ECC_CLRECC (1<<1) |
| 96 | #define CS_NAND_ECC_ENECC (1<<0) |
| 97 | |
| 98 | static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 99 | { |
| 100 | struct nand_chip *this = mtd_to_nand(mtd); |
| 101 | |
| 102 | while (unlikely(len > 0x800)) { |
| 103 | memcpy_fromio(buf, this->IO_ADDR_R, 0x800); |
| 104 | buf += 0x800; |
| 105 | len -= 0x800; |
| 106 | } |
| 107 | memcpy_fromio(buf, this->IO_ADDR_R, len); |
| 108 | } |
| 109 | |
| 110 | static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 111 | { |
| 112 | struct nand_chip *this = mtd_to_nand(mtd); |
| 113 | |
| 114 | while (unlikely(len > 0x800)) { |
| 115 | memcpy_toio(this->IO_ADDR_R, buf, 0x800); |
| 116 | buf += 0x800; |
| 117 | len -= 0x800; |
| 118 | } |
| 119 | memcpy_toio(this->IO_ADDR_R, buf, len); |
| 120 | } |
| 121 | |
| 122 | static unsigned char cs553x_read_byte(struct mtd_info *mtd) |
| 123 | { |
| 124 | struct nand_chip *this = mtd_to_nand(mtd); |
| 125 | return readb(this->IO_ADDR_R); |
| 126 | } |
| 127 | |
| 128 | static void cs553x_write_byte(struct mtd_info *mtd, u_char byte) |
| 129 | { |
| 130 | struct nand_chip *this = mtd_to_nand(mtd); |
| 131 | int i = 100000; |
| 132 | |
| 133 | while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) { |
| 134 | udelay(1); |
| 135 | i--; |
| 136 | } |
| 137 | writeb(byte, this->IO_ADDR_W + 0x801); |
| 138 | } |
| 139 | |
| 140 | static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd, |
| 141 | unsigned int ctrl) |
| 142 | { |
| 143 | struct nand_chip *this = mtd_to_nand(mtd); |
| 144 | void __iomem *mmio_base = this->IO_ADDR_R; |
| 145 | if (ctrl & NAND_CTRL_CHANGE) { |
| 146 | unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01; |
| 147 | writeb(ctl, mmio_base + MM_NAND_CTL); |
| 148 | } |
| 149 | if (cmd != NAND_CMD_NONE) |
| 150 | cs553x_write_byte(mtd, cmd); |
| 151 | } |
| 152 | |
| 153 | static int cs553x_device_ready(struct mtd_info *mtd) |
| 154 | { |
| 155 | struct nand_chip *this = mtd_to_nand(mtd); |
| 156 | void __iomem *mmio_base = this->IO_ADDR_R; |
| 157 | unsigned char foo = readb(mmio_base + MM_NAND_STS); |
| 158 | |
| 159 | return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY); |
| 160 | } |
| 161 | |
| 162 | static void cs_enable_hwecc(struct mtd_info *mtd, int mode) |
| 163 | { |
| 164 | struct nand_chip *this = mtd_to_nand(mtd); |
| 165 | void __iomem *mmio_base = this->IO_ADDR_R; |
| 166 | |
| 167 | writeb(0x07, mmio_base + MM_NAND_ECC_CTL); |
| 168 | } |
| 169 | |
| 170 | static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
| 171 | { |
| 172 | uint32_t ecc; |
| 173 | struct nand_chip *this = mtd_to_nand(mtd); |
| 174 | void __iomem *mmio_base = this->IO_ADDR_R; |
| 175 | |
| 176 | ecc = readl(mmio_base + MM_NAND_STS); |
| 177 | |
| 178 | ecc_code[1] = ecc >> 8; |
| 179 | ecc_code[0] = ecc >> 16; |
| 180 | ecc_code[2] = ecc >> 24; |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | static struct mtd_info *cs553x_mtd[4]; |
| 185 | |
| 186 | static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) |
| 187 | { |
| 188 | int err = 0; |
| 189 | struct nand_chip *this; |
| 190 | struct mtd_info *new_mtd; |
| 191 | |
| 192 | printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr); |
| 193 | |
| 194 | if (!mmio) { |
| 195 | printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n"); |
| 196 | return -ENXIO; |
| 197 | } |
| 198 | |
| 199 | /* Allocate memory for MTD device structure and private data */ |
| 200 | this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL); |
| 201 | if (!this) { |
| 202 | err = -ENOMEM; |
| 203 | goto out; |
| 204 | } |
| 205 | |
| 206 | new_mtd = nand_to_mtd(this); |
| 207 | |
| 208 | /* Link the private data with the MTD structure */ |
| 209 | new_mtd->owner = THIS_MODULE; |
| 210 | |
| 211 | /* map physical address */ |
| 212 | this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096); |
| 213 | if (!this->IO_ADDR_R) { |
| 214 | printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr); |
| 215 | err = -EIO; |
| 216 | goto out_mtd; |
| 217 | } |
| 218 | |
| 219 | this->cmd_ctrl = cs553x_hwcontrol; |
| 220 | this->dev_ready = cs553x_device_ready; |
| 221 | this->read_byte = cs553x_read_byte; |
| 222 | this->read_buf = cs553x_read_buf; |
| 223 | this->write_buf = cs553x_write_buf; |
| 224 | |
| 225 | this->chip_delay = 0; |
| 226 | |
| 227 | this->ecc.mode = NAND_ECC_HW; |
| 228 | this->ecc.size = 256; |
| 229 | this->ecc.bytes = 3; |
| 230 | this->ecc.hwctl = cs_enable_hwecc; |
| 231 | this->ecc.calculate = cs_calculate_ecc; |
| 232 | this->ecc.correct = nand_correct_data; |
| 233 | this->ecc.strength = 1; |
| 234 | |
| 235 | /* Enable the following for a flash based bad block table */ |
| 236 | this->bbt_options = NAND_BBT_USE_FLASH; |
| 237 | |
| 238 | new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs); |
| 239 | if (!new_mtd->name) { |
| 240 | err = -ENOMEM; |
| 241 | goto out_ior; |
| 242 | } |
| 243 | |
| 244 | /* Scan to find existence of the device */ |
| 245 | if (nand_scan(new_mtd, 1)) { |
| 246 | err = -ENXIO; |
| 247 | goto out_free; |
| 248 | } |
| 249 | |
| 250 | cs553x_mtd[cs] = new_mtd; |
| 251 | goto out; |
| 252 | |
| 253 | out_free: |
| 254 | kfree(new_mtd->name); |
| 255 | out_ior: |
| 256 | iounmap(this->IO_ADDR_R); |
| 257 | out_mtd: |
| 258 | kfree(this); |
| 259 | out: |
| 260 | return err; |
| 261 | } |
| 262 | |
| 263 | static int is_geode(void) |
| 264 | { |
| 265 | /* These are the CPUs which will have a CS553[56] companion chip */ |
| 266 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
| 267 | boot_cpu_data.x86 == 5 && |
| 268 | boot_cpu_data.x86_model == 10) |
| 269 | return 1; /* Geode LX */ |
| 270 | |
| 271 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC || |
| 272 | boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) && |
| 273 | boot_cpu_data.x86 == 5 && |
| 274 | boot_cpu_data.x86_model == 5) |
| 275 | return 1; /* Geode GX (née GX2) */ |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static int __init cs553x_init(void) |
| 281 | { |
| 282 | int err = -ENXIO; |
| 283 | int i; |
| 284 | uint64_t val; |
| 285 | |
| 286 | /* If the CPU isn't a Geode GX or LX, abort */ |
| 287 | if (!is_geode()) |
| 288 | return -ENXIO; |
| 289 | |
| 290 | /* If it doesn't have the CS553[56], abort */ |
| 291 | rdmsrl(MSR_DIVIL_GLD_CAP, val); |
| 292 | val &= ~0xFFULL; |
| 293 | if (val != CAP_CS5535 && val != CAP_CS5536) |
| 294 | return -ENXIO; |
| 295 | |
| 296 | /* If it doesn't have the NAND controller enabled, abort */ |
| 297 | rdmsrl(MSR_DIVIL_BALL_OPTS, val); |
| 298 | if (val & PIN_OPT_IDE) { |
| 299 | printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n"); |
| 300 | return -ENXIO; |
| 301 | } |
| 302 | |
| 303 | for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { |
| 304 | rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val); |
| 305 | |
| 306 | if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND)) |
| 307 | err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF); |
| 308 | } |
| 309 | |
| 310 | /* Register all devices together here. This means we can easily hack it to |
| 311 | do mtdconcat etc. if we want to. */ |
| 312 | for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { |
| 313 | if (cs553x_mtd[i]) { |
| 314 | /* If any devices registered, return success. Else the last error. */ |
| 315 | mtd_device_parse_register(cs553x_mtd[i], NULL, NULL, |
| 316 | NULL, 0); |
| 317 | err = 0; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | return err; |
| 322 | } |
| 323 | |
| 324 | module_init(cs553x_init); |
| 325 | |
| 326 | static void __exit cs553x_cleanup(void) |
| 327 | { |
| 328 | int i; |
| 329 | |
| 330 | for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { |
| 331 | struct mtd_info *mtd = cs553x_mtd[i]; |
| 332 | struct nand_chip *this; |
| 333 | void __iomem *mmio_base; |
| 334 | |
| 335 | if (!mtd) |
| 336 | continue; |
| 337 | |
| 338 | this = mtd_to_nand(mtd); |
| 339 | mmio_base = this->IO_ADDR_R; |
| 340 | |
| 341 | /* Release resources, unregister device */ |
| 342 | nand_release(mtd); |
| 343 | kfree(mtd->name); |
| 344 | cs553x_mtd[i] = NULL; |
| 345 | |
| 346 | /* unmap physical address */ |
| 347 | iounmap(mmio_base); |
| 348 | |
| 349 | /* Free the MTD device structure */ |
| 350 | kfree(this); |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | module_exit(cs553x_cleanup); |
| 355 | |
| 356 | MODULE_LICENSE("GPL"); |
| 357 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); |
| 358 | MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip"); |