[linux-block.git] / drivers / misc / mei / pci-me.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
 * Intel Management Engine Interface (Intel MEI) Linux driver
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(dev->dev);

	return pci_read_config_dword(pdev, where, val);
}

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg;
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;

	cfg = mei_me_get_cfg(ent->driver_data);
	if (!cfg)
		return -ENODEV;

	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions and mapping IO device memory for mei driver */
	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto end;
	}

	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto end;
	}

	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(&pdev->dev, cfg, false);
	if (!dev) {
		err = -ENOMEM;
		goto end;
	}
	hw = to_me_hw(dev);
	hw->mem_addr = pcim_iomap_table(pdev)[0];
	hw->read_fws = mei_me_read_fws;

	pci_enable_msi(pdev);

	hw->irq = pdev->irq;

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto end;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	 * MEI requires to resume from runtime suspend mode
	 * in order to perform link reset flow upon system suspend.
	 */
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);

	/*
	 * ME maps runtime suspend/resume to D0i states,
	 * hence we need to go around native PCI runtime service which
	 * eventually brings the device into D3cold/hot state,
	 * but the mei device cannot wake up from D3 unlike from D0i3.
	 * To get around the PCI device native runtime pm,
	 * ME uses runtime pm domain handlers which take precedence
	 * over the driver's pm handlers.
	 */
	mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev)) {
		pm_runtime_put_noidle(&pdev->dev);
		if (hw->d0i3_supported)
			pm_runtime_allow(&pdev->dev);
	}

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_shutdown - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_shutdown is called from the reboot notifier
 * it's a simplified version of remove so we go down
 * faster.
 */
static void mei_me_shutdown(struct pci_dev *pdev)
{
	struct mei_device *dev = pci_get_drvdata(pdev);

	dev_dbg(&pdev->dev, "shutdown\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);

	mei_deregister(dev);
}

#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_prepare(struct device *device)
{
	pm_runtime_resume(device);
	return 0;
}

static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);
	unsigned int irqflags;
	int err;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}

static void mei_me_pci_complete(struct device *device)
{
	pm_runtime_suspend(device);
}
#else /* CONFIG_PM_SLEEP */

#define mei_me_pci_prepare NULL
#define mei_me_pci_complete NULL

#endif /* !CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct mei_device *dev = dev_get_drvdata(device);

	dev_dbg(device, "rpm: me: runtime_idle\n");

	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct mei_device *dev = dev_get_drvdata(device);
	int ret;

	dev_dbg(device, "rpm: me: runtime suspend\n");

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct mei_device *dev = dev_get_drvdata(device);
	int ret;

	dev_dbg(device, "rpm: me: runtime resume\n");

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	.prepare = mei_me_pci_prepare,
	.complete = mei_me_pci_complete,
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_shutdown,
	.driver.pm = MEI_ME_PM_OPS,
	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
	4	* Intel Management Engine Interface (Intel MEI) Linux driver
	5	*/
	6
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
	9	#include <linux/device.h>
	10	#include <linux/errno.h>
	11	#include <linux/types.h>
	12	#include <linux/pci.h>
	13	#include <linux/dma-mapping.h>
	14	#include <linux/sched.h>
	15	#include <linux/interrupt.h>
	16
	17	#include <linux/pm_domain.h>
	18	#include <linux/pm_runtime.h>
	19
	20	#include <linux/mei.h>
	21
	22	#include "mei_dev.h"
	23	#include "client.h"
	24	#include "hw-me-regs.h"
	25	#include "hw-me.h"
	26
	27	/* mei_pci_tbl - PCI Device ID Table */
	28	static const struct pci_device_id mei_me_pci_tbl[] = {
	29	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	30	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	31	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	32	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	33	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	34	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	35	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	36	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	37	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	38	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	39	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
	40
	41	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	42	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	43	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	44	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	45	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	46	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
	50
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
	55
	56	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
	57	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
	58	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	59	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	60	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
	63	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	64	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
	65	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	66	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
	67	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
	69
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	71	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	72	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
	73	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	74	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
	75	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
	76
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
	79
	80	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
	81
	82	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
	83
	84	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
	85	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
	86	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
	87
	88	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
	89	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	90	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
	91	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
	92
	93	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
	94	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	95	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
	96	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
	97	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
	98
	99	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
	100	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
	101
	102	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
	103	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
	104
	105	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
	106
	107	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
	108	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
	109
	110	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
	111
	112	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
	113
	114	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
	115	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
	116	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
	117	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
	118
	119	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
	120
	121	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
	122	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
	123	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
	124
	125	{MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
	126
	127	/* required last entry */
	128	{0, }
	129	};
	130
	131	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
	132
	133	#ifdef CONFIG_PM
	134	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	135	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	136	#else
	137	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	138	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
	139	#endif /* CONFIG_PM */
	140
	141	static int mei_me_read_fws(const struct mei_device dev, int where, u32 val)
	142	{
	143	struct pci_dev *pdev = to_pci_dev(dev->dev);
	144
	145	return pci_read_config_dword(pdev, where, val);
	146	}
	147
	148	/**
	149	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
	150	*
	151	* @pdev: PCI device structure
	152	* @cfg: per generation config
	153	*
	154	* Return: true if ME Interface is valid, false otherwise
	155	*/
	156	static bool mei_me_quirk_probe(struct pci_dev *pdev,
	157	const struct mei_cfg *cfg)
	158	{
	159	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	160	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	161	return false;
	162	}
	163
	164	return true;
	165	}
	166
	167	/**
	168	* mei_me_probe - Device Initialization Routine
	169	*
	170	* @pdev: PCI device structure
	171	* @ent: entry in kcs_pci_tbl
	172	*
	173	* Return: 0 on success, <0 on failure.
	174	*/
	175	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
	176	{
	177	const struct mei_cfg *cfg;
	178	struct mei_device *dev;
	179	struct mei_me_hw *hw;
	180	unsigned int irqflags;
	181	int err;
	182
	183	cfg = mei_me_get_cfg(ent->driver_data);
	184	if (!cfg)
	185	return -ENODEV;
	186
	187	if (!mei_me_quirk_probe(pdev, cfg))
	188	return -ENODEV;
	189
	190	/* enable pci dev */
	191	err = pcim_enable_device(pdev);
	192	if (err) {
	193	dev_err(&pdev->dev, "failed to enable pci device.\n");
	194	goto end;
	195	}
	196	/* set PCI host mastering */
	197	pci_set_master(pdev);
	198	/* pci request regions and mapping IO device memory for mei driver */
	199	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	200	if (err) {
	201	dev_err(&pdev->dev, "failed to get pci regions.\n");
	202	goto end;
	203	}
	204
	205	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	206	if (err) {
	207	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
	208	goto end;
	209	}
	210
	211	/* allocates and initializes the mei dev structure */
	212	dev = mei_me_dev_init(&pdev->dev, cfg, false);
	213	if (!dev) {
	214	err = -ENOMEM;
	215	goto end;
	216	}
	217	hw = to_me_hw(dev);
	218	hw->mem_addr = pcim_iomap_table(pdev)[0];
	219	hw->read_fws = mei_me_read_fws;
	220
	221	pci_enable_msi(pdev);
	222
	223	hw->irq = pdev->irq;
	224
	225	/* request and enable interrupt */
	226	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	227
	228	err = request_threaded_irq(pdev->irq,
	229	mei_me_irq_quick_handler,
	230	mei_me_irq_thread_handler,
	231	irqflags, KBUILD_MODNAME, dev);
	232	if (err) {
	233	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	234	pdev->irq);
	235	goto end;
	236	}
	237
	238	if (mei_start(dev)) {
	239	dev_err(&pdev->dev, "init hw failure.\n");
	240	err = -ENODEV;
	241	goto release_irq;
	242	}
	243
	244	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	245	pm_runtime_use_autosuspend(&pdev->dev);
	246
	247	err = mei_register(dev, &pdev->dev);
	248	if (err)
	249	goto stop;
	250
	251	pci_set_drvdata(pdev, dev);
	252
	253	/*
	254	* MEI requires to resume from runtime suspend mode
	255	* in order to perform link reset flow upon system suspend.
	256	*/
	257	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
	258
	259	/*
	260	* ME maps runtime suspend/resume to D0i states,
	261	* hence we need to go around native PCI runtime service which
	262	* eventually brings the device into D3cold/hot state,
	263	* but the mei device cannot wake up from D3 unlike from D0i3.
	264	* To get around the PCI device native runtime pm,
	265	* ME uses runtime pm domain handlers which take precedence
	266	* over the driver's pm handlers.
	267	*/
	268	mei_me_set_pm_domain(dev);
	269
	270	if (mei_pg_is_enabled(dev)) {
	271	pm_runtime_put_noidle(&pdev->dev);
	272	if (hw->d0i3_supported)
	273	pm_runtime_allow(&pdev->dev);
	274	}
	275
	276	dev_dbg(&pdev->dev, "initialization successful.\n");
	277
	278	return 0;
	279
	280	stop:
	281	mei_stop(dev);
	282	release_irq:
	283	mei_cancel_work(dev);
	284	mei_disable_interrupts(dev);
	285	free_irq(pdev->irq, dev);
	286	end:
	287	dev_err(&pdev->dev, "initialization failed.\n");
	288	return err;
	289	}
	290
	291	/**
	292	* mei_me_shutdown - Device Removal Routine
	293	*
	294	* @pdev: PCI device structure
	295	*
	296	* mei_me_shutdown is called from the reboot notifier
	297	* it's a simplified version of remove so we go down
	298	* faster.
	299	*/
	300	static void mei_me_shutdown(struct pci_dev *pdev)
	301	{
	302	struct mei_device *dev = pci_get_drvdata(pdev);
	303
	304	dev_dbg(&pdev->dev, "shutdown\n");
	305	mei_stop(dev);
	306
	307	mei_me_unset_pm_domain(dev);
	308
	309	mei_disable_interrupts(dev);
	310	free_irq(pdev->irq, dev);
	311	}
	312
	313	/**
	314	* mei_me_remove - Device Removal Routine
	315	*
	316	* @pdev: PCI device structure
	317	*
	318	* mei_me_remove is called by the PCI subsystem to alert the driver
	319	* that it should release a PCI device.
	320	*/
	321	static void mei_me_remove(struct pci_dev *pdev)
	322	{
	323	struct mei_device *dev = pci_get_drvdata(pdev);
	324
	325	if (mei_pg_is_enabled(dev))
	326	pm_runtime_get_noresume(&pdev->dev);
	327
	328	dev_dbg(&pdev->dev, "stop\n");
	329	mei_stop(dev);
	330
	331	mei_me_unset_pm_domain(dev);
	332
	333	mei_disable_interrupts(dev);
	334
	335	free_irq(pdev->irq, dev);
	336
	337	mei_deregister(dev);
	338	}
	339
	340	#ifdef CONFIG_PM_SLEEP
	341	static int mei_me_pci_prepare(struct device *device)
	342	{
	343	pm_runtime_resume(device);
	344	return 0;
	345	}
	346
	347	static int mei_me_pci_suspend(struct device *device)
	348	{
	349	struct pci_dev *pdev = to_pci_dev(device);
	350	struct mei_device *dev = pci_get_drvdata(pdev);
	351
	352	dev_dbg(&pdev->dev, "suspend\n");
	353
	354	mei_stop(dev);
	355
	356	mei_disable_interrupts(dev);
	357
	358	free_irq(pdev->irq, dev);
	359	pci_disable_msi(pdev);
	360
	361	return 0;
	362	}
	363
	364	static int mei_me_pci_resume(struct device *device)
	365	{
	366	struct pci_dev *pdev = to_pci_dev(device);
	367	struct mei_device *dev = pci_get_drvdata(pdev);
	368	unsigned int irqflags;
	369	int err;
	370
	371	pci_enable_msi(pdev);
	372
	373	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	374
	375	/* request and enable interrupt */
	376	err = request_threaded_irq(pdev->irq,
	377	mei_me_irq_quick_handler,
	378	mei_me_irq_thread_handler,
	379	irqflags, KBUILD_MODNAME, dev);
	380
	381	if (err) {
	382	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	383	pdev->irq);
	384	return err;
	385	}
	386
	387	err = mei_restart(dev);
	388	if (err)
	389	return err;
	390
	391	/* Start timer if stopped in suspend */
	392	schedule_delayed_work(&dev->timer_work, HZ);
	393
	394	return 0;
	395	}
	396
	397	static void mei_me_pci_complete(struct device *device)
	398	{
	399	pm_runtime_suspend(device);
	400	}
	401	#else /* CONFIG_PM_SLEEP */
	402
	403	#define mei_me_pci_prepare NULL
	404	#define mei_me_pci_complete NULL
	405
	406	#endif /* !CONFIG_PM_SLEEP */
	407
	408	#ifdef CONFIG_PM
	409	static int mei_me_pm_runtime_idle(struct device *device)
	410	{
	411	struct mei_device *dev = dev_get_drvdata(device);
	412
	413	dev_dbg(device, "rpm: me: runtime_idle\n");
	414
	415	if (mei_write_is_idle(dev))
	416	pm_runtime_autosuspend(device);
	417
	418	return -EBUSY;
	419	}
	420
	421	static int mei_me_pm_runtime_suspend(struct device *device)
	422	{
	423	struct mei_device *dev = dev_get_drvdata(device);
	424	int ret;
	425
	426	dev_dbg(device, "rpm: me: runtime suspend\n");
	427
	428	mutex_lock(&dev->device_lock);
	429
	430	if (mei_write_is_idle(dev))
	431	ret = mei_me_pg_enter_sync(dev);
	432	else
	433	ret = -EAGAIN;
	434
	435	mutex_unlock(&dev->device_lock);
	436
	437	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
	438
	439	if (ret && ret != -EAGAIN)
	440	schedule_work(&dev->reset_work);
	441
	442	return ret;
	443	}
	444
	445	static int mei_me_pm_runtime_resume(struct device *device)
	446	{
	447	struct mei_device *dev = dev_get_drvdata(device);
	448	int ret;
	449
	450	dev_dbg(device, "rpm: me: runtime resume\n");
	451
	452	mutex_lock(&dev->device_lock);
	453
	454	ret = mei_me_pg_exit_sync(dev);
	455
	456	mutex_unlock(&dev->device_lock);
	457
	458	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
	459
	460	if (ret)
	461	schedule_work(&dev->reset_work);
	462
	463	return ret;
	464	}
	465
	466	/**
	467	* mei_me_set_pm_domain - fill and set pm domain structure for device
	468	*
	469	* @dev: mei_device
	470	*/
	471	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	472	{
	473	struct pci_dev *pdev = to_pci_dev(dev->dev);
	474
	475	if (pdev->dev.bus && pdev->dev.bus->pm) {
	476	dev->pg_domain.ops = *pdev->dev.bus->pm;
	477
	478	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	479	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	480	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	481
	482	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	483	}
	484	}
	485
	486	/**
	487	* mei_me_unset_pm_domain - clean pm domain structure for device
	488	*
	489	* @dev: mei_device
	490	*/
	491	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	492	{
	493	/* stop using pm callbacks if any */
	494	dev_pm_domain_set(dev->dev, NULL);
	495	}
	496
	497	static const struct dev_pm_ops mei_me_pm_ops = {
	498	.prepare = mei_me_pci_prepare,
	499	.complete = mei_me_pci_complete,
	500	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	501	mei_me_pci_resume)
	502	SET_RUNTIME_PM_OPS(
	503	mei_me_pm_runtime_suspend,
	504	mei_me_pm_runtime_resume,
	505	mei_me_pm_runtime_idle)
	506	};
	507
	508	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
	509	#else
	510	#define MEI_ME_PM_OPS NULL
	511	#endif /* CONFIG_PM */
	512	/*
	513	* PCI driver structure
	514	*/
	515	static struct pci_driver mei_me_driver = {
	516	.name = KBUILD_MODNAME,
	517	.id_table = mei_me_pci_tbl,
	518	.probe = mei_me_probe,
	519	.remove = mei_me_remove,
	520	.shutdown = mei_me_shutdown,
	521	.driver.pm = MEI_ME_PM_OPS,
	522	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
	523	};
	524
	525	module_pci_driver(mei_me_driver);
	526
	527	MODULE_AUTHOR("Intel Corporation");
	528	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	529	MODULE_LICENSE("GPL v2");