| 1 | /* |
| 2 | * tw68-core.c |
| 3 | * Core functions for the Techwell 68xx driver |
| 4 | * |
| 5 | * Much of this code is derived from the cx88 and sa7134 drivers, which |
| 6 | * were in turn derived from the bt87x driver. The original work was by |
| 7 | * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab, |
| 8 | * Hans Verkuil, Andy Walls and many others. Their work is gratefully |
| 9 | * acknowledged. Full credit goes to them - any problems within this code |
| 10 | * are mine. |
| 11 | * |
| 12 | * Copyright (C) 2009 William M. Brack |
| 13 | * |
| 14 | * Refactored and updated to the latest v4l core frameworks: |
| 15 | * |
| 16 | * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl> |
| 17 | * |
| 18 | * This program is free software; you can redistribute it and/or modify |
| 19 | * it under the terms of the GNU General Public License as published by |
| 20 | * the Free Software Foundation; either version 2 of the License, or |
| 21 | * (at your option) any later version. |
| 22 | * |
| 23 | * This program is distributed in the hope that it will be useful, |
| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 26 | * GNU General Public License for more details. |
| 27 | */ |
| 28 | |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/list.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/kernel.h> |
| 33 | #include <linux/slab.h> |
| 34 | #include <linux/kmod.h> |
| 35 | #include <linux/sound.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/delay.h> |
| 38 | #include <linux/mutex.h> |
| 39 | #include <linux/dma-mapping.h> |
| 40 | #include <linux/pci_ids.h> |
| 41 | #include <linux/pm.h> |
| 42 | |
| 43 | #include <media/v4l2-dev.h> |
| 44 | #include "tw68.h" |
| 45 | #include "tw68-reg.h" |
| 46 | |
| 47 | MODULE_DESCRIPTION("v4l2 driver module for tw6800 based video capture cards"); |
| 48 | MODULE_AUTHOR("William M. Brack"); |
| 49 | MODULE_AUTHOR("Hans Verkuil <hverkuil@xs4all.nl>"); |
| 50 | MODULE_LICENSE("GPL"); |
| 51 | |
| 52 | static unsigned int latency = UNSET; |
| 53 | module_param(latency, int, 0444); |
| 54 | MODULE_PARM_DESC(latency, "pci latency timer"); |
| 55 | |
| 56 | static unsigned int video_nr[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; |
| 57 | module_param_array(video_nr, int, NULL, 0444); |
| 58 | MODULE_PARM_DESC(video_nr, "video device number"); |
| 59 | |
| 60 | static unsigned int card[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; |
| 61 | module_param_array(card, int, NULL, 0444); |
| 62 | MODULE_PARM_DESC(card, "card type"); |
| 63 | |
| 64 | static atomic_t tw68_instance = ATOMIC_INIT(0); |
| 65 | |
| 66 | /* ------------------------------------------------------------------ */ |
| 67 | |
| 68 | /* |
| 69 | * Please add any new PCI IDs to: http://pci-ids.ucw.cz. This keeps |
| 70 | * the PCI ID database up to date. Note that the entries must be |
| 71 | * added under vendor 0x1797 (Techwell Inc.) as subsystem IDs. |
| 72 | */ |
| 73 | static const struct pci_device_id tw68_pci_tbl[] = { |
| 74 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6800)}, |
| 75 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6801)}, |
| 76 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6804)}, |
| 77 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_1)}, |
| 78 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_2)}, |
| 79 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_3)}, |
| 80 | {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_4)}, |
| 81 | {0,} |
| 82 | }; |
| 83 | |
| 84 | /* ------------------------------------------------------------------ */ |
| 85 | |
| 86 | |
| 87 | /* |
| 88 | * The device is given a "soft reset". According to the specifications, |
| 89 | * after this "all register content remain unchanged", so we also write |
| 90 | * to all specified registers manually as well (mostly to manufacturer's |
| 91 | * specified reset values) |
| 92 | */ |
| 93 | static int tw68_hw_init1(struct tw68_dev *dev) |
| 94 | { |
| 95 | /* Assure all interrupts are disabled */ |
| 96 | tw_writel(TW68_INTMASK, 0); /* 020 */ |
| 97 | /* Clear any pending interrupts */ |
| 98 | tw_writel(TW68_INTSTAT, 0xffffffff); /* 01C */ |
| 99 | /* Stop risc processor, set default buffer level */ |
| 100 | tw_writel(TW68_DMAC, 0x1600); |
| 101 | |
| 102 | tw_writeb(TW68_ACNTL, 0x80); /* 218 soft reset */ |
| 103 | msleep(100); |
| 104 | |
| 105 | tw_writeb(TW68_INFORM, 0x40); /* 208 mux0, 27mhz xtal */ |
| 106 | tw_writeb(TW68_OPFORM, 0x04); /* 20C analog line-lock */ |
| 107 | tw_writeb(TW68_HSYNC, 0); /* 210 color-killer high sens */ |
| 108 | tw_writeb(TW68_ACNTL, 0x42); /* 218 int vref #2, chroma adc off */ |
| 109 | |
| 110 | tw_writeb(TW68_CROP_HI, 0x02); /* 21C Hactive m.s. bits */ |
| 111 | tw_writeb(TW68_VDELAY_LO, 0x12);/* 220 Mfg specified reset value */ |
| 112 | tw_writeb(TW68_VACTIVE_LO, 0xf0); |
| 113 | tw_writeb(TW68_HDELAY_LO, 0x0f); |
| 114 | tw_writeb(TW68_HACTIVE_LO, 0xd0); |
| 115 | |
| 116 | tw_writeb(TW68_CNTRL1, 0xcd); /* 230 Wide Chroma BPF B/W |
| 117 | * Secam reduction, Adap comb for |
| 118 | * NTSC, Op Mode 1 */ |
| 119 | |
| 120 | tw_writeb(TW68_VSCALE_LO, 0); /* 234 */ |
| 121 | tw_writeb(TW68_SCALE_HI, 0x11); /* 238 */ |
| 122 | tw_writeb(TW68_HSCALE_LO, 0); /* 23c */ |
| 123 | tw_writeb(TW68_BRIGHT, 0); /* 240 */ |
| 124 | tw_writeb(TW68_CONTRAST, 0x5c); /* 244 */ |
| 125 | tw_writeb(TW68_SHARPNESS, 0x51);/* 248 */ |
| 126 | tw_writeb(TW68_SAT_U, 0x80); /* 24C */ |
| 127 | tw_writeb(TW68_SAT_V, 0x80); /* 250 */ |
| 128 | tw_writeb(TW68_HUE, 0x00); /* 254 */ |
| 129 | |
| 130 | /* TODO - Check that none of these are set by control defaults */ |
| 131 | tw_writeb(TW68_SHARP2, 0x53); /* 258 Mfg specified reset val */ |
| 132 | tw_writeb(TW68_VSHARP, 0x80); /* 25C Sharpness Coring val 8 */ |
| 133 | tw_writeb(TW68_CORING, 0x44); /* 260 CTI and Vert Peak coring */ |
| 134 | tw_writeb(TW68_CNTRL2, 0x00); /* 268 No power saving enabled */ |
| 135 | tw_writeb(TW68_SDT, 0x07); /* 270 Enable shadow reg, auto-det */ |
| 136 | tw_writeb(TW68_SDTR, 0x7f); /* 274 All stds recog, don't start */ |
| 137 | tw_writeb(TW68_CLMPG, 0x50); /* 280 Clamp end at 40 sys clocks */ |
| 138 | tw_writeb(TW68_IAGC, 0x22); /* 284 Mfg specified reset val */ |
| 139 | tw_writeb(TW68_AGCGAIN, 0xf0); /* 288 AGC gain when loop disabled */ |
| 140 | tw_writeb(TW68_PEAKWT, 0xd8); /* 28C White peak threshold */ |
| 141 | tw_writeb(TW68_CLMPL, 0x3c); /* 290 Y channel clamp level */ |
| 142 | /* tw_writeb(TW68_SYNCT, 0x38);*/ /* 294 Sync amplitude */ |
| 143 | tw_writeb(TW68_SYNCT, 0x30); /* 294 Sync amplitude */ |
| 144 | tw_writeb(TW68_MISSCNT, 0x44); /* 298 Horiz sync, VCR detect sens */ |
| 145 | tw_writeb(TW68_PCLAMP, 0x28); /* 29C Clamp pos from PLL sync */ |
| 146 | /* Bit DETV of VCNTL1 helps sync multi cams/chip board */ |
| 147 | tw_writeb(TW68_VCNTL1, 0x04); /* 2A0 */ |
| 148 | tw_writeb(TW68_VCNTL2, 0); /* 2A4 */ |
| 149 | tw_writeb(TW68_CKILL, 0x68); /* 2A8 Mfg specified reset val */ |
| 150 | tw_writeb(TW68_COMB, 0x44); /* 2AC Mfg specified reset val */ |
| 151 | tw_writeb(TW68_LDLY, 0x30); /* 2B0 Max positive luma delay */ |
| 152 | tw_writeb(TW68_MISC1, 0x14); /* 2B4 Mfg specified reset val */ |
| 153 | tw_writeb(TW68_LOOP, 0xa5); /* 2B8 Mfg specified reset val */ |
| 154 | tw_writeb(TW68_MISC2, 0xe0); /* 2BC Enable colour killer */ |
| 155 | tw_writeb(TW68_MVSN, 0); /* 2C0 */ |
| 156 | tw_writeb(TW68_CLMD, 0x05); /* 2CC slice level auto, clamp med. */ |
| 157 | tw_writeb(TW68_IDCNTL, 0); /* 2D0 Writing zero to this register |
| 158 | * selects NTSC ID detection, |
| 159 | * but doesn't change the |
| 160 | * sensitivity (which has a reset |
| 161 | * value of 1E). Since we are |
| 162 | * not doing auto-detection, it |
| 163 | * has no real effect */ |
| 164 | tw_writeb(TW68_CLCNTL1, 0); /* 2D4 */ |
| 165 | tw_writel(TW68_VBIC, 0x03); /* 010 */ |
| 166 | tw_writel(TW68_CAP_CTL, 0x03); /* 040 Enable both even & odd flds */ |
| 167 | tw_writel(TW68_DMAC, 0x2000); /* patch set had 0x2080 */ |
| 168 | tw_writel(TW68_TESTREG, 0); /* 02C */ |
| 169 | |
| 170 | /* |
| 171 | * Some common boards, especially inexpensive single-chip models, |
| 172 | * use the GPIO bits 0-3 to control an on-board video-output mux. |
| 173 | * For these boards, we need to set up the GPIO register into |
| 174 | * "normal" mode, set bits 0-3 as output, and then set those bits |
| 175 | * zero. |
| 176 | * |
| 177 | * Eventually, it would be nice if we could identify these boards |
| 178 | * uniquely, and only do this initialisation if the board has been |
| 179 | * identify. For the moment, however, it shouldn't hurt anything |
| 180 | * to do these steps. |
| 181 | */ |
| 182 | tw_writel(TW68_GPIOC, 0); /* Set the GPIO to "normal", no ints */ |
| 183 | tw_writel(TW68_GPOE, 0x0f); /* Set bits 0-3 to "output" */ |
| 184 | tw_writel(TW68_GPDATA, 0); /* Set all bits to low state */ |
| 185 | |
| 186 | /* Initialize the device control structures */ |
| 187 | mutex_init(&dev->lock); |
| 188 | spin_lock_init(&dev->slock); |
| 189 | |
| 190 | /* Initialize any subsystems */ |
| 191 | tw68_video_init1(dev); |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | static irqreturn_t tw68_irq(int irq, void *dev_id) |
| 196 | { |
| 197 | struct tw68_dev *dev = dev_id; |
| 198 | u32 status, orig; |
| 199 | int loop; |
| 200 | |
| 201 | status = orig = tw_readl(TW68_INTSTAT) & dev->pci_irqmask; |
| 202 | /* Check if anything to do */ |
| 203 | if (0 == status) |
| 204 | return IRQ_NONE; /* Nope - return */ |
| 205 | for (loop = 0; loop < 10; loop++) { |
| 206 | if (status & dev->board_virqmask) /* video interrupt */ |
| 207 | tw68_irq_video_done(dev, status); |
| 208 | status = tw_readl(TW68_INTSTAT) & dev->pci_irqmask; |
| 209 | if (0 == status) |
| 210 | return IRQ_HANDLED; |
| 211 | } |
| 212 | dev_dbg(&dev->pci->dev, "%s: **** INTERRUPT NOT HANDLED - clearing mask (orig 0x%08x, cur 0x%08x)", |
| 213 | dev->name, orig, tw_readl(TW68_INTSTAT)); |
| 214 | dev_dbg(&dev->pci->dev, "%s: pci_irqmask 0x%08x; board_virqmask 0x%08x ****\n", |
| 215 | dev->name, dev->pci_irqmask, dev->board_virqmask); |
| 216 | tw_clearl(TW68_INTMASK, dev->pci_irqmask); |
| 217 | return IRQ_HANDLED; |
| 218 | } |
| 219 | |
| 220 | static int tw68_initdev(struct pci_dev *pci_dev, |
| 221 | const struct pci_device_id *pci_id) |
| 222 | { |
| 223 | struct tw68_dev *dev; |
| 224 | int vidnr = -1; |
| 225 | int err; |
| 226 | |
| 227 | dev = devm_kzalloc(&pci_dev->dev, sizeof(*dev), GFP_KERNEL); |
| 228 | if (NULL == dev) |
| 229 | return -ENOMEM; |
| 230 | |
| 231 | dev->instance = v4l2_device_set_name(&dev->v4l2_dev, "tw68", |
| 232 | &tw68_instance); |
| 233 | |
| 234 | err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); |
| 235 | if (err) |
| 236 | return err; |
| 237 | |
| 238 | /* pci init */ |
| 239 | dev->pci = pci_dev; |
| 240 | if (pci_enable_device(pci_dev)) { |
| 241 | err = -EIO; |
| 242 | goto fail1; |
| 243 | } |
| 244 | |
| 245 | dev->name = dev->v4l2_dev.name; |
| 246 | |
| 247 | if (UNSET != latency) { |
| 248 | pr_info("%s: setting pci latency timer to %d\n", |
| 249 | dev->name, latency); |
| 250 | pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency); |
| 251 | } |
| 252 | |
| 253 | /* print pci info */ |
| 254 | pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); |
| 255 | pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); |
| 256 | pr_info("%s: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", |
| 257 | dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq, |
| 258 | dev->pci_lat, (u64)pci_resource_start(pci_dev, 0)); |
| 259 | pci_set_master(pci_dev); |
| 260 | if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) { |
| 261 | pr_info("%s: Oops: no 32bit PCI DMA ???\n", dev->name); |
| 262 | err = -EIO; |
| 263 | goto fail1; |
| 264 | } |
| 265 | |
| 266 | switch (pci_id->device) { |
| 267 | case PCI_DEVICE_ID_TECHWELL_6800: /* TW6800 */ |
| 268 | dev->vdecoder = TW6800; |
| 269 | dev->board_virqmask = TW68_VID_INTS; |
| 270 | break; |
| 271 | case PCI_DEVICE_ID_TECHWELL_6801: /* Video decoder for TW6802 */ |
| 272 | dev->vdecoder = TW6801; |
| 273 | dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX; |
| 274 | break; |
| 275 | case PCI_DEVICE_ID_TECHWELL_6804: /* Video decoder for TW6804 */ |
| 276 | dev->vdecoder = TW6804; |
| 277 | dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX; |
| 278 | break; |
| 279 | default: |
| 280 | dev->vdecoder = TWXXXX; /* To be announced */ |
| 281 | dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX; |
| 282 | break; |
| 283 | } |
| 284 | |
| 285 | /* get mmio */ |
| 286 | if (!request_mem_region(pci_resource_start(pci_dev, 0), |
| 287 | pci_resource_len(pci_dev, 0), |
| 288 | dev->name)) { |
| 289 | err = -EBUSY; |
| 290 | pr_err("%s: can't get MMIO memory @ 0x%llx\n", |
| 291 | dev->name, |
| 292 | (unsigned long long)pci_resource_start(pci_dev, 0)); |
| 293 | goto fail1; |
| 294 | } |
| 295 | dev->lmmio = ioremap(pci_resource_start(pci_dev, 0), |
| 296 | pci_resource_len(pci_dev, 0)); |
| 297 | dev->bmmio = (__u8 __iomem *)dev->lmmio; |
| 298 | if (NULL == dev->lmmio) { |
| 299 | err = -EIO; |
| 300 | pr_err("%s: can't ioremap() MMIO memory\n", |
| 301 | dev->name); |
| 302 | goto fail2; |
| 303 | } |
| 304 | /* initialize hardware #1 */ |
| 305 | /* Then do any initialisation wanted before interrupts are on */ |
| 306 | tw68_hw_init1(dev); |
| 307 | |
| 308 | dev->alloc_ctx = vb2_dma_sg_init_ctx(&pci_dev->dev); |
| 309 | if (IS_ERR(dev->alloc_ctx)) { |
| 310 | err = PTR_ERR(dev->alloc_ctx); |
| 311 | goto fail3; |
| 312 | } |
| 313 | |
| 314 | /* get irq */ |
| 315 | err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw68_irq, |
| 316 | IRQF_SHARED, dev->name, dev); |
| 317 | if (err < 0) { |
| 318 | pr_err("%s: can't get IRQ %d\n", |
| 319 | dev->name, pci_dev->irq); |
| 320 | goto fail4; |
| 321 | } |
| 322 | |
| 323 | /* |
| 324 | * Now do remainder of initialisation, first for |
| 325 | * things unique for this card, then for general board |
| 326 | */ |
| 327 | if (dev->instance < TW68_MAXBOARDS) |
| 328 | vidnr = video_nr[dev->instance]; |
| 329 | /* initialise video function first */ |
| 330 | err = tw68_video_init2(dev, vidnr); |
| 331 | if (err < 0) { |
| 332 | pr_err("%s: can't register video device\n", |
| 333 | dev->name); |
| 334 | goto fail5; |
| 335 | } |
| 336 | tw_setl(TW68_INTMASK, dev->pci_irqmask); |
| 337 | |
| 338 | pr_info("%s: registered device %s\n", |
| 339 | dev->name, video_device_node_name(&dev->vdev)); |
| 340 | |
| 341 | return 0; |
| 342 | |
| 343 | fail5: |
| 344 | video_unregister_device(&dev->vdev); |
| 345 | fail4: |
| 346 | vb2_dma_sg_cleanup_ctx(dev->alloc_ctx); |
| 347 | fail3: |
| 348 | iounmap(dev->lmmio); |
| 349 | fail2: |
| 350 | release_mem_region(pci_resource_start(pci_dev, 0), |
| 351 | pci_resource_len(pci_dev, 0)); |
| 352 | fail1: |
| 353 | v4l2_device_unregister(&dev->v4l2_dev); |
| 354 | return err; |
| 355 | } |
| 356 | |
| 357 | static void tw68_finidev(struct pci_dev *pci_dev) |
| 358 | { |
| 359 | struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); |
| 360 | struct tw68_dev *dev = |
| 361 | container_of(v4l2_dev, struct tw68_dev, v4l2_dev); |
| 362 | |
| 363 | /* shutdown subsystems */ |
| 364 | tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN); |
| 365 | tw_writel(TW68_INTMASK, 0); |
| 366 | |
| 367 | /* unregister */ |
| 368 | video_unregister_device(&dev->vdev); |
| 369 | v4l2_ctrl_handler_free(&dev->hdl); |
| 370 | vb2_dma_sg_cleanup_ctx(dev->alloc_ctx); |
| 371 | |
| 372 | /* release resources */ |
| 373 | iounmap(dev->lmmio); |
| 374 | release_mem_region(pci_resource_start(pci_dev, 0), |
| 375 | pci_resource_len(pci_dev, 0)); |
| 376 | |
| 377 | v4l2_device_unregister(&dev->v4l2_dev); |
| 378 | } |
| 379 | |
| 380 | #ifdef CONFIG_PM |
| 381 | |
| 382 | static int tw68_suspend(struct pci_dev *pci_dev , pm_message_t state) |
| 383 | { |
| 384 | struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); |
| 385 | struct tw68_dev *dev = container_of(v4l2_dev, |
| 386 | struct tw68_dev, v4l2_dev); |
| 387 | |
| 388 | tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN); |
| 389 | dev->pci_irqmask &= ~TW68_VID_INTS; |
| 390 | tw_writel(TW68_INTMASK, 0); |
| 391 | |
| 392 | synchronize_irq(pci_dev->irq); |
| 393 | |
| 394 | pci_save_state(pci_dev); |
| 395 | pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state)); |
| 396 | vb2_discard_done(&dev->vidq); |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | static int tw68_resume(struct pci_dev *pci_dev) |
| 402 | { |
| 403 | struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); |
| 404 | struct tw68_dev *dev = container_of(v4l2_dev, |
| 405 | struct tw68_dev, v4l2_dev); |
| 406 | struct tw68_buf *buf; |
| 407 | unsigned long flags; |
| 408 | |
| 409 | pci_set_power_state(pci_dev, PCI_D0); |
| 410 | pci_restore_state(pci_dev); |
| 411 | |
| 412 | /* Do things that are done in tw68_initdev , |
| 413 | except of initializing memory structures.*/ |
| 414 | |
| 415 | msleep(100); |
| 416 | |
| 417 | tw68_set_tvnorm_hw(dev); |
| 418 | |
| 419 | /*resume unfinished buffer(s)*/ |
| 420 | spin_lock_irqsave(&dev->slock, flags); |
| 421 | buf = container_of(dev->active.next, struct tw68_buf, list); |
| 422 | |
| 423 | tw68_video_start_dma(dev, buf); |
| 424 | |
| 425 | spin_unlock_irqrestore(&dev->slock, flags); |
| 426 | |
| 427 | return 0; |
| 428 | } |
| 429 | #endif |
| 430 | |
| 431 | /* ----------------------------------------------------------- */ |
| 432 | |
| 433 | static struct pci_driver tw68_pci_driver = { |
| 434 | .name = "tw68", |
| 435 | .id_table = tw68_pci_tbl, |
| 436 | .probe = tw68_initdev, |
| 437 | .remove = tw68_finidev, |
| 438 | #ifdef CONFIG_PM |
| 439 | .suspend = tw68_suspend, |
| 440 | .resume = tw68_resume |
| 441 | #endif |
| 442 | }; |
| 443 | |
| 444 | module_pci_driver(tw68_pci_driver); |