| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // Socionext MN88443x series demodulator driver for ISDB-S/ISDB-T. |
| 4 | // |
| 5 | // Copyright (c) 2018 Socionext Inc. |
| 6 | |
| 7 | #include <linux/bitfield.h> |
| 8 | #include <linux/clk.h> |
| 9 | #include <linux/delay.h> |
| 10 | #include <linux/gpio/consumer.h> |
| 11 | #include <linux/of_device.h> |
| 12 | #include <linux/regmap.h> |
| 13 | #include <media/dvb_math.h> |
| 14 | |
| 15 | #include "mn88443x.h" |
| 16 | |
| 17 | /* ISDB-S registers */ |
| 18 | #define ATSIDU_S 0x2f |
| 19 | #define ATSIDL_S 0x30 |
| 20 | #define TSSET_S 0x31 |
| 21 | #define AGCREAD_S 0x5a |
| 22 | #define CPMON1_S 0x5e |
| 23 | #define CPMON1_S_FSYNC BIT(5) |
| 24 | #define CPMON1_S_ERRMON BIT(4) |
| 25 | #define CPMON1_S_SIGOFF BIT(3) |
| 26 | #define CPMON1_S_W2LOCK BIT(2) |
| 27 | #define CPMON1_S_W1LOCK BIT(1) |
| 28 | #define CPMON1_S_DW1LOCK BIT(0) |
| 29 | #define TRMON_S 0x60 |
| 30 | #define BERCNFLG_S 0x68 |
| 31 | #define BERCNFLG_S_BERVRDY BIT(5) |
| 32 | #define BERCNFLG_S_BERVCHK BIT(4) |
| 33 | #define BERCNFLG_S_BERDRDY BIT(3) |
| 34 | #define BERCNFLG_S_BERDCHK BIT(2) |
| 35 | #define CNRDXU_S 0x69 |
| 36 | #define CNRDXL_S 0x6a |
| 37 | #define CNRDYU_S 0x6b |
| 38 | #define CNRDYL_S 0x6c |
| 39 | #define BERVRDU_S 0x71 |
| 40 | #define BERVRDL_S 0x72 |
| 41 | #define DOSET1_S 0x73 |
| 42 | |
| 43 | /* Primary ISDB-T */ |
| 44 | #define PLLASET1 0x00 |
| 45 | #define PLLASET2 0x01 |
| 46 | #define PLLBSET1 0x02 |
| 47 | #define PLLBSET2 0x03 |
| 48 | #define PLLSET 0x04 |
| 49 | #define OUTCSET 0x08 |
| 50 | #define OUTCSET_CHDRV_8MA 0xff |
| 51 | #define OUTCSET_CHDRV_4MA 0x00 |
| 52 | #define PLDWSET 0x09 |
| 53 | #define PLDWSET_NORMAL 0x00 |
| 54 | #define PLDWSET_PULLDOWN 0xff |
| 55 | #define HIZSET1 0x0a |
| 56 | #define HIZSET2 0x0b |
| 57 | |
| 58 | /* Secondary ISDB-T (for MN884434 only) */ |
| 59 | #define RCVSET 0x00 |
| 60 | #define TSSET1_M 0x01 |
| 61 | #define TSSET2_M 0x02 |
| 62 | #define TSSET3_M 0x03 |
| 63 | #define INTACSET 0x08 |
| 64 | #define HIZSET3 0x0b |
| 65 | |
| 66 | /* ISDB-T registers */ |
| 67 | #define TSSET1 0x05 |
| 68 | #define TSSET1_TSASEL_MASK GENMASK(4, 3) |
| 69 | #define TSSET1_TSASEL_ISDBT (0x0 << 3) |
| 70 | #define TSSET1_TSASEL_ISDBS (0x1 << 3) |
| 71 | #define TSSET1_TSASEL_NONE (0x2 << 3) |
| 72 | #define TSSET1_TSBSEL_MASK GENMASK(2, 1) |
| 73 | #define TSSET1_TSBSEL_ISDBS (0x0 << 1) |
| 74 | #define TSSET1_TSBSEL_ISDBT (0x1 << 1) |
| 75 | #define TSSET1_TSBSEL_NONE (0x2 << 1) |
| 76 | #define TSSET2 0x06 |
| 77 | #define TSSET3 0x07 |
| 78 | #define TSSET3_INTASEL_MASK GENMASK(7, 6) |
| 79 | #define TSSET3_INTASEL_T (0x0 << 6) |
| 80 | #define TSSET3_INTASEL_S (0x1 << 6) |
| 81 | #define TSSET3_INTASEL_NONE (0x2 << 6) |
| 82 | #define TSSET3_INTBSEL_MASK GENMASK(5, 4) |
| 83 | #define TSSET3_INTBSEL_S (0x0 << 4) |
| 84 | #define TSSET3_INTBSEL_T (0x1 << 4) |
| 85 | #define TSSET3_INTBSEL_NONE (0x2 << 4) |
| 86 | #define OUTSET2 0x0d |
| 87 | #define PWDSET 0x0f |
| 88 | #define PWDSET_OFDMPD_MASK GENMASK(3, 2) |
| 89 | #define PWDSET_OFDMPD_DOWN BIT(3) |
| 90 | #define PWDSET_PSKPD_MASK GENMASK(1, 0) |
| 91 | #define PWDSET_PSKPD_DOWN BIT(1) |
| 92 | #define CLKSET1_T 0x11 |
| 93 | #define MDSET_T 0x13 |
| 94 | #define MDSET_T_MDAUTO_MASK GENMASK(7, 4) |
| 95 | #define MDSET_T_MDAUTO_AUTO (0xf << 4) |
| 96 | #define MDSET_T_MDAUTO_MANUAL (0x0 << 4) |
| 97 | #define MDSET_T_FFTS_MASK GENMASK(3, 2) |
| 98 | #define MDSET_T_FFTS_MODE1 (0x0 << 2) |
| 99 | #define MDSET_T_FFTS_MODE2 (0x1 << 2) |
| 100 | #define MDSET_T_FFTS_MODE3 (0x2 << 2) |
| 101 | #define MDSET_T_GI_MASK GENMASK(1, 0) |
| 102 | #define MDSET_T_GI_1_32 (0x0 << 0) |
| 103 | #define MDSET_T_GI_1_16 (0x1 << 0) |
| 104 | #define MDSET_T_GI_1_8 (0x2 << 0) |
| 105 | #define MDSET_T_GI_1_4 (0x3 << 0) |
| 106 | #define MDASET_T 0x14 |
| 107 | #define ADCSET1_T 0x20 |
| 108 | #define ADCSET1_T_REFSEL_MASK GENMASK(1, 0) |
| 109 | #define ADCSET1_T_REFSEL_2V (0x3 << 0) |
| 110 | #define ADCSET1_T_REFSEL_1_5V (0x2 << 0) |
| 111 | #define ADCSET1_T_REFSEL_1V (0x1 << 0) |
| 112 | #define NCOFREQU_T 0x24 |
| 113 | #define NCOFREQM_T 0x25 |
| 114 | #define NCOFREQL_T 0x26 |
| 115 | #define FADU_T 0x27 |
| 116 | #define FADM_T 0x28 |
| 117 | #define FADL_T 0x29 |
| 118 | #define AGCSET2_T 0x2c |
| 119 | #define AGCSET2_T_IFPOLINV_INC BIT(0) |
| 120 | #define AGCSET2_T_RFPOLINV_INC BIT(1) |
| 121 | #define AGCV3_T 0x3e |
| 122 | #define MDRD_T 0xa2 |
| 123 | #define MDRD_T_SEGID_MASK GENMASK(5, 4) |
| 124 | #define MDRD_T_SEGID_13 (0x0 << 4) |
| 125 | #define MDRD_T_SEGID_1 (0x1 << 4) |
| 126 | #define MDRD_T_SEGID_3 (0x2 << 4) |
| 127 | #define MDRD_T_FFTS_MASK GENMASK(3, 2) |
| 128 | #define MDRD_T_FFTS_MODE1 (0x0 << 2) |
| 129 | #define MDRD_T_FFTS_MODE2 (0x1 << 2) |
| 130 | #define MDRD_T_FFTS_MODE3 (0x2 << 2) |
| 131 | #define MDRD_T_GI_MASK GENMASK(1, 0) |
| 132 | #define MDRD_T_GI_1_32 (0x0 << 0) |
| 133 | #define MDRD_T_GI_1_16 (0x1 << 0) |
| 134 | #define MDRD_T_GI_1_8 (0x2 << 0) |
| 135 | #define MDRD_T_GI_1_4 (0x3 << 0) |
| 136 | #define SSEQRD_T 0xa3 |
| 137 | #define SSEQRD_T_SSEQSTRD_MASK GENMASK(3, 0) |
| 138 | #define SSEQRD_T_SSEQSTRD_RESET (0x0 << 0) |
| 139 | #define SSEQRD_T_SSEQSTRD_TUNING (0x1 << 0) |
| 140 | #define SSEQRD_T_SSEQSTRD_AGC (0x2 << 0) |
| 141 | #define SSEQRD_T_SSEQSTRD_SEARCH (0x3 << 0) |
| 142 | #define SSEQRD_T_SSEQSTRD_CLOCK_SYNC (0x4 << 0) |
| 143 | #define SSEQRD_T_SSEQSTRD_FREQ_SYNC (0x8 << 0) |
| 144 | #define SSEQRD_T_SSEQSTRD_FRAME_SYNC (0x9 << 0) |
| 145 | #define SSEQRD_T_SSEQSTRD_SYNC (0xa << 0) |
| 146 | #define SSEQRD_T_SSEQSTRD_LOCK (0xb << 0) |
| 147 | #define AGCRDU_T 0xa8 |
| 148 | #define AGCRDL_T 0xa9 |
| 149 | #define CNRDU_T 0xbe |
| 150 | #define CNRDL_T 0xbf |
| 151 | #define BERFLG_T 0xc0 |
| 152 | #define BERFLG_T_BERDRDY BIT(7) |
| 153 | #define BERFLG_T_BERDCHK BIT(6) |
| 154 | #define BERFLG_T_BERVRDYA BIT(5) |
| 155 | #define BERFLG_T_BERVCHKA BIT(4) |
| 156 | #define BERFLG_T_BERVRDYB BIT(3) |
| 157 | #define BERFLG_T_BERVCHKB BIT(2) |
| 158 | #define BERFLG_T_BERVRDYC BIT(1) |
| 159 | #define BERFLG_T_BERVCHKC BIT(0) |
| 160 | #define BERRDU_T 0xc1 |
| 161 | #define BERRDM_T 0xc2 |
| 162 | #define BERRDL_T 0xc3 |
| 163 | #define BERLENRDU_T 0xc4 |
| 164 | #define BERLENRDL_T 0xc5 |
| 165 | #define ERRFLG_T 0xc6 |
| 166 | #define ERRFLG_T_BERDOVF BIT(7) |
| 167 | #define ERRFLG_T_BERVOVFA BIT(6) |
| 168 | #define ERRFLG_T_BERVOVFB BIT(5) |
| 169 | #define ERRFLG_T_BERVOVFC BIT(4) |
| 170 | #define ERRFLG_T_NERRFA BIT(3) |
| 171 | #define ERRFLG_T_NERRFB BIT(2) |
| 172 | #define ERRFLG_T_NERRFC BIT(1) |
| 173 | #define ERRFLG_T_NERRF BIT(0) |
| 174 | #define DOSET1_T 0xcf |
| 175 | |
| 176 | #define CLK_LOW 4000000 |
| 177 | #define CLK_DIRECT 20200000 |
| 178 | #define CLK_MAX 25410000 |
| 179 | |
| 180 | #define S_T_FREQ 8126984 /* 512 / 63 MHz */ |
| 181 | |
| 182 | struct mn88443x_spec { |
| 183 | bool primary; |
| 184 | }; |
| 185 | |
| 186 | struct mn88443x_priv { |
| 187 | const struct mn88443x_spec *spec; |
| 188 | |
| 189 | struct dvb_frontend fe; |
| 190 | struct clk *mclk; |
| 191 | struct gpio_desc *reset_gpio; |
| 192 | u32 clk_freq; |
| 193 | u32 if_freq; |
| 194 | |
| 195 | /* Common */ |
| 196 | bool use_clkbuf; |
| 197 | |
| 198 | /* ISDB-S */ |
| 199 | struct i2c_client *client_s; |
| 200 | struct regmap *regmap_s; |
| 201 | |
| 202 | /* ISDB-T */ |
| 203 | struct i2c_client *client_t; |
| 204 | struct regmap *regmap_t; |
| 205 | }; |
| 206 | |
| 207 | static void mn88443x_cmn_power_on(struct mn88443x_priv *chip) |
| 208 | { |
| 209 | struct regmap *r_t = chip->regmap_t; |
| 210 | |
| 211 | clk_prepare_enable(chip->mclk); |
| 212 | |
| 213 | gpiod_set_value_cansleep(chip->reset_gpio, 1); |
| 214 | usleep_range(100, 1000); |
| 215 | gpiod_set_value_cansleep(chip->reset_gpio, 0); |
| 216 | |
| 217 | if (chip->spec->primary) { |
| 218 | regmap_write(r_t, OUTCSET, OUTCSET_CHDRV_8MA); |
| 219 | regmap_write(r_t, PLDWSET, PLDWSET_NORMAL); |
| 220 | regmap_write(r_t, HIZSET1, 0x80); |
| 221 | regmap_write(r_t, HIZSET2, 0xe0); |
| 222 | } else { |
| 223 | regmap_write(r_t, HIZSET3, 0x8f); |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | static void mn88443x_cmn_power_off(struct mn88443x_priv *chip) |
| 228 | { |
| 229 | gpiod_set_value_cansleep(chip->reset_gpio, 1); |
| 230 | |
| 231 | clk_disable_unprepare(chip->mclk); |
| 232 | } |
| 233 | |
| 234 | static void mn88443x_s_sleep(struct mn88443x_priv *chip) |
| 235 | { |
| 236 | struct regmap *r_t = chip->regmap_t; |
| 237 | |
| 238 | regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK, |
| 239 | PWDSET_PSKPD_DOWN); |
| 240 | } |
| 241 | |
| 242 | static void mn88443x_s_wake(struct mn88443x_priv *chip) |
| 243 | { |
| 244 | struct regmap *r_t = chip->regmap_t; |
| 245 | |
| 246 | regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK, 0); |
| 247 | } |
| 248 | |
| 249 | static void mn88443x_s_tune(struct mn88443x_priv *chip, |
| 250 | struct dtv_frontend_properties *c) |
| 251 | { |
| 252 | struct regmap *r_s = chip->regmap_s; |
| 253 | |
| 254 | regmap_write(r_s, ATSIDU_S, c->stream_id >> 8); |
| 255 | regmap_write(r_s, ATSIDL_S, c->stream_id); |
| 256 | regmap_write(r_s, TSSET_S, 0); |
| 257 | } |
| 258 | |
| 259 | static int mn88443x_s_read_status(struct mn88443x_priv *chip, |
| 260 | struct dtv_frontend_properties *c, |
| 261 | enum fe_status *status) |
| 262 | { |
| 263 | struct regmap *r_s = chip->regmap_s; |
| 264 | u32 cpmon, tmpu, tmpl, flg; |
| 265 | u64 tmp; |
| 266 | |
| 267 | /* Sync detection */ |
| 268 | regmap_read(r_s, CPMON1_S, &cpmon); |
| 269 | |
| 270 | *status = 0; |
| 271 | if (cpmon & CPMON1_S_FSYNC) |
| 272 | *status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; |
| 273 | if (cpmon & CPMON1_S_W2LOCK) |
| 274 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; |
| 275 | |
| 276 | /* Signal strength */ |
| 277 | c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 278 | |
| 279 | if (*status & FE_HAS_SIGNAL) { |
| 280 | u32 agc; |
| 281 | |
| 282 | regmap_read(r_s, AGCREAD_S, &tmpu); |
| 283 | agc = tmpu << 8; |
| 284 | |
| 285 | c->strength.len = 1; |
| 286 | c->strength.stat[0].scale = FE_SCALE_RELATIVE; |
| 287 | c->strength.stat[0].uvalue = agc; |
| 288 | } |
| 289 | |
| 290 | /* C/N rate */ |
| 291 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 292 | |
| 293 | if (*status & FE_HAS_VITERBI) { |
| 294 | u32 cnr = 0, x, y, d; |
| 295 | u64 d_3 = 0; |
| 296 | |
| 297 | regmap_read(r_s, CNRDXU_S, &tmpu); |
| 298 | regmap_read(r_s, CNRDXL_S, &tmpl); |
| 299 | x = (tmpu << 8) | tmpl; |
| 300 | regmap_read(r_s, CNRDYU_S, &tmpu); |
| 301 | regmap_read(r_s, CNRDYL_S, &tmpl); |
| 302 | y = (tmpu << 8) | tmpl; |
| 303 | |
| 304 | /* CNR[dB]: 10 * log10(D) - 30.74 / D^3 - 3 */ |
| 305 | /* D = x^2 / (2^15 * y - x^2) */ |
| 306 | d = (y << 15) - x * x; |
| 307 | if (d > 0) { |
| 308 | /* (2^4 * D)^3 = 2^12 * D^3 */ |
| 309 | /* 3.074 * 2^(12 + 24) = 211243671486 */ |
| 310 | d_3 = div_u64(16 * x * x, d); |
| 311 | d_3 = d_3 * d_3 * d_3; |
| 312 | if (d_3) |
| 313 | d_3 = div_u64(211243671486ULL, d_3); |
| 314 | } |
| 315 | |
| 316 | if (d_3) { |
| 317 | /* 0.3 * 2^24 = 5033164 */ |
| 318 | tmp = (s64)2 * intlog10(x) - intlog10(abs(d)) - d_3 |
| 319 | - 5033164; |
| 320 | cnr = div_u64(tmp * 10000, 1 << 24); |
| 321 | } |
| 322 | |
| 323 | if (cnr) { |
| 324 | c->cnr.len = 1; |
| 325 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; |
| 326 | c->cnr.stat[0].uvalue = cnr; |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | /* BER */ |
| 331 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 332 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 333 | |
| 334 | regmap_read(r_s, BERCNFLG_S, &flg); |
| 335 | |
| 336 | if ((*status & FE_HAS_VITERBI) && (flg & BERCNFLG_S_BERVRDY)) { |
| 337 | u32 bit_err, bit_cnt; |
| 338 | |
| 339 | regmap_read(r_s, BERVRDU_S, &tmpu); |
| 340 | regmap_read(r_s, BERVRDL_S, &tmpl); |
| 341 | bit_err = (tmpu << 8) | tmpl; |
| 342 | bit_cnt = (1 << 13) * 204; |
| 343 | |
| 344 | if (bit_cnt) { |
| 345 | c->post_bit_error.len = 1; |
| 346 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; |
| 347 | c->post_bit_error.stat[0].uvalue = bit_err; |
| 348 | c->post_bit_count.len = 1; |
| 349 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; |
| 350 | c->post_bit_count.stat[0].uvalue = bit_cnt; |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | static void mn88443x_t_sleep(struct mn88443x_priv *chip) |
| 358 | { |
| 359 | struct regmap *r_t = chip->regmap_t; |
| 360 | |
| 361 | regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK, |
| 362 | PWDSET_OFDMPD_DOWN); |
| 363 | } |
| 364 | |
| 365 | static void mn88443x_t_wake(struct mn88443x_priv *chip) |
| 366 | { |
| 367 | struct regmap *r_t = chip->regmap_t; |
| 368 | |
| 369 | regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK, 0); |
| 370 | } |
| 371 | |
| 372 | static bool mn88443x_t_is_valid_clk(u32 adckt, u32 if_freq) |
| 373 | { |
| 374 | if (if_freq == DIRECT_IF_57MHZ) { |
| 375 | if (adckt >= CLK_DIRECT && adckt <= 21000000) |
| 376 | return true; |
| 377 | if (adckt >= 25300000 && adckt <= CLK_MAX) |
| 378 | return true; |
| 379 | } else if (if_freq == DIRECT_IF_44MHZ) { |
| 380 | if (adckt >= 25000000 && adckt <= CLK_MAX) |
| 381 | return true; |
| 382 | } else if (if_freq >= LOW_IF_4MHZ && if_freq < DIRECT_IF_44MHZ) { |
| 383 | if (adckt >= CLK_DIRECT && adckt <= CLK_MAX) |
| 384 | return true; |
| 385 | } |
| 386 | |
| 387 | return false; |
| 388 | } |
| 389 | |
| 390 | static int mn88443x_t_set_freq(struct mn88443x_priv *chip) |
| 391 | { |
| 392 | struct device *dev = &chip->client_s->dev; |
| 393 | struct regmap *r_t = chip->regmap_t; |
| 394 | s64 adckt, nco, ad_t; |
| 395 | u32 m, v; |
| 396 | |
| 397 | /* Clock buffer (but not supported) or XTAL */ |
| 398 | if (chip->clk_freq >= CLK_LOW && chip->clk_freq < CLK_DIRECT) { |
| 399 | chip->use_clkbuf = true; |
| 400 | regmap_write(r_t, CLKSET1_T, 0x07); |
| 401 | |
| 402 | adckt = 0; |
| 403 | } else { |
| 404 | chip->use_clkbuf = false; |
| 405 | regmap_write(r_t, CLKSET1_T, 0x00); |
| 406 | |
| 407 | adckt = chip->clk_freq; |
| 408 | } |
| 409 | if (!mn88443x_t_is_valid_clk(adckt, chip->if_freq)) { |
| 410 | dev_err(dev, "Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\n", |
| 411 | chip->clk_freq, adckt, chip->if_freq); |
| 412 | return -EINVAL; |
| 413 | } |
| 414 | |
| 415 | /* Direct IF or Low IF */ |
| 416 | if (chip->if_freq == DIRECT_IF_57MHZ || |
| 417 | chip->if_freq == DIRECT_IF_44MHZ) |
| 418 | nco = adckt * 2 - chip->if_freq; |
| 419 | else |
| 420 | nco = -((s64)chip->if_freq); |
| 421 | nco = div_s64(nco << 24, adckt); |
| 422 | ad_t = div_s64(adckt << 22, S_T_FREQ); |
| 423 | |
| 424 | regmap_write(r_t, NCOFREQU_T, nco >> 16); |
| 425 | regmap_write(r_t, NCOFREQM_T, nco >> 8); |
| 426 | regmap_write(r_t, NCOFREQL_T, nco); |
| 427 | regmap_write(r_t, FADU_T, ad_t >> 16); |
| 428 | regmap_write(r_t, FADM_T, ad_t >> 8); |
| 429 | regmap_write(r_t, FADL_T, ad_t); |
| 430 | |
| 431 | /* Level of IF */ |
| 432 | m = ADCSET1_T_REFSEL_MASK; |
| 433 | v = ADCSET1_T_REFSEL_1_5V; |
| 434 | regmap_update_bits(r_t, ADCSET1_T, m, v); |
| 435 | |
| 436 | /* Polarity of AGC */ |
| 437 | v = AGCSET2_T_IFPOLINV_INC | AGCSET2_T_RFPOLINV_INC; |
| 438 | regmap_update_bits(r_t, AGCSET2_T, v, v); |
| 439 | |
| 440 | /* Lower output level of AGC */ |
| 441 | regmap_write(r_t, AGCV3_T, 0x00); |
| 442 | |
| 443 | regmap_write(r_t, MDSET_T, 0xfa); |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static void mn88443x_t_tune(struct mn88443x_priv *chip, |
| 449 | struct dtv_frontend_properties *c) |
| 450 | { |
| 451 | struct regmap *r_t = chip->regmap_t; |
| 452 | u32 m, v; |
| 453 | |
| 454 | m = MDSET_T_MDAUTO_MASK | MDSET_T_FFTS_MASK | MDSET_T_GI_MASK; |
| 455 | v = MDSET_T_MDAUTO_AUTO | MDSET_T_FFTS_MODE3 | MDSET_T_GI_1_8; |
| 456 | regmap_update_bits(r_t, MDSET_T, m, v); |
| 457 | |
| 458 | regmap_write(r_t, MDASET_T, 0); |
| 459 | } |
| 460 | |
| 461 | static int mn88443x_t_read_status(struct mn88443x_priv *chip, |
| 462 | struct dtv_frontend_properties *c, |
| 463 | enum fe_status *status) |
| 464 | { |
| 465 | struct regmap *r_t = chip->regmap_t; |
| 466 | u32 seqrd, st, flg, tmpu, tmpm, tmpl; |
| 467 | u64 tmp; |
| 468 | |
| 469 | /* Sync detection */ |
| 470 | regmap_read(r_t, SSEQRD_T, &seqrd); |
| 471 | st = seqrd & SSEQRD_T_SSEQSTRD_MASK; |
| 472 | |
| 473 | *status = 0; |
| 474 | if (st >= SSEQRD_T_SSEQSTRD_SYNC) |
| 475 | *status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; |
| 476 | if (st >= SSEQRD_T_SSEQSTRD_FRAME_SYNC) |
| 477 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; |
| 478 | |
| 479 | /* Signal strength */ |
| 480 | c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 481 | |
| 482 | if (*status & FE_HAS_SIGNAL) { |
| 483 | u32 agc; |
| 484 | |
| 485 | regmap_read(r_t, AGCRDU_T, &tmpu); |
| 486 | regmap_read(r_t, AGCRDL_T, &tmpl); |
| 487 | agc = (tmpu << 8) | tmpl; |
| 488 | |
| 489 | c->strength.len = 1; |
| 490 | c->strength.stat[0].scale = FE_SCALE_RELATIVE; |
| 491 | c->strength.stat[0].uvalue = agc; |
| 492 | } |
| 493 | |
| 494 | /* C/N rate */ |
| 495 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 496 | |
| 497 | if (*status & FE_HAS_VITERBI) { |
| 498 | u32 cnr; |
| 499 | |
| 500 | regmap_read(r_t, CNRDU_T, &tmpu); |
| 501 | regmap_read(r_t, CNRDL_T, &tmpl); |
| 502 | |
| 503 | if (tmpu || tmpl) { |
| 504 | /* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */ |
| 505 | /* intlog10(65536) = 80807124, 0.2 * 2^24 = 3355443 */ |
| 506 | tmp = (u64)80807124 - intlog10((tmpu << 8) | tmpl) |
| 507 | + 3355443; |
| 508 | cnr = div_u64(tmp * 10000, 1 << 24); |
| 509 | } else { |
| 510 | cnr = 0; |
| 511 | } |
| 512 | |
| 513 | c->cnr.len = 1; |
| 514 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; |
| 515 | c->cnr.stat[0].uvalue = cnr; |
| 516 | } |
| 517 | |
| 518 | /* BER */ |
| 519 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 520 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
| 521 | |
| 522 | regmap_read(r_t, BERFLG_T, &flg); |
| 523 | |
| 524 | if ((*status & FE_HAS_VITERBI) && (flg & BERFLG_T_BERVRDYA)) { |
| 525 | u32 bit_err, bit_cnt; |
| 526 | |
| 527 | regmap_read(r_t, BERRDU_T, &tmpu); |
| 528 | regmap_read(r_t, BERRDM_T, &tmpm); |
| 529 | regmap_read(r_t, BERRDL_T, &tmpl); |
| 530 | bit_err = (tmpu << 16) | (tmpm << 8) | tmpl; |
| 531 | |
| 532 | regmap_read(r_t, BERLENRDU_T, &tmpu); |
| 533 | regmap_read(r_t, BERLENRDL_T, &tmpl); |
| 534 | bit_cnt = ((tmpu << 8) | tmpl) * 203 * 8; |
| 535 | |
| 536 | if (bit_cnt) { |
| 537 | c->post_bit_error.len = 1; |
| 538 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; |
| 539 | c->post_bit_error.stat[0].uvalue = bit_err; |
| 540 | c->post_bit_count.len = 1; |
| 541 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; |
| 542 | c->post_bit_count.stat[0].uvalue = bit_cnt; |
| 543 | } |
| 544 | } |
| 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | static int mn88443x_sleep(struct dvb_frontend *fe) |
| 550 | { |
| 551 | struct mn88443x_priv *chip = fe->demodulator_priv; |
| 552 | |
| 553 | mn88443x_s_sleep(chip); |
| 554 | mn88443x_t_sleep(chip); |
| 555 | |
| 556 | return 0; |
| 557 | } |
| 558 | |
| 559 | static int mn88443x_set_frontend(struct dvb_frontend *fe) |
| 560 | { |
| 561 | struct mn88443x_priv *chip = fe->demodulator_priv; |
| 562 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
| 563 | struct regmap *r_s = chip->regmap_s; |
| 564 | struct regmap *r_t = chip->regmap_t; |
| 565 | u8 tssel = 0, intsel = 0; |
| 566 | |
| 567 | if (c->delivery_system == SYS_ISDBS) { |
| 568 | mn88443x_s_wake(chip); |
| 569 | mn88443x_t_sleep(chip); |
| 570 | |
| 571 | tssel = TSSET1_TSASEL_ISDBS; |
| 572 | intsel = TSSET3_INTASEL_S; |
| 573 | } else if (c->delivery_system == SYS_ISDBT) { |
| 574 | mn88443x_s_sleep(chip); |
| 575 | mn88443x_t_wake(chip); |
| 576 | |
| 577 | mn88443x_t_set_freq(chip); |
| 578 | |
| 579 | tssel = TSSET1_TSASEL_ISDBT; |
| 580 | intsel = TSSET3_INTASEL_T; |
| 581 | } |
| 582 | |
| 583 | regmap_update_bits(r_t, TSSET1, |
| 584 | TSSET1_TSASEL_MASK | TSSET1_TSBSEL_MASK, |
| 585 | tssel | TSSET1_TSBSEL_NONE); |
| 586 | regmap_write(r_t, TSSET2, 0); |
| 587 | regmap_update_bits(r_t, TSSET3, |
| 588 | TSSET3_INTASEL_MASK | TSSET3_INTBSEL_MASK, |
| 589 | intsel | TSSET3_INTBSEL_NONE); |
| 590 | |
| 591 | regmap_write(r_t, DOSET1_T, 0x95); |
| 592 | regmap_write(r_s, DOSET1_S, 0x80); |
| 593 | |
| 594 | if (c->delivery_system == SYS_ISDBS) |
| 595 | mn88443x_s_tune(chip, c); |
| 596 | else if (c->delivery_system == SYS_ISDBT) |
| 597 | mn88443x_t_tune(chip, c); |
| 598 | |
| 599 | if (fe->ops.tuner_ops.set_params) { |
| 600 | if (fe->ops.i2c_gate_ctrl) |
| 601 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 602 | fe->ops.tuner_ops.set_params(fe); |
| 603 | if (fe->ops.i2c_gate_ctrl) |
| 604 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 605 | } |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | static int mn88443x_get_tune_settings(struct dvb_frontend *fe, |
| 611 | struct dvb_frontend_tune_settings *s) |
| 612 | { |
| 613 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
| 614 | |
| 615 | s->min_delay_ms = 850; |
| 616 | |
| 617 | if (c->delivery_system == SYS_ISDBS) { |
| 618 | s->max_drift = 30000 * 2 + 1; |
| 619 | s->step_size = 30000; |
| 620 | } else if (c->delivery_system == SYS_ISDBT) { |
| 621 | s->max_drift = 142857 * 2 + 1; |
| 622 | s->step_size = 142857 * 2; |
| 623 | } |
| 624 | |
| 625 | return 0; |
| 626 | } |
| 627 | |
| 628 | static int mn88443x_read_status(struct dvb_frontend *fe, enum fe_status *status) |
| 629 | { |
| 630 | struct mn88443x_priv *chip = fe->demodulator_priv; |
| 631 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
| 632 | |
| 633 | if (c->delivery_system == SYS_ISDBS) |
| 634 | return mn88443x_s_read_status(chip, c, status); |
| 635 | |
| 636 | if (c->delivery_system == SYS_ISDBT) |
| 637 | return mn88443x_t_read_status(chip, c, status); |
| 638 | |
| 639 | return -EINVAL; |
| 640 | } |
| 641 | |
| 642 | static const struct dvb_frontend_ops mn88443x_ops = { |
| 643 | .delsys = { SYS_ISDBS, SYS_ISDBT }, |
| 644 | .info = { |
| 645 | .name = "Socionext MN88443x", |
| 646 | .frequency_min_hz = 470 * MHz, |
| 647 | .frequency_max_hz = 2071 * MHz, |
| 648 | .symbol_rate_min = 28860000, |
| 649 | .symbol_rate_max = 28860000, |
| 650 | .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | |
| 651 | FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | |
| 652 | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, |
| 653 | }, |
| 654 | |
| 655 | .sleep = mn88443x_sleep, |
| 656 | .set_frontend = mn88443x_set_frontend, |
| 657 | .get_tune_settings = mn88443x_get_tune_settings, |
| 658 | .read_status = mn88443x_read_status, |
| 659 | }; |
| 660 | |
| 661 | static const struct regmap_config regmap_config = { |
| 662 | .reg_bits = 8, |
| 663 | .val_bits = 8, |
| 664 | .cache_type = REGCACHE_NONE, |
| 665 | }; |
| 666 | |
| 667 | static int mn88443x_probe(struct i2c_client *client, |
| 668 | const struct i2c_device_id *id) |
| 669 | { |
| 670 | struct mn88443x_config *conf = client->dev.platform_data; |
| 671 | struct mn88443x_priv *chip; |
| 672 | struct device *dev = &client->dev; |
| 673 | int ret; |
| 674 | |
| 675 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
| 676 | if (!chip) |
| 677 | return -ENOMEM; |
| 678 | |
| 679 | if (dev->of_node) |
| 680 | chip->spec = of_device_get_match_data(dev); |
| 681 | else |
| 682 | chip->spec = (struct mn88443x_spec *)id->driver_data; |
| 683 | if (!chip->spec) |
| 684 | return -EINVAL; |
| 685 | |
| 686 | chip->mclk = devm_clk_get(dev, "mclk"); |
| 687 | if (IS_ERR(chip->mclk) && !conf) { |
| 688 | dev_err(dev, "Failed to request mclk: %ld\n", |
| 689 | PTR_ERR(chip->mclk)); |
| 690 | return PTR_ERR(chip->mclk); |
| 691 | } |
| 692 | |
| 693 | ret = of_property_read_u32(dev->of_node, "if-frequency", |
| 694 | &chip->if_freq); |
| 695 | if (ret && !conf) { |
| 696 | dev_err(dev, "Failed to load IF frequency: %d.\n", ret); |
| 697 | return ret; |
| 698 | } |
| 699 | |
| 700 | chip->reset_gpio = devm_gpiod_get_optional(dev, "reset", |
| 701 | GPIOD_OUT_HIGH); |
| 702 | if (IS_ERR(chip->reset_gpio)) { |
| 703 | dev_err(dev, "Failed to request reset_gpio: %ld\n", |
| 704 | PTR_ERR(chip->reset_gpio)); |
| 705 | return PTR_ERR(chip->reset_gpio); |
| 706 | } |
| 707 | |
| 708 | if (conf) { |
| 709 | chip->mclk = conf->mclk; |
| 710 | chip->if_freq = conf->if_freq; |
| 711 | chip->reset_gpio = conf->reset_gpio; |
| 712 | |
| 713 | *conf->fe = &chip->fe; |
| 714 | } |
| 715 | |
| 716 | chip->client_s = client; |
| 717 | chip->regmap_s = devm_regmap_init_i2c(chip->client_s, ®map_config); |
| 718 | if (IS_ERR(chip->regmap_s)) |
| 719 | return PTR_ERR(chip->regmap_s); |
| 720 | |
| 721 | /* |
| 722 | * Chip has two I2C addresses for each satellite/terrestrial system. |
| 723 | * ISDB-T uses address ISDB-S + 4, so we register a dummy client. |
| 724 | */ |
| 725 | chip->client_t = i2c_new_dummy_device(client->adapter, client->addr + 4); |
| 726 | if (IS_ERR(chip->client_t)) |
| 727 | return PTR_ERR(chip->client_t); |
| 728 | |
| 729 | chip->regmap_t = devm_regmap_init_i2c(chip->client_t, ®map_config); |
| 730 | if (IS_ERR(chip->regmap_t)) { |
| 731 | ret = PTR_ERR(chip->regmap_t); |
| 732 | goto err_i2c_t; |
| 733 | } |
| 734 | |
| 735 | chip->clk_freq = clk_get_rate(chip->mclk); |
| 736 | |
| 737 | memcpy(&chip->fe.ops, &mn88443x_ops, sizeof(mn88443x_ops)); |
| 738 | chip->fe.demodulator_priv = chip; |
| 739 | i2c_set_clientdata(client, chip); |
| 740 | |
| 741 | mn88443x_cmn_power_on(chip); |
| 742 | mn88443x_s_sleep(chip); |
| 743 | mn88443x_t_sleep(chip); |
| 744 | |
| 745 | return 0; |
| 746 | |
| 747 | err_i2c_t: |
| 748 | i2c_unregister_device(chip->client_t); |
| 749 | |
| 750 | return ret; |
| 751 | } |
| 752 | |
| 753 | static int mn88443x_remove(struct i2c_client *client) |
| 754 | { |
| 755 | struct mn88443x_priv *chip = i2c_get_clientdata(client); |
| 756 | |
| 757 | mn88443x_cmn_power_off(chip); |
| 758 | |
| 759 | i2c_unregister_device(chip->client_t); |
| 760 | |
| 761 | return 0; |
| 762 | } |
| 763 | |
| 764 | static const struct mn88443x_spec mn88443x_spec_pri = { |
| 765 | .primary = true, |
| 766 | }; |
| 767 | |
| 768 | static const struct mn88443x_spec mn88443x_spec_sec = { |
| 769 | .primary = false, |
| 770 | }; |
| 771 | |
| 772 | static const struct of_device_id mn88443x_of_match[] = { |
| 773 | { .compatible = "socionext,mn884433", .data = &mn88443x_spec_pri, }, |
| 774 | { .compatible = "socionext,mn884434-0", .data = &mn88443x_spec_pri, }, |
| 775 | { .compatible = "socionext,mn884434-1", .data = &mn88443x_spec_sec, }, |
| 776 | {} |
| 777 | }; |
| 778 | MODULE_DEVICE_TABLE(of, mn88443x_of_match); |
| 779 | |
| 780 | static const struct i2c_device_id mn88443x_i2c_id[] = { |
| 781 | { "mn884433", (kernel_ulong_t)&mn88443x_spec_pri }, |
| 782 | { "mn884434-0", (kernel_ulong_t)&mn88443x_spec_pri }, |
| 783 | { "mn884434-1", (kernel_ulong_t)&mn88443x_spec_sec }, |
| 784 | {} |
| 785 | }; |
| 786 | MODULE_DEVICE_TABLE(i2c, mn88443x_i2c_id); |
| 787 | |
| 788 | static struct i2c_driver mn88443x_driver = { |
| 789 | .driver = { |
| 790 | .name = "mn88443x", |
| 791 | .of_match_table = of_match_ptr(mn88443x_of_match), |
| 792 | }, |
| 793 | .probe = mn88443x_probe, |
| 794 | .remove = mn88443x_remove, |
| 795 | .id_table = mn88443x_i2c_id, |
| 796 | }; |
| 797 | |
| 798 | module_i2c_driver(mn88443x_driver); |
| 799 | |
| 800 | MODULE_AUTHOR("Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>"); |
| 801 | MODULE_DESCRIPTION("Socionext MN88443x series demodulator driver."); |
| 802 | MODULE_LICENSE("GPL v2"); |