[linux-2.6-block.git] / drivers / ide / pci / pdc202xx_old.c

/*
 *  linux/drivers/ide/pci/pdc202xx_old.c	Version 0.52	Aug 27, 2007
 *
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
 *  compiled into the kernel if you have more than one card installed.
 *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
 *  safe chipset tuning, including this support is harmless
 *
 *  Promise Ultra66 cards with BIOS v1.11 this
 *  compiled into the kernel if you have more than one card installed.
 *
 *  Promise Ultra100 cards.
 *
 *  The latest chipset code will support the following ::
 *  Three Ultra33 controllers and 12 drives.
 *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
 *  The 8/4 ratio is a BIOS code limit by promise.
 *
 *  UNLESS you enable "CONFIG_PDC202XX_BURST"
 *
 */

/*
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (drive->id->capability & 4)
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
{
	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);

	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->dma_master + 0x11;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->dma_master + 0x11;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static int pdc202xx_quirkproc (ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || drive->addressing == 1) {
		struct request *rq	= HWGROUP(drive)->rq;
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16   = hwif->dma_master;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || drive->addressing == 1) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->dma_master;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return __ide_dma_end(drive);
}

static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->dma_master;
	u8 dma_stat		= inb(hwif->dma_status);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->resetproc != NULL)
		hwif->resetproc(drive);

	ide_dma_lost_irq(drive);
}

static void pdc202xx_dma_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->resetproc != NULL)
		hwif->resetproc(drive);

	ide_dma_timeout(drive);
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->dma_master;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;

	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);

	ide_set_max_pio(drive);
}

static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
							const char *name)
{
	return dev->irq;
}

static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;

	/* PDC20265 has problems with large LBA48 requests */
	if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
	    (dev->device == PCI_DEVICE_ID_PROMISE_20265))
		hwif->rqsize = 256;

	hwif->set_pio_mode = &pdc202xx_set_pio_mode;
	hwif->set_dma_mode = &pdc202xx_set_mode;

	hwif->quirkproc = &pdc202xx_quirkproc;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
		hwif->resetproc = &pdc202xx_reset;

	hwif->err_stops_fifo = 1;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;

	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
	hwif->dma_timeout = &pdc202xx_dma_timeout;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
		if (hwif->cbl != ATA_CBL_PATA40_SHORT)
			hwif->cbl = pdc202xx_old_cable_detect(hwif);

		hwif->dma_start = &pdc202xx_old_ide_dma_start;
		hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	} 
	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
}

static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
{
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (hwif->channel) {
		ide_setup_dma(hwif, dmabase, 8);
		return;
	}

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", hwif->cds->name,
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

#ifdef CONFIG_PDC202XX_BURST
	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			hwif->cds->name, udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
#endif /* CONFIG_PDC202XX_BURST */

	ide_setup_dma(hwif, dmabase, 8);
}

static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
					   ide_pci_device_t *d)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s: pci-config space interrupt "
				"mirror fixed.\n", d->name);
		}
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20265(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	if ((dev->bus->self) &&
	    (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	    ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
	     (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
		printk(KERN_INFO "ide: Skipping Promise PDC20265 "
			"attached to I2O RAID controller.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20246",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.extra		= 16,
		.host_flags	= IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x07, /* udma0-2 */
	},{	/* 1 */
		.name		= "PDC20262",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.extra		= 48,
		.host_flags	= IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 2 */
		.name		= "PDC20263",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.extra		= 48,
		.host_flags	= IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 3 */
		.name		= "PDC20265",
		.init_setup	= init_setup_pdc20265,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.extra		= 48,
		.host_flags	= IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 4 */
		.name		= "PDC20267",
		.init_setup	= init_setup_pdc202xx,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.extra		= 48,
		.host_flags	= IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	}
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202xx_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
	1	/*
	2	* linux/drivers/ide/pci/pdc202xx_old.c Version 0.52 Aug 27, 2007
	3	*
	4	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
	5	* Copyright (C) 2006-2007 MontaVista Software, Inc.
	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
	7	*
	8	* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
	9	* compiled into the kernel if you have more than one card installed.
	10	* Note that BIOS v1.29 is reported to fix the problem. Since this is
	11	* safe chipset tuning, including this support is harmless
	12	*
	13	* Promise Ultra66 cards with BIOS v1.11 this
	14	* compiled into the kernel if you have more than one card installed.
	15	*
	16	* Promise Ultra100 cards.
	17	*
	18	* The latest chipset code will support the following ::
	19	* Three Ultra33 controllers and 12 drives.
	20	* 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
	21	* The 8/4 ratio is a BIOS code limit by promise.
	22	*
	23	* UNLESS you enable "CONFIG_PDC202XX_BURST"
	24	*
	25	*/
	26
	27	/*
	28	* Portions Copyright (C) 1999 Promise Technology, Inc.
	29	* Author: Frank Tiernan (frankt@promise.com)
	30	* Released under terms of General Public License
	31	*/
	32
	33	#include <linux/types.h>
	34	#include <linux/module.h>
	35	#include <linux/kernel.h>
	36	#include <linux/delay.h>
	37	#include <linux/timer.h>
	38	#include <linux/mm.h>
	39	#include <linux/ioport.h>
	40	#include <linux/blkdev.h>
	41	#include <linux/hdreg.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/pci.h>
	44	#include <linux/init.h>
	45	#include <linux/ide.h>
	46
	47	#include <asm/io.h>
	48	#include <asm/irq.h>
	49
	50	#define PDC202XX_DEBUG_DRIVE_INFO 0
	51
	52	static const char *pdc_quirk_drives[] = {
	53	"QUANTUM FIREBALLlct08 08",
	54	"QUANTUM FIREBALLP KA6.4",
	55	"QUANTUM FIREBALLP KA9.1",
	56	"QUANTUM FIREBALLP LM20.4",
	57	"QUANTUM FIREBALLP KX13.6",
	58	"QUANTUM FIREBALLP KX20.5",
	59	"QUANTUM FIREBALLP KX27.3",
	60	"QUANTUM FIREBALLP LM20.5",
	61	NULL
	62	};
	63
	64	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
	65
	66	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
	67	{
	68	ide_hwif_t *hwif = HWIF(drive);
	69	struct pci_dev *dev = hwif->pci_dev;
	70	u8 drive_pci = 0x60 + (drive->dn << 2);
	71
	72	u8 AP = 0, BP = 0, CP = 0;
	73	u8 TA = 0, TB = 0, TC = 0;
	74
	75	#if PDC202XX_DEBUG_DRIVE_INFO
	76	u32 drive_conf = 0;
	77	pci_read_config_dword(dev, drive_pci, &drive_conf);
	78	#endif
	79
	80	/*
	81	* TODO: do this once per channel
	82	*/
	83	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	84	pdc_old_disable_66MHz_clock(hwif);
	85
	86	pci_read_config_byte(dev, drive_pci, &AP);
	87	pci_read_config_byte(dev, drive_pci + 1, &BP);
	88	pci_read_config_byte(dev, drive_pci + 2, &CP);
	89
	90	switch(speed) {
	91	case XFER_UDMA_5:
	92	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	93	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	94	case XFER_UDMA_3:
	95	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	96	case XFER_UDMA_0:
	97	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	98	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
	99	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
	100	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	101	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	102	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	103	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	104	case XFER_PIO_0:
	105	default: TA = 0x09; TB = 0x13; break;
	106	}
	107
	108	if (speed < XFER_SW_DMA_0) {
	109	/*
	110	* preserve SYNC_INT / ERDDY_EN bits while clearing
	111	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	112	*/
	113	AP &= ~0x3f;
	114	if (drive->id->capability & 4)
	115	AP \|= 0x20; /* set IORDY_EN bit */
	116	if (drive->media == ide_disk)
	117	AP \|= 0x10; /* set Prefetch_EN bit */
	118	/* clear PB[4:0] bits of register B */
	119	BP &= ~0x1f;
	120	pci_write_config_byte(dev, drive_pci, AP \| TA);
	121	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	122	} else {
	123	/* clear MB[2:0] bits of register B */
	124	BP &= ~0xe0;
	125	/* clear MC[3:0] bits of register C */
	126	CP &= ~0x0f;
	127	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	128	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
	129	}
	130
	131	#if PDC202XX_DEBUG_DRIVE_INFO
	132	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	133	drive->name, ide_xfer_verbose(speed),
	134	drive->dn, drive_conf);
	135	pci_read_config_dword(dev, drive_pci, &drive_conf);
	136	printk("0x%08x\n", drive_conf);
	137	#endif
	138	}
	139
	140	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
	141	{
	142	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
	143	}
	144
	145	static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
	146	{
	147	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
	148
	149	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
	150
	151	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	152	}
	153
	154	/*
	155	* Set the control register to use the 66MHz system
	156	* clock for UDMA 3/4/5 mode operation when necessary.
	157	*
	158	* FIXME: this register is shared by both channels, some locking is needed
	159	*
	160	* It may also be possible to leave the 66MHz clock on
	161	* and readjust the timing parameters.
	162	*/
	163	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	164	{
	165	unsigned long clock_reg = hwif->dma_master + 0x11;
	166	u8 clock = inb(clock_reg);
	167
	168	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
	169	}
	170
	171	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	172	{
	173	unsigned long clock_reg = hwif->dma_master + 0x11;
	174	u8 clock = inb(clock_reg);
	175
	176	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
	177	}
	178
	179	static int pdc202xx_quirkproc (ide_drive_t *drive)
	180	{
	181	const char *list, model = drive->id->model;
	182
	183	for (list = pdc_quirk_drives; *list != NULL; list++)
	184	if (strstr(model, *list) != NULL)
	185	return 2;
	186	return 0;
	187	}
	188
	189	static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
	190	{
	191	if (drive->current_speed > XFER_UDMA_2)
	192	pdc_old_enable_66MHz_clock(drive->hwif);
	193	if (drive->media != ide_disk \|\| drive->addressing == 1) {
	194	struct request *rq = HWGROUP(drive)->rq;
	195	ide_hwif_t *hwif = HWIF(drive);
	196	unsigned long high_16 = hwif->dma_master;
	197	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	198	u32 word_count = 0;
	199	u8 clock = inb(high_16 + 0x11);
	200
	201	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
	202	word_count = (rq->nr_sectors << 8);
	203	word_count = (rq_data_dir(rq) == READ) ?
	204	word_count \| 0x05000000 :
	205	word_count \| 0x06000000;
	206	outl(word_count, atapi_reg);
	207	}
	208	ide_dma_start(drive);
	209	}
	210
	211	static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
	212	{
	213	if (drive->media != ide_disk \|\| drive->addressing == 1) {
	214	ide_hwif_t *hwif = HWIF(drive);
	215	unsigned long high_16 = hwif->dma_master;
	216	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	217	u8 clock = 0;
	218
	219	outl(0, atapi_reg); /* zero out extra */
	220	clock = inb(high_16 + 0x11);
	221	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	222	}
	223	if (drive->current_speed > XFER_UDMA_2)
	224	pdc_old_disable_66MHz_clock(drive->hwif);
	225	return __ide_dma_end(drive);
	226	}
	227
	228	static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
	229	{
	230	ide_hwif_t *hwif = HWIF(drive);
	231	unsigned long high_16 = hwif->dma_master;
	232	u8 dma_stat = inb(hwif->dma_status);
	233	u8 sc1d = inb(high_16 + 0x001d);
	234
	235	if (hwif->channel) {
	236	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	237	if ((sc1d & 0x50) == 0x50)
	238	goto somebody_else;
	239	else if ((sc1d & 0x40) == 0x40)
	240	return (dma_stat & 4) == 4;
	241	} else {
	242	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	243	if ((sc1d & 0x05) == 0x05)
	244	goto somebody_else;
	245	else if ((sc1d & 0x04) == 0x04)
	246	return (dma_stat & 4) == 4;
	247	}
	248	somebody_else:
	249	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	250	}
	251
	252	static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
	253	{
	254	ide_hwif_t *hwif = HWIF(drive);
	255
	256	if (hwif->resetproc != NULL)
	257	hwif->resetproc(drive);
	258
	259	ide_dma_lost_irq(drive);
	260	}
	261
	262	static void pdc202xx_dma_timeout(ide_drive_t *drive)
	263	{
	264	ide_hwif_t *hwif = HWIF(drive);
	265
	266	if (hwif->resetproc != NULL)
	267	hwif->resetproc(drive);
	268
	269	ide_dma_timeout(drive);
	270	}
	271
	272	static void pdc202xx_reset_host (ide_hwif_t *hwif)
	273	{
	274	unsigned long high_16 = hwif->dma_master;
	275	u8 udma_speed_flag = inb(high_16 \| 0x001f);
	276
	277	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
	278	mdelay(100);
	279	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
	280	mdelay(2000); /* 2 seconds ?! */
	281
	282	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	283	hwif->channel ? "Secondary" : "Primary");
	284	}
	285
	286	static void pdc202xx_reset (ide_drive_t *drive)
	287	{
	288	ide_hwif_t *hwif = HWIF(drive);
	289	ide_hwif_t *mate = hwif->mate;
	290
	291	pdc202xx_reset_host(hwif);
	292	pdc202xx_reset_host(mate);
	293
	294	ide_set_max_pio(drive);
	295	}
	296
	297	static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
	298	const char *name)
	299	{
	300	return dev->irq;
	301	}
	302
	303	static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
	304	{
	305	struct pci_dev *dev = hwif->pci_dev;
	306
	307	/* PDC20265 has problems with large LBA48 requests */
	308	if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) \|\|
	309	(dev->device == PCI_DEVICE_ID_PROMISE_20265))
	310	hwif->rqsize = 256;
	311
	312	hwif->set_pio_mode = &pdc202xx_set_pio_mode;
	313	hwif->set_dma_mode = &pdc202xx_set_mode;
	314
	315	hwif->quirkproc = &pdc202xx_quirkproc;
	316
	317	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
	318	hwif->resetproc = &pdc202xx_reset;
	319
	320	hwif->err_stops_fifo = 1;
	321
	322	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
	323
	324	if (hwif->dma_base == 0)
	325	return;
	326
	327	hwif->ultra_mask = hwif->cds->udma_mask;
	328	hwif->mwdma_mask = 0x07;
	329
	330	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
	331	hwif->dma_timeout = &pdc202xx_dma_timeout;
	332
	333	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
	334	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
	335	hwif->cbl = pdc202xx_old_cable_detect(hwif);
	336
	337	hwif->dma_start = &pdc202xx_old_ide_dma_start;
	338	hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	339	}
	340	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
	341	}
	342
	343	static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
	344	{
	345	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
	346
	347	if (hwif->channel) {
	348	ide_setup_dma(hwif, dmabase, 8);
	349	return;
	350	}
	351
	352	udma_speed_flag = inb(dmabase \| 0x1f);
	353	primary_mode = inb(dmabase \| 0x1a);
	354	secondary_mode = inb(dmabase \| 0x1b);
	355	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
	356	"Primary %s Mode " \
	357	"Secondary %s Mode.\n", hwif->cds->name,
	358	(udma_speed_flag & 1) ? "EN" : "DIS",
	359	(primary_mode & 1) ? "MASTER" : "PCI",
	360	(secondary_mode & 1) ? "MASTER" : "PCI" );
	361
	362	#ifdef CONFIG_PDC202XX_BURST
	363	if (!(udma_speed_flag & 1)) {
	364	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
	365	hwif->cds->name, udma_speed_flag,
	366	(udma_speed_flag\|1));
	367	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
	368	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
	369	}
	370	#endif /* CONFIG_PDC202XX_BURST */
	371
	372	ide_setup_dma(hwif, dmabase, 8);
	373	}
	374
	375	static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
	376	ide_pci_device_t *d)
	377	{
	378	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	379	u8 irq = 0, irq2 = 0;
	380	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	381	/* 0xbc */
	382	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	383	if (irq != irq2) {
	384	pci_write_config_byte(dev,
	385	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
	386	printk(KERN_INFO "%s: pci-config space interrupt "
	387	"mirror fixed.\n", d->name);
	388	}
	389	}
	390	return ide_setup_pci_device(dev, d);
	391	}
	392
	393	static int __devinit init_setup_pdc20265(struct pci_dev *dev,
	394	ide_pci_device_t *d)
	395	{
	396	if ((dev->bus->self) &&
	397	(dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	398	((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) \|\|
	399	(dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
	400	printk(KERN_INFO "ide: Skipping Promise PDC20265 "
	401	"attached to I2O RAID controller.\n");
	402	return -ENODEV;
	403	}
	404	return ide_setup_pci_device(dev, d);
	405	}
	406
	407	static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
	408	ide_pci_device_t *d)
	409	{
	410	return ide_setup_pci_device(dev, d);
	411	}
	412
	413	static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
	414	{ /* 0 */
	415	.name = "PDC20246",
	416	.init_setup = init_setup_pdc202ata4,
	417	.init_chipset = init_chipset_pdc202xx,
	418	.init_hwif = init_hwif_pdc202xx,
	419	.init_dma = init_dma_pdc202xx,
	420	.extra = 16,
	421	.host_flags = IDE_HFLAG_OFF_BOARD,
	422	.pio_mask = ATA_PIO4,
	423	.udma_mask = 0x07, /* udma0-2 */
	424	},{ /* 1 */
	425	.name = "PDC20262",
	426	.init_setup = init_setup_pdc202ata4,
	427	.init_chipset = init_chipset_pdc202xx,
	428	.init_hwif = init_hwif_pdc202xx,
	429	.init_dma = init_dma_pdc202xx,
	430	.extra = 48,
	431	.host_flags = IDE_HFLAG_OFF_BOARD,
	432	.pio_mask = ATA_PIO4,
	433	.udma_mask = 0x1f, /* udma0-4 */
	434	},{ /* 2 */
	435	.name = "PDC20263",
	436	.init_setup = init_setup_pdc202ata4,
	437	.init_chipset = init_chipset_pdc202xx,
	438	.init_hwif = init_hwif_pdc202xx,
	439	.init_dma = init_dma_pdc202xx,
	440	.extra = 48,
	441	.host_flags = IDE_HFLAG_OFF_BOARD,
	442	.pio_mask = ATA_PIO4,
	443	.udma_mask = 0x1f, /* udma0-4 */
	444	},{ /* 3 */
	445	.name = "PDC20265",
	446	.init_setup = init_setup_pdc20265,
	447	.init_chipset = init_chipset_pdc202xx,
	448	.init_hwif = init_hwif_pdc202xx,
	449	.init_dma = init_dma_pdc202xx,
	450	.extra = 48,
	451	.host_flags = IDE_HFLAG_OFF_BOARD,
	452	.pio_mask = ATA_PIO4,
	453	.udma_mask = 0x3f, /* udma0-5 */
	454	},{ /* 4 */
	455	.name = "PDC20267",
	456	.init_setup = init_setup_pdc202xx,
	457	.init_chipset = init_chipset_pdc202xx,
	458	.init_hwif = init_hwif_pdc202xx,
	459	.init_dma = init_dma_pdc202xx,
	460	.extra = 48,
	461	.host_flags = IDE_HFLAG_OFF_BOARD,
	462	.pio_mask = ATA_PIO4,
	463	.udma_mask = 0x3f, /* udma0-5 */
	464	}
	465	};
	466
	467	/**
	468	* pdc202xx_init_one - called when a PDC202xx is found
	469	* @dev: the pdc202xx device
	470	* @id: the matching pci id
	471	*
	472	* Called when the PCI registration layer (or the IDE initialization)
	473	* finds a device matching our IDE device tables.
	474	*/
	475
	476	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	477	{
	478	ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
	479
	480	return d->init_setup(dev, d);
	481	}
	482
	483	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	484	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	485	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	486	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
	487	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
	488	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
	489	{ 0, },
	490	};
	491	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	492
	493	static struct pci_driver driver = {
	494	.name = "Promise_Old_IDE",
	495	.id_table = pdc202xx_pci_tbl,
	496	.probe = pdc202xx_init_one,
	497	};
	498
	499	static int __init pdc202xx_ide_init(void)
	500	{
	501	return ide_pci_register_driver(&driver);
	502	}
	503
	504	module_init(pdc202xx_ide_init);
	505
	506	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	507	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	508	MODULE_LICENSE("GPL");