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i2c: piix4: Replace hardcoded memory map size with a #define
[linux-2.6-block.git] / drivers / i2c / busses / i2c-piix4.c
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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
4 Philip Edelbrock <phil@netroedge.com>
5
6*/
7
8/*
9 Supports:
10 Intel PIIX4, 440MX
11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
13 AMD Hudson-2, ML, CZ
14 Hygon CZ
15 SMSC Victory66
16
17 Note: we assume there can only be one device, with one or more
18 SMBus interfaces.
19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
20 For devices supporting multiple ports the i2c_adapter should provide
21 an i2c_algorithm to access them.
22*/
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/stddef.h>
30#include <linux/ioport.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/dmi.h>
34#include <linux/acpi.h>
35#include <linux/io.h>
36
37
38/* PIIX4 SMBus address offsets */
39#define SMBHSTSTS (0 + piix4_smba)
40#define SMBHSLVSTS (1 + piix4_smba)
41#define SMBHSTCNT (2 + piix4_smba)
42#define SMBHSTCMD (3 + piix4_smba)
43#define SMBHSTADD (4 + piix4_smba)
44#define SMBHSTDAT0 (5 + piix4_smba)
45#define SMBHSTDAT1 (6 + piix4_smba)
46#define SMBBLKDAT (7 + piix4_smba)
47#define SMBSLVCNT (8 + piix4_smba)
48#define SMBSHDWCMD (9 + piix4_smba)
49#define SMBSLVEVT (0xA + piix4_smba)
50#define SMBSLVDAT (0xC + piix4_smba)
51
52/* count for request_region */
53#define SMBIOSIZE 9
54
55/* PCI Address Constants */
56#define SMBBA 0x090
57#define SMBHSTCFG 0x0D2
58#define SMBSLVC 0x0D3
59#define SMBSHDW1 0x0D4
60#define SMBSHDW2 0x0D5
61#define SMBREV 0x0D6
62
63/* Other settings */
64#define MAX_TIMEOUT 500
65#define ENABLE_INT9 0
66
67/* PIIX4 constants */
68#define PIIX4_QUICK 0x00
69#define PIIX4_BYTE 0x04
70#define PIIX4_BYTE_DATA 0x08
71#define PIIX4_WORD_DATA 0x0C
72#define PIIX4_BLOCK_DATA 0x14
73
74/* Multi-port constants */
75#define PIIX4_MAX_ADAPTERS 4
76#define HUDSON2_MAIN_PORTS 2 /* HUDSON2, KERNCZ reserves ports 3, 4 */
77
78/* SB800 constants */
79#define SB800_PIIX4_SMB_IDX 0xcd6
80#define SB800_PIIX4_SMB_MAP_SIZE 2
81
82#define KERNCZ_IMC_IDX 0x3e
83#define KERNCZ_IMC_DATA 0x3f
84
85/*
86 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
87 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
88 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
89 */
90#define SB800_PIIX4_PORT_IDX 0x2c
91#define SB800_PIIX4_PORT_IDX_ALT 0x2e
92#define SB800_PIIX4_PORT_IDX_SEL 0x2f
93#define SB800_PIIX4_PORT_IDX_MASK 0x06
94#define SB800_PIIX4_PORT_IDX_SHIFT 1
95
96/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
97#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
98#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
99#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
100
101/* insmod parameters */
102
103/* If force is set to anything different from 0, we forcibly enable the
104 PIIX4. DANGEROUS! */
105static int force;
106module_param (force, int, 0);
107MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
108
109/* If force_addr is set to anything different from 0, we forcibly enable
110 the PIIX4 at the given address. VERY DANGEROUS! */
111static int force_addr;
112module_param_hw(force_addr, int, ioport, 0);
113MODULE_PARM_DESC(force_addr,
114 "Forcibly enable the PIIX4 at the given address. "
115 "EXTREMELY DANGEROUS!");
116
117static int srvrworks_csb5_delay;
118static struct pci_driver piix4_driver;
119
120static const struct dmi_system_id piix4_dmi_blacklist[] = {
121 {
122 .ident = "Sapphire AM2RD790",
123 .matches = {
124 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
125 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
126 },
127 },
128 {
129 .ident = "DFI Lanparty UT 790FX",
130 .matches = {
131 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
132 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
133 },
134 },
135 { }
136};
137
138/* The IBM entry is in a separate table because we only check it
139 on Intel-based systems */
140static const struct dmi_system_id piix4_dmi_ibm[] = {
141 {
142 .ident = "IBM",
143 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
144 },
145 { },
146};
147
148/*
149 * SB800 globals
150 */
151static u8 piix4_port_sel_sb800;
152static u8 piix4_port_mask_sb800;
153static u8 piix4_port_shift_sb800;
154static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
155 " port 0", " port 2", " port 3", " port 4"
156};
157static const char *piix4_aux_port_name_sb800 = " port 1";
158
159struct i2c_piix4_adapdata {
160 unsigned short smba;
161
162 /* SB800 */
163 bool sb800_main;
164 bool notify_imc;
165 u8 port; /* Port number, shifted */
166};
167
168static int piix4_setup(struct pci_dev *PIIX4_dev,
169 const struct pci_device_id *id)
170{
171 unsigned char temp;
172 unsigned short piix4_smba;
173
174 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
175 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
176 srvrworks_csb5_delay = 1;
177
178 /* On some motherboards, it was reported that accessing the SMBus
179 caused severe hardware problems */
180 if (dmi_check_system(piix4_dmi_blacklist)) {
181 dev_err(&PIIX4_dev->dev,
182 "Accessing the SMBus on this system is unsafe!\n");
183 return -EPERM;
184 }
185
186 /* Don't access SMBus on IBM systems which get corrupted eeproms */
187 if (dmi_check_system(piix4_dmi_ibm) &&
188 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
189 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
190 "may corrupt your serial eeprom! Refusing to load "
191 "module!\n");
192 return -EPERM;
193 }
194
195 /* Determine the address of the SMBus areas */
196 if (force_addr) {
197 piix4_smba = force_addr & 0xfff0;
198 force = 0;
199 } else {
200 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
201 piix4_smba &= 0xfff0;
202 if(piix4_smba == 0) {
203 dev_err(&PIIX4_dev->dev, "SMBus base address "
204 "uninitialized - upgrade BIOS or use "
205 "force_addr=0xaddr\n");
206 return -ENODEV;
207 }
208 }
209
210 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
211 return -ENODEV;
212
213 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
214 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
215 piix4_smba);
216 return -EBUSY;
217 }
218
219 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
220
221 /* If force_addr is set, we program the new address here. Just to make
222 sure, we disable the PIIX4 first. */
223 if (force_addr) {
224 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
225 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
226 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
227 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
228 "new address %04x!\n", piix4_smba);
229 } else if ((temp & 1) == 0) {
230 if (force) {
231 /* This should never need to be done, but has been
232 * noted that many Dell machines have the SMBus
233 * interface on the PIIX4 disabled!? NOTE: This assumes
234 * I/O space and other allocations WERE done by the
235 * Bios! Don't complain if your hardware does weird
236 * things after enabling this. :') Check for Bios
237 * updates before resorting to this.
238 */
239 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
240 temp | 1);
241 dev_notice(&PIIX4_dev->dev,
242 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
243 } else {
244 dev_err(&PIIX4_dev->dev,
245 "SMBus Host Controller not enabled!\n");
246 release_region(piix4_smba, SMBIOSIZE);
247 return -ENODEV;
248 }
249 }
250
251 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
252 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
253 else if ((temp & 0x0E) == 0)
254 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
255 else
256 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
257 "(or code out of date)!\n");
258
259 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
260 dev_info(&PIIX4_dev->dev,
261 "SMBus Host Controller at 0x%x, revision %d\n",
262 piix4_smba, temp);
263
264 return piix4_smba;
265}
266
267static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
268 const struct pci_device_id *id, u8 aux)
269{
270 unsigned short piix4_smba;
271 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
272 u8 i2ccfg, i2ccfg_offset = 0x10;
273
274 /* SB800 and later SMBus does not support forcing address */
275 if (force || force_addr) {
276 dev_err(&PIIX4_dev->dev, "SMBus does not support "
277 "forcing address!\n");
278 return -EINVAL;
279 }
280
281 /* Determine the address of the SMBus areas */
282 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
283 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
284 PIIX4_dev->revision >= 0x41) ||
285 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
286 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
287 PIIX4_dev->revision >= 0x49) ||
288 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
289 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
290 smb_en = 0x00;
291 else
292 smb_en = (aux) ? 0x28 : 0x2c;
293
294 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE,
295 "sb800_piix4_smb")) {
296 dev_err(&PIIX4_dev->dev,
297 "SMB base address index region 0x%x already in use.\n",
298 SB800_PIIX4_SMB_IDX);
299 return -EBUSY;
300 }
301
302 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
303 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
304 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
305 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
306
307 release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
308
309 if (!smb_en) {
310 smb_en_status = smba_en_lo & 0x10;
311 piix4_smba = smba_en_hi << 8;
312 if (aux)
313 piix4_smba |= 0x20;
314 } else {
315 smb_en_status = smba_en_lo & 0x01;
316 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
317 }
318
319 if (!smb_en_status) {
320 dev_err(&PIIX4_dev->dev,
321 "SMBus Host Controller not enabled!\n");
322 return -ENODEV;
323 }
324
325 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
326 return -ENODEV;
327
328 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
329 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
330 piix4_smba);
331 return -EBUSY;
332 }
333
334 /* Aux SMBus does not support IRQ information */
335 if (aux) {
336 dev_info(&PIIX4_dev->dev,
337 "Auxiliary SMBus Host Controller at 0x%x\n",
338 piix4_smba);
339 return piix4_smba;
340 }
341
342 /* Request the SMBus I2C bus config region */
343 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
344 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
345 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
346 release_region(piix4_smba, SMBIOSIZE);
347 return -EBUSY;
348 }
349 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
350 release_region(piix4_smba + i2ccfg_offset, 1);
351
352 if (i2ccfg & 1)
353 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
354 else
355 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
356
357 dev_info(&PIIX4_dev->dev,
358 "SMBus Host Controller at 0x%x, revision %d\n",
359 piix4_smba, i2ccfg >> 4);
360
361 /* Find which register is used for port selection */
362 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
363 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
364 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
365 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
366 PIIX4_dev->revision >= 0x1F)) {
367 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
368 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
369 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
370 } else {
371 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
372 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
373 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
374 }
375 } else {
376 if (!request_muxed_region(SB800_PIIX4_SMB_IDX,
377 SB800_PIIX4_SMB_MAP_SIZE,
378 "sb800_piix4_smb")) {
379 release_region(piix4_smba, SMBIOSIZE);
380 return -EBUSY;
381 }
382
383 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
384 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
385 piix4_port_sel_sb800 = (port_sel & 0x01) ?
386 SB800_PIIX4_PORT_IDX_ALT :
387 SB800_PIIX4_PORT_IDX;
388 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
389 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
390 release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
391 }
392
393 dev_info(&PIIX4_dev->dev,
394 "Using register 0x%02x for SMBus port selection\n",
395 (unsigned int)piix4_port_sel_sb800);
396
397 return piix4_smba;
398}
399
400static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
401 const struct pci_device_id *id,
402 unsigned short base_reg_addr)
403{
404 /* Set up auxiliary SMBus controllers found on some
405 * AMD chipsets e.g. SP5100 (SB700 derivative) */
406
407 unsigned short piix4_smba;
408
409 /* Read address of auxiliary SMBus controller */
410 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
411 if ((piix4_smba & 1) == 0) {
412 dev_dbg(&PIIX4_dev->dev,
413 "Auxiliary SMBus controller not enabled\n");
414 return -ENODEV;
415 }
416
417 piix4_smba &= 0xfff0;
418 if (piix4_smba == 0) {
419 dev_dbg(&PIIX4_dev->dev,
420 "Auxiliary SMBus base address uninitialized\n");
421 return -ENODEV;
422 }
423
424 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
425 return -ENODEV;
426
427 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
428 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
429 "already in use!\n", piix4_smba);
430 return -EBUSY;
431 }
432
433 dev_info(&PIIX4_dev->dev,
434 "Auxiliary SMBus Host Controller at 0x%x\n",
435 piix4_smba);
436
437 return piix4_smba;
438}
439
440static int piix4_transaction(struct i2c_adapter *piix4_adapter)
441{
442 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
443 unsigned short piix4_smba = adapdata->smba;
444 int temp;
445 int result = 0;
446 int timeout = 0;
447
448 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
449 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
450 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
451 inb_p(SMBHSTDAT1));
452
453 /* Make sure the SMBus host is ready to start transmitting */
454 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
455 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
456 "Resetting...\n", temp);
457 outb_p(temp, SMBHSTSTS);
458 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
459 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
460 return -EBUSY;
461 } else {
462 dev_dbg(&piix4_adapter->dev, "Successful!\n");
463 }
464 }
465
466 /* start the transaction by setting bit 6 */
467 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
468
469 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
470 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
471 usleep_range(2000, 2100);
472 else
473 usleep_range(250, 500);
474
475 while ((++timeout < MAX_TIMEOUT) &&
476 ((temp = inb_p(SMBHSTSTS)) & 0x01))
477 usleep_range(250, 500);
478
479 /* If the SMBus is still busy, we give up */
480 if (timeout == MAX_TIMEOUT) {
481 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
482 result = -ETIMEDOUT;
483 }
484
485 if (temp & 0x10) {
486 result = -EIO;
487 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
488 }
489
490 if (temp & 0x08) {
491 result = -EIO;
492 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
493 "locked until next hard reset. (sorry!)\n");
494 /* Clock stops and slave is stuck in mid-transmission */
495 }
496
497 if (temp & 0x04) {
498 result = -ENXIO;
499 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
500 }
501
502 if (inb_p(SMBHSTSTS) != 0x00)
503 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
504
505 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
506 dev_err(&piix4_adapter->dev, "Failed reset at end of "
507 "transaction (%02x)\n", temp);
508 }
509 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
510 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
511 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
512 inb_p(SMBHSTDAT1));
513 return result;
514}
515
516/* Return negative errno on error. */
517static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
518 unsigned short flags, char read_write,
519 u8 command, int size, union i2c_smbus_data * data)
520{
521 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
522 unsigned short piix4_smba = adapdata->smba;
523 int i, len;
524 int status;
525
526 switch (size) {
527 case I2C_SMBUS_QUICK:
528 outb_p((addr << 1) | read_write,
529 SMBHSTADD);
530 size = PIIX4_QUICK;
531 break;
532 case I2C_SMBUS_BYTE:
533 outb_p((addr << 1) | read_write,
534 SMBHSTADD);
535 if (read_write == I2C_SMBUS_WRITE)
536 outb_p(command, SMBHSTCMD);
537 size = PIIX4_BYTE;
538 break;
539 case I2C_SMBUS_BYTE_DATA:
540 outb_p((addr << 1) | read_write,
541 SMBHSTADD);
542 outb_p(command, SMBHSTCMD);
543 if (read_write == I2C_SMBUS_WRITE)
544 outb_p(data->byte, SMBHSTDAT0);
545 size = PIIX4_BYTE_DATA;
546 break;
547 case I2C_SMBUS_WORD_DATA:
548 outb_p((addr << 1) | read_write,
549 SMBHSTADD);
550 outb_p(command, SMBHSTCMD);
551 if (read_write == I2C_SMBUS_WRITE) {
552 outb_p(data->word & 0xff, SMBHSTDAT0);
553 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
554 }
555 size = PIIX4_WORD_DATA;
556 break;
557 case I2C_SMBUS_BLOCK_DATA:
558 outb_p((addr << 1) | read_write,
559 SMBHSTADD);
560 outb_p(command, SMBHSTCMD);
561 if (read_write == I2C_SMBUS_WRITE) {
562 len = data->block[0];
563 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
564 return -EINVAL;
565 outb_p(len, SMBHSTDAT0);
566 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
567 for (i = 1; i <= len; i++)
568 outb_p(data->block[i], SMBBLKDAT);
569 }
570 size = PIIX4_BLOCK_DATA;
571 break;
572 default:
573 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
574 return -EOPNOTSUPP;
575 }
576
577 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
578
579 status = piix4_transaction(adap);
580 if (status)
581 return status;
582
583 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
584 return 0;
585
586
587 switch (size) {
588 case PIIX4_BYTE:
589 case PIIX4_BYTE_DATA:
590 data->byte = inb_p(SMBHSTDAT0);
591 break;
592 case PIIX4_WORD_DATA:
593 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
594 break;
595 case PIIX4_BLOCK_DATA:
596 data->block[0] = inb_p(SMBHSTDAT0);
597 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
598 return -EPROTO;
599 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
600 for (i = 1; i <= data->block[0]; i++)
601 data->block[i] = inb_p(SMBBLKDAT);
602 break;
603 }
604 return 0;
605}
606
607static uint8_t piix4_imc_read(uint8_t idx)
608{
609 outb_p(idx, KERNCZ_IMC_IDX);
610 return inb_p(KERNCZ_IMC_DATA);
611}
612
613static void piix4_imc_write(uint8_t idx, uint8_t value)
614{
615 outb_p(idx, KERNCZ_IMC_IDX);
616 outb_p(value, KERNCZ_IMC_DATA);
617}
618
619static int piix4_imc_sleep(void)
620{
621 int timeout = MAX_TIMEOUT;
622
623 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
624 return -EBUSY;
625
626 /* clear response register */
627 piix4_imc_write(0x82, 0x00);
628 /* request ownership flag */
629 piix4_imc_write(0x83, 0xB4);
630 /* kick off IMC Mailbox command 96 */
631 piix4_imc_write(0x80, 0x96);
632
633 while (timeout--) {
634 if (piix4_imc_read(0x82) == 0xfa) {
635 release_region(KERNCZ_IMC_IDX, 2);
636 return 0;
637 }
638 usleep_range(1000, 2000);
639 }
640
641 release_region(KERNCZ_IMC_IDX, 2);
642 return -ETIMEDOUT;
643}
644
645static void piix4_imc_wakeup(void)
646{
647 int timeout = MAX_TIMEOUT;
648
649 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
650 return;
651
652 /* clear response register */
653 piix4_imc_write(0x82, 0x00);
654 /* release ownership flag */
655 piix4_imc_write(0x83, 0xB5);
656 /* kick off IMC Mailbox command 96 */
657 piix4_imc_write(0x80, 0x96);
658
659 while (timeout--) {
660 if (piix4_imc_read(0x82) == 0xfa)
661 break;
662 usleep_range(1000, 2000);
663 }
664
665 release_region(KERNCZ_IMC_IDX, 2);
666}
667
668/*
669 * Handles access to multiple SMBus ports on the SB800.
670 * The port is selected by bits 2:1 of the smb_en register (0x2c).
671 * Returns negative errno on error.
672 *
673 * Note: The selected port must be returned to the initial selection to avoid
674 * problems on certain systems.
675 */
676static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
677 unsigned short flags, char read_write,
678 u8 command, int size, union i2c_smbus_data *data)
679{
680 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
681 unsigned short piix4_smba = adapdata->smba;
682 int retries = MAX_TIMEOUT;
683 int smbslvcnt;
684 u8 smba_en_lo;
685 u8 port;
686 int retval;
687
688 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE,
689 "sb800_piix4_smb"))
690 return -EBUSY;
691
692 /* Request the SMBUS semaphore, avoid conflicts with the IMC */
693 smbslvcnt = inb_p(SMBSLVCNT);
694 do {
695 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
696
697 /* Check the semaphore status */
698 smbslvcnt = inb_p(SMBSLVCNT);
699 if (smbslvcnt & 0x10)
700 break;
701
702 usleep_range(1000, 2000);
703 } while (--retries);
704 /* SMBus is still owned by the IMC, we give up */
705 if (!retries) {
706 retval = -EBUSY;
707 goto release;
708 }
709
710 /*
711 * Notify the IMC (Integrated Micro Controller) if required.
712 * Among other responsibilities, the IMC is in charge of monitoring
713 * the System fans and temperature sensors, and act accordingly.
714 * All this is done through SMBus and can/will collide
715 * with our transactions if they are long (BLOCK_DATA).
716 * Therefore we need to request the ownership flag during those
717 * transactions.
718 */
719 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
720 int ret;
721
722 ret = piix4_imc_sleep();
723 switch (ret) {
724 case -EBUSY:
725 dev_warn(&adap->dev,
726 "IMC base address index region 0x%x already in use.\n",
727 KERNCZ_IMC_IDX);
728 break;
729 case -ETIMEDOUT:
730 dev_warn(&adap->dev,
731 "Failed to communicate with the IMC.\n");
732 break;
733 default:
734 break;
735 }
736
737 /* If IMC communication fails do not retry */
738 if (ret) {
739 dev_warn(&adap->dev,
740 "Continuing without IMC notification.\n");
741 adapdata->notify_imc = false;
742 }
743 }
744
745 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
746 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
747
748 port = adapdata->port;
749 if ((smba_en_lo & piix4_port_mask_sb800) != port)
750 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
751 SB800_PIIX4_SMB_IDX + 1);
752
753 retval = piix4_access(adap, addr, flags, read_write,
754 command, size, data);
755
756 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
757
758 /* Release the semaphore */
759 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
760
761 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
762 piix4_imc_wakeup();
763
764release:
765 release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
766 return retval;
767}
768
769static u32 piix4_func(struct i2c_adapter *adapter)
770{
771 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
772 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
773 I2C_FUNC_SMBUS_BLOCK_DATA;
774}
775
776static const struct i2c_algorithm smbus_algorithm = {
777 .smbus_xfer = piix4_access,
778 .functionality = piix4_func,
779};
780
781static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
782 .smbus_xfer = piix4_access_sb800,
783 .functionality = piix4_func,
784};
785
786static const struct pci_device_id piix4_ids[] = {
787 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
788 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
789 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
790 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
791 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
792 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
793 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
794 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
795 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
796 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
797 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
798 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
799 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
800 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
801 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
802 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
803 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
804 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
805 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
806 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
807 { 0, }
808};
809
810MODULE_DEVICE_TABLE (pci, piix4_ids);
811
812static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
813static struct i2c_adapter *piix4_aux_adapter;
814static int piix4_adapter_count;
815
816static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
817 bool sb800_main, u8 port, bool notify_imc,
818 u8 hw_port_nr, const char *name,
819 struct i2c_adapter **padap)
820{
821 struct i2c_adapter *adap;
822 struct i2c_piix4_adapdata *adapdata;
823 int retval;
824
825 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
826 if (adap == NULL) {
827 release_region(smba, SMBIOSIZE);
828 return -ENOMEM;
829 }
830
831 adap->owner = THIS_MODULE;
832 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
833 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
834 : &smbus_algorithm;
835
836 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
837 if (adapdata == NULL) {
838 kfree(adap);
839 release_region(smba, SMBIOSIZE);
840 return -ENOMEM;
841 }
842
843 adapdata->smba = smba;
844 adapdata->sb800_main = sb800_main;
845 adapdata->port = port << piix4_port_shift_sb800;
846 adapdata->notify_imc = notify_imc;
847
848 /* set up the sysfs linkage to our parent device */
849 adap->dev.parent = &dev->dev;
850
851 if (has_acpi_companion(&dev->dev)) {
852 acpi_preset_companion(&adap->dev,
853 ACPI_COMPANION(&dev->dev),
854 hw_port_nr);
855 }
856
857 snprintf(adap->name, sizeof(adap->name),
858 "SMBus PIIX4 adapter%s at %04x", name, smba);
859
860 i2c_set_adapdata(adap, adapdata);
861
862 retval = i2c_add_adapter(adap);
863 if (retval) {
864 kfree(adapdata);
865 kfree(adap);
866 release_region(smba, SMBIOSIZE);
867 return retval;
868 }
869
870 *padap = adap;
871 return 0;
872}
873
874static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
875 bool notify_imc)
876{
877 struct i2c_piix4_adapdata *adapdata;
878 int port;
879 int retval;
880
881 if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
882 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
883 dev->revision >= 0x1F)) {
884 piix4_adapter_count = HUDSON2_MAIN_PORTS;
885 } else {
886 piix4_adapter_count = PIIX4_MAX_ADAPTERS;
887 }
888
889 for (port = 0; port < piix4_adapter_count; port++) {
890 u8 hw_port_nr = port == 0 ? 0 : port + 1;
891
892 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
893 hw_port_nr,
894 piix4_main_port_names_sb800[port],
895 &piix4_main_adapters[port]);
896 if (retval < 0)
897 goto error;
898 }
899
900 return retval;
901
902error:
903 dev_err(&dev->dev,
904 "Error setting up SB800 adapters. Unregistering!\n");
905 while (--port >= 0) {
906 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
907 if (adapdata->smba) {
908 i2c_del_adapter(piix4_main_adapters[port]);
909 kfree(adapdata);
910 kfree(piix4_main_adapters[port]);
911 piix4_main_adapters[port] = NULL;
912 }
913 }
914
915 return retval;
916}
917
918static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
919{
920 int retval;
921 bool is_sb800 = false;
922
923 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
924 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
925 dev->revision >= 0x40) ||
926 dev->vendor == PCI_VENDOR_ID_AMD ||
927 dev->vendor == PCI_VENDOR_ID_HYGON) {
928 bool notify_imc = false;
929 is_sb800 = true;
930
931 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
932 dev->vendor == PCI_VENDOR_ID_HYGON) &&
933 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
934 u8 imc;
935
936 /*
937 * Detect if IMC is active or not, this method is
938 * described on coreboot's AMD IMC notes
939 */
940 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
941 0x40, &imc);
942 if (imc & 0x80)
943 notify_imc = true;
944 }
945
946 /* base address location etc changed in SB800 */
947 retval = piix4_setup_sb800(dev, id, 0);
948 if (retval < 0)
949 return retval;
950
951 /*
952 * Try to register multiplexed main SMBus adapter,
953 * give up if we can't
954 */
955 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
956 if (retval < 0)
957 return retval;
958 } else {
959 retval = piix4_setup(dev, id);
960 if (retval < 0)
961 return retval;
962
963 /* Try to register main SMBus adapter, give up if we can't */
964 retval = piix4_add_adapter(dev, retval, false, 0, false, 0,
965 "", &piix4_main_adapters[0]);
966 if (retval < 0)
967 return retval;
968 }
969
970 /* Check for auxiliary SMBus on some AMD chipsets */
971 retval = -ENODEV;
972
973 if (dev->vendor == PCI_VENDOR_ID_ATI &&
974 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
975 if (dev->revision < 0x40) {
976 retval = piix4_setup_aux(dev, id, 0x58);
977 } else {
978 /* SB800 added aux bus too */
979 retval = piix4_setup_sb800(dev, id, 1);
980 }
981 }
982
983 if (dev->vendor == PCI_VENDOR_ID_AMD &&
984 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
985 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
986 retval = piix4_setup_sb800(dev, id, 1);
987 }
988
989 if (retval > 0) {
990 /* Try to add the aux adapter if it exists,
991 * piix4_add_adapter will clean up if this fails */
992 piix4_add_adapter(dev, retval, false, 0, false, 1,
993 is_sb800 ? piix4_aux_port_name_sb800 : "",
994 &piix4_aux_adapter);
995 }
996
997 return 0;
998}
999
1000static void piix4_adap_remove(struct i2c_adapter *adap)
1001{
1002 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
1003
1004 if (adapdata->smba) {
1005 i2c_del_adapter(adap);
1006 if (adapdata->port == (0 << piix4_port_shift_sb800))
1007 release_region(adapdata->smba, SMBIOSIZE);
1008 kfree(adapdata);
1009 kfree(adap);
1010 }
1011}
1012
1013static void piix4_remove(struct pci_dev *dev)
1014{
1015 int port = piix4_adapter_count;
1016
1017 while (--port >= 0) {
1018 if (piix4_main_adapters[port]) {
1019 piix4_adap_remove(piix4_main_adapters[port]);
1020 piix4_main_adapters[port] = NULL;
1021 }
1022 }
1023
1024 if (piix4_aux_adapter) {
1025 piix4_adap_remove(piix4_aux_adapter);
1026 piix4_aux_adapter = NULL;
1027 }
1028}
1029
1030static struct pci_driver piix4_driver = {
1031 .name = "piix4_smbus",
1032 .id_table = piix4_ids,
1033 .probe = piix4_probe,
1034 .remove = piix4_remove,
1035};
1036
1037module_pci_driver(piix4_driver);
1038
1039MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
1040MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>");
1041MODULE_DESCRIPTION("PIIX4 SMBus driver");
1042MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)