| 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include "drmP.h" |
| 29 | #include "radeon_drm.h" |
| 30 | #include "radeon_reg.h" |
| 31 | #include "radeon.h" |
| 32 | #include "atom.h" |
| 33 | |
| 34 | /* 10 khz */ |
| 35 | static uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) |
| 36 | { |
| 37 | struct radeon_pll *spll = &rdev->clock.spll; |
| 38 | uint32_t fb_div, ref_div, post_div, sclk; |
| 39 | |
| 40 | fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
| 41 | fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; |
| 42 | fb_div <<= 1; |
| 43 | fb_div *= spll->reference_freq; |
| 44 | |
| 45 | ref_div = |
| 46 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
| 47 | sclk = fb_div / ref_div; |
| 48 | |
| 49 | post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; |
| 50 | if (post_div == 2) |
| 51 | sclk >>= 1; |
| 52 | else if (post_div == 3) |
| 53 | sclk >>= 2; |
| 54 | else if (post_div == 4) |
| 55 | sclk >>= 4; |
| 56 | |
| 57 | return sclk; |
| 58 | } |
| 59 | |
| 60 | /* 10 khz */ |
| 61 | static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) |
| 62 | { |
| 63 | struct radeon_pll *mpll = &rdev->clock.mpll; |
| 64 | uint32_t fb_div, ref_div, post_div, mclk; |
| 65 | |
| 66 | fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
| 67 | fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; |
| 68 | fb_div <<= 1; |
| 69 | fb_div *= mpll->reference_freq; |
| 70 | |
| 71 | ref_div = |
| 72 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
| 73 | mclk = fb_div / ref_div; |
| 74 | |
| 75 | post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; |
| 76 | if (post_div == 2) |
| 77 | mclk >>= 1; |
| 78 | else if (post_div == 3) |
| 79 | mclk >>= 2; |
| 80 | else if (post_div == 4) |
| 81 | mclk >>= 4; |
| 82 | |
| 83 | return mclk; |
| 84 | } |
| 85 | |
| 86 | void radeon_get_clock_info(struct drm_device *dev) |
| 87 | { |
| 88 | struct radeon_device *rdev = dev->dev_private; |
| 89 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
| 90 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
| 91 | struct radeon_pll *spll = &rdev->clock.spll; |
| 92 | struct radeon_pll *mpll = &rdev->clock.mpll; |
| 93 | int ret; |
| 94 | |
| 95 | if (rdev->is_atom_bios) |
| 96 | ret = radeon_atom_get_clock_info(dev); |
| 97 | else |
| 98 | ret = radeon_combios_get_clock_info(dev); |
| 99 | |
| 100 | if (ret) { |
| 101 | if (p1pll->reference_div < 2) |
| 102 | p1pll->reference_div = 12; |
| 103 | if (p2pll->reference_div < 2) |
| 104 | p2pll->reference_div = 12; |
| 105 | if (rdev->family < CHIP_RS600) { |
| 106 | if (spll->reference_div < 2) |
| 107 | spll->reference_div = |
| 108 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
| 109 | RADEON_M_SPLL_REF_DIV_MASK; |
| 110 | } |
| 111 | if (mpll->reference_div < 2) |
| 112 | mpll->reference_div = spll->reference_div; |
| 113 | } else { |
| 114 | if (ASIC_IS_AVIVO(rdev)) { |
| 115 | /* TODO FALLBACK */ |
| 116 | } else { |
| 117 | DRM_INFO("Using generic clock info\n"); |
| 118 | |
| 119 | if (rdev->flags & RADEON_IS_IGP) { |
| 120 | p1pll->reference_freq = 1432; |
| 121 | p2pll->reference_freq = 1432; |
| 122 | spll->reference_freq = 1432; |
| 123 | mpll->reference_freq = 1432; |
| 124 | } else { |
| 125 | p1pll->reference_freq = 2700; |
| 126 | p2pll->reference_freq = 2700; |
| 127 | spll->reference_freq = 2700; |
| 128 | mpll->reference_freq = 2700; |
| 129 | } |
| 130 | p1pll->reference_div = |
| 131 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
| 132 | if (p1pll->reference_div < 2) |
| 133 | p1pll->reference_div = 12; |
| 134 | p2pll->reference_div = p1pll->reference_div; |
| 135 | |
| 136 | if (rdev->family >= CHIP_R420) { |
| 137 | p1pll->pll_in_min = 100; |
| 138 | p1pll->pll_in_max = 1350; |
| 139 | p1pll->pll_out_min = 20000; |
| 140 | p1pll->pll_out_max = 50000; |
| 141 | p2pll->pll_in_min = 100; |
| 142 | p2pll->pll_in_max = 1350; |
| 143 | p2pll->pll_out_min = 20000; |
| 144 | p2pll->pll_out_max = 50000; |
| 145 | } else { |
| 146 | p1pll->pll_in_min = 40; |
| 147 | p1pll->pll_in_max = 500; |
| 148 | p1pll->pll_out_min = 12500; |
| 149 | p1pll->pll_out_max = 35000; |
| 150 | p2pll->pll_in_min = 40; |
| 151 | p2pll->pll_in_max = 500; |
| 152 | p2pll->pll_out_min = 12500; |
| 153 | p2pll->pll_out_max = 35000; |
| 154 | } |
| 155 | |
| 156 | spll->reference_div = |
| 157 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
| 158 | RADEON_M_SPLL_REF_DIV_MASK; |
| 159 | mpll->reference_div = spll->reference_div; |
| 160 | rdev->clock.default_sclk = |
| 161 | radeon_legacy_get_engine_clock(rdev); |
| 162 | rdev->clock.default_mclk = |
| 163 | radeon_legacy_get_memory_clock(rdev); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* pixel clocks */ |
| 168 | if (ASIC_IS_AVIVO(rdev)) { |
| 169 | p1pll->min_post_div = 2; |
| 170 | p1pll->max_post_div = 0x7f; |
| 171 | p1pll->min_frac_feedback_div = 0; |
| 172 | p1pll->max_frac_feedback_div = 9; |
| 173 | p2pll->min_post_div = 2; |
| 174 | p2pll->max_post_div = 0x7f; |
| 175 | p2pll->min_frac_feedback_div = 0; |
| 176 | p2pll->max_frac_feedback_div = 9; |
| 177 | } else { |
| 178 | p1pll->min_post_div = 1; |
| 179 | p1pll->max_post_div = 16; |
| 180 | p1pll->min_frac_feedback_div = 0; |
| 181 | p1pll->max_frac_feedback_div = 0; |
| 182 | p2pll->min_post_div = 1; |
| 183 | p2pll->max_post_div = 12; |
| 184 | p2pll->min_frac_feedback_div = 0; |
| 185 | p2pll->max_frac_feedback_div = 0; |
| 186 | } |
| 187 | |
| 188 | p1pll->min_ref_div = 2; |
| 189 | p1pll->max_ref_div = 0x3ff; |
| 190 | p1pll->min_feedback_div = 4; |
| 191 | p1pll->max_feedback_div = 0x7ff; |
| 192 | p1pll->best_vco = 0; |
| 193 | |
| 194 | p2pll->min_ref_div = 2; |
| 195 | p2pll->max_ref_div = 0x3ff; |
| 196 | p2pll->min_feedback_div = 4; |
| 197 | p2pll->max_feedback_div = 0x7ff; |
| 198 | p2pll->best_vco = 0; |
| 199 | |
| 200 | /* system clock */ |
| 201 | spll->min_post_div = 1; |
| 202 | spll->max_post_div = 1; |
| 203 | spll->min_ref_div = 2; |
| 204 | spll->max_ref_div = 0xff; |
| 205 | spll->min_feedback_div = 4; |
| 206 | spll->max_feedback_div = 0xff; |
| 207 | spll->best_vco = 0; |
| 208 | |
| 209 | /* memory clock */ |
| 210 | mpll->min_post_div = 1; |
| 211 | mpll->max_post_div = 1; |
| 212 | mpll->min_ref_div = 2; |
| 213 | mpll->max_ref_div = 0xff; |
| 214 | mpll->min_feedback_div = 4; |
| 215 | mpll->max_feedback_div = 0xff; |
| 216 | mpll->best_vco = 0; |
| 217 | |
| 218 | } |
| 219 | |
| 220 | /* 10 khz */ |
| 221 | static uint32_t calc_eng_mem_clock(struct radeon_device *rdev, |
| 222 | uint32_t req_clock, |
| 223 | int *fb_div, int *post_div) |
| 224 | { |
| 225 | struct radeon_pll *spll = &rdev->clock.spll; |
| 226 | int ref_div = spll->reference_div; |
| 227 | |
| 228 | if (!ref_div) |
| 229 | ref_div = |
| 230 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
| 231 | RADEON_M_SPLL_REF_DIV_MASK; |
| 232 | |
| 233 | if (req_clock < 15000) { |
| 234 | *post_div = 8; |
| 235 | req_clock *= 8; |
| 236 | } else if (req_clock < 30000) { |
| 237 | *post_div = 4; |
| 238 | req_clock *= 4; |
| 239 | } else if (req_clock < 60000) { |
| 240 | *post_div = 2; |
| 241 | req_clock *= 2; |
| 242 | } else |
| 243 | *post_div = 1; |
| 244 | |
| 245 | req_clock *= ref_div; |
| 246 | req_clock += spll->reference_freq; |
| 247 | req_clock /= (2 * spll->reference_freq); |
| 248 | |
| 249 | *fb_div = req_clock & 0xff; |
| 250 | |
| 251 | req_clock = (req_clock & 0xffff) << 1; |
| 252 | req_clock *= spll->reference_freq; |
| 253 | req_clock /= ref_div; |
| 254 | req_clock /= *post_div; |
| 255 | |
| 256 | return req_clock; |
| 257 | } |
| 258 | |
| 259 | /* 10 khz */ |
| 260 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, |
| 261 | uint32_t eng_clock) |
| 262 | { |
| 263 | uint32_t tmp; |
| 264 | int fb_div, post_div; |
| 265 | |
| 266 | /* XXX: wait for idle */ |
| 267 | |
| 268 | eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); |
| 269 | |
| 270 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| 271 | tmp &= ~RADEON_DONT_USE_XTALIN; |
| 272 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| 273 | |
| 274 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 275 | tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
| 276 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 277 | |
| 278 | udelay(10); |
| 279 | |
| 280 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| 281 | tmp |= RADEON_SPLL_SLEEP; |
| 282 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| 283 | |
| 284 | udelay(2); |
| 285 | |
| 286 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| 287 | tmp |= RADEON_SPLL_RESET; |
| 288 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| 289 | |
| 290 | udelay(200); |
| 291 | |
| 292 | tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
| 293 | tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); |
| 294 | tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; |
| 295 | WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); |
| 296 | |
| 297 | /* XXX: verify on different asics */ |
| 298 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| 299 | tmp &= ~RADEON_SPLL_PVG_MASK; |
| 300 | if ((eng_clock * post_div) >= 90000) |
| 301 | tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); |
| 302 | else |
| 303 | tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); |
| 304 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| 305 | |
| 306 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| 307 | tmp &= ~RADEON_SPLL_SLEEP; |
| 308 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| 309 | |
| 310 | udelay(2); |
| 311 | |
| 312 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| 313 | tmp &= ~RADEON_SPLL_RESET; |
| 314 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| 315 | |
| 316 | udelay(200); |
| 317 | |
| 318 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 319 | tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
| 320 | switch (post_div) { |
| 321 | case 1: |
| 322 | default: |
| 323 | tmp |= 1; |
| 324 | break; |
| 325 | case 2: |
| 326 | tmp |= 2; |
| 327 | break; |
| 328 | case 4: |
| 329 | tmp |= 3; |
| 330 | break; |
| 331 | case 8: |
| 332 | tmp |= 4; |
| 333 | break; |
| 334 | } |
| 335 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 336 | |
| 337 | udelay(20); |
| 338 | |
| 339 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| 340 | tmp |= RADEON_DONT_USE_XTALIN; |
| 341 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| 342 | |
| 343 | udelay(10); |
| 344 | } |
| 345 | |
| 346 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) |
| 347 | { |
| 348 | uint32_t tmp; |
| 349 | |
| 350 | if (enable) { |
| 351 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
| 352 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 353 | if ((RREG32(RADEON_CONFIG_CNTL) & |
| 354 | RADEON_CFG_ATI_REV_ID_MASK) > |
| 355 | RADEON_CFG_ATI_REV_A13) { |
| 356 | tmp &= |
| 357 | ~(RADEON_SCLK_FORCE_CP | |
| 358 | RADEON_SCLK_FORCE_RB); |
| 359 | } |
| 360 | tmp &= |
| 361 | ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | |
| 362 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | |
| 363 | RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | |
| 364 | RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | |
| 365 | RADEON_SCLK_FORCE_TDM); |
| 366 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 367 | } else if (ASIC_IS_R300(rdev)) { |
| 368 | if ((rdev->family == CHIP_RS400) || |
| 369 | (rdev->family == CHIP_RS480)) { |
| 370 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 371 | tmp &= |
| 372 | ~(RADEON_SCLK_FORCE_DISP2 | |
| 373 | RADEON_SCLK_FORCE_CP | |
| 374 | RADEON_SCLK_FORCE_HDP | |
| 375 | RADEON_SCLK_FORCE_DISP1 | |
| 376 | RADEON_SCLK_FORCE_TOP | |
| 377 | RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
| 378 | | RADEON_SCLK_FORCE_IDCT | |
| 379 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
| 380 | | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
| 381 | | R300_SCLK_FORCE_US | |
| 382 | RADEON_SCLK_FORCE_TV_SCLK | |
| 383 | R300_SCLK_FORCE_SU | |
| 384 | RADEON_SCLK_FORCE_OV0); |
| 385 | tmp |= RADEON_DYN_STOP_LAT_MASK; |
| 386 | tmp |= |
| 387 | RADEON_SCLK_FORCE_TOP | |
| 388 | RADEON_SCLK_FORCE_VIP; |
| 389 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 390 | |
| 391 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| 392 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
| 393 | tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
| 394 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| 395 | |
| 396 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 397 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| 398 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| 399 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 400 | |
| 401 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 402 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
| 403 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| 404 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| 405 | R300_DVOCLK_ALWAYS_ONb | |
| 406 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| 407 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
| 408 | R300_PIXCLK_DVO_ALWAYS_ONb | |
| 409 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 410 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 411 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 412 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 413 | R300_P2G2CLK_ALWAYS_ONb | |
| 414 | R300_P2G2CLK_ALWAYS_ONb); |
| 415 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 416 | } else if (rdev->family >= CHIP_RV350) { |
| 417 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| 418 | tmp &= ~(R300_SCLK_FORCE_TCL | |
| 419 | R300_SCLK_FORCE_GA | |
| 420 | R300_SCLK_FORCE_CBA); |
| 421 | tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | |
| 422 | R300_SCLK_GA_MAX_DYN_STOP_LAT | |
| 423 | R300_SCLK_CBA_MAX_DYN_STOP_LAT); |
| 424 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| 425 | |
| 426 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 427 | tmp &= |
| 428 | ~(RADEON_SCLK_FORCE_DISP2 | |
| 429 | RADEON_SCLK_FORCE_CP | |
| 430 | RADEON_SCLK_FORCE_HDP | |
| 431 | RADEON_SCLK_FORCE_DISP1 | |
| 432 | RADEON_SCLK_FORCE_TOP | |
| 433 | RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
| 434 | | RADEON_SCLK_FORCE_IDCT | |
| 435 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
| 436 | | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
| 437 | | R300_SCLK_FORCE_US | |
| 438 | RADEON_SCLK_FORCE_TV_SCLK | |
| 439 | R300_SCLK_FORCE_SU | |
| 440 | RADEON_SCLK_FORCE_OV0); |
| 441 | tmp |= RADEON_DYN_STOP_LAT_MASK; |
| 442 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 443 | |
| 444 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| 445 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
| 446 | tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
| 447 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| 448 | |
| 449 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 450 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| 451 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| 452 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 453 | |
| 454 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 455 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
| 456 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| 457 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| 458 | R300_DVOCLK_ALWAYS_ONb | |
| 459 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| 460 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
| 461 | R300_PIXCLK_DVO_ALWAYS_ONb | |
| 462 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 463 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 464 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 465 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 466 | R300_P2G2CLK_ALWAYS_ONb | |
| 467 | R300_P2G2CLK_ALWAYS_ONb); |
| 468 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 469 | |
| 470 | tmp = RREG32_PLL(RADEON_MCLK_MISC); |
| 471 | tmp |= (RADEON_MC_MCLK_DYN_ENABLE | |
| 472 | RADEON_IO_MCLK_DYN_ENABLE); |
| 473 | WREG32_PLL(RADEON_MCLK_MISC, tmp); |
| 474 | |
| 475 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| 476 | tmp |= (RADEON_FORCEON_MCLKA | |
| 477 | RADEON_FORCEON_MCLKB); |
| 478 | |
| 479 | tmp &= ~(RADEON_FORCEON_YCLKA | |
| 480 | RADEON_FORCEON_YCLKB | |
| 481 | RADEON_FORCEON_MC); |
| 482 | |
| 483 | /* Some releases of vbios have set DISABLE_MC_MCLKA |
| 484 | and DISABLE_MC_MCLKB bits in the vbios table. Setting these |
| 485 | bits will cause H/W hang when reading video memory with dynamic clocking |
| 486 | enabled. */ |
| 487 | if ((tmp & R300_DISABLE_MC_MCLKA) && |
| 488 | (tmp & R300_DISABLE_MC_MCLKB)) { |
| 489 | /* If both bits are set, then check the active channels */ |
| 490 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| 491 | if (rdev->mc.vram_width == 64) { |
| 492 | if (RREG32(RADEON_MEM_CNTL) & |
| 493 | R300_MEM_USE_CD_CH_ONLY) |
| 494 | tmp &= |
| 495 | ~R300_DISABLE_MC_MCLKB; |
| 496 | else |
| 497 | tmp &= |
| 498 | ~R300_DISABLE_MC_MCLKA; |
| 499 | } else { |
| 500 | tmp &= ~(R300_DISABLE_MC_MCLKA | |
| 501 | R300_DISABLE_MC_MCLKB); |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| 506 | } else { |
| 507 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 508 | tmp &= ~(R300_SCLK_FORCE_VAP); |
| 509 | tmp |= RADEON_SCLK_FORCE_CP; |
| 510 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 511 | udelay(15000); |
| 512 | |
| 513 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| 514 | tmp &= ~(R300_SCLK_FORCE_TCL | |
| 515 | R300_SCLK_FORCE_GA | |
| 516 | R300_SCLK_FORCE_CBA); |
| 517 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| 518 | } |
| 519 | } else { |
| 520 | tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
| 521 | |
| 522 | tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | |
| 523 | RADEON_DISP_DYN_STOP_LAT_MASK | |
| 524 | RADEON_DYN_STOP_MODE_MASK); |
| 525 | |
| 526 | tmp |= (RADEON_ENGIN_DYNCLK_MODE | |
| 527 | (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); |
| 528 | WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); |
| 529 | udelay(15000); |
| 530 | |
| 531 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| 532 | tmp |= RADEON_SCLK_DYN_START_CNTL; |
| 533 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| 534 | udelay(15000); |
| 535 | |
| 536 | /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 |
| 537 | to lockup randomly, leave them as set by BIOS. |
| 538 | */ |
| 539 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 540 | /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */ |
| 541 | tmp &= ~RADEON_SCLK_FORCEON_MASK; |
| 542 | |
| 543 | /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */ |
| 544 | if (((rdev->family == CHIP_RV250) && |
| 545 | ((RREG32(RADEON_CONFIG_CNTL) & |
| 546 | RADEON_CFG_ATI_REV_ID_MASK) < |
| 547 | RADEON_CFG_ATI_REV_A13)) |
| 548 | || ((rdev->family == CHIP_RV100) |
| 549 | && |
| 550 | ((RREG32(RADEON_CONFIG_CNTL) & |
| 551 | RADEON_CFG_ATI_REV_ID_MASK) <= |
| 552 | RADEON_CFG_ATI_REV_A13))) { |
| 553 | tmp |= RADEON_SCLK_FORCE_CP; |
| 554 | tmp |= RADEON_SCLK_FORCE_VIP; |
| 555 | } |
| 556 | |
| 557 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 558 | |
| 559 | if ((rdev->family == CHIP_RV200) || |
| 560 | (rdev->family == CHIP_RV250) || |
| 561 | (rdev->family == CHIP_RV280)) { |
| 562 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| 563 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
| 564 | |
| 565 | /* RV200::A11 A12 RV250::A11 A12 */ |
| 566 | if (((rdev->family == CHIP_RV200) || |
| 567 | (rdev->family == CHIP_RV250)) && |
| 568 | ((RREG32(RADEON_CONFIG_CNTL) & |
| 569 | RADEON_CFG_ATI_REV_ID_MASK) < |
| 570 | RADEON_CFG_ATI_REV_A13)) { |
| 571 | tmp |= RADEON_SCLK_MORE_FORCEON; |
| 572 | } |
| 573 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| 574 | udelay(15000); |
| 575 | } |
| 576 | |
| 577 | /* RV200::A11 A12, RV250::A11 A12 */ |
| 578 | if (((rdev->family == CHIP_RV200) || |
| 579 | (rdev->family == CHIP_RV250)) && |
| 580 | ((RREG32(RADEON_CONFIG_CNTL) & |
| 581 | RADEON_CFG_ATI_REV_ID_MASK) < |
| 582 | RADEON_CFG_ATI_REV_A13)) { |
| 583 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
| 584 | tmp |= RADEON_TCL_BYPASS_DISABLE; |
| 585 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
| 586 | } |
| 587 | udelay(15000); |
| 588 | |
| 589 | /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ |
| 590 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 591 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
| 592 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| 593 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| 594 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
| 595 | RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
| 596 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 597 | RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
| 598 | |
| 599 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 600 | udelay(15000); |
| 601 | |
| 602 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 603 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| 604 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| 605 | |
| 606 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 607 | udelay(15000); |
| 608 | } |
| 609 | } else { |
| 610 | /* Turn everything OFF (ForceON to everything) */ |
| 611 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
| 612 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 613 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | |
| 614 | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
| 615 | | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | |
| 616 | RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | |
| 617 | RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | |
| 618 | RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | |
| 619 | RADEON_SCLK_FORCE_RB); |
| 620 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 621 | } else if ((rdev->family == CHIP_RS400) || |
| 622 | (rdev->family == CHIP_RS480)) { |
| 623 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 624 | tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
| 625 | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
| 626 | | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
| 627 | R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
| 628 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
| 629 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
| 630 | R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
| 631 | R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
| 632 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 633 | |
| 634 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| 635 | tmp |= RADEON_SCLK_MORE_FORCEON; |
| 636 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| 637 | |
| 638 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 639 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
| 640 | RADEON_PIXCLK_DAC_ALWAYS_ONb | |
| 641 | R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
| 642 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 643 | |
| 644 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 645 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
| 646 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| 647 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| 648 | R300_DVOCLK_ALWAYS_ONb | |
| 649 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| 650 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
| 651 | R300_PIXCLK_DVO_ALWAYS_ONb | |
| 652 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 653 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 654 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 655 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 656 | R300_P2G2CLK_ALWAYS_ONb | |
| 657 | R300_P2G2CLK_ALWAYS_ONb | |
| 658 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| 659 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 660 | } else if (rdev->family >= CHIP_RV350) { |
| 661 | /* for RV350/M10, no delays are required. */ |
| 662 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| 663 | tmp |= (R300_SCLK_FORCE_TCL | |
| 664 | R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); |
| 665 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| 666 | |
| 667 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 668 | tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
| 669 | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
| 670 | | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
| 671 | R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
| 672 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
| 673 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
| 674 | R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
| 675 | R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
| 676 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 677 | |
| 678 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| 679 | tmp |= RADEON_SCLK_MORE_FORCEON; |
| 680 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| 681 | |
| 682 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| 683 | tmp |= (RADEON_FORCEON_MCLKA | |
| 684 | RADEON_FORCEON_MCLKB | |
| 685 | RADEON_FORCEON_YCLKA | |
| 686 | RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC); |
| 687 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| 688 | |
| 689 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 690 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
| 691 | RADEON_PIXCLK_DAC_ALWAYS_ONb | |
| 692 | R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
| 693 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 694 | |
| 695 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 696 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
| 697 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| 698 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| 699 | R300_DVOCLK_ALWAYS_ONb | |
| 700 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| 701 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
| 702 | R300_PIXCLK_DVO_ALWAYS_ONb | |
| 703 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 704 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 705 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 706 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 707 | R300_P2G2CLK_ALWAYS_ONb | |
| 708 | R300_P2G2CLK_ALWAYS_ONb | |
| 709 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| 710 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 711 | } else { |
| 712 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 713 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); |
| 714 | tmp |= RADEON_SCLK_FORCE_SE; |
| 715 | |
| 716 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
| 717 | tmp |= (RADEON_SCLK_FORCE_RB | |
| 718 | RADEON_SCLK_FORCE_TDM | |
| 719 | RADEON_SCLK_FORCE_TAM | |
| 720 | RADEON_SCLK_FORCE_PB | |
| 721 | RADEON_SCLK_FORCE_RE | |
| 722 | RADEON_SCLK_FORCE_VIP | |
| 723 | RADEON_SCLK_FORCE_IDCT | |
| 724 | RADEON_SCLK_FORCE_TOP | |
| 725 | RADEON_SCLK_FORCE_DISP1 | |
| 726 | RADEON_SCLK_FORCE_DISP2 | |
| 727 | RADEON_SCLK_FORCE_HDP); |
| 728 | } else if ((rdev->family == CHIP_R300) || |
| 729 | (rdev->family == CHIP_R350)) { |
| 730 | tmp |= (RADEON_SCLK_FORCE_HDP | |
| 731 | RADEON_SCLK_FORCE_DISP1 | |
| 732 | RADEON_SCLK_FORCE_DISP2 | |
| 733 | RADEON_SCLK_FORCE_TOP | |
| 734 | RADEON_SCLK_FORCE_IDCT | |
| 735 | RADEON_SCLK_FORCE_VIP); |
| 736 | } |
| 737 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 738 | |
| 739 | udelay(16000); |
| 740 | |
| 741 | if ((rdev->family == CHIP_R300) || |
| 742 | (rdev->family == CHIP_R350)) { |
| 743 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| 744 | tmp |= (R300_SCLK_FORCE_TCL | |
| 745 | R300_SCLK_FORCE_GA | |
| 746 | R300_SCLK_FORCE_CBA); |
| 747 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| 748 | udelay(16000); |
| 749 | } |
| 750 | |
| 751 | if (rdev->flags & RADEON_IS_IGP) { |
| 752 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| 753 | tmp &= ~(RADEON_FORCEON_MCLKA | |
| 754 | RADEON_FORCEON_YCLKA); |
| 755 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| 756 | udelay(16000); |
| 757 | } |
| 758 | |
| 759 | if ((rdev->family == CHIP_RV200) || |
| 760 | (rdev->family == CHIP_RV250) || |
| 761 | (rdev->family == CHIP_RV280)) { |
| 762 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| 763 | tmp |= RADEON_SCLK_MORE_FORCEON; |
| 764 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| 765 | udelay(16000); |
| 766 | } |
| 767 | |
| 768 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 769 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
| 770 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| 771 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| 772 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
| 773 | RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
| 774 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 775 | RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
| 776 | |
| 777 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 778 | udelay(16000); |
| 779 | |
| 780 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 781 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
| 782 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| 783 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 784 | } |
| 785 | } |
| 786 | } |
| 787 | |
| 788 | static void radeon_apply_clock_quirks(struct radeon_device *rdev) |
| 789 | { |
| 790 | uint32_t tmp; |
| 791 | |
| 792 | /* XXX make sure engine is idle */ |
| 793 | |
| 794 | if (rdev->family < CHIP_RS600) { |
| 795 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 796 | if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev)) |
| 797 | tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; |
| 798 | if ((rdev->family == CHIP_RV250) |
| 799 | || (rdev->family == CHIP_RV280)) |
| 800 | tmp |= |
| 801 | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2; |
| 802 | if ((rdev->family == CHIP_RV350) |
| 803 | || (rdev->family == CHIP_RV380)) |
| 804 | tmp |= R300_SCLK_FORCE_VAP; |
| 805 | if (rdev->family == CHIP_R420) |
| 806 | tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX; |
| 807 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| 808 | } else if (rdev->family < CHIP_R600) { |
| 809 | tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL); |
| 810 | tmp |= AVIVO_CP_FORCEON; |
| 811 | WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp); |
| 812 | |
| 813 | tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL); |
| 814 | tmp |= AVIVO_E2_FORCEON; |
| 815 | WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp); |
| 816 | |
| 817 | tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL); |
| 818 | tmp |= AVIVO_IDCT_FORCEON; |
| 819 | WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp); |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | int radeon_static_clocks_init(struct drm_device *dev) |
| 824 | { |
| 825 | struct radeon_device *rdev = dev->dev_private; |
| 826 | |
| 827 | /* XXX make sure engine is idle */ |
| 828 | |
| 829 | if (radeon_dynclks != -1) { |
| 830 | if (radeon_dynclks) |
| 831 | radeon_set_clock_gating(rdev, 1); |
| 832 | } |
| 833 | radeon_apply_clock_quirks(rdev); |
| 834 | return 0; |
| 835 | } |