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Merge tag 'drm-intel-next-2012-06-04' of git://people.freedesktop.org/~danvet/drm...
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96extern int radeon_msi;
97extern int radeon_lockup_timeout;
98
99/*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
103#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105/* RADEON_IB_POOL_SIZE must be a power of 2 */
106#define RADEON_IB_POOL_SIZE 16
107#define RADEON_DEBUGFS_MAX_COMPONENTS 32
108#define RADEONFB_CONN_LIMIT 4
109#define RADEON_BIOS_NUM_SCRATCH 8
110
111/* max number of rings */
112#define RADEON_NUM_RINGS 3
113
114/* fence seq are set to this number when signaled */
115#define RADEON_FENCE_SIGNALED_SEQ 0LL
116#define RADEON_FENCE_NOTEMITED_SEQ (~0LL)
117
118/* internal ring indices */
119/* r1xx+ has gfx CP ring */
120#define RADEON_RING_TYPE_GFX_INDEX 0
121
122/* cayman has 2 compute CP rings */
123#define CAYMAN_RING_TYPE_CP1_INDEX 1
124#define CAYMAN_RING_TYPE_CP2_INDEX 2
125
126/* hardcode those limit for now */
127#define RADEON_VA_RESERVED_SIZE (8 << 20)
128#define RADEON_IB_VM_MAX_SIZE (64 << 10)
129
130/*
131 * Errata workarounds.
132 */
133enum radeon_pll_errata {
134 CHIP_ERRATA_R300_CG = 0x00000001,
135 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
136 CHIP_ERRATA_PLL_DELAY = 0x00000004
137};
138
139
140struct radeon_device;
141
142
143/*
144 * BIOS.
145 */
146#define ATRM_BIOS_PAGE 4096
147
148#if defined(CONFIG_VGA_SWITCHEROO)
149bool radeon_atrm_supported(struct pci_dev *pdev);
150int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
151#else
152static inline bool radeon_atrm_supported(struct pci_dev *pdev)
153{
154 return false;
155}
156
157static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
158 return -EINVAL;
159}
160#endif
161bool radeon_get_bios(struct radeon_device *rdev);
162
163
164/*
165 * Mutex which allows recursive locking from the same process.
166 */
167struct radeon_mutex {
168 struct mutex mutex;
169 struct task_struct *owner;
170 int level;
171};
172
173static inline void radeon_mutex_init(struct radeon_mutex *mutex)
174{
175 mutex_init(&mutex->mutex);
176 mutex->owner = NULL;
177 mutex->level = 0;
178}
179
180static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
181{
182 if (mutex_trylock(&mutex->mutex)) {
183 /* The mutex was unlocked before, so it's ours now */
184 mutex->owner = current;
185 } else if (mutex->owner != current) {
186 /* Another process locked the mutex, take it */
187 mutex_lock(&mutex->mutex);
188 mutex->owner = current;
189 }
190 /* Otherwise the mutex was already locked by this process */
191
192 mutex->level++;
193}
194
195static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
196{
197 if (--mutex->level > 0)
198 return;
199
200 mutex->owner = NULL;
201 mutex_unlock(&mutex->mutex);
202}
203
204
205/*
206 * Dummy page
207 */
208struct radeon_dummy_page {
209 struct page *page;
210 dma_addr_t addr;
211};
212int radeon_dummy_page_init(struct radeon_device *rdev);
213void radeon_dummy_page_fini(struct radeon_device *rdev);
214
215
216/*
217 * Clocks
218 */
219struct radeon_clock {
220 struct radeon_pll p1pll;
221 struct radeon_pll p2pll;
222 struct radeon_pll dcpll;
223 struct radeon_pll spll;
224 struct radeon_pll mpll;
225 /* 10 Khz units */
226 uint32_t default_mclk;
227 uint32_t default_sclk;
228 uint32_t default_dispclk;
229 uint32_t dp_extclk;
230 uint32_t max_pixel_clock;
231};
232
233/*
234 * Power management
235 */
236int radeon_pm_init(struct radeon_device *rdev);
237void radeon_pm_fini(struct radeon_device *rdev);
238void radeon_pm_compute_clocks(struct radeon_device *rdev);
239void radeon_pm_suspend(struct radeon_device *rdev);
240void radeon_pm_resume(struct radeon_device *rdev);
241void radeon_combios_get_power_modes(struct radeon_device *rdev);
242void radeon_atombios_get_power_modes(struct radeon_device *rdev);
243void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
244void rs690_pm_info(struct radeon_device *rdev);
245extern int rv6xx_get_temp(struct radeon_device *rdev);
246extern int rv770_get_temp(struct radeon_device *rdev);
247extern int evergreen_get_temp(struct radeon_device *rdev);
248extern int sumo_get_temp(struct radeon_device *rdev);
249extern int si_get_temp(struct radeon_device *rdev);
250extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
251 unsigned *bankh, unsigned *mtaspect,
252 unsigned *tile_split);
253
254/*
255 * Fences.
256 */
257struct radeon_fence_driver {
258 uint32_t scratch_reg;
259 uint64_t gpu_addr;
260 volatile uint32_t *cpu_addr;
261 /* seq is protected by ring emission lock */
262 uint64_t seq;
263 atomic64_t last_seq;
264 unsigned long last_activity;
265 bool initialized;
266};
267
268struct radeon_fence {
269 struct radeon_device *rdev;
270 struct kref kref;
271 /* protected by radeon_fence.lock */
272 uint64_t seq;
273 /* RB, DMA, etc. */
274 unsigned ring;
275};
276
277int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
278int radeon_fence_driver_init(struct radeon_device *rdev);
279void radeon_fence_driver_fini(struct radeon_device *rdev);
280int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
281int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
282void radeon_fence_process(struct radeon_device *rdev, int ring);
283bool radeon_fence_signaled(struct radeon_fence *fence);
284int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
285int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
286int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
287int radeon_fence_wait_any(struct radeon_device *rdev,
288 struct radeon_fence **fences,
289 bool intr);
290struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
291void radeon_fence_unref(struct radeon_fence **fence);
292unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
293
294/*
295 * Tiling registers
296 */
297struct radeon_surface_reg {
298 struct radeon_bo *bo;
299};
300
301#define RADEON_GEM_MAX_SURFACES 8
302
303/*
304 * TTM.
305 */
306struct radeon_mman {
307 struct ttm_bo_global_ref bo_global_ref;
308 struct drm_global_reference mem_global_ref;
309 struct ttm_bo_device bdev;
310 bool mem_global_referenced;
311 bool initialized;
312};
313
314/* bo virtual address in a specific vm */
315struct radeon_bo_va {
316 /* bo list is protected by bo being reserved */
317 struct list_head bo_list;
318 /* vm list is protected by vm mutex */
319 struct list_head vm_list;
320 /* constant after initialization */
321 struct radeon_vm *vm;
322 struct radeon_bo *bo;
323 uint64_t soffset;
324 uint64_t eoffset;
325 uint32_t flags;
326 bool valid;
327};
328
329struct radeon_bo {
330 /* Protected by gem.mutex */
331 struct list_head list;
332 /* Protected by tbo.reserved */
333 u32 placements[3];
334 struct ttm_placement placement;
335 struct ttm_buffer_object tbo;
336 struct ttm_bo_kmap_obj kmap;
337 unsigned pin_count;
338 void *kptr;
339 u32 tiling_flags;
340 u32 pitch;
341 int surface_reg;
342 /* list of all virtual address to which this bo
343 * is associated to
344 */
345 struct list_head va;
346 /* Constant after initialization */
347 struct radeon_device *rdev;
348 struct drm_gem_object gem_base;
349
350 struct ttm_bo_kmap_obj dma_buf_vmap;
351 int vmapping_count;
352};
353#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
354
355struct radeon_bo_list {
356 struct ttm_validate_buffer tv;
357 struct radeon_bo *bo;
358 uint64_t gpu_offset;
359 unsigned rdomain;
360 unsigned wdomain;
361 u32 tiling_flags;
362};
363
364/* sub-allocation manager, it has to be protected by another lock.
365 * By conception this is an helper for other part of the driver
366 * like the indirect buffer or semaphore, which both have their
367 * locking.
368 *
369 * Principe is simple, we keep a list of sub allocation in offset
370 * order (first entry has offset == 0, last entry has the highest
371 * offset).
372 *
373 * When allocating new object we first check if there is room at
374 * the end total_size - (last_object_offset + last_object_size) >=
375 * alloc_size. If so we allocate new object there.
376 *
377 * When there is not enough room at the end, we start waiting for
378 * each sub object until we reach object_offset+object_size >=
379 * alloc_size, this object then become the sub object we return.
380 *
381 * Alignment can't be bigger than page size.
382 *
383 * Hole are not considered for allocation to keep things simple.
384 * Assumption is that there won't be hole (all object on same
385 * alignment).
386 */
387struct radeon_sa_manager {
388 spinlock_t lock;
389 struct radeon_bo *bo;
390 struct list_head *hole;
391 struct list_head flist[RADEON_NUM_RINGS];
392 struct list_head olist;
393 unsigned size;
394 uint64_t gpu_addr;
395 void *cpu_ptr;
396 uint32_t domain;
397};
398
399struct radeon_sa_bo;
400
401/* sub-allocation buffer */
402struct radeon_sa_bo {
403 struct list_head olist;
404 struct list_head flist;
405 struct radeon_sa_manager *manager;
406 unsigned soffset;
407 unsigned eoffset;
408 struct radeon_fence *fence;
409};
410
411/*
412 * GEM objects.
413 */
414struct radeon_gem {
415 struct mutex mutex;
416 struct list_head objects;
417};
418
419int radeon_gem_init(struct radeon_device *rdev);
420void radeon_gem_fini(struct radeon_device *rdev);
421int radeon_gem_object_create(struct radeon_device *rdev, int size,
422 int alignment, int initial_domain,
423 bool discardable, bool kernel,
424 struct drm_gem_object **obj);
425
426int radeon_mode_dumb_create(struct drm_file *file_priv,
427 struct drm_device *dev,
428 struct drm_mode_create_dumb *args);
429int radeon_mode_dumb_mmap(struct drm_file *filp,
430 struct drm_device *dev,
431 uint32_t handle, uint64_t *offset_p);
432int radeon_mode_dumb_destroy(struct drm_file *file_priv,
433 struct drm_device *dev,
434 uint32_t handle);
435
436/*
437 * Semaphores.
438 */
439/* everything here is constant */
440struct radeon_semaphore {
441 struct radeon_sa_bo *sa_bo;
442 signed waiters;
443 uint64_t gpu_addr;
444};
445
446int radeon_semaphore_create(struct radeon_device *rdev,
447 struct radeon_semaphore **semaphore);
448void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
449 struct radeon_semaphore *semaphore);
450void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
451 struct radeon_semaphore *semaphore);
452int radeon_semaphore_sync_rings(struct radeon_device *rdev,
453 struct radeon_semaphore *semaphore,
454 bool sync_to[RADEON_NUM_RINGS],
455 int dst_ring);
456void radeon_semaphore_free(struct radeon_device *rdev,
457 struct radeon_semaphore *semaphore,
458 struct radeon_fence *fence);
459
460/*
461 * GART structures, functions & helpers
462 */
463struct radeon_mc;
464
465#define RADEON_GPU_PAGE_SIZE 4096
466#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
467#define RADEON_GPU_PAGE_SHIFT 12
468#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
469
470struct radeon_gart {
471 dma_addr_t table_addr;
472 struct radeon_bo *robj;
473 void *ptr;
474 unsigned num_gpu_pages;
475 unsigned num_cpu_pages;
476 unsigned table_size;
477 struct page **pages;
478 dma_addr_t *pages_addr;
479 bool ready;
480};
481
482int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
483void radeon_gart_table_ram_free(struct radeon_device *rdev);
484int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
485void radeon_gart_table_vram_free(struct radeon_device *rdev);
486int radeon_gart_table_vram_pin(struct radeon_device *rdev);
487void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
488int radeon_gart_init(struct radeon_device *rdev);
489void radeon_gart_fini(struct radeon_device *rdev);
490void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
491 int pages);
492int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
493 int pages, struct page **pagelist,
494 dma_addr_t *dma_addr);
495void radeon_gart_restore(struct radeon_device *rdev);
496
497
498/*
499 * GPU MC structures, functions & helpers
500 */
501struct radeon_mc {
502 resource_size_t aper_size;
503 resource_size_t aper_base;
504 resource_size_t agp_base;
505 /* for some chips with <= 32MB we need to lie
506 * about vram size near mc fb location */
507 u64 mc_vram_size;
508 u64 visible_vram_size;
509 u64 gtt_size;
510 u64 gtt_start;
511 u64 gtt_end;
512 u64 vram_start;
513 u64 vram_end;
514 unsigned vram_width;
515 u64 real_vram_size;
516 int vram_mtrr;
517 bool vram_is_ddr;
518 bool igp_sideport_enabled;
519 u64 gtt_base_align;
520};
521
522bool radeon_combios_sideport_present(struct radeon_device *rdev);
523bool radeon_atombios_sideport_present(struct radeon_device *rdev);
524
525/*
526 * GPU scratch registers structures, functions & helpers
527 */
528struct radeon_scratch {
529 unsigned num_reg;
530 uint32_t reg_base;
531 bool free[32];
532 uint32_t reg[32];
533};
534
535int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
536void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
537
538
539/*
540 * IRQS.
541 */
542
543struct radeon_unpin_work {
544 struct work_struct work;
545 struct radeon_device *rdev;
546 int crtc_id;
547 struct radeon_fence *fence;
548 struct drm_pending_vblank_event *event;
549 struct radeon_bo *old_rbo;
550 u64 new_crtc_base;
551};
552
553struct r500_irq_stat_regs {
554 u32 disp_int;
555 u32 hdmi0_status;
556};
557
558struct r600_irq_stat_regs {
559 u32 disp_int;
560 u32 disp_int_cont;
561 u32 disp_int_cont2;
562 u32 d1grph_int;
563 u32 d2grph_int;
564 u32 hdmi0_status;
565 u32 hdmi1_status;
566};
567
568struct evergreen_irq_stat_regs {
569 u32 disp_int;
570 u32 disp_int_cont;
571 u32 disp_int_cont2;
572 u32 disp_int_cont3;
573 u32 disp_int_cont4;
574 u32 disp_int_cont5;
575 u32 d1grph_int;
576 u32 d2grph_int;
577 u32 d3grph_int;
578 u32 d4grph_int;
579 u32 d5grph_int;
580 u32 d6grph_int;
581 u32 afmt_status1;
582 u32 afmt_status2;
583 u32 afmt_status3;
584 u32 afmt_status4;
585 u32 afmt_status5;
586 u32 afmt_status6;
587};
588
589union radeon_irq_stat_regs {
590 struct r500_irq_stat_regs r500;
591 struct r600_irq_stat_regs r600;
592 struct evergreen_irq_stat_regs evergreen;
593};
594
595#define RADEON_MAX_HPD_PINS 6
596#define RADEON_MAX_CRTCS 6
597#define RADEON_MAX_AFMT_BLOCKS 6
598
599struct radeon_irq {
600 bool installed;
601 bool sw_int[RADEON_NUM_RINGS];
602 bool crtc_vblank_int[RADEON_MAX_CRTCS];
603 bool pflip[RADEON_MAX_CRTCS];
604 wait_queue_head_t vblank_queue;
605 bool hpd[RADEON_MAX_HPD_PINS];
606 bool gui_idle;
607 bool gui_idle_acked;
608 wait_queue_head_t idle_queue;
609 bool afmt[RADEON_MAX_AFMT_BLOCKS];
610 spinlock_t sw_lock;
611 int sw_refcount[RADEON_NUM_RINGS];
612 union radeon_irq_stat_regs stat_regs;
613 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
614 int pflip_refcount[RADEON_MAX_CRTCS];
615};
616
617int radeon_irq_kms_init(struct radeon_device *rdev);
618void radeon_irq_kms_fini(struct radeon_device *rdev);
619void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
620void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
621void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
622void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
623
624/*
625 * CP & rings.
626 */
627
628struct radeon_ib {
629 struct radeon_sa_bo *sa_bo;
630 uint32_t length_dw;
631 uint64_t gpu_addr;
632 uint32_t *ptr;
633 struct radeon_fence *fence;
634 unsigned vm_id;
635 bool is_const_ib;
636 struct radeon_semaphore *semaphore;
637};
638
639struct radeon_ring {
640 struct radeon_bo *ring_obj;
641 volatile uint32_t *ring;
642 unsigned rptr;
643 unsigned rptr_offs;
644 unsigned rptr_reg;
645 unsigned wptr;
646 unsigned wptr_old;
647 unsigned wptr_reg;
648 unsigned ring_size;
649 unsigned ring_free_dw;
650 int count_dw;
651 unsigned long last_activity;
652 unsigned last_rptr;
653 uint64_t gpu_addr;
654 uint32_t align_mask;
655 uint32_t ptr_mask;
656 bool ready;
657 u32 ptr_reg_shift;
658 u32 ptr_reg_mask;
659 u32 nop;
660};
661
662/*
663 * VM
664 */
665struct radeon_vm {
666 struct list_head list;
667 struct list_head va;
668 int id;
669 unsigned last_pfn;
670 u64 pt_gpu_addr;
671 u64 *pt;
672 struct radeon_sa_bo *sa_bo;
673 struct mutex mutex;
674 /* last fence for cs using this vm */
675 struct radeon_fence *fence;
676};
677
678struct radeon_vm_funcs {
679 int (*init)(struct radeon_device *rdev);
680 void (*fini)(struct radeon_device *rdev);
681 /* cs mutex must be lock for schedule_ib */
682 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
683 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
684 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
685 uint32_t (*page_flags)(struct radeon_device *rdev,
686 struct radeon_vm *vm,
687 uint32_t flags);
688 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
689 unsigned pfn, uint64_t addr, uint32_t flags);
690};
691
692struct radeon_vm_manager {
693 struct list_head lru_vm;
694 uint32_t use_bitmap;
695 struct radeon_sa_manager sa_manager;
696 uint32_t max_pfn;
697 /* fields constant after init */
698 const struct radeon_vm_funcs *funcs;
699 /* number of VMIDs */
700 unsigned nvm;
701 /* vram base address for page table entry */
702 u64 vram_base_offset;
703 /* is vm enabled? */
704 bool enabled;
705};
706
707/*
708 * file private structure
709 */
710struct radeon_fpriv {
711 struct radeon_vm vm;
712};
713
714/*
715 * R6xx+ IH ring
716 */
717struct r600_ih {
718 struct radeon_bo *ring_obj;
719 volatile uint32_t *ring;
720 unsigned rptr;
721 unsigned rptr_offs;
722 unsigned wptr;
723 unsigned wptr_old;
724 unsigned ring_size;
725 uint64_t gpu_addr;
726 uint32_t ptr_mask;
727 spinlock_t lock;
728 bool enabled;
729};
730
731struct r600_blit_cp_primitives {
732 void (*set_render_target)(struct radeon_device *rdev, int format,
733 int w, int h, u64 gpu_addr);
734 void (*cp_set_surface_sync)(struct radeon_device *rdev,
735 u32 sync_type, u32 size,
736 u64 mc_addr);
737 void (*set_shaders)(struct radeon_device *rdev);
738 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
739 void (*set_tex_resource)(struct radeon_device *rdev,
740 int format, int w, int h, int pitch,
741 u64 gpu_addr, u32 size);
742 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
743 int x2, int y2);
744 void (*draw_auto)(struct radeon_device *rdev);
745 void (*set_default_state)(struct radeon_device *rdev);
746};
747
748struct r600_blit {
749 struct radeon_bo *shader_obj;
750 struct r600_blit_cp_primitives primitives;
751 int max_dim;
752 int ring_size_common;
753 int ring_size_per_loop;
754 u64 shader_gpu_addr;
755 u32 vs_offset, ps_offset;
756 u32 state_offset;
757 u32 state_len;
758};
759
760void r600_blit_suspend(struct radeon_device *rdev);
761
762/*
763 * SI RLC stuff
764 */
765struct si_rlc {
766 /* for power gating */
767 struct radeon_bo *save_restore_obj;
768 uint64_t save_restore_gpu_addr;
769 /* for clear state */
770 struct radeon_bo *clear_state_obj;
771 uint64_t clear_state_gpu_addr;
772};
773
774int radeon_ib_get(struct radeon_device *rdev, int ring,
775 struct radeon_ib *ib, unsigned size);
776void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
777int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
778int radeon_ib_pool_init(struct radeon_device *rdev);
779void radeon_ib_pool_fini(struct radeon_device *rdev);
780int radeon_ib_pool_start(struct radeon_device *rdev);
781int radeon_ib_pool_suspend(struct radeon_device *rdev);
782int radeon_ib_ring_tests(struct radeon_device *rdev);
783/* Ring access between begin & end cannot sleep */
784int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
785void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
786int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
787int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
788void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
789void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
790void radeon_ring_undo(struct radeon_ring *ring);
791void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
792int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
793void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
794void radeon_ring_lockup_update(struct radeon_ring *ring);
795bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
796int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
797 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
798 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
799void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
800
801
802/*
803 * CS.
804 */
805struct radeon_cs_reloc {
806 struct drm_gem_object *gobj;
807 struct radeon_bo *robj;
808 struct radeon_bo_list lobj;
809 uint32_t handle;
810 uint32_t flags;
811};
812
813struct radeon_cs_chunk {
814 uint32_t chunk_id;
815 uint32_t length_dw;
816 int kpage_idx[2];
817 uint32_t *kpage[2];
818 uint32_t *kdata;
819 void __user *user_ptr;
820 int last_copied_page;
821 int last_page_index;
822};
823
824struct radeon_cs_parser {
825 struct device *dev;
826 struct radeon_device *rdev;
827 struct drm_file *filp;
828 /* chunks */
829 unsigned nchunks;
830 struct radeon_cs_chunk *chunks;
831 uint64_t *chunks_array;
832 /* IB */
833 unsigned idx;
834 /* relocations */
835 unsigned nrelocs;
836 struct radeon_cs_reloc *relocs;
837 struct radeon_cs_reloc **relocs_ptr;
838 struct list_head validated;
839 /* indices of various chunks */
840 int chunk_ib_idx;
841 int chunk_relocs_idx;
842 int chunk_flags_idx;
843 int chunk_const_ib_idx;
844 struct radeon_ib ib;
845 struct radeon_ib const_ib;
846 void *track;
847 unsigned family;
848 int parser_error;
849 u32 cs_flags;
850 u32 ring;
851 s32 priority;
852};
853
854extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
855extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
856
857struct radeon_cs_packet {
858 unsigned idx;
859 unsigned type;
860 unsigned reg;
861 unsigned opcode;
862 int count;
863 unsigned one_reg_wr;
864};
865
866typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
867 struct radeon_cs_packet *pkt,
868 unsigned idx, unsigned reg);
869typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
870 struct radeon_cs_packet *pkt);
871
872
873/*
874 * AGP
875 */
876int radeon_agp_init(struct radeon_device *rdev);
877void radeon_agp_resume(struct radeon_device *rdev);
878void radeon_agp_suspend(struct radeon_device *rdev);
879void radeon_agp_fini(struct radeon_device *rdev);
880
881
882/*
883 * Writeback
884 */
885struct radeon_wb {
886 struct radeon_bo *wb_obj;
887 volatile uint32_t *wb;
888 uint64_t gpu_addr;
889 bool enabled;
890 bool use_event;
891};
892
893#define RADEON_WB_SCRATCH_OFFSET 0
894#define RADEON_WB_CP_RPTR_OFFSET 1024
895#define RADEON_WB_CP1_RPTR_OFFSET 1280
896#define RADEON_WB_CP2_RPTR_OFFSET 1536
897#define R600_WB_IH_WPTR_OFFSET 2048
898#define R600_WB_EVENT_OFFSET 3072
899
900/**
901 * struct radeon_pm - power management datas
902 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
903 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
904 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
905 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
906 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
907 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
908 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
909 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
910 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
911 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
912 * @needed_bandwidth: current bandwidth needs
913 *
914 * It keeps track of various data needed to take powermanagement decision.
915 * Bandwidth need is used to determine minimun clock of the GPU and memory.
916 * Equation between gpu/memory clock and available bandwidth is hw dependent
917 * (type of memory, bus size, efficiency, ...)
918 */
919
920enum radeon_pm_method {
921 PM_METHOD_PROFILE,
922 PM_METHOD_DYNPM,
923};
924
925enum radeon_dynpm_state {
926 DYNPM_STATE_DISABLED,
927 DYNPM_STATE_MINIMUM,
928 DYNPM_STATE_PAUSED,
929 DYNPM_STATE_ACTIVE,
930 DYNPM_STATE_SUSPENDED,
931};
932enum radeon_dynpm_action {
933 DYNPM_ACTION_NONE,
934 DYNPM_ACTION_MINIMUM,
935 DYNPM_ACTION_DOWNCLOCK,
936 DYNPM_ACTION_UPCLOCK,
937 DYNPM_ACTION_DEFAULT
938};
939
940enum radeon_voltage_type {
941 VOLTAGE_NONE = 0,
942 VOLTAGE_GPIO,
943 VOLTAGE_VDDC,
944 VOLTAGE_SW
945};
946
947enum radeon_pm_state_type {
948 POWER_STATE_TYPE_DEFAULT,
949 POWER_STATE_TYPE_POWERSAVE,
950 POWER_STATE_TYPE_BATTERY,
951 POWER_STATE_TYPE_BALANCED,
952 POWER_STATE_TYPE_PERFORMANCE,
953};
954
955enum radeon_pm_profile_type {
956 PM_PROFILE_DEFAULT,
957 PM_PROFILE_AUTO,
958 PM_PROFILE_LOW,
959 PM_PROFILE_MID,
960 PM_PROFILE_HIGH,
961};
962
963#define PM_PROFILE_DEFAULT_IDX 0
964#define PM_PROFILE_LOW_SH_IDX 1
965#define PM_PROFILE_MID_SH_IDX 2
966#define PM_PROFILE_HIGH_SH_IDX 3
967#define PM_PROFILE_LOW_MH_IDX 4
968#define PM_PROFILE_MID_MH_IDX 5
969#define PM_PROFILE_HIGH_MH_IDX 6
970#define PM_PROFILE_MAX 7
971
972struct radeon_pm_profile {
973 int dpms_off_ps_idx;
974 int dpms_on_ps_idx;
975 int dpms_off_cm_idx;
976 int dpms_on_cm_idx;
977};
978
979enum radeon_int_thermal_type {
980 THERMAL_TYPE_NONE,
981 THERMAL_TYPE_RV6XX,
982 THERMAL_TYPE_RV770,
983 THERMAL_TYPE_EVERGREEN,
984 THERMAL_TYPE_SUMO,
985 THERMAL_TYPE_NI,
986 THERMAL_TYPE_SI,
987};
988
989struct radeon_voltage {
990 enum radeon_voltage_type type;
991 /* gpio voltage */
992 struct radeon_gpio_rec gpio;
993 u32 delay; /* delay in usec from voltage drop to sclk change */
994 bool active_high; /* voltage drop is active when bit is high */
995 /* VDDC voltage */
996 u8 vddc_id; /* index into vddc voltage table */
997 u8 vddci_id; /* index into vddci voltage table */
998 bool vddci_enabled;
999 /* r6xx+ sw */
1000 u16 voltage;
1001 /* evergreen+ vddci */
1002 u16 vddci;
1003};
1004
1005/* clock mode flags */
1006#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1007
1008struct radeon_pm_clock_info {
1009 /* memory clock */
1010 u32 mclk;
1011 /* engine clock */
1012 u32 sclk;
1013 /* voltage info */
1014 struct radeon_voltage voltage;
1015 /* standardized clock flags */
1016 u32 flags;
1017};
1018
1019/* state flags */
1020#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1021
1022struct radeon_power_state {
1023 enum radeon_pm_state_type type;
1024 struct radeon_pm_clock_info *clock_info;
1025 /* number of valid clock modes in this power state */
1026 int num_clock_modes;
1027 struct radeon_pm_clock_info *default_clock_mode;
1028 /* standardized state flags */
1029 u32 flags;
1030 u32 misc; /* vbios specific flags */
1031 u32 misc2; /* vbios specific flags */
1032 int pcie_lanes; /* pcie lanes */
1033};
1034
1035/*
1036 * Some modes are overclocked by very low value, accept them
1037 */
1038#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1039
1040struct radeon_pm {
1041 struct mutex mutex;
1042 u32 active_crtcs;
1043 int active_crtc_count;
1044 int req_vblank;
1045 bool vblank_sync;
1046 bool gui_idle;
1047 fixed20_12 max_bandwidth;
1048 fixed20_12 igp_sideport_mclk;
1049 fixed20_12 igp_system_mclk;
1050 fixed20_12 igp_ht_link_clk;
1051 fixed20_12 igp_ht_link_width;
1052 fixed20_12 k8_bandwidth;
1053 fixed20_12 sideport_bandwidth;
1054 fixed20_12 ht_bandwidth;
1055 fixed20_12 core_bandwidth;
1056 fixed20_12 sclk;
1057 fixed20_12 mclk;
1058 fixed20_12 needed_bandwidth;
1059 struct radeon_power_state *power_state;
1060 /* number of valid power states */
1061 int num_power_states;
1062 int current_power_state_index;
1063 int current_clock_mode_index;
1064 int requested_power_state_index;
1065 int requested_clock_mode_index;
1066 int default_power_state_index;
1067 u32 current_sclk;
1068 u32 current_mclk;
1069 u16 current_vddc;
1070 u16 current_vddci;
1071 u32 default_sclk;
1072 u32 default_mclk;
1073 u16 default_vddc;
1074 u16 default_vddci;
1075 struct radeon_i2c_chan *i2c_bus;
1076 /* selected pm method */
1077 enum radeon_pm_method pm_method;
1078 /* dynpm power management */
1079 struct delayed_work dynpm_idle_work;
1080 enum radeon_dynpm_state dynpm_state;
1081 enum radeon_dynpm_action dynpm_planned_action;
1082 unsigned long dynpm_action_timeout;
1083 bool dynpm_can_upclock;
1084 bool dynpm_can_downclock;
1085 /* profile-based power management */
1086 enum radeon_pm_profile_type profile;
1087 int profile_index;
1088 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1089 /* internal thermal controller on rv6xx+ */
1090 enum radeon_int_thermal_type int_thermal_type;
1091 struct device *int_hwmon_dev;
1092};
1093
1094int radeon_pm_get_type_index(struct radeon_device *rdev,
1095 enum radeon_pm_state_type ps_type,
1096 int instance);
1097
1098struct r600_audio {
1099 int channels;
1100 int rate;
1101 int bits_per_sample;
1102 u8 status_bits;
1103 u8 category_code;
1104};
1105
1106/*
1107 * Benchmarking
1108 */
1109void radeon_benchmark(struct radeon_device *rdev, int test_number);
1110
1111
1112/*
1113 * Testing
1114 */
1115void radeon_test_moves(struct radeon_device *rdev);
1116void radeon_test_ring_sync(struct radeon_device *rdev,
1117 struct radeon_ring *cpA,
1118 struct radeon_ring *cpB);
1119void radeon_test_syncing(struct radeon_device *rdev);
1120
1121
1122/*
1123 * Debugfs
1124 */
1125struct radeon_debugfs {
1126 struct drm_info_list *files;
1127 unsigned num_files;
1128};
1129
1130int radeon_debugfs_add_files(struct radeon_device *rdev,
1131 struct drm_info_list *files,
1132 unsigned nfiles);
1133int radeon_debugfs_fence_init(struct radeon_device *rdev);
1134
1135
1136/*
1137 * ASIC specific functions.
1138 */
1139struct radeon_asic {
1140 int (*init)(struct radeon_device *rdev);
1141 void (*fini)(struct radeon_device *rdev);
1142 int (*resume)(struct radeon_device *rdev);
1143 int (*suspend)(struct radeon_device *rdev);
1144 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1145 int (*asic_reset)(struct radeon_device *rdev);
1146 /* ioctl hw specific callback. Some hw might want to perform special
1147 * operation on specific ioctl. For instance on wait idle some hw
1148 * might want to perform and HDP flush through MMIO as it seems that
1149 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1150 * through ring.
1151 */
1152 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1153 /* check if 3D engine is idle */
1154 bool (*gui_idle)(struct radeon_device *rdev);
1155 /* wait for mc_idle */
1156 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1157 /* gart */
1158 struct {
1159 void (*tlb_flush)(struct radeon_device *rdev);
1160 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1161 } gart;
1162 /* ring specific callbacks */
1163 struct {
1164 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1165 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1166 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1167 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1168 struct radeon_semaphore *semaphore, bool emit_wait);
1169 int (*cs_parse)(struct radeon_cs_parser *p);
1170 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1171 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1172 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1173 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1174 } ring[RADEON_NUM_RINGS];
1175 /* irqs */
1176 struct {
1177 int (*set)(struct radeon_device *rdev);
1178 int (*process)(struct radeon_device *rdev);
1179 } irq;
1180 /* displays */
1181 struct {
1182 /* display watermarks */
1183 void (*bandwidth_update)(struct radeon_device *rdev);
1184 /* get frame count */
1185 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1186 /* wait for vblank */
1187 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1188 } display;
1189 /* copy functions for bo handling */
1190 struct {
1191 int (*blit)(struct radeon_device *rdev,
1192 uint64_t src_offset,
1193 uint64_t dst_offset,
1194 unsigned num_gpu_pages,
1195 struct radeon_fence *fence);
1196 u32 blit_ring_index;
1197 int (*dma)(struct radeon_device *rdev,
1198 uint64_t src_offset,
1199 uint64_t dst_offset,
1200 unsigned num_gpu_pages,
1201 struct radeon_fence *fence);
1202 u32 dma_ring_index;
1203 /* method used for bo copy */
1204 int (*copy)(struct radeon_device *rdev,
1205 uint64_t src_offset,
1206 uint64_t dst_offset,
1207 unsigned num_gpu_pages,
1208 struct radeon_fence *fence);
1209 /* ring used for bo copies */
1210 u32 copy_ring_index;
1211 } copy;
1212 /* surfaces */
1213 struct {
1214 int (*set_reg)(struct radeon_device *rdev, int reg,
1215 uint32_t tiling_flags, uint32_t pitch,
1216 uint32_t offset, uint32_t obj_size);
1217 void (*clear_reg)(struct radeon_device *rdev, int reg);
1218 } surface;
1219 /* hotplug detect */
1220 struct {
1221 void (*init)(struct radeon_device *rdev);
1222 void (*fini)(struct radeon_device *rdev);
1223 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1224 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1225 } hpd;
1226 /* power management */
1227 struct {
1228 void (*misc)(struct radeon_device *rdev);
1229 void (*prepare)(struct radeon_device *rdev);
1230 void (*finish)(struct radeon_device *rdev);
1231 void (*init_profile)(struct radeon_device *rdev);
1232 void (*get_dynpm_state)(struct radeon_device *rdev);
1233 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1234 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1235 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1236 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1237 int (*get_pcie_lanes)(struct radeon_device *rdev);
1238 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1239 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1240 } pm;
1241 /* pageflipping */
1242 struct {
1243 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1244 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1245 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1246 } pflip;
1247};
1248
1249/*
1250 * Asic structures
1251 */
1252struct r100_asic {
1253 const unsigned *reg_safe_bm;
1254 unsigned reg_safe_bm_size;
1255 u32 hdp_cntl;
1256};
1257
1258struct r300_asic {
1259 const unsigned *reg_safe_bm;
1260 unsigned reg_safe_bm_size;
1261 u32 resync_scratch;
1262 u32 hdp_cntl;
1263};
1264
1265struct r600_asic {
1266 unsigned max_pipes;
1267 unsigned max_tile_pipes;
1268 unsigned max_simds;
1269 unsigned max_backends;
1270 unsigned max_gprs;
1271 unsigned max_threads;
1272 unsigned max_stack_entries;
1273 unsigned max_hw_contexts;
1274 unsigned max_gs_threads;
1275 unsigned sx_max_export_size;
1276 unsigned sx_max_export_pos_size;
1277 unsigned sx_max_export_smx_size;
1278 unsigned sq_num_cf_insts;
1279 unsigned tiling_nbanks;
1280 unsigned tiling_npipes;
1281 unsigned tiling_group_size;
1282 unsigned tile_config;
1283 unsigned backend_map;
1284};
1285
1286struct rv770_asic {
1287 unsigned max_pipes;
1288 unsigned max_tile_pipes;
1289 unsigned max_simds;
1290 unsigned max_backends;
1291 unsigned max_gprs;
1292 unsigned max_threads;
1293 unsigned max_stack_entries;
1294 unsigned max_hw_contexts;
1295 unsigned max_gs_threads;
1296 unsigned sx_max_export_size;
1297 unsigned sx_max_export_pos_size;
1298 unsigned sx_max_export_smx_size;
1299 unsigned sq_num_cf_insts;
1300 unsigned sx_num_of_sets;
1301 unsigned sc_prim_fifo_size;
1302 unsigned sc_hiz_tile_fifo_size;
1303 unsigned sc_earlyz_tile_fifo_fize;
1304 unsigned tiling_nbanks;
1305 unsigned tiling_npipes;
1306 unsigned tiling_group_size;
1307 unsigned tile_config;
1308 unsigned backend_map;
1309};
1310
1311struct evergreen_asic {
1312 unsigned num_ses;
1313 unsigned max_pipes;
1314 unsigned max_tile_pipes;
1315 unsigned max_simds;
1316 unsigned max_backends;
1317 unsigned max_gprs;
1318 unsigned max_threads;
1319 unsigned max_stack_entries;
1320 unsigned max_hw_contexts;
1321 unsigned max_gs_threads;
1322 unsigned sx_max_export_size;
1323 unsigned sx_max_export_pos_size;
1324 unsigned sx_max_export_smx_size;
1325 unsigned sq_num_cf_insts;
1326 unsigned sx_num_of_sets;
1327 unsigned sc_prim_fifo_size;
1328 unsigned sc_hiz_tile_fifo_size;
1329 unsigned sc_earlyz_tile_fifo_size;
1330 unsigned tiling_nbanks;
1331 unsigned tiling_npipes;
1332 unsigned tiling_group_size;
1333 unsigned tile_config;
1334 unsigned backend_map;
1335};
1336
1337struct cayman_asic {
1338 unsigned max_shader_engines;
1339 unsigned max_pipes_per_simd;
1340 unsigned max_tile_pipes;
1341 unsigned max_simds_per_se;
1342 unsigned max_backends_per_se;
1343 unsigned max_texture_channel_caches;
1344 unsigned max_gprs;
1345 unsigned max_threads;
1346 unsigned max_gs_threads;
1347 unsigned max_stack_entries;
1348 unsigned sx_num_of_sets;
1349 unsigned sx_max_export_size;
1350 unsigned sx_max_export_pos_size;
1351 unsigned sx_max_export_smx_size;
1352 unsigned max_hw_contexts;
1353 unsigned sq_num_cf_insts;
1354 unsigned sc_prim_fifo_size;
1355 unsigned sc_hiz_tile_fifo_size;
1356 unsigned sc_earlyz_tile_fifo_size;
1357
1358 unsigned num_shader_engines;
1359 unsigned num_shader_pipes_per_simd;
1360 unsigned num_tile_pipes;
1361 unsigned num_simds_per_se;
1362 unsigned num_backends_per_se;
1363 unsigned backend_disable_mask_per_asic;
1364 unsigned backend_map;
1365 unsigned num_texture_channel_caches;
1366 unsigned mem_max_burst_length_bytes;
1367 unsigned mem_row_size_in_kb;
1368 unsigned shader_engine_tile_size;
1369 unsigned num_gpus;
1370 unsigned multi_gpu_tile_size;
1371
1372 unsigned tile_config;
1373};
1374
1375struct si_asic {
1376 unsigned max_shader_engines;
1377 unsigned max_tile_pipes;
1378 unsigned max_cu_per_sh;
1379 unsigned max_sh_per_se;
1380 unsigned max_backends_per_se;
1381 unsigned max_texture_channel_caches;
1382 unsigned max_gprs;
1383 unsigned max_gs_threads;
1384 unsigned max_hw_contexts;
1385 unsigned sc_prim_fifo_size_frontend;
1386 unsigned sc_prim_fifo_size_backend;
1387 unsigned sc_hiz_tile_fifo_size;
1388 unsigned sc_earlyz_tile_fifo_size;
1389
1390 unsigned num_tile_pipes;
1391 unsigned num_backends_per_se;
1392 unsigned backend_disable_mask_per_asic;
1393 unsigned backend_map;
1394 unsigned num_texture_channel_caches;
1395 unsigned mem_max_burst_length_bytes;
1396 unsigned mem_row_size_in_kb;
1397 unsigned shader_engine_tile_size;
1398 unsigned num_gpus;
1399 unsigned multi_gpu_tile_size;
1400
1401 unsigned tile_config;
1402};
1403
1404union radeon_asic_config {
1405 struct r300_asic r300;
1406 struct r100_asic r100;
1407 struct r600_asic r600;
1408 struct rv770_asic rv770;
1409 struct evergreen_asic evergreen;
1410 struct cayman_asic cayman;
1411 struct si_asic si;
1412};
1413
1414/*
1415 * asic initizalization from radeon_asic.c
1416 */
1417void radeon_agp_disable(struct radeon_device *rdev);
1418int radeon_asic_init(struct radeon_device *rdev);
1419
1420
1421/*
1422 * IOCTL.
1423 */
1424int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1425 struct drm_file *filp);
1426int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1427 struct drm_file *filp);
1428int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1429 struct drm_file *file_priv);
1430int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1431 struct drm_file *file_priv);
1432int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1433 struct drm_file *file_priv);
1434int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1435 struct drm_file *file_priv);
1436int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1437 struct drm_file *filp);
1438int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1439 struct drm_file *filp);
1440int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1441 struct drm_file *filp);
1442int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1443 struct drm_file *filp);
1444int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1445 struct drm_file *filp);
1446int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1447int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *filp);
1449int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *filp);
1451
1452/* VRAM scratch page for HDP bug, default vram page */
1453struct r600_vram_scratch {
1454 struct radeon_bo *robj;
1455 volatile uint32_t *ptr;
1456 u64 gpu_addr;
1457};
1458
1459
1460/*
1461 * Core structure, functions and helpers.
1462 */
1463typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1464typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1465
1466struct radeon_device {
1467 struct device *dev;
1468 struct drm_device *ddev;
1469 struct pci_dev *pdev;
1470 /* ASIC */
1471 union radeon_asic_config config;
1472 enum radeon_family family;
1473 unsigned long flags;
1474 int usec_timeout;
1475 enum radeon_pll_errata pll_errata;
1476 int num_gb_pipes;
1477 int num_z_pipes;
1478 int disp_priority;
1479 /* BIOS */
1480 uint8_t *bios;
1481 bool is_atom_bios;
1482 uint16_t bios_header_start;
1483 struct radeon_bo *stollen_vga_memory;
1484 /* Register mmio */
1485 resource_size_t rmmio_base;
1486 resource_size_t rmmio_size;
1487 void __iomem *rmmio;
1488 radeon_rreg_t mc_rreg;
1489 radeon_wreg_t mc_wreg;
1490 radeon_rreg_t pll_rreg;
1491 radeon_wreg_t pll_wreg;
1492 uint32_t pcie_reg_mask;
1493 radeon_rreg_t pciep_rreg;
1494 radeon_wreg_t pciep_wreg;
1495 /* io port */
1496 void __iomem *rio_mem;
1497 resource_size_t rio_mem_size;
1498 struct radeon_clock clock;
1499 struct radeon_mc mc;
1500 struct radeon_gart gart;
1501 struct radeon_mode_info mode_info;
1502 struct radeon_scratch scratch;
1503 struct radeon_mman mman;
1504 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1505 wait_queue_head_t fence_queue;
1506 struct mutex ring_lock;
1507 struct radeon_ring ring[RADEON_NUM_RINGS];
1508 bool ib_pool_ready;
1509 struct radeon_sa_manager ring_tmp_bo;
1510 struct radeon_irq irq;
1511 struct radeon_asic *asic;
1512 struct radeon_gem gem;
1513 struct radeon_pm pm;
1514 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1515 struct radeon_mutex cs_mutex;
1516 struct radeon_wb wb;
1517 struct radeon_dummy_page dummy_page;
1518 bool shutdown;
1519 bool suspend;
1520 bool need_dma32;
1521 bool accel_working;
1522 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1523 const struct firmware *me_fw; /* all family ME firmware */
1524 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1525 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1526 const struct firmware *mc_fw; /* NI MC firmware */
1527 const struct firmware *ce_fw; /* SI CE firmware */
1528 struct r600_blit r600_blit;
1529 struct r600_vram_scratch vram_scratch;
1530 int msi_enabled; /* msi enabled */
1531 struct r600_ih ih; /* r6/700 interrupt ring */
1532 struct si_rlc rlc;
1533 struct work_struct hotplug_work;
1534 struct work_struct audio_work;
1535 int num_crtc; /* number of crtcs */
1536 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1537 struct mutex vram_mutex;
1538 bool audio_enabled;
1539 struct r600_audio audio_status; /* audio stuff */
1540 struct notifier_block acpi_nb;
1541 /* only one userspace can use Hyperz features or CMASK at a time */
1542 struct drm_file *hyperz_filp;
1543 struct drm_file *cmask_filp;
1544 /* i2c buses */
1545 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1546 /* debugfs */
1547 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1548 unsigned debugfs_count;
1549 /* virtual memory */
1550 struct radeon_vm_manager vm_manager;
1551};
1552
1553int radeon_device_init(struct radeon_device *rdev,
1554 struct drm_device *ddev,
1555 struct pci_dev *pdev,
1556 uint32_t flags);
1557void radeon_device_fini(struct radeon_device *rdev);
1558int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1559
1560uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1561void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1562u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1563void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1564
1565/*
1566 * Cast helper
1567 */
1568#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1569
1570/*
1571 * Registers read & write functions.
1572 */
1573#define RREG8(reg) readb((rdev->rmmio) + (reg))
1574#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1575#define RREG16(reg) readw((rdev->rmmio) + (reg))
1576#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1577#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1578#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1579#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1580#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1581#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1582#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1583#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1584#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1585#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1586#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1587#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1588#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1589#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1590#define WREG32_P(reg, val, mask) \
1591 do { \
1592 uint32_t tmp_ = RREG32(reg); \
1593 tmp_ &= (mask); \
1594 tmp_ |= ((val) & ~(mask)); \
1595 WREG32(reg, tmp_); \
1596 } while (0)
1597#define WREG32_PLL_P(reg, val, mask) \
1598 do { \
1599 uint32_t tmp_ = RREG32_PLL(reg); \
1600 tmp_ &= (mask); \
1601 tmp_ |= ((val) & ~(mask)); \
1602 WREG32_PLL(reg, tmp_); \
1603 } while (0)
1604#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1605#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1606#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1607
1608/*
1609 * Indirect registers accessor
1610 */
1611static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1612{
1613 uint32_t r;
1614
1615 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1616 r = RREG32(RADEON_PCIE_DATA);
1617 return r;
1618}
1619
1620static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1621{
1622 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1623 WREG32(RADEON_PCIE_DATA, (v));
1624}
1625
1626void r100_pll_errata_after_index(struct radeon_device *rdev);
1627
1628
1629/*
1630 * ASICs helpers.
1631 */
1632#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1633 (rdev->pdev->device == 0x5969))
1634#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1635 (rdev->family == CHIP_RV200) || \
1636 (rdev->family == CHIP_RS100) || \
1637 (rdev->family == CHIP_RS200) || \
1638 (rdev->family == CHIP_RV250) || \
1639 (rdev->family == CHIP_RV280) || \
1640 (rdev->family == CHIP_RS300))
1641#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1642 (rdev->family == CHIP_RV350) || \
1643 (rdev->family == CHIP_R350) || \
1644 (rdev->family == CHIP_RV380) || \
1645 (rdev->family == CHIP_R420) || \
1646 (rdev->family == CHIP_R423) || \
1647 (rdev->family == CHIP_RV410) || \
1648 (rdev->family == CHIP_RS400) || \
1649 (rdev->family == CHIP_RS480))
1650#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1651 (rdev->ddev->pdev->device == 0x9443) || \
1652 (rdev->ddev->pdev->device == 0x944B) || \
1653 (rdev->ddev->pdev->device == 0x9506) || \
1654 (rdev->ddev->pdev->device == 0x9509) || \
1655 (rdev->ddev->pdev->device == 0x950F) || \
1656 (rdev->ddev->pdev->device == 0x689C) || \
1657 (rdev->ddev->pdev->device == 0x689D))
1658#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1659#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1660 (rdev->family == CHIP_RS690) || \
1661 (rdev->family == CHIP_RS740) || \
1662 (rdev->family >= CHIP_R600))
1663#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1664#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1665#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1666#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1667 (rdev->flags & RADEON_IS_IGP))
1668#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1669#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1670#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1671 (rdev->flags & RADEON_IS_IGP))
1672
1673/*
1674 * BIOS helpers.
1675 */
1676#define RBIOS8(i) (rdev->bios[i])
1677#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1678#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1679
1680int radeon_combios_init(struct radeon_device *rdev);
1681void radeon_combios_fini(struct radeon_device *rdev);
1682int radeon_atombios_init(struct radeon_device *rdev);
1683void radeon_atombios_fini(struct radeon_device *rdev);
1684
1685
1686/*
1687 * RING helpers.
1688 */
1689#if DRM_DEBUG_CODE == 0
1690static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1691{
1692 ring->ring[ring->wptr++] = v;
1693 ring->wptr &= ring->ptr_mask;
1694 ring->count_dw--;
1695 ring->ring_free_dw--;
1696}
1697#else
1698/* With debugging this is just too big to inline */
1699void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1700#endif
1701
1702/*
1703 * ASICs macro.
1704 */
1705#define radeon_init(rdev) (rdev)->asic->init((rdev))
1706#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1707#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1708#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1709#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1710#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1711#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1712#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1713#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1714#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1715#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1716#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1717#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1718#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1719#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1720#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1721#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1722#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1723#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1724#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1725#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1726#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1727#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1728#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1729#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1730#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1731#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1732#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1733#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1734#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1735#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1736#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1737#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1738#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1739#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1740#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1741#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1742#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1743#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1744#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1745#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1746#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1747#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1748#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1749#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1750#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1751#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1752#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1753#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1754#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1755#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1756
1757/* Common functions */
1758/* AGP */
1759extern int radeon_gpu_reset(struct radeon_device *rdev);
1760extern void radeon_agp_disable(struct radeon_device *rdev);
1761extern int radeon_modeset_init(struct radeon_device *rdev);
1762extern void radeon_modeset_fini(struct radeon_device *rdev);
1763extern bool radeon_card_posted(struct radeon_device *rdev);
1764extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1765extern void radeon_update_display_priority(struct radeon_device *rdev);
1766extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1767extern void radeon_scratch_init(struct radeon_device *rdev);
1768extern void radeon_wb_fini(struct radeon_device *rdev);
1769extern int radeon_wb_init(struct radeon_device *rdev);
1770extern void radeon_wb_disable(struct radeon_device *rdev);
1771extern void radeon_surface_init(struct radeon_device *rdev);
1772extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1773extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1774extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1775extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1776extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1777extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1778extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1779extern int radeon_resume_kms(struct drm_device *dev);
1780extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1781extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1782
1783/*
1784 * vm
1785 */
1786int radeon_vm_manager_init(struct radeon_device *rdev);
1787void radeon_vm_manager_fini(struct radeon_device *rdev);
1788int radeon_vm_manager_start(struct radeon_device *rdev);
1789int radeon_vm_manager_suspend(struct radeon_device *rdev);
1790int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1791void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1792int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1793void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1794int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1795 struct radeon_vm *vm,
1796 struct radeon_bo *bo,
1797 struct ttm_mem_reg *mem);
1798void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1799 struct radeon_bo *bo);
1800int radeon_vm_bo_add(struct radeon_device *rdev,
1801 struct radeon_vm *vm,
1802 struct radeon_bo *bo,
1803 uint64_t offset,
1804 uint32_t flags);
1805int radeon_vm_bo_rmv(struct radeon_device *rdev,
1806 struct radeon_vm *vm,
1807 struct radeon_bo *bo);
1808
1809/* audio */
1810void r600_audio_update_hdmi(struct work_struct *work);
1811
1812/*
1813 * R600 vram scratch functions
1814 */
1815int r600_vram_scratch_init(struct radeon_device *rdev);
1816void r600_vram_scratch_fini(struct radeon_device *rdev);
1817
1818/*
1819 * r600 cs checking helper
1820 */
1821unsigned r600_mip_minify(unsigned size, unsigned level);
1822bool r600_fmt_is_valid_color(u32 format);
1823bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1824int r600_fmt_get_blocksize(u32 format);
1825int r600_fmt_get_nblocksx(u32 format, u32 w);
1826int r600_fmt_get_nblocksy(u32 format, u32 h);
1827
1828/*
1829 * r600 functions used by radeon_encoder.c
1830 */
1831struct radeon_hdmi_acr {
1832 u32 clock;
1833
1834 int n_32khz;
1835 int cts_32khz;
1836
1837 int n_44_1khz;
1838 int cts_44_1khz;
1839
1840 int n_48khz;
1841 int cts_48khz;
1842
1843};
1844
1845extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1846
1847extern void r600_hdmi_enable(struct drm_encoder *encoder);
1848extern void r600_hdmi_disable(struct drm_encoder *encoder);
1849extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1850extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1851 u32 tiling_pipe_num,
1852 u32 max_rb_num,
1853 u32 total_max_rb_num,
1854 u32 enabled_rb_mask);
1855
1856/*
1857 * evergreen functions used by radeon_encoder.c
1858 */
1859
1860extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1861
1862extern int ni_init_microcode(struct radeon_device *rdev);
1863extern int ni_mc_load_microcode(struct radeon_device *rdev);
1864
1865/* radeon_acpi.c */
1866#if defined(CONFIG_ACPI)
1867extern int radeon_acpi_init(struct radeon_device *rdev);
1868#else
1869static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1870#endif
1871
1872#include "radeon_object.h"
1873
1874#endif
Linux 6.x block layer and io_uring tree(s)