| 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "nouveau_drm.h" |
| 26 | #include "nouveau_dma.h" |
| 27 | #include "nouveau_fence.h" |
| 28 | |
| 29 | #include "nv50_display.h" |
| 30 | |
| 31 | u64 |
| 32 | nv84_fence_crtc(struct nouveau_channel *chan, int crtc) |
| 33 | { |
| 34 | struct nv84_fence_chan *fctx = chan->fence; |
| 35 | return fctx->dispc_vma[crtc].offset; |
| 36 | } |
| 37 | |
| 38 | static int |
| 39 | nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) |
| 40 | { |
| 41 | int ret = RING_SPACE(chan, 8); |
| 42 | if (ret == 0) { |
| 43 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); |
| 44 | OUT_RING (chan, chan->vram.handle); |
| 45 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); |
| 46 | OUT_RING (chan, upper_32_bits(virtual)); |
| 47 | OUT_RING (chan, lower_32_bits(virtual)); |
| 48 | OUT_RING (chan, sequence); |
| 49 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); |
| 50 | OUT_RING (chan, 0x00000000); |
| 51 | FIRE_RING (chan); |
| 52 | } |
| 53 | return ret; |
| 54 | } |
| 55 | |
| 56 | static int |
| 57 | nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) |
| 58 | { |
| 59 | int ret = RING_SPACE(chan, 7); |
| 60 | if (ret == 0) { |
| 61 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); |
| 62 | OUT_RING (chan, chan->vram.handle); |
| 63 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
| 64 | OUT_RING (chan, upper_32_bits(virtual)); |
| 65 | OUT_RING (chan, lower_32_bits(virtual)); |
| 66 | OUT_RING (chan, sequence); |
| 67 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); |
| 68 | FIRE_RING (chan); |
| 69 | } |
| 70 | return ret; |
| 71 | } |
| 72 | |
| 73 | static int |
| 74 | nv84_fence_emit(struct nouveau_fence *fence) |
| 75 | { |
| 76 | struct nouveau_channel *chan = fence->channel; |
| 77 | struct nv84_fence_chan *fctx = chan->fence; |
| 78 | u64 addr = chan->chid * 16; |
| 79 | |
| 80 | if (fence->sysmem) |
| 81 | addr += fctx->vma_gart.offset; |
| 82 | else |
| 83 | addr += fctx->vma.offset; |
| 84 | |
| 85 | return fctx->base.emit32(chan, addr, fence->base.seqno); |
| 86 | } |
| 87 | |
| 88 | static int |
| 89 | nv84_fence_sync(struct nouveau_fence *fence, |
| 90 | struct nouveau_channel *prev, struct nouveau_channel *chan) |
| 91 | { |
| 92 | struct nv84_fence_chan *fctx = chan->fence; |
| 93 | u64 addr = prev->chid * 16; |
| 94 | |
| 95 | if (fence->sysmem) |
| 96 | addr += fctx->vma_gart.offset; |
| 97 | else |
| 98 | addr += fctx->vma.offset; |
| 99 | |
| 100 | return fctx->base.sync32(chan, addr, fence->base.seqno); |
| 101 | } |
| 102 | |
| 103 | static u32 |
| 104 | nv84_fence_read(struct nouveau_channel *chan) |
| 105 | { |
| 106 | struct nv84_fence_priv *priv = chan->drm->fence; |
| 107 | return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); |
| 108 | } |
| 109 | |
| 110 | static void |
| 111 | nv84_fence_context_del(struct nouveau_channel *chan) |
| 112 | { |
| 113 | struct drm_device *dev = chan->drm->dev; |
| 114 | struct nv84_fence_priv *priv = chan->drm->fence; |
| 115 | struct nv84_fence_chan *fctx = chan->fence; |
| 116 | int i; |
| 117 | |
| 118 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
| 119 | struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); |
| 120 | nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); |
| 121 | } |
| 122 | |
| 123 | nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); |
| 124 | nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); |
| 125 | nouveau_bo_vma_del(priv->bo, &fctx->vma); |
| 126 | nouveau_fence_context_del(&fctx->base); |
| 127 | chan->fence = NULL; |
| 128 | nouveau_fence_context_free(&fctx->base); |
| 129 | } |
| 130 | |
| 131 | int |
| 132 | nv84_fence_context_new(struct nouveau_channel *chan) |
| 133 | { |
| 134 | struct nouveau_cli *cli = (void *)chan->user.client; |
| 135 | struct nv84_fence_priv *priv = chan->drm->fence; |
| 136 | struct nv84_fence_chan *fctx; |
| 137 | int ret, i; |
| 138 | |
| 139 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); |
| 140 | if (!fctx) |
| 141 | return -ENOMEM; |
| 142 | |
| 143 | nouveau_fence_context_new(chan, &fctx->base); |
| 144 | fctx->base.emit = nv84_fence_emit; |
| 145 | fctx->base.sync = nv84_fence_sync; |
| 146 | fctx->base.read = nv84_fence_read; |
| 147 | fctx->base.emit32 = nv84_fence_emit32; |
| 148 | fctx->base.sync32 = nv84_fence_sync32; |
| 149 | fctx->base.sequence = nv84_fence_read(chan); |
| 150 | |
| 151 | ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma); |
| 152 | if (ret == 0) { |
| 153 | ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm, |
| 154 | &fctx->vma_gart); |
| 155 | } |
| 156 | |
| 157 | /* map display semaphore buffers into channel's vm */ |
| 158 | for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { |
| 159 | struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i); |
| 160 | ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]); |
| 161 | } |
| 162 | |
| 163 | if (ret) |
| 164 | nv84_fence_context_del(chan); |
| 165 | return ret; |
| 166 | } |
| 167 | |
| 168 | static bool |
| 169 | nv84_fence_suspend(struct nouveau_drm *drm) |
| 170 | { |
| 171 | struct nv84_fence_priv *priv = drm->fence; |
| 172 | int i; |
| 173 | |
| 174 | priv->suspend = vmalloc(priv->base.contexts * sizeof(u32)); |
| 175 | if (priv->suspend) { |
| 176 | for (i = 0; i < priv->base.contexts; i++) |
| 177 | priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4); |
| 178 | } |
| 179 | |
| 180 | return priv->suspend != NULL; |
| 181 | } |
| 182 | |
| 183 | static void |
| 184 | nv84_fence_resume(struct nouveau_drm *drm) |
| 185 | { |
| 186 | struct nv84_fence_priv *priv = drm->fence; |
| 187 | int i; |
| 188 | |
| 189 | if (priv->suspend) { |
| 190 | for (i = 0; i < priv->base.contexts; i++) |
| 191 | nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]); |
| 192 | vfree(priv->suspend); |
| 193 | priv->suspend = NULL; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | static void |
| 198 | nv84_fence_destroy(struct nouveau_drm *drm) |
| 199 | { |
| 200 | struct nv84_fence_priv *priv = drm->fence; |
| 201 | nouveau_bo_unmap(priv->bo_gart); |
| 202 | if (priv->bo_gart) |
| 203 | nouveau_bo_unpin(priv->bo_gart); |
| 204 | nouveau_bo_ref(NULL, &priv->bo_gart); |
| 205 | nouveau_bo_unmap(priv->bo); |
| 206 | if (priv->bo) |
| 207 | nouveau_bo_unpin(priv->bo); |
| 208 | nouveau_bo_ref(NULL, &priv->bo); |
| 209 | drm->fence = NULL; |
| 210 | kfree(priv); |
| 211 | } |
| 212 | |
| 213 | int |
| 214 | nv84_fence_create(struct nouveau_drm *drm) |
| 215 | { |
| 216 | struct nvkm_fifo *fifo = nvxx_fifo(&drm->device); |
| 217 | struct nv84_fence_priv *priv; |
| 218 | u32 domain; |
| 219 | int ret; |
| 220 | |
| 221 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 222 | if (!priv) |
| 223 | return -ENOMEM; |
| 224 | |
| 225 | priv->base.dtor = nv84_fence_destroy; |
| 226 | priv->base.suspend = nv84_fence_suspend; |
| 227 | priv->base.resume = nv84_fence_resume; |
| 228 | priv->base.context_new = nv84_fence_context_new; |
| 229 | priv->base.context_del = nv84_fence_context_del; |
| 230 | |
| 231 | priv->base.contexts = fifo->max + 1; |
| 232 | priv->base.context_base = fence_context_alloc(priv->base.contexts); |
| 233 | priv->base.uevent = true; |
| 234 | |
| 235 | /* Use VRAM if there is any ; otherwise fallback to system memory */ |
| 236 | domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : |
| 237 | /* |
| 238 | * fences created in sysmem must be non-cached or we |
| 239 | * will lose CPU/GPU coherency! |
| 240 | */ |
| 241 | TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; |
| 242 | ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0, |
| 243 | 0, NULL, NULL, &priv->bo); |
| 244 | if (ret == 0) { |
| 245 | ret = nouveau_bo_pin(priv->bo, domain, false); |
| 246 | if (ret == 0) { |
| 247 | ret = nouveau_bo_map(priv->bo); |
| 248 | if (ret) |
| 249 | nouveau_bo_unpin(priv->bo); |
| 250 | } |
| 251 | if (ret) |
| 252 | nouveau_bo_ref(NULL, &priv->bo); |
| 253 | } |
| 254 | |
| 255 | if (ret == 0) |
| 256 | ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, |
| 257 | TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0, |
| 258 | 0, NULL, NULL, &priv->bo_gart); |
| 259 | if (ret == 0) { |
| 260 | ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT, false); |
| 261 | if (ret == 0) { |
| 262 | ret = nouveau_bo_map(priv->bo_gart); |
| 263 | if (ret) |
| 264 | nouveau_bo_unpin(priv->bo_gart); |
| 265 | } |
| 266 | if (ret) |
| 267 | nouveau_bo_ref(NULL, &priv->bo_gart); |
| 268 | } |
| 269 | |
| 270 | if (ret) |
| 271 | nv84_fence_destroy(drm); |
| 272 | return ret; |
| 273 | } |