| | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| | 2 | */ |
| | 3 | /* |
| | 4 | * |
| | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| | 6 | * All Rights Reserved. |
| | 7 | * |
| | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| | 9 | * copy of this software and associated documentation files (the |
| | 10 | * "Software"), to deal in the Software without restriction, including |
| | 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| | 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| | 13 | * permit persons to whom the Software is furnished to do so, subject to |
| | 14 | * the following conditions: |
| | 15 | * |
| | 16 | * The above copyright notice and this permission notice (including the |
| | 17 | * next paragraph) shall be included in all copies or substantial portions |
| | 18 | * of the Software. |
| | 19 | * |
| | 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| | 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| | 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| | 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| | 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| | 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| | 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| | 27 | * |
| | 28 | */ |
| | 29 | |
| | 30 | #ifndef _I915_DRV_H_ |
| | 31 | #define _I915_DRV_H_ |
| | 32 | |
| | 33 | #include <uapi/drm/i915_drm.h> |
| | 34 | |
| | 35 | #include <linux/pm_qos.h> |
| | 36 | |
| | 37 | #include <drm/ttm/ttm_device.h> |
| | 38 | |
| | 39 | #include "display/intel_display_limits.h" |
| | 40 | #include "display/intel_display_core.h" |
| | 41 | |
| | 42 | #include "gem/i915_gem_context_types.h" |
| | 43 | #include "gem/i915_gem_shrinker.h" |
| | 44 | #include "gem/i915_gem_stolen.h" |
| | 45 | |
| | 46 | #include "gt/intel_engine.h" |
| | 47 | #include "gt/intel_gt_types.h" |
| | 48 | #include "gt/intel_region_lmem.h" |
| | 49 | #include "gt/intel_workarounds.h" |
| | 50 | #include "gt/uc/intel_uc.h" |
| | 51 | |
| | 52 | #include "i915_drm_client.h" |
| | 53 | #include "i915_gem.h" |
| | 54 | #include "i915_gpu_error.h" |
| | 55 | #include "i915_params.h" |
| | 56 | #include "i915_perf_types.h" |
| | 57 | #include "i915_scheduler.h" |
| | 58 | #include "i915_utils.h" |
| | 59 | #include "intel_device_info.h" |
| | 60 | #include "intel_memory_region.h" |
| | 61 | #include "intel_runtime_pm.h" |
| | 62 | #include "intel_step.h" |
| | 63 | #include "intel_uncore.h" |
| | 64 | |
| | 65 | struct drm_i915_clock_gating_funcs; |
| | 66 | struct vlv_s0ix_state; |
| | 67 | struct intel_pxp; |
| | 68 | |
| | 69 | #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) |
| | 70 | |
| | 71 | /* Data Stolen Memory (DSM) aka "i915 stolen memory" */ |
| | 72 | struct i915_dsm { |
| | 73 | /* |
| | 74 | * The start and end of DSM which we can optionally use to create GEM |
| | 75 | * objects backed by stolen memory. |
| | 76 | * |
| | 77 | * Note that usable_size tells us exactly how much of this we are |
| | 78 | * actually allowed to use, given that some portion of it is in fact |
| | 79 | * reserved for use by hardware functions. |
| | 80 | */ |
| | 81 | struct resource stolen; |
| | 82 | |
| | 83 | /* |
| | 84 | * Reserved portion of DSM. |
| | 85 | */ |
| | 86 | struct resource reserved; |
| | 87 | |
| | 88 | /* |
| | 89 | * Total size minus reserved ranges. |
| | 90 | * |
| | 91 | * DSM is segmented in hardware with different portions offlimits to |
| | 92 | * certain functions. |
| | 93 | * |
| | 94 | * The drm_mm is initialised to the total accessible range, as found |
| | 95 | * from the PCI config. On Broadwell+, this is further restricted to |
| | 96 | * avoid the first page! The upper end of DSM is reserved for hardware |
| | 97 | * functions and similarly removed from the accessible range. |
| | 98 | */ |
| | 99 | resource_size_t usable_size; |
| | 100 | }; |
| | 101 | |
| | 102 | #define MAX_L3_SLICES 2 |
| | 103 | struct intel_l3_parity { |
| | 104 | u32 *remap_info[MAX_L3_SLICES]; |
| | 105 | struct work_struct error_work; |
| | 106 | int which_slice; |
| | 107 | }; |
| | 108 | |
| | 109 | struct i915_gem_mm { |
| | 110 | /* |
| | 111 | * Shortcut for the stolen region. This points to either |
| | 112 | * INTEL_REGION_STOLEN_SMEM for integrated platforms, or |
| | 113 | * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't |
| | 114 | * support stolen. |
| | 115 | */ |
| | 116 | struct intel_memory_region *stolen_region; |
| | 117 | /** Memory allocator for GTT stolen memory */ |
| | 118 | struct drm_mm stolen; |
| | 119 | /** Protects the usage of the GTT stolen memory allocator. This is |
| | 120 | * always the inner lock when overlapping with struct_mutex. */ |
| | 121 | struct mutex stolen_lock; |
| | 122 | |
| | 123 | /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ |
| | 124 | spinlock_t obj_lock; |
| | 125 | |
| | 126 | /** |
| | 127 | * List of objects which are purgeable. |
| | 128 | */ |
| | 129 | struct list_head purge_list; |
| | 130 | |
| | 131 | /** |
| | 132 | * List of objects which have allocated pages and are shrinkable. |
| | 133 | */ |
| | 134 | struct list_head shrink_list; |
| | 135 | |
| | 136 | /** |
| | 137 | * List of objects which are pending destruction. |
| | 138 | */ |
| | 139 | struct llist_head free_list; |
| | 140 | struct work_struct free_work; |
| | 141 | /** |
| | 142 | * Count of objects pending destructions. Used to skip needlessly |
| | 143 | * waiting on an RCU barrier if no objects are waiting to be freed. |
| | 144 | */ |
| | 145 | atomic_t free_count; |
| | 146 | |
| | 147 | /** |
| | 148 | * tmpfs instance used for shmem backed objects |
| | 149 | */ |
| | 150 | struct vfsmount *gemfs; |
| | 151 | |
| | 152 | struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; |
| | 153 | |
| | 154 | struct notifier_block oom_notifier; |
| | 155 | struct notifier_block vmap_notifier; |
| | 156 | struct shrinker *shrinker; |
| | 157 | |
| | 158 | /* shrinker accounting, also useful for userland debugging */ |
| | 159 | u64 shrink_memory; |
| | 160 | u32 shrink_count; |
| | 161 | }; |
| | 162 | |
| | 163 | struct i915_virtual_gpu { |
| | 164 | struct mutex lock; /* serialises sending of g2v_notify command pkts */ |
| | 165 | bool active; |
| | 166 | u32 caps; |
| | 167 | u32 *initial_mmio; |
| | 168 | u8 *initial_cfg_space; |
| | 169 | struct list_head entry; |
| | 170 | }; |
| | 171 | |
| | 172 | struct i915_selftest_stash { |
| | 173 | atomic_t counter; |
| | 174 | struct ida mock_region_instances; |
| | 175 | }; |
| | 176 | |
| | 177 | struct drm_i915_private { |
| | 178 | struct drm_device drm; |
| | 179 | |
| | 180 | struct intel_display display; |
| | 181 | |
| | 182 | /* FIXME: Device release actions should all be moved to drmm_ */ |
| | 183 | bool do_release; |
| | 184 | |
| | 185 | /* i915 device parameters */ |
| | 186 | struct i915_params params; |
| | 187 | |
| | 188 | const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ |
| | 189 | struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ |
| | 190 | struct intel_driver_caps caps; |
| | 191 | |
| | 192 | struct i915_dsm dsm; |
| | 193 | |
| | 194 | struct intel_uncore uncore; |
| | 195 | struct intel_uncore_mmio_debug mmio_debug; |
| | 196 | |
| | 197 | struct i915_virtual_gpu vgpu; |
| | 198 | |
| | 199 | struct intel_gvt *gvt; |
| | 200 | |
| | 201 | struct { |
| | 202 | struct pci_dev *pdev; |
| | 203 | struct resource mch_res; |
| | 204 | bool mchbar_need_disable; |
| | 205 | } gmch; |
| | 206 | |
| | 207 | /* |
| | 208 | * Chaining user engines happens in multiple stages, starting with a |
| | 209 | * simple lock-less linked list created by intel_engine_add_user(), |
| | 210 | * which later gets sorted and converted to an intermediate regular |
| | 211 | * list, just to be converted once again to its final rb tree structure |
| | 212 | * in intel_engines_driver_register(). |
| | 213 | * |
| | 214 | * Make sure to use the right iterator helper, depending on if the code |
| | 215 | * in question runs before or after intel_engines_driver_register() -- |
| | 216 | * for_each_uabi_engine() can only be used afterwards! |
| | 217 | */ |
| | 218 | union { |
| | 219 | struct llist_head uabi_engines_llist; |
| | 220 | struct list_head uabi_engines_list; |
| | 221 | struct rb_root uabi_engines; |
| | 222 | }; |
| | 223 | unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; |
| | 224 | |
| | 225 | bool irqs_enabled; |
| | 226 | |
| | 227 | /* LPT/WPT IOSF sideband protection */ |
| | 228 | struct mutex sbi_lock; |
| | 229 | |
| | 230 | /* VLV/CHV IOSF sideband */ |
| | 231 | struct { |
| | 232 | struct mutex lock; /* protect sideband access */ |
| | 233 | struct pm_qos_request qos; |
| | 234 | } vlv_iosf_sb; |
| | 235 | |
| | 236 | /* Sideband mailbox protection */ |
| | 237 | struct mutex sb_lock; |
| | 238 | |
| | 239 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
| | 240 | u32 irq_mask; |
| | 241 | |
| | 242 | bool preserve_bios_swizzle; |
| | 243 | |
| | 244 | unsigned int fsb_freq, mem_freq, is_ddr3; |
| | 245 | |
| | 246 | unsigned int hpll_freq; |
| | 247 | unsigned int czclk_freq; |
| | 248 | |
| | 249 | /** |
| | 250 | * wq - Driver workqueue for GEM. |
| | 251 | * |
| | 252 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
| | 253 | * locks, for otherwise the flushing done in the pageflip code will |
| | 254 | * result in deadlocks. |
| | 255 | */ |
| | 256 | struct workqueue_struct *wq; |
| | 257 | |
| | 258 | /** |
| | 259 | * unordered_wq - internal workqueue for unordered work |
| | 260 | * |
| | 261 | * This workqueue should be used for all unordered work |
| | 262 | * scheduling within i915, which used to be scheduled on the |
| | 263 | * system_wq before moving to a driver instance due |
| | 264 | * deprecation of flush_scheduled_work(). |
| | 265 | */ |
| | 266 | struct workqueue_struct *unordered_wq; |
| | 267 | |
| | 268 | /* pm private clock gating functions */ |
| | 269 | const struct drm_i915_clock_gating_funcs *clock_gating_funcs; |
| | 270 | |
| | 271 | unsigned long gem_quirks; |
| | 272 | |
| | 273 | struct i915_gem_mm mm; |
| | 274 | |
| | 275 | struct intel_l3_parity l3_parity; |
| | 276 | |
| | 277 | /* |
| | 278 | * edram size in MB. |
| | 279 | * Cannot be determined by PCIID. You must always read a register. |
| | 280 | */ |
| | 281 | u32 edram_size_mb; |
| | 282 | |
| | 283 | struct i915_gpu_error gpu_error; |
| | 284 | |
| | 285 | u32 suspend_count; |
| | 286 | struct vlv_s0ix_state *vlv_s0ix_state; |
| | 287 | |
| | 288 | struct dram_info { |
| | 289 | bool wm_lv_0_adjust_needed; |
| | 290 | u8 num_channels; |
| | 291 | bool symmetric_memory; |
| | 292 | enum intel_dram_type { |
| | 293 | INTEL_DRAM_UNKNOWN, |
| | 294 | INTEL_DRAM_DDR3, |
| | 295 | INTEL_DRAM_DDR4, |
| | 296 | INTEL_DRAM_LPDDR3, |
| | 297 | INTEL_DRAM_LPDDR4, |
| | 298 | INTEL_DRAM_DDR5, |
| | 299 | INTEL_DRAM_LPDDR5, |
| | 300 | INTEL_DRAM_GDDR, |
| | 301 | INTEL_DRAM_GDDR_ECC, |
| | 302 | __INTEL_DRAM_TYPE_MAX, |
| | 303 | } type; |
| | 304 | u8 num_qgv_points; |
| | 305 | u8 num_psf_gv_points; |
| | 306 | } dram_info; |
| | 307 | |
| | 308 | struct intel_runtime_pm runtime_pm; |
| | 309 | |
| | 310 | struct i915_perf perf; |
| | 311 | |
| | 312 | struct i915_hwmon *hwmon; |
| | 313 | |
| | 314 | struct intel_gt *gt[I915_MAX_GT]; |
| | 315 | |
| | 316 | struct kobject *sysfs_gt; |
| | 317 | |
| | 318 | /* Quick lookup of media GT (current platforms only have one) */ |
| | 319 | struct intel_gt *media_gt; |
| | 320 | |
| | 321 | struct { |
| | 322 | struct i915_gem_contexts { |
| | 323 | spinlock_t lock; /* locks list */ |
| | 324 | struct list_head list; |
| | 325 | } contexts; |
| | 326 | |
| | 327 | /* |
| | 328 | * We replace the local file with a global mappings as the |
| | 329 | * backing storage for the mmap is on the device and not |
| | 330 | * on the struct file, and we do not want to prolong the |
| | 331 | * lifetime of the local fd. To minimise the number of |
| | 332 | * anonymous inodes we create, we use a global singleton to |
| | 333 | * share the global mapping. |
| | 334 | */ |
| | 335 | struct file *mmap_singleton; |
| | 336 | } gem; |
| | 337 | |
| | 338 | struct intel_pxp *pxp; |
| | 339 | |
| | 340 | struct i915_pmu pmu; |
| | 341 | |
| | 342 | /* The TTM device structure. */ |
| | 343 | struct ttm_device bdev; |
| | 344 | |
| | 345 | I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) |
| | 346 | |
| | 347 | /* |
| | 348 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
| | 349 | * will be rejected. Instead look for a better place. |
| | 350 | */ |
| | 351 | }; |
| | 352 | |
| | 353 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
| | 354 | { |
| | 355 | return container_of(dev, struct drm_i915_private, drm); |
| | 356 | } |
| | 357 | |
| | 358 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
| | 359 | { |
| | 360 | struct drm_device *drm = dev_get_drvdata(kdev); |
| | 361 | |
| | 362 | return drm ? to_i915(drm) : NULL; |
| | 363 | } |
| | 364 | |
| | 365 | static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) |
| | 366 | { |
| | 367 | struct drm_device *drm = pci_get_drvdata(pdev); |
| | 368 | |
| | 369 | return drm ? to_i915(drm) : NULL; |
| | 370 | } |
| | 371 | |
| | 372 | static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) |
| | 373 | { |
| | 374 | return i915->gt[0]; |
| | 375 | } |
| | 376 | |
| | 377 | #define rb_to_uabi_engine(rb) \ |
| | 378 | rb_entry_safe(rb, struct intel_engine_cs, uabi_node) |
| | 379 | |
| | 380 | #define for_each_uabi_engine(engine__, i915__) \ |
| | 381 | for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ |
| | 382 | (engine__); \ |
| | 383 | (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) |
| | 384 | |
| | 385 | #define INTEL_INFO(i915) ((i915)->__info) |
| | 386 | #define RUNTIME_INFO(i915) (&(i915)->__runtime) |
| | 387 | #define DRIVER_CAPS(i915) (&(i915)->caps) |
| | 388 | |
| | 389 | #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) |
| | 390 | |
| | 391 | #define IP_VER(ver, rel) ((ver) << 8 | (rel)) |
| | 392 | |
| | 393 | #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) |
| | 394 | #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ |
| | 395 | RUNTIME_INFO(i915)->graphics.ip.rel) |
| | 396 | #define IS_GRAPHICS_VER(i915, from, until) \ |
| | 397 | (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) |
| | 398 | |
| | 399 | #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) |
| | 400 | #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ |
| | 401 | RUNTIME_INFO(i915)->media.ip.rel) |
| | 402 | #define IS_MEDIA_VER(i915, from, until) \ |
| | 403 | (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) |
| | 404 | |
| | 405 | #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) |
| | 406 | |
| | 407 | #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) |
| | 408 | #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) |
| | 409 | |
| | 410 | #define IS_GRAPHICS_STEP(__i915, since, until) \ |
| | 411 | (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ |
| | 412 | INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) |
| | 413 | |
| | 414 | #define IS_MEDIA_STEP(__i915, since, until) \ |
| | 415 | (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ |
| | 416 | INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) |
| | 417 | |
| | 418 | static __always_inline unsigned int |
| | 419 | __platform_mask_index(const struct intel_runtime_info *info, |
| | 420 | enum intel_platform p) |
| | 421 | { |
| | 422 | const unsigned int pbits = |
| | 423 | BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; |
| | 424 | |
| | 425 | /* Expand the platform_mask array if this fails. */ |
| | 426 | BUILD_BUG_ON(INTEL_MAX_PLATFORMS > |
| | 427 | pbits * ARRAY_SIZE(info->platform_mask)); |
| | 428 | |
| | 429 | return p / pbits; |
| | 430 | } |
| | 431 | |
| | 432 | static __always_inline unsigned int |
| | 433 | __platform_mask_bit(const struct intel_runtime_info *info, |
| | 434 | enum intel_platform p) |
| | 435 | { |
| | 436 | const unsigned int pbits = |
| | 437 | BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; |
| | 438 | |
| | 439 | return p % pbits + INTEL_SUBPLATFORM_BITS; |
| | 440 | } |
| | 441 | |
| | 442 | static inline u32 |
| | 443 | intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) |
| | 444 | { |
| | 445 | const unsigned int pi = __platform_mask_index(info, p); |
| | 446 | |
| | 447 | return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; |
| | 448 | } |
| | 449 | |
| | 450 | static __always_inline bool |
| | 451 | IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) |
| | 452 | { |
| | 453 | const struct intel_runtime_info *info = RUNTIME_INFO(i915); |
| | 454 | const unsigned int pi = __platform_mask_index(info, p); |
| | 455 | const unsigned int pb = __platform_mask_bit(info, p); |
| | 456 | |
| | 457 | BUILD_BUG_ON(!__builtin_constant_p(p)); |
| | 458 | |
| | 459 | return info->platform_mask[pi] & BIT(pb); |
| | 460 | } |
| | 461 | |
| | 462 | static __always_inline bool |
| | 463 | IS_SUBPLATFORM(const struct drm_i915_private *i915, |
| | 464 | enum intel_platform p, unsigned int s) |
| | 465 | { |
| | 466 | const struct intel_runtime_info *info = RUNTIME_INFO(i915); |
| | 467 | const unsigned int pi = __platform_mask_index(info, p); |
| | 468 | const unsigned int pb = __platform_mask_bit(info, p); |
| | 469 | const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; |
| | 470 | const u32 mask = info->platform_mask[pi]; |
| | 471 | |
| | 472 | BUILD_BUG_ON(!__builtin_constant_p(p)); |
| | 473 | BUILD_BUG_ON(!__builtin_constant_p(s)); |
| | 474 | BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); |
| | 475 | |
| | 476 | /* Shift and test on the MSB position so sign flag can be used. */ |
| | 477 | return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); |
| | 478 | } |
| | 479 | |
| | 480 | #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) |
| | 481 | #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) |
| | 482 | |
| | 483 | #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) |
| | 484 | #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) |
| | 485 | #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) |
| | 486 | #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) |
| | 487 | #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) |
| | 488 | #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) |
| | 489 | #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) |
| | 490 | #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) |
| | 491 | #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) |
| | 492 | #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) |
| | 493 | #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) |
| | 494 | #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) |
| | 495 | #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) |
| | 496 | #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) |
| | 497 | #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) |
| | 498 | #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) |
| | 499 | #define IS_IRONLAKE_M(i915) \ |
| | 500 | (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) |
| | 501 | #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) |
| | 502 | #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) |
| | 503 | #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) |
| | 504 | #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) |
| | 505 | #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) |
| | 506 | #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) |
| | 507 | #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) |
| | 508 | #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) |
| | 509 | #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) |
| | 510 | #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) |
| | 511 | #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) |
| | 512 | #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) |
| | 513 | #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) |
| | 514 | #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) |
| | 515 | #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) |
| | 516 | #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) |
| | 517 | #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) |
| | 518 | #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) |
| | 519 | #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) |
| | 520 | #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) |
| | 521 | #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) |
| | 522 | #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) |
| | 523 | /* |
| | 524 | * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, |
| | 525 | * so we need to define these even on platforms that the i915 base driver |
| | 526 | * doesn't support. Ensure the parameter is used in the definition to |
| | 527 | * avoid 'unused variable' warnings when compiling the shared display code |
| | 528 | * for i915. |
| | 529 | */ |
| | 530 | #define IS_LUNARLAKE(i915) (0 && i915) |
| | 531 | #define IS_BATTLEMAGE(i915) (0 && i915) |
| | 532 | #define IS_PANTHERLAKE(i915) (0 && i915) |
| | 533 | |
| | 534 | #define IS_ARROWLAKE_H(i915) \ |
| | 535 | IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H) |
| | 536 | #define IS_ARROWLAKE_U(i915) \ |
| | 537 | IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U) |
| | 538 | #define IS_ARROWLAKE_S(i915) \ |
| | 539 | IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S) |
| | 540 | #define IS_DG2_G10(i915) \ |
| | 541 | IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) |
| | 542 | #define IS_DG2_G11(i915) \ |
| | 543 | IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) |
| | 544 | #define IS_DG2_G12(i915) \ |
| | 545 | IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) |
| | 546 | #define IS_DG2_D(i915) \ |
| | 547 | IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D) |
| | 548 | #define IS_RAPTORLAKE_S(i915) \ |
| | 549 | IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) |
| | 550 | #define IS_ALDERLAKE_P_N(i915) \ |
| | 551 | IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) |
| | 552 | #define IS_RAPTORLAKE_P(i915) \ |
| | 553 | IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) |
| | 554 | #define IS_RAPTORLAKE_U(i915) \ |
| | 555 | IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) |
| | 556 | #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ |
| | 557 | (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) |
| | 558 | #define IS_BROADWELL_ULT(i915) \ |
| | 559 | IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) |
| | 560 | #define IS_BROADWELL_ULX(i915) \ |
| | 561 | IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) |
| | 562 | #define IS_HASWELL_ULT(i915) \ |
| | 563 | IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) |
| | 564 | /* ULX machines are also considered ULT. */ |
| | 565 | #define IS_HASWELL_ULX(i915) \ |
| | 566 | IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) |
| | 567 | #define IS_SKYLAKE_ULT(i915) \ |
| | 568 | IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) |
| | 569 | #define IS_SKYLAKE_ULX(i915) \ |
| | 570 | IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) |
| | 571 | #define IS_KABYLAKE_ULT(i915) \ |
| | 572 | IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) |
| | 573 | #define IS_KABYLAKE_ULX(i915) \ |
| | 574 | IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) |
| | 575 | #define IS_COFFEELAKE_ULT(i915) \ |
| | 576 | IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) |
| | 577 | #define IS_COFFEELAKE_ULX(i915) \ |
| | 578 | IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) |
| | 579 | #define IS_COMETLAKE_ULT(i915) \ |
| | 580 | IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) |
| | 581 | #define IS_COMETLAKE_ULX(i915) \ |
| | 582 | IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) |
| | 583 | |
| | 584 | #define IS_ICL_WITH_PORT_F(i915) \ |
| | 585 | IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) |
| | 586 | |
| | 587 | #define IS_TIGERLAKE_UY(i915) \ |
| | 588 | IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) |
| | 589 | |
| | 590 | #define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) |
| | 591 | #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915)) |
| | 592 | |
| | 593 | #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) |
| | 594 | #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) |
| | 595 | |
| | 596 | #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ |
| | 597 | unsigned int first__ = (first); \ |
| | 598 | unsigned int count__ = (count); \ |
| | 599 | ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ |
| | 600 | }) |
| | 601 | |
| | 602 | #define ENGINE_INSTANCES_MASK(gt, first, count) \ |
| | 603 | __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) |
| | 604 | |
| | 605 | #define RCS_MASK(gt) \ |
| | 606 | ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) |
| | 607 | #define BCS_MASK(gt) \ |
| | 608 | ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) |
| | 609 | #define VDBOX_MASK(gt) \ |
| | 610 | ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) |
| | 611 | #define VEBOX_MASK(gt) \ |
| | 612 | ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) |
| | 613 | #define CCS_MASK(gt) \ |
| | 614 | ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) |
| | 615 | |
| | 616 | #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) |
| | 617 | |
| | 618 | /* |
| | 619 | * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution |
| | 620 | * All later gens can run the final buffer from the ppgtt |
| | 621 | */ |
| | 622 | #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) |
| | 623 | |
| | 624 | #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) |
| | 625 | #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) |
| | 626 | #define HAS_EDRAM(i915) ((i915)->edram_size_mb) |
| | 627 | #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) |
| | 628 | #define HAS_WT(i915) HAS_EDRAM(i915) |
| | 629 | |
| | 630 | #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) |
| | 631 | |
| | 632 | #define HAS_LOGICAL_RING_CONTEXTS(i915) \ |
| | 633 | (INTEL_INFO(i915)->has_logical_ring_contexts) |
| | 634 | #define HAS_LOGICAL_RING_ELSQ(i915) \ |
| | 635 | (INTEL_INFO(i915)->has_logical_ring_elsq) |
| | 636 | |
| | 637 | #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) |
| | 638 | |
| | 639 | #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) |
| | 640 | #define HAS_PPGTT(i915) \ |
| | 641 | (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) |
| | 642 | #define HAS_FULL_PPGTT(i915) \ |
| | 643 | (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) |
| | 644 | |
| | 645 | #define HAS_PAGE_SIZES(i915, sizes) ({ \ |
| | 646 | GEM_BUG_ON((sizes) == 0); \ |
| | 647 | ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ |
| | 648 | }) |
| | 649 | |
| | 650 | #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ |
| | 651 | (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) |
| | 652 | |
| | 653 | /* WaRsDisableCoarsePowerGating:skl,cnl */ |
| | 654 | #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ |
| | 655 | (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4)) |
| | 656 | |
| | 657 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| | 658 | * rows, which changed the alignment requirements and fence programming. |
| | 659 | */ |
| | 660 | #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ |
| | 661 | !(IS_I915G(i915) || IS_I915GM(i915))) |
| | 662 | |
| | 663 | #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) |
| | 664 | #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) |
| | 665 | #define HAS_RC6pp(i915) (false) /* HW was never validated */ |
| | 666 | |
| | 667 | #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) |
| | 668 | |
| | 669 | #define HAS_PXP(i915) \ |
| | 670 | (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp) |
| | 671 | |
| | 672 | #define HAS_HECI_PXP(i915) \ |
| | 673 | (INTEL_INFO(i915)->has_heci_pxp) |
| | 674 | |
| | 675 | #define HAS_HECI_GSCFI(i915) \ |
| | 676 | (INTEL_INFO(i915)->has_heci_gscfi) |
| | 677 | |
| | 678 | #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) |
| | 679 | |
| | 680 | #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) |
| | 681 | #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) |
| | 682 | |
| | 683 | #define HAS_OA_BPC_REPORTING(i915) \ |
| | 684 | (INTEL_INFO(i915)->has_oa_bpc_reporting) |
| | 685 | #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ |
| | 686 | (INTEL_INFO(i915)->has_oa_slice_contrib_limits) |
| | 687 | #define HAS_OAM(i915) \ |
| | 688 | (INTEL_INFO(i915)->has_oam) |
| | 689 | |
| | 690 | /* |
| | 691 | * Set this flag, when platform requires 64K GTT page sizes or larger for |
| | 692 | * device local memory access. |
| | 693 | */ |
| | 694 | #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) |
| | 695 | |
| | 696 | #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id)) |
| | 697 | #define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0) |
| | 698 | |
| | 699 | #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) |
| | 700 | |
| | 701 | /* |
| | 702 | * Platform has the dedicated compression control state for each lmem surfaces |
| | 703 | * stored in lmem to support the 3D and media compression formats. |
| | 704 | */ |
| | 705 | #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) |
| | 706 | |
| | 707 | #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) |
| | 708 | |
| | 709 | #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) |
| | 710 | |
| | 711 | #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) |
| | 712 | |
| | 713 | #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) |
| | 714 | |
| | 715 | #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) |
| | 716 | |
| | 717 | /* DPF == dynamic parity feature */ |
| | 718 | #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) |
| | 719 | #define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \ |
| | 720 | 2 : HAS_L3_DPF(i915)) |
| | 721 | |
| | 722 | #define HAS_GUC_DEPRIVILEGE(i915) \ |
| | 723 | (INTEL_INFO(i915)->has_guc_deprivilege) |
| | 724 | |
| | 725 | #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation) |
| | 726 | |
| | 727 | #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) |
| | 728 | |
| | 729 | #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) |
| | 730 | |
| | 731 | #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ |
| | 732 | GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) |
| | 733 | |
| | 734 | #endif |
projects / linux-2.6-block.git / blame_incremental