| 1 | // SPDX-License-Identifier: MIT |
| 2 | /* |
| 3 | * Copyright © 2018 Intel Corp |
| 4 | * |
| 5 | * Author: |
| 6 | * Manasi Navare <manasi.d.navare@intel.com> |
| 7 | */ |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/byteorder/generic.h> |
| 14 | #include <drm/drm_dp_helper.h> |
| 15 | #include <drm/drm_dsc.h> |
| 16 | |
| 17 | /** |
| 18 | * DOC: dsc helpers |
| 19 | * |
| 20 | * These functions contain some common logic and helpers to deal with VESA |
| 21 | * Display Stream Compression standard required for DSC on Display Port/eDP or |
| 22 | * MIPI display interfaces. |
| 23 | */ |
| 24 | |
| 25 | /** |
| 26 | * drm_dsc_dp_pps_header_init() - Initializes the PPS Header |
| 27 | * for DisplayPort as per the DP 1.4 spec. |
| 28 | * @pps_sdp: Secondary data packet for DSC Picture Parameter Set |
| 29 | */ |
| 30 | void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp) |
| 31 | { |
| 32 | memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header)); |
| 33 | |
| 34 | pps_sdp->pps_header.HB1 = DP_SDP_PPS; |
| 35 | pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; |
| 36 | } |
| 37 | EXPORT_SYMBOL(drm_dsc_dp_pps_header_init); |
| 38 | |
| 39 | /** |
| 40 | * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe |
| 41 | * using the DSC configuration parameters in the order expected |
| 42 | * by the DSC Display Sink device. For the DSC, the sink device |
| 43 | * expects the PPS payload in the big endian format for the fields |
| 44 | * that span more than 1 byte. |
| 45 | * |
| 46 | * @pps_sdp: |
| 47 | * Secondary data packet for DSC Picture Parameter Set |
| 48 | * @dsc_cfg: |
| 49 | * DSC Configuration data filled by driver |
| 50 | */ |
| 51 | void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, |
| 52 | const struct drm_dsc_config *dsc_cfg) |
| 53 | { |
| 54 | int i; |
| 55 | |
| 56 | /* Protect against someone accidently changing struct size */ |
| 57 | BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) != |
| 58 | DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); |
| 59 | |
| 60 | memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload)); |
| 61 | |
| 62 | /* PPS 0 */ |
| 63 | pps_sdp->pps_payload.dsc_version = |
| 64 | dsc_cfg->dsc_version_minor | |
| 65 | dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; |
| 66 | |
| 67 | /* PPS 1, 2 is 0 */ |
| 68 | |
| 69 | /* PPS 3 */ |
| 70 | pps_sdp->pps_payload.pps_3 = |
| 71 | dsc_cfg->line_buf_depth | |
| 72 | dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; |
| 73 | |
| 74 | /* PPS 4 */ |
| 75 | pps_sdp->pps_payload.pps_4 = |
| 76 | ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> |
| 77 | DSC_PPS_MSB_SHIFT) | |
| 78 | dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | |
| 79 | dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | |
| 80 | dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | |
| 81 | dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; |
| 82 | |
| 83 | /* PPS 5 */ |
| 84 | pps_sdp->pps_payload.bits_per_pixel_low = |
| 85 | (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); |
| 86 | |
| 87 | /* |
| 88 | * The DSC panel expects the PPS packet to have big endian format |
| 89 | * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert |
| 90 | * to big endian format. If format is little endian, it will swap |
| 91 | * bytes to convert to Big endian else keep it unchanged. |
| 92 | */ |
| 93 | |
| 94 | /* PPS 6, 7 */ |
| 95 | pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height); |
| 96 | |
| 97 | /* PPS 8, 9 */ |
| 98 | pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width); |
| 99 | |
| 100 | /* PPS 10, 11 */ |
| 101 | pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height); |
| 102 | |
| 103 | /* PPS 12, 13 */ |
| 104 | pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width); |
| 105 | |
| 106 | /* PPS 14, 15 */ |
| 107 | pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); |
| 108 | |
| 109 | /* PPS 16 */ |
| 110 | pps_sdp->pps_payload.initial_xmit_delay_high = |
| 111 | ((dsc_cfg->initial_xmit_delay & |
| 112 | DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> |
| 113 | DSC_PPS_MSB_SHIFT); |
| 114 | |
| 115 | /* PPS 17 */ |
| 116 | pps_sdp->pps_payload.initial_xmit_delay_low = |
| 117 | (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); |
| 118 | |
| 119 | /* PPS 18, 19 */ |
| 120 | pps_sdp->pps_payload.initial_dec_delay = |
| 121 | cpu_to_be16(dsc_cfg->initial_dec_delay); |
| 122 | |
| 123 | /* PPS 20 is 0 */ |
| 124 | |
| 125 | /* PPS 21 */ |
| 126 | pps_sdp->pps_payload.initial_scale_value = |
| 127 | dsc_cfg->initial_scale_value; |
| 128 | |
| 129 | /* PPS 22, 23 */ |
| 130 | pps_sdp->pps_payload.scale_increment_interval = |
| 131 | cpu_to_be16(dsc_cfg->scale_increment_interval); |
| 132 | |
| 133 | /* PPS 24 */ |
| 134 | pps_sdp->pps_payload.scale_decrement_interval_high = |
| 135 | ((dsc_cfg->scale_decrement_interval & |
| 136 | DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> |
| 137 | DSC_PPS_MSB_SHIFT); |
| 138 | |
| 139 | /* PPS 25 */ |
| 140 | pps_sdp->pps_payload.scale_decrement_interval_low = |
| 141 | (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); |
| 142 | |
| 143 | /* PPS 26[7:0], PPS 27[7:5] RESERVED */ |
| 144 | |
| 145 | /* PPS 27 */ |
| 146 | pps_sdp->pps_payload.first_line_bpg_offset = |
| 147 | dsc_cfg->first_line_bpg_offset; |
| 148 | |
| 149 | /* PPS 28, 29 */ |
| 150 | pps_sdp->pps_payload.nfl_bpg_offset = |
| 151 | cpu_to_be16(dsc_cfg->nfl_bpg_offset); |
| 152 | |
| 153 | /* PPS 30, 31 */ |
| 154 | pps_sdp->pps_payload.slice_bpg_offset = |
| 155 | cpu_to_be16(dsc_cfg->slice_bpg_offset); |
| 156 | |
| 157 | /* PPS 32, 33 */ |
| 158 | pps_sdp->pps_payload.initial_offset = |
| 159 | cpu_to_be16(dsc_cfg->initial_offset); |
| 160 | |
| 161 | /* PPS 34, 35 */ |
| 162 | pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset); |
| 163 | |
| 164 | /* PPS 36 */ |
| 165 | pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp; |
| 166 | |
| 167 | /* PPS 37 */ |
| 168 | pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp; |
| 169 | |
| 170 | /* PPS 38, 39 */ |
| 171 | pps_sdp->pps_payload.rc_model_size = |
| 172 | cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); |
| 173 | |
| 174 | /* PPS 40 */ |
| 175 | pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; |
| 176 | |
| 177 | /* PPS 41 */ |
| 178 | pps_sdp->pps_payload.rc_quant_incr_limit0 = |
| 179 | dsc_cfg->rc_quant_incr_limit0; |
| 180 | |
| 181 | /* PPS 42 */ |
| 182 | pps_sdp->pps_payload.rc_quant_incr_limit1 = |
| 183 | dsc_cfg->rc_quant_incr_limit1; |
| 184 | |
| 185 | /* PPS 43 */ |
| 186 | pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | |
| 187 | DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; |
| 188 | |
| 189 | /* PPS 44 - 57 */ |
| 190 | for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) |
| 191 | pps_sdp->pps_payload.rc_buf_thresh[i] = |
| 192 | dsc_cfg->rc_buf_thresh[i]; |
| 193 | |
| 194 | /* PPS 58 - 87 */ |
| 195 | /* |
| 196 | * For DSC sink programming the RC Range parameter fields |
| 197 | * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] |
| 198 | */ |
| 199 | for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { |
| 200 | pps_sdp->pps_payload.rc_range_parameters[i] = |
| 201 | ((dsc_cfg->rc_range_params[i].range_min_qp << |
| 202 | DSC_PPS_RC_RANGE_MINQP_SHIFT) | |
| 203 | (dsc_cfg->rc_range_params[i].range_max_qp << |
| 204 | DSC_PPS_RC_RANGE_MAXQP_SHIFT) | |
| 205 | (dsc_cfg->rc_range_params[i].range_bpg_offset)); |
| 206 | pps_sdp->pps_payload.rc_range_parameters[i] = |
| 207 | cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]); |
| 208 | } |
| 209 | |
| 210 | /* PPS 88 */ |
| 211 | pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 | |
| 212 | dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; |
| 213 | |
| 214 | /* PPS 89 */ |
| 215 | pps_sdp->pps_payload.second_line_bpg_offset = |
| 216 | dsc_cfg->second_line_bpg_offset; |
| 217 | |
| 218 | /* PPS 90, 91 */ |
| 219 | pps_sdp->pps_payload.nsl_bpg_offset = |
| 220 | cpu_to_be16(dsc_cfg->nsl_bpg_offset); |
| 221 | |
| 222 | /* PPS 92, 93 */ |
| 223 | pps_sdp->pps_payload.second_line_offset_adj = |
| 224 | cpu_to_be16(dsc_cfg->second_line_offset_adj); |
| 225 | |
| 226 | /* PPS 94 - 127 are O */ |
| 227 | } |
| 228 | EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack); |