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[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
29#include "dm_services_types.h"
30#include "dc.h"
31#include "link_enc_cfg.h"
32#include "dc/inc/core_types.h"
33#include "dal_asic_id.h"
34#include "dmub/dmub_srv.h"
35#include "dc/inc/hw/dmcu.h"
36#include "dc/inc/hw/abm.h"
37#include "dc/dc_dmub_srv.h"
38#include "dc/dc_edid_parser.h"
39#include "dc/dc_stat.h"
40#include "dc/dc_state.h"
41#include "amdgpu_dm_trace.h"
42#include "dpcd_defs.h"
43#include "link/protocols/link_dpcd.h"
44#include "link_service_types.h"
45#include "link/protocols/link_dp_capability.h"
46#include "link/protocols/link_ddc.h"
47
48#include "vid.h"
49#include "amdgpu.h"
50#include "amdgpu_display.h"
51#include "amdgpu_ucode.h"
52#include "atom.h"
53#include "amdgpu_dm.h"
54#include "amdgpu_dm_plane.h"
55#include "amdgpu_dm_crtc.h"
56#include "amdgpu_dm_hdcp.h"
57#include <drm/display/drm_hdcp_helper.h>
58#include "amdgpu_dm_wb.h"
59#include "amdgpu_pm.h"
60#include "amdgpu_atombios.h"
61
62#include "amd_shared.h"
63#include "amdgpu_dm_irq.h"
64#include "dm_helpers.h"
65#include "amdgpu_dm_mst_types.h"
66#if defined(CONFIG_DEBUG_FS)
67#include "amdgpu_dm_debugfs.h"
68#endif
69#include "amdgpu_dm_psr.h"
70#include "amdgpu_dm_replay.h"
71
72#include "ivsrcid/ivsrcid_vislands30.h"
73
74#include <linux/backlight.h>
75#include <linux/module.h>
76#include <linux/moduleparam.h>
77#include <linux/types.h>
78#include <linux/pm_runtime.h>
79#include <linux/pci.h>
80#include <linux/power_supply.h>
81#include <linux/firmware.h>
82#include <linux/component.h>
83#include <linux/sort.h>
84
85#include <drm/display/drm_dp_mst_helper.h>
86#include <drm/display/drm_hdmi_helper.h>
87#include <drm/drm_atomic.h>
88#include <drm/drm_atomic_uapi.h>
89#include <drm/drm_atomic_helper.h>
90#include <drm/drm_blend.h>
91#include <drm/drm_fixed.h>
92#include <drm/drm_fourcc.h>
93#include <drm/drm_edid.h>
94#include <drm/drm_eld.h>
95#include <drm/drm_utils.h>
96#include <drm/drm_vblank.h>
97#include <drm/drm_audio_component.h>
98#include <drm/drm_gem_atomic_helper.h>
99
100#include <media/cec-notifier.h>
101#include <acpi/video.h>
102
103#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
104
105#include "dcn/dcn_1_0_offset.h"
106#include "dcn/dcn_1_0_sh_mask.h"
107#include "soc15_hw_ip.h"
108#include "soc15_common.h"
109#include "vega10_ip_offset.h"
110
111#include "gc/gc_11_0_0_offset.h"
112#include "gc/gc_11_0_0_sh_mask.h"
113
114#include "modules/inc/mod_freesync.h"
115#include "modules/power/power_helpers.h"
116
117static_assert(AMDGPU_DMUB_NOTIFICATION_MAX == DMUB_NOTIFICATION_MAX, "AMDGPU_DMUB_NOTIFICATION_MAX mismatch");
118
119#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
120MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
121#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
122MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
123#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
124MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
125#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
126MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
127#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
128MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
129#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
130MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
131#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
132MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
133#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
134MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
135#define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
136MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
137#define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
138MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
139#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
140MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
141
142#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
143MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
144#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
145MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
146
147#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
148MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
149
150#define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
151MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
152
153#define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
154MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
155
156#define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin"
157MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB);
158
159#define FIRMWARE_DCN_36_DMUB "amdgpu/dcn_3_6_dmcub.bin"
160MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB);
161
162#define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin"
163MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);
164
165/* Number of bytes in PSP header for firmware. */
166#define PSP_HEADER_BYTES 0x100
167
168/* Number of bytes in PSP footer for firmware. */
169#define PSP_FOOTER_BYTES 0x100
170
171/**
172 * DOC: overview
173 *
174 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
175 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
176 * requests into DC requests, and DC responses into DRM responses.
177 *
178 * The root control structure is &struct amdgpu_display_manager.
179 */
180
181/* basic init/fini API */
182static int amdgpu_dm_init(struct amdgpu_device *adev);
183static void amdgpu_dm_fini(struct amdgpu_device *adev);
184static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
185static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state);
186static struct amdgpu_i2c_adapter *
187create_i2c(struct ddc_service *ddc_service, bool oem);
188
189static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
190{
191 switch (link->dpcd_caps.dongle_type) {
192 case DISPLAY_DONGLE_NONE:
193 return DRM_MODE_SUBCONNECTOR_Native;
194 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
195 return DRM_MODE_SUBCONNECTOR_VGA;
196 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
197 case DISPLAY_DONGLE_DP_DVI_DONGLE:
198 return DRM_MODE_SUBCONNECTOR_DVID;
199 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
200 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
201 return DRM_MODE_SUBCONNECTOR_HDMIA;
202 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
203 default:
204 return DRM_MODE_SUBCONNECTOR_Unknown;
205 }
206}
207
208static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
209{
210 struct dc_link *link = aconnector->dc_link;
211 struct drm_connector *connector = &aconnector->base;
212 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
213
214 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
215 return;
216
217 if (aconnector->dc_sink)
218 subconnector = get_subconnector_type(link);
219
220 drm_object_property_set_value(&connector->base,
221 connector->dev->mode_config.dp_subconnector_property,
222 subconnector);
223}
224
225/*
226 * initializes drm_device display related structures, based on the information
227 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
228 * drm_encoder, drm_mode_config
229 *
230 * Returns 0 on success
231 */
232static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
233/* removes and deallocates the drm structures, created by the above function */
234static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
235
236static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
237 struct amdgpu_dm_connector *amdgpu_dm_connector,
238 u32 link_index,
239 struct amdgpu_encoder *amdgpu_encoder);
240static int amdgpu_dm_encoder_init(struct drm_device *dev,
241 struct amdgpu_encoder *aencoder,
242 uint32_t link_index);
243
244static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
245
246static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
247
248static int amdgpu_dm_atomic_check(struct drm_device *dev,
249 struct drm_atomic_state *state);
250
251static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
252static void handle_hpd_rx_irq(void *param);
253
254static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
255 int bl_idx,
256 u32 user_brightness);
257
258static bool
259is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
260 struct drm_crtc_state *new_crtc_state);
261/*
262 * dm_vblank_get_counter
263 *
264 * @brief
265 * Get counter for number of vertical blanks
266 *
267 * @param
268 * struct amdgpu_device *adev - [in] desired amdgpu device
269 * int disp_idx - [in] which CRTC to get the counter from
270 *
271 * @return
272 * Counter for vertical blanks
273 */
274static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
275{
276 struct amdgpu_crtc *acrtc = NULL;
277
278 if (crtc >= adev->mode_info.num_crtc)
279 return 0;
280
281 acrtc = adev->mode_info.crtcs[crtc];
282
283 if (!acrtc->dm_irq_params.stream) {
284 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n",
285 crtc);
286 return 0;
287 }
288
289 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
290}
291
292static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
293 u32 *vbl, u32 *position)
294{
295 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0;
296 struct amdgpu_crtc *acrtc = NULL;
297 struct dc *dc = adev->dm.dc;
298
299 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
300 return -EINVAL;
301
302 acrtc = adev->mode_info.crtcs[crtc];
303
304 if (!acrtc->dm_irq_params.stream) {
305 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n",
306 crtc);
307 return 0;
308 }
309
310 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
311 dc_allow_idle_optimizations(dc, false);
312
313 /*
314 * TODO rework base driver to use values directly.
315 * for now parse it back into reg-format
316 */
317 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
318 &v_blank_start,
319 &v_blank_end,
320 &h_position,
321 &v_position);
322
323 *position = v_position | (h_position << 16);
324 *vbl = v_blank_start | (v_blank_end << 16);
325
326 return 0;
327}
328
329static bool dm_is_idle(struct amdgpu_ip_block *ip_block)
330{
331 /* XXX todo */
332 return true;
333}
334
335static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block)
336{
337 /* XXX todo */
338 return 0;
339}
340
341static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block)
342{
343 return false;
344}
345
346static int dm_soft_reset(struct amdgpu_ip_block *ip_block)
347{
348 /* XXX todo */
349 return 0;
350}
351
352static struct amdgpu_crtc *
353get_crtc_by_otg_inst(struct amdgpu_device *adev,
354 int otg_inst)
355{
356 struct drm_device *dev = adev_to_drm(adev);
357 struct drm_crtc *crtc;
358 struct amdgpu_crtc *amdgpu_crtc;
359
360 if (WARN_ON(otg_inst == -1))
361 return adev->mode_info.crtcs[0];
362
363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
364 amdgpu_crtc = to_amdgpu_crtc(crtc);
365
366 if (amdgpu_crtc->otg_inst == otg_inst)
367 return amdgpu_crtc;
368 }
369
370 return NULL;
371}
372
373static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
374 struct dm_crtc_state *new_state)
375{
376 if (new_state->stream->adjust.timing_adjust_pending)
377 return true;
378 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
379 return true;
380 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
381 return true;
382 else
383 return false;
384}
385
386/*
387 * DC will program planes with their z-order determined by their ordering
388 * in the dc_surface_updates array. This comparator is used to sort them
389 * by descending zpos.
390 */
391static int dm_plane_layer_index_cmp(const void *a, const void *b)
392{
393 const struct dc_surface_update *sa = (struct dc_surface_update *)a;
394 const struct dc_surface_update *sb = (struct dc_surface_update *)b;
395
396 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */
397 return sb->surface->layer_index - sa->surface->layer_index;
398}
399
400/**
401 * update_planes_and_stream_adapter() - Send planes to be updated in DC
402 *
403 * DC has a generic way to update planes and stream via
404 * dc_update_planes_and_stream function; however, DM might need some
405 * adjustments and preparation before calling it. This function is a wrapper
406 * for the dc_update_planes_and_stream that does any required configuration
407 * before passing control to DC.
408 *
409 * @dc: Display Core control structure
410 * @update_type: specify whether it is FULL/MEDIUM/FAST update
411 * @planes_count: planes count to update
412 * @stream: stream state
413 * @stream_update: stream update
414 * @array_of_surface_update: dc surface update pointer
415 *
416 */
417static inline bool update_planes_and_stream_adapter(struct dc *dc,
418 int update_type,
419 int planes_count,
420 struct dc_stream_state *stream,
421 struct dc_stream_update *stream_update,
422 struct dc_surface_update *array_of_surface_update)
423{
424 sort(array_of_surface_update, planes_count,
425 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);
426
427 /*
428 * Previous frame finished and HW is ready for optimization.
429 */
430 if (update_type == UPDATE_TYPE_FAST)
431 dc_post_update_surfaces_to_stream(dc);
432
433 return dc_update_planes_and_stream(dc,
434 array_of_surface_update,
435 planes_count,
436 stream,
437 stream_update);
438}
439
440/**
441 * dm_pflip_high_irq() - Handle pageflip interrupt
442 * @interrupt_params: ignored
443 *
444 * Handles the pageflip interrupt by notifying all interested parties
445 * that the pageflip has been completed.
446 */
447static void dm_pflip_high_irq(void *interrupt_params)
448{
449 struct amdgpu_crtc *amdgpu_crtc;
450 struct common_irq_params *irq_params = interrupt_params;
451 struct amdgpu_device *adev = irq_params->adev;
452 struct drm_device *dev = adev_to_drm(adev);
453 unsigned long flags;
454 struct drm_pending_vblank_event *e;
455 u32 vpos, hpos, v_blank_start, v_blank_end;
456 bool vrr_active;
457
458 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
459
460 /* IRQ could occur when in initial stage */
461 /* TODO work and BO cleanup */
462 if (amdgpu_crtc == NULL) {
463 drm_dbg_state(dev, "CRTC is null, returning.\n");
464 return;
465 }
466
467 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
468
469 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
470 drm_dbg_state(dev,
471 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
472 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
473 amdgpu_crtc->crtc_id, amdgpu_crtc);
474 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
475 return;
476 }
477
478 /* page flip completed. */
479 e = amdgpu_crtc->event;
480 amdgpu_crtc->event = NULL;
481
482 WARN_ON(!e);
483
484 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
485
486 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
487 if (!vrr_active ||
488 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
489 &v_blank_end, &hpos, &vpos) ||
490 (vpos < v_blank_start)) {
491 /* Update to correct count and vblank timestamp if racing with
492 * vblank irq. This also updates to the correct vblank timestamp
493 * even in VRR mode, as scanout is past the front-porch atm.
494 */
495 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
496
497 /* Wake up userspace by sending the pageflip event with proper
498 * count and timestamp of vblank of flip completion.
499 */
500 if (e) {
501 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
502
503 /* Event sent, so done with vblank for this flip */
504 drm_crtc_vblank_put(&amdgpu_crtc->base);
505 }
506 } else if (e) {
507 /* VRR active and inside front-porch: vblank count and
508 * timestamp for pageflip event will only be up to date after
509 * drm_crtc_handle_vblank() has been executed from late vblank
510 * irq handler after start of back-porch (vline 0). We queue the
511 * pageflip event for send-out by drm_crtc_handle_vblank() with
512 * updated timestamp and count, once it runs after us.
513 *
514 * We need to open-code this instead of using the helper
515 * drm_crtc_arm_vblank_event(), as that helper would
516 * call drm_crtc_accurate_vblank_count(), which we must
517 * not call in VRR mode while we are in front-porch!
518 */
519
520 /* sequence will be replaced by real count during send-out. */
521 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
522 e->pipe = amdgpu_crtc->crtc_id;
523
524 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
525 e = NULL;
526 }
527
528 /* Keep track of vblank of this flip for flip throttling. We use the
529 * cooked hw counter, as that one incremented at start of this vblank
530 * of pageflip completion, so last_flip_vblank is the forbidden count
531 * for queueing new pageflips if vsync + VRR is enabled.
532 */
533 amdgpu_crtc->dm_irq_params.last_flip_vblank =
534 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
535
536 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
537 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
538
539 drm_dbg_state(dev,
540 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
541 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
542}
543
544static void dm_vupdate_high_irq(void *interrupt_params)
545{
546 struct common_irq_params *irq_params = interrupt_params;
547 struct amdgpu_device *adev = irq_params->adev;
548 struct amdgpu_crtc *acrtc;
549 struct drm_device *drm_dev;
550 struct drm_vblank_crtc *vblank;
551 ktime_t frame_duration_ns, previous_timestamp;
552 unsigned long flags;
553 int vrr_active;
554
555 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
556
557 if (acrtc) {
558 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
559 drm_dev = acrtc->base.dev;
560 vblank = drm_crtc_vblank_crtc(&acrtc->base);
561 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
562 frame_duration_ns = vblank->time - previous_timestamp;
563
564 if (frame_duration_ns > 0) {
565 trace_amdgpu_refresh_rate_track(acrtc->base.index,
566 frame_duration_ns,
567 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
568 atomic64_set(&irq_params->previous_timestamp, vblank->time);
569 }
570
571 drm_dbg_vbl(drm_dev,
572 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
573 vrr_active);
574
575 /* Core vblank handling is done here after end of front-porch in
576 * vrr mode, as vblank timestamping will give valid results
577 * while now done after front-porch. This will also deliver
578 * page-flip completion events that have been queued to us
579 * if a pageflip happened inside front-porch.
580 */
581 if (vrr_active) {
582 amdgpu_dm_crtc_handle_vblank(acrtc);
583
584 /* BTR processing for pre-DCE12 ASICs */
585 if (acrtc->dm_irq_params.stream &&
586 adev->family < AMDGPU_FAMILY_AI) {
587 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
588 mod_freesync_handle_v_update(
589 adev->dm.freesync_module,
590 acrtc->dm_irq_params.stream,
591 &acrtc->dm_irq_params.vrr_params);
592
593 dc_stream_adjust_vmin_vmax(
594 adev->dm.dc,
595 acrtc->dm_irq_params.stream,
596 &acrtc->dm_irq_params.vrr_params.adjust);
597 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
598 }
599 }
600 }
601}
602
603/**
604 * dm_crtc_high_irq() - Handles CRTC interrupt
605 * @interrupt_params: used for determining the CRTC instance
606 *
607 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
608 * event handler.
609 */
610static void dm_crtc_high_irq(void *interrupt_params)
611{
612 struct common_irq_params *irq_params = interrupt_params;
613 struct amdgpu_device *adev = irq_params->adev;
614 struct drm_writeback_job *job;
615 struct amdgpu_crtc *acrtc;
616 unsigned long flags;
617 int vrr_active;
618
619 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
620 if (!acrtc)
621 return;
622
623 if (acrtc->wb_conn) {
624 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
625
626 if (acrtc->wb_pending) {
627 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,
628 struct drm_writeback_job,
629 list_entry);
630 acrtc->wb_pending = false;
631 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
632
633 if (job) {
634 unsigned int v_total, refresh_hz;
635 struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
636
637 v_total = stream->adjust.v_total_max ?
638 stream->adjust.v_total_max : stream->timing.v_total;
639 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
640 100LL, (v_total * stream->timing.h_total));
641 mdelay(1000 / refresh_hz);
642
643 drm_writeback_signal_completion(acrtc->wb_conn, 0);
644 dc_stream_fc_disable_writeback(adev->dm.dc,
645 acrtc->dm_irq_params.stream, 0);
646 }
647 } else
648 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
649 }
650
651 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
652
653 drm_dbg_vbl(adev_to_drm(adev),
654 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
655 vrr_active, acrtc->dm_irq_params.active_planes);
656
657 /**
658 * Core vblank handling at start of front-porch is only possible
659 * in non-vrr mode, as only there vblank timestamping will give
660 * valid results while done in front-porch. Otherwise defer it
661 * to dm_vupdate_high_irq after end of front-porch.
662 */
663 if (!vrr_active)
664 amdgpu_dm_crtc_handle_vblank(acrtc);
665
666 /**
667 * Following stuff must happen at start of vblank, for crc
668 * computation and below-the-range btr support in vrr mode.
669 */
670 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
671
672 /* BTR updates need to happen before VUPDATE on Vega and above. */
673 if (adev->family < AMDGPU_FAMILY_AI)
674 return;
675
676 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
677
678 if (acrtc->dm_irq_params.stream &&
679 acrtc->dm_irq_params.vrr_params.supported &&
680 acrtc->dm_irq_params.freesync_config.state ==
681 VRR_STATE_ACTIVE_VARIABLE) {
682 mod_freesync_handle_v_update(adev->dm.freesync_module,
683 acrtc->dm_irq_params.stream,
684 &acrtc->dm_irq_params.vrr_params);
685
686 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
687 &acrtc->dm_irq_params.vrr_params.adjust);
688 }
689
690 /*
691 * If there aren't any active_planes then DCH HUBP may be clock-gated.
692 * In that case, pageflip completion interrupts won't fire and pageflip
693 * completion events won't get delivered. Prevent this by sending
694 * pending pageflip events from here if a flip is still pending.
695 *
696 * If any planes are enabled, use dm_pflip_high_irq() instead, to
697 * avoid race conditions between flip programming and completion,
698 * which could cause too early flip completion events.
699 */
700 if (adev->family >= AMDGPU_FAMILY_RV &&
701 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
702 acrtc->dm_irq_params.active_planes == 0) {
703 if (acrtc->event) {
704 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
705 acrtc->event = NULL;
706 drm_crtc_vblank_put(&acrtc->base);
707 }
708 acrtc->pflip_status = AMDGPU_FLIP_NONE;
709 }
710
711 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
712}
713
714#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
715/**
716 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
717 * DCN generation ASICs
718 * @interrupt_params: interrupt parameters
719 *
720 * Used to set crc window/read out crc value at vertical line 0 position
721 */
722static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
723{
724 struct common_irq_params *irq_params = interrupt_params;
725 struct amdgpu_device *adev = irq_params->adev;
726 struct amdgpu_crtc *acrtc;
727
728 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
729
730 if (!acrtc)
731 return;
732
733 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
734}
735#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
736
737/**
738 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
739 * @adev: amdgpu_device pointer
740 * @notify: dmub notification structure
741 *
742 * Dmub AUX or SET_CONFIG command completion processing callback
743 * Copies dmub notification to DM which is to be read by AUX command.
744 * issuing thread and also signals the event to wake up the thread.
745 */
746static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
747 struct dmub_notification *notify)
748{
749 if (adev->dm.dmub_notify)
750 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
751 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
752 complete(&adev->dm.dmub_aux_transfer_done);
753}
754
755static void dmub_aux_fused_io_callback(struct amdgpu_device *adev,
756 struct dmub_notification *notify)
757{
758 if (!adev || !notify) {
759 ASSERT(false);
760 return;
761 }
762
763 const struct dmub_cmd_fused_request *req = &notify->fused_request;
764 const uint8_t ddc_line = req->u.aux.ddc_line;
765
766 if (ddc_line >= ARRAY_SIZE(adev->dm.fused_io)) {
767 ASSERT(false);
768 return;
769 }
770
771 struct fused_io_sync *sync = &adev->dm.fused_io[ddc_line];
772
773 static_assert(sizeof(*req) <= sizeof(sync->reply_data), "Size mismatch");
774 memcpy(sync->reply_data, req, sizeof(*req));
775 complete(&sync->replied);
776}
777
778/**
779 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
780 * @adev: amdgpu_device pointer
781 * @notify: dmub notification structure
782 *
783 * Dmub Hpd interrupt processing callback. Gets displayindex through the
784 * ink index and calls helper to do the processing.
785 */
786static void dmub_hpd_callback(struct amdgpu_device *adev,
787 struct dmub_notification *notify)
788{
789 struct amdgpu_dm_connector *aconnector;
790 struct amdgpu_dm_connector *hpd_aconnector = NULL;
791 struct drm_connector *connector;
792 struct drm_connector_list_iter iter;
793 struct dc_link *link;
794 u8 link_index = 0;
795 struct drm_device *dev;
796
797 if (adev == NULL)
798 return;
799
800 if (notify == NULL) {
801 drm_err(adev_to_drm(adev), "DMUB HPD callback notification was NULL");
802 return;
803 }
804
805 if (notify->link_index > adev->dm.dc->link_count) {
806 drm_err(adev_to_drm(adev), "DMUB HPD index (%u)is abnormal", notify->link_index);
807 return;
808 }
809
810 /* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */
811 if (notify->type == DMUB_NOTIFICATION_HPD && adev->in_suspend) {
812 drm_info(adev_to_drm(adev), "Skip DMUB HPD IRQ callback in suspend/resume\n");
813 return;
814 }
815
816 link_index = notify->link_index;
817 link = adev->dm.dc->links[link_index];
818 dev = adev->dm.ddev;
819
820 drm_connector_list_iter_begin(dev, &iter);
821 drm_for_each_connector_iter(connector, &iter) {
822
823 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
824 continue;
825
826 aconnector = to_amdgpu_dm_connector(connector);
827 if (link && aconnector->dc_link == link) {
828 if (notify->type == DMUB_NOTIFICATION_HPD)
829 drm_info(adev_to_drm(adev), "DMUB HPD IRQ callback: link_index=%u\n", link_index);
830 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
831 drm_info(adev_to_drm(adev), "DMUB HPD RX IRQ callback: link_index=%u\n", link_index);
832 else
833 drm_warn(adev_to_drm(adev), "DMUB Unknown HPD callback type %d, link_index=%u\n",
834 notify->type, link_index);
835
836 hpd_aconnector = aconnector;
837 break;
838 }
839 }
840 drm_connector_list_iter_end(&iter);
841
842 if (hpd_aconnector) {
843 if (notify->type == DMUB_NOTIFICATION_HPD) {
844 if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG))
845 drm_warn(adev_to_drm(adev), "DMUB reported hpd status unchanged. link_index=%u\n", link_index);
846 handle_hpd_irq_helper(hpd_aconnector);
847 } else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) {
848 handle_hpd_rx_irq(hpd_aconnector);
849 }
850 }
851}
852
853/**
854 * dmub_hpd_sense_callback - DMUB HPD sense processing callback.
855 * @adev: amdgpu_device pointer
856 * @notify: dmub notification structure
857 *
858 * HPD sense changes can occur during low power states and need to be
859 * notified from firmware to driver.
860 */
861static void dmub_hpd_sense_callback(struct amdgpu_device *adev,
862 struct dmub_notification *notify)
863{
864 drm_dbg_driver(adev_to_drm(adev), "DMUB HPD SENSE callback.\n");
865}
866
867/**
868 * register_dmub_notify_callback - Sets callback for DMUB notify
869 * @adev: amdgpu_device pointer
870 * @type: Type of dmub notification
871 * @callback: Dmub interrupt callback function
872 * @dmub_int_thread_offload: offload indicator
873 *
874 * API to register a dmub callback handler for a dmub notification
875 * Also sets indicator whether callback processing to be offloaded.
876 * to dmub interrupt handling thread
877 * Return: true if successfully registered, false if there is existing registration
878 */
879static bool register_dmub_notify_callback(struct amdgpu_device *adev,
880 enum dmub_notification_type type,
881 dmub_notify_interrupt_callback_t callback,
882 bool dmub_int_thread_offload)
883{
884 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
885 adev->dm.dmub_callback[type] = callback;
886 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
887 } else
888 return false;
889
890 return true;
891}
892
893static void dm_handle_hpd_work(struct work_struct *work)
894{
895 struct dmub_hpd_work *dmub_hpd_wrk;
896
897 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
898
899 if (!dmub_hpd_wrk->dmub_notify) {
900 drm_err(adev_to_drm(dmub_hpd_wrk->adev), "dmub_hpd_wrk dmub_notify is NULL");
901 return;
902 }
903
904 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
905 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
906 dmub_hpd_wrk->dmub_notify);
907 }
908
909 kfree(dmub_hpd_wrk->dmub_notify);
910 kfree(dmub_hpd_wrk);
911
912}
913
914static const char *dmub_notification_type_str(enum dmub_notification_type e)
915{
916 switch (e) {
917 case DMUB_NOTIFICATION_NO_DATA:
918 return "NO_DATA";
919 case DMUB_NOTIFICATION_AUX_REPLY:
920 return "AUX_REPLY";
921 case DMUB_NOTIFICATION_HPD:
922 return "HPD";
923 case DMUB_NOTIFICATION_HPD_IRQ:
924 return "HPD_IRQ";
925 case DMUB_NOTIFICATION_SET_CONFIG_REPLY:
926 return "SET_CONFIG_REPLY";
927 case DMUB_NOTIFICATION_DPIA_NOTIFICATION:
928 return "DPIA_NOTIFICATION";
929 case DMUB_NOTIFICATION_HPD_SENSE_NOTIFY:
930 return "HPD_SENSE_NOTIFY";
931 case DMUB_NOTIFICATION_FUSED_IO:
932 return "FUSED_IO";
933 default:
934 return "<unknown>";
935 }
936}
937
938#define DMUB_TRACE_MAX_READ 64
939/**
940 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
941 * @interrupt_params: used for determining the Outbox instance
942 *
943 * Handles the Outbox Interrupt
944 * event handler.
945 */
946static void dm_dmub_outbox1_low_irq(void *interrupt_params)
947{
948 struct dmub_notification notify = {0};
949 struct common_irq_params *irq_params = interrupt_params;
950 struct amdgpu_device *adev = irq_params->adev;
951 struct amdgpu_display_manager *dm = &adev->dm;
952 struct dmcub_trace_buf_entry entry = { 0 };
953 u32 count = 0;
954 struct dmub_hpd_work *dmub_hpd_wrk;
955
956 do {
957 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
958 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
959 entry.param0, entry.param1);
960
961 drm_dbg_driver(adev_to_drm(adev), "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
962 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
963 } else
964 break;
965
966 count++;
967
968 } while (count <= DMUB_TRACE_MAX_READ);
969
970 if (count > DMUB_TRACE_MAX_READ)
971 drm_dbg_driver(adev_to_drm(adev), "Warning : count > DMUB_TRACE_MAX_READ");
972
973 if (dc_enable_dmub_notifications(adev->dm.dc) &&
974 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
975
976 do {
977 dc_stat_get_dmub_notification(adev->dm.dc, &notify);
978 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
979 drm_err(adev_to_drm(adev), "DM: notify type %d invalid!", notify.type);
980 continue;
981 }
982 if (!dm->dmub_callback[notify.type]) {
983 drm_warn(adev_to_drm(adev), "DMUB notification skipped due to no handler: type=%s\n",
984 dmub_notification_type_str(notify.type));
985 continue;
986 }
987 if (dm->dmub_thread_offload[notify.type] == true) {
988 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
989 if (!dmub_hpd_wrk) {
990 drm_err(adev_to_drm(adev), "Failed to allocate dmub_hpd_wrk");
991 return;
992 }
993 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
994 GFP_ATOMIC);
995 if (!dmub_hpd_wrk->dmub_notify) {
996 kfree(dmub_hpd_wrk);
997 drm_err(adev_to_drm(adev), "Failed to allocate dmub_hpd_wrk->dmub_notify");
998 return;
999 }
1000 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
1001 dmub_hpd_wrk->adev = adev;
1002 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
1003 } else {
1004 dm->dmub_callback[notify.type](adev, &notify);
1005 }
1006 } while (notify.pending_notification);
1007 }
1008}
1009
1010static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1011 enum amd_clockgating_state state)
1012{
1013 return 0;
1014}
1015
1016static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
1017 enum amd_powergating_state state)
1018{
1019 return 0;
1020}
1021
1022/* Prototypes of private functions */
1023static int dm_early_init(struct amdgpu_ip_block *ip_block);
1024
1025/* Allocate memory for FBC compressed data */
1026static void amdgpu_dm_fbc_init(struct drm_connector *connector)
1027{
1028 struct amdgpu_device *adev = drm_to_adev(connector->dev);
1029 struct dm_compressor_info *compressor = &adev->dm.compressor;
1030 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
1031 struct drm_display_mode *mode;
1032 unsigned long max_size = 0;
1033
1034 if (adev->dm.dc->fbc_compressor == NULL)
1035 return;
1036
1037 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
1038 return;
1039
1040 if (compressor->bo_ptr)
1041 return;
1042
1043
1044 list_for_each_entry(mode, &connector->modes, head) {
1045 if (max_size < (unsigned long) mode->htotal * mode->vtotal)
1046 max_size = (unsigned long) mode->htotal * mode->vtotal;
1047 }
1048
1049 if (max_size) {
1050 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
1051 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
1052 &compressor->gpu_addr, &compressor->cpu_addr);
1053
1054 if (r)
1055 drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n");
1056 else {
1057 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
1058 drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4);
1059 }
1060
1061 }
1062
1063}
1064
1065static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
1066 int pipe, bool *enabled,
1067 unsigned char *buf, int max_bytes)
1068{
1069 struct drm_device *dev = dev_get_drvdata(kdev);
1070 struct amdgpu_device *adev = drm_to_adev(dev);
1071 struct drm_connector *connector;
1072 struct drm_connector_list_iter conn_iter;
1073 struct amdgpu_dm_connector *aconnector;
1074 int ret = 0;
1075
1076 *enabled = false;
1077
1078 mutex_lock(&adev->dm.audio_lock);
1079
1080 drm_connector_list_iter_begin(dev, &conn_iter);
1081 drm_for_each_connector_iter(connector, &conn_iter) {
1082
1083 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
1084 continue;
1085
1086 aconnector = to_amdgpu_dm_connector(connector);
1087 if (aconnector->audio_inst != port)
1088 continue;
1089
1090 *enabled = true;
1091 mutex_lock(&connector->eld_mutex);
1092 ret = drm_eld_size(connector->eld);
1093 memcpy(buf, connector->eld, min(max_bytes, ret));
1094 mutex_unlock(&connector->eld_mutex);
1095
1096 break;
1097 }
1098 drm_connector_list_iter_end(&conn_iter);
1099
1100 mutex_unlock(&adev->dm.audio_lock);
1101
1102 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
1103
1104 return ret;
1105}
1106
1107static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
1108 .get_eld = amdgpu_dm_audio_component_get_eld,
1109};
1110
1111static int amdgpu_dm_audio_component_bind(struct device *kdev,
1112 struct device *hda_kdev, void *data)
1113{
1114 struct drm_device *dev = dev_get_drvdata(kdev);
1115 struct amdgpu_device *adev = drm_to_adev(dev);
1116 struct drm_audio_component *acomp = data;
1117
1118 acomp->ops = &amdgpu_dm_audio_component_ops;
1119 acomp->dev = kdev;
1120 adev->dm.audio_component = acomp;
1121
1122 return 0;
1123}
1124
1125static void amdgpu_dm_audio_component_unbind(struct device *kdev,
1126 struct device *hda_kdev, void *data)
1127{
1128 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
1129 struct drm_audio_component *acomp = data;
1130
1131 acomp->ops = NULL;
1132 acomp->dev = NULL;
1133 adev->dm.audio_component = NULL;
1134}
1135
1136static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1137 .bind = amdgpu_dm_audio_component_bind,
1138 .unbind = amdgpu_dm_audio_component_unbind,
1139};
1140
1141static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1142{
1143 int i, ret;
1144
1145 if (!amdgpu_audio)
1146 return 0;
1147
1148 adev->mode_info.audio.enabled = true;
1149
1150 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1151
1152 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1153 adev->mode_info.audio.pin[i].channels = -1;
1154 adev->mode_info.audio.pin[i].rate = -1;
1155 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1156 adev->mode_info.audio.pin[i].status_bits = 0;
1157 adev->mode_info.audio.pin[i].category_code = 0;
1158 adev->mode_info.audio.pin[i].connected = false;
1159 adev->mode_info.audio.pin[i].id =
1160 adev->dm.dc->res_pool->audios[i]->inst;
1161 adev->mode_info.audio.pin[i].offset = 0;
1162 }
1163
1164 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1165 if (ret < 0)
1166 return ret;
1167
1168 adev->dm.audio_registered = true;
1169
1170 return 0;
1171}
1172
1173static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1174{
1175 if (!amdgpu_audio)
1176 return;
1177
1178 if (!adev->mode_info.audio.enabled)
1179 return;
1180
1181 if (adev->dm.audio_registered) {
1182 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1183 adev->dm.audio_registered = false;
1184 }
1185
1186 /* TODO: Disable audio? */
1187
1188 adev->mode_info.audio.enabled = false;
1189}
1190
1191static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1192{
1193 struct drm_audio_component *acomp = adev->dm.audio_component;
1194
1195 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1196 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1197
1198 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1199 pin, -1);
1200 }
1201}
1202
1203static int dm_dmub_hw_init(struct amdgpu_device *adev)
1204{
1205 const struct dmcub_firmware_header_v1_0 *hdr;
1206 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1207 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1208 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1209 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1210 struct abm *abm = adev->dm.dc->res_pool->abm;
1211 struct dc_context *ctx = adev->dm.dc->ctx;
1212 struct dmub_srv_hw_params hw_params;
1213 enum dmub_status status;
1214 const unsigned char *fw_inst_const, *fw_bss_data;
1215 u32 i, fw_inst_const_size, fw_bss_data_size;
1216 bool has_hw_support;
1217
1218 if (!dmub_srv)
1219 /* DMUB isn't supported on the ASIC. */
1220 return 0;
1221
1222 if (!fb_info) {
1223 drm_err(adev_to_drm(adev), "No framebuffer info for DMUB service.\n");
1224 return -EINVAL;
1225 }
1226
1227 if (!dmub_fw) {
1228 /* Firmware required for DMUB support. */
1229 drm_err(adev_to_drm(adev), "No firmware provided for DMUB.\n");
1230 return -EINVAL;
1231 }
1232
1233 /* initialize register offsets for ASICs with runtime initialization available */
1234 if (dmub_srv->hw_funcs.init_reg_offsets)
1235 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1236
1237 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1238 if (status != DMUB_STATUS_OK) {
1239 drm_err(adev_to_drm(adev), "Error checking HW support for DMUB: %d\n", status);
1240 return -EINVAL;
1241 }
1242
1243 if (!has_hw_support) {
1244 drm_info(adev_to_drm(adev), "DMUB unsupported on ASIC\n");
1245 return 0;
1246 }
1247
1248 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1249 status = dmub_srv_hw_reset(dmub_srv);
1250 if (status != DMUB_STATUS_OK)
1251 drm_warn(adev_to_drm(adev), "Error resetting DMUB HW: %d\n", status);
1252
1253 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1254
1255 fw_inst_const = dmub_fw->data +
1256 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1257 PSP_HEADER_BYTES;
1258
1259 fw_bss_data = dmub_fw->data +
1260 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1261 le32_to_cpu(hdr->inst_const_bytes);
1262
1263 /* Copy firmware and bios info into FB memory. */
1264 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1265 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1266
1267 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1268
1269 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1270 * amdgpu_ucode_init_single_fw will load dmub firmware
1271 * fw_inst_const part to cw0; otherwise, the firmware back door load
1272 * will be done by dm_dmub_hw_init
1273 */
1274 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1275 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1276 fw_inst_const_size);
1277 }
1278
1279 if (fw_bss_data_size)
1280 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1281 fw_bss_data, fw_bss_data_size);
1282
1283 /* Copy firmware bios info into FB memory. */
1284 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1285 adev->bios_size);
1286
1287 /* Reset regions that need to be reset. */
1288 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1289 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1290
1291 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1292 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1293
1294 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1295 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1296
1297 memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0,
1298 fb_info->fb[DMUB_WINDOW_SHARED_STATE].size);
1299
1300 /* Initialize hardware. */
1301 memset(&hw_params, 0, sizeof(hw_params));
1302 hw_params.fb_base = adev->gmc.fb_start;
1303 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1304
1305 /* backdoor load firmware and trigger dmub running */
1306 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1307 hw_params.load_inst_const = true;
1308
1309 if (dmcu)
1310 hw_params.psp_version = dmcu->psp_version;
1311
1312 for (i = 0; i < fb_info->num_fb; ++i)
1313 hw_params.fb[i] = &fb_info->fb[i];
1314
1315 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1316 case IP_VERSION(3, 1, 3):
1317 case IP_VERSION(3, 1, 4):
1318 case IP_VERSION(3, 5, 0):
1319 case IP_VERSION(3, 5, 1):
1320 case IP_VERSION(3, 6, 0):
1321 case IP_VERSION(4, 0, 1):
1322 hw_params.dpia_supported = true;
1323 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1330 case IP_VERSION(3, 5, 0):
1331 case IP_VERSION(3, 5, 1):
1332 case IP_VERSION(3, 6, 0):
1333 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
1334 hw_params.lower_hbr3_phy_ssc = true;
1335 break;
1336 default:
1337 break;
1338 }
1339
1340 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1341 if (status != DMUB_STATUS_OK) {
1342 drm_err(adev_to_drm(adev), "Error initializing DMUB HW: %d\n", status);
1343 return -EINVAL;
1344 }
1345
1346 /* Wait for firmware load to finish. */
1347 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1348 if (status != DMUB_STATUS_OK)
1349 drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status);
1350
1351 /* Init DMCU and ABM if available. */
1352 if (dmcu && abm) {
1353 dmcu->funcs->dmcu_init(dmcu);
1354 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1355 }
1356
1357 if (!adev->dm.dc->ctx->dmub_srv)
1358 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1359 if (!adev->dm.dc->ctx->dmub_srv) {
1360 drm_err(adev_to_drm(adev), "Couldn't allocate DC DMUB server!\n");
1361 return -ENOMEM;
1362 }
1363
1364 drm_info(adev_to_drm(adev), "DMUB hardware initialized: version=0x%08X\n",
1365 adev->dm.dmcub_fw_version);
1366
1367 /* Keeping sanity checks off if
1368 * DCN31 >= 4.0.59.0
1369 * DCN314 >= 8.0.16.0
1370 * Otherwise, turn on sanity checks
1371 */
1372 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1373 case IP_VERSION(3, 1, 2):
1374 case IP_VERSION(3, 1, 3):
1375 if (adev->dm.dmcub_fw_version &&
1376 adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
1377 adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
1378 adev->dm.dc->debug.sanity_checks = true;
1379 break;
1380 case IP_VERSION(3, 1, 4):
1381 if (adev->dm.dmcub_fw_version &&
1382 adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
1383 adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
1384 adev->dm.dc->debug.sanity_checks = true;
1385 break;
1386 default:
1387 break;
1388 }
1389
1390 return 0;
1391}
1392
1393static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1394{
1395 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1396 enum dmub_status status;
1397 bool init;
1398 int r;
1399
1400 if (!dmub_srv) {
1401 /* DMUB isn't supported on the ASIC. */
1402 return;
1403 }
1404
1405 status = dmub_srv_is_hw_init(dmub_srv, &init);
1406 if (status != DMUB_STATUS_OK)
1407 drm_warn(adev_to_drm(adev), "DMUB hardware init check failed: %d\n", status);
1408
1409 if (status == DMUB_STATUS_OK && init) {
1410 /* Wait for firmware load to finish. */
1411 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1412 if (status != DMUB_STATUS_OK)
1413 drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status);
1414 } else {
1415 /* Perform the full hardware initialization. */
1416 r = dm_dmub_hw_init(adev);
1417 if (r)
1418 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);
1419 }
1420}
1421
1422static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1423{
1424 u64 pt_base;
1425 u32 logical_addr_low;
1426 u32 logical_addr_high;
1427 u32 agp_base, agp_bot, agp_top;
1428 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1429
1430 memset(pa_config, 0, sizeof(*pa_config));
1431
1432 agp_base = 0;
1433 agp_bot = adev->gmc.agp_start >> 24;
1434 agp_top = adev->gmc.agp_end >> 24;
1435
1436 /* AGP aperture is disabled */
1437 if (agp_bot > agp_top) {
1438 logical_addr_low = adev->gmc.fb_start >> 18;
1439 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1440 AMD_APU_IS_RENOIR |
1441 AMD_APU_IS_GREEN_SARDINE))
1442 /*
1443 * Raven2 has a HW issue that it is unable to use the vram which
1444 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1445 * workaround that increase system aperture high address (add 1)
1446 * to get rid of the VM fault and hardware hang.
1447 */
1448 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1449 else
1450 logical_addr_high = adev->gmc.fb_end >> 18;
1451 } else {
1452 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1453 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1454 AMD_APU_IS_RENOIR |
1455 AMD_APU_IS_GREEN_SARDINE))
1456 /*
1457 * Raven2 has a HW issue that it is unable to use the vram which
1458 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1459 * workaround that increase system aperture high address (add 1)
1460 * to get rid of the VM fault and hardware hang.
1461 */
1462 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1463 else
1464 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1465 }
1466
1467 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1468
1469 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1470 AMDGPU_GPU_PAGE_SHIFT);
1471 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1472 AMDGPU_GPU_PAGE_SHIFT);
1473 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1474 AMDGPU_GPU_PAGE_SHIFT);
1475 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1476 AMDGPU_GPU_PAGE_SHIFT);
1477 page_table_base.high_part = upper_32_bits(pt_base);
1478 page_table_base.low_part = lower_32_bits(pt_base);
1479
1480 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1481 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1482
1483 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1484 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1485 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1486
1487 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1488 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1489 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1490
1491 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1492 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1493 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1494
1495 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1496
1497}
1498
1499static void force_connector_state(
1500 struct amdgpu_dm_connector *aconnector,
1501 enum drm_connector_force force_state)
1502{
1503 struct drm_connector *connector = &aconnector->base;
1504
1505 mutex_lock(&connector->dev->mode_config.mutex);
1506 aconnector->base.force = force_state;
1507 mutex_unlock(&connector->dev->mode_config.mutex);
1508
1509 mutex_lock(&aconnector->hpd_lock);
1510 drm_kms_helper_connector_hotplug_event(connector);
1511 mutex_unlock(&aconnector->hpd_lock);
1512}
1513
1514static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1515{
1516 struct hpd_rx_irq_offload_work *offload_work;
1517 struct amdgpu_dm_connector *aconnector;
1518 struct dc_link *dc_link;
1519 struct amdgpu_device *adev;
1520 enum dc_connection_type new_connection_type = dc_connection_none;
1521 unsigned long flags;
1522 union test_response test_response;
1523
1524 memset(&test_response, 0, sizeof(test_response));
1525
1526 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1527 aconnector = offload_work->offload_wq->aconnector;
1528 adev = offload_work->adev;
1529
1530 if (!aconnector) {
1531 drm_err(adev_to_drm(adev), "Can't retrieve aconnector in hpd_rx_irq_offload_work");
1532 goto skip;
1533 }
1534
1535 dc_link = aconnector->dc_link;
1536
1537 mutex_lock(&aconnector->hpd_lock);
1538 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1539 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");
1540 mutex_unlock(&aconnector->hpd_lock);
1541
1542 if (new_connection_type == dc_connection_none)
1543 goto skip;
1544
1545 if (amdgpu_in_reset(adev))
1546 goto skip;
1547
1548 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1549 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1550 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1551 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1552 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1553 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1554 goto skip;
1555 }
1556
1557 mutex_lock(&adev->dm.dc_lock);
1558 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1559 dc_link_dp_handle_automated_test(dc_link);
1560
1561 if (aconnector->timing_changed) {
1562 /* force connector disconnect and reconnect */
1563 force_connector_state(aconnector, DRM_FORCE_OFF);
1564 msleep(100);
1565 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1566 }
1567
1568 test_response.bits.ACK = 1;
1569
1570 core_link_write_dpcd(
1571 dc_link,
1572 DP_TEST_RESPONSE,
1573 &test_response.raw,
1574 sizeof(test_response));
1575 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1576 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1577 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1578 /* offload_work->data is from handle_hpd_rx_irq->
1579 * schedule_hpd_rx_offload_work.this is defer handle
1580 * for hpd short pulse. upon here, link status may be
1581 * changed, need get latest link status from dpcd
1582 * registers. if link status is good, skip run link
1583 * training again.
1584 */
1585 union hpd_irq_data irq_data;
1586
1587 memset(&irq_data, 0, sizeof(irq_data));
1588
1589 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1590 * request be added to work queue if link lost at end of dc_link_
1591 * dp_handle_link_loss
1592 */
1593 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1594 offload_work->offload_wq->is_handling_link_loss = false;
1595 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1596
1597 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1598 dc_link_check_link_loss_status(dc_link, &irq_data))
1599 dc_link_dp_handle_link_loss(dc_link);
1600 }
1601 mutex_unlock(&adev->dm.dc_lock);
1602
1603skip:
1604 kfree(offload_work);
1605
1606}
1607
1608static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct amdgpu_device *adev)
1609{
1610 struct dc *dc = adev->dm.dc;
1611 int max_caps = dc->caps.max_links;
1612 int i = 0;
1613 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1614
1615 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1616
1617 if (!hpd_rx_offload_wq)
1618 return NULL;
1619
1620
1621 for (i = 0; i < max_caps; i++) {
1622 hpd_rx_offload_wq[i].wq =
1623 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1624
1625 if (hpd_rx_offload_wq[i].wq == NULL) {
1626 drm_err(adev_to_drm(adev), "create amdgpu_dm_hpd_rx_offload_wq fail!");
1627 goto out_err;
1628 }
1629
1630 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1631 }
1632
1633 return hpd_rx_offload_wq;
1634
1635out_err:
1636 for (i = 0; i < max_caps; i++) {
1637 if (hpd_rx_offload_wq[i].wq)
1638 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1639 }
1640 kfree(hpd_rx_offload_wq);
1641 return NULL;
1642}
1643
1644struct amdgpu_stutter_quirk {
1645 u16 chip_vendor;
1646 u16 chip_device;
1647 u16 subsys_vendor;
1648 u16 subsys_device;
1649 u8 revision;
1650};
1651
1652static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1653 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1654 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1655 { 0, 0, 0, 0, 0 },
1656};
1657
1658static bool dm_should_disable_stutter(struct pci_dev *pdev)
1659{
1660 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1661
1662 while (p && p->chip_device != 0) {
1663 if (pdev->vendor == p->chip_vendor &&
1664 pdev->device == p->chip_device &&
1665 pdev->subsystem_vendor == p->subsys_vendor &&
1666 pdev->subsystem_device == p->subsys_device &&
1667 pdev->revision == p->revision) {
1668 return true;
1669 }
1670 ++p;
1671 }
1672 return false;
1673}
1674
1675
1676void*
1677dm_allocate_gpu_mem(
1678 struct amdgpu_device *adev,
1679 enum dc_gpu_mem_alloc_type type,
1680 size_t size,
1681 long long *addr)
1682{
1683 struct dal_allocation *da;
1684 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1685 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1686 int ret;
1687
1688 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1689 if (!da)
1690 return NULL;
1691
1692 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1693 domain, &da->bo,
1694 &da->gpu_addr, &da->cpu_ptr);
1695
1696 *addr = da->gpu_addr;
1697
1698 if (ret) {
1699 kfree(da);
1700 return NULL;
1701 }
1702
1703 /* add da to list in dm */
1704 list_add(&da->list, &adev->dm.da_list);
1705
1706 return da->cpu_ptr;
1707}
1708
1709void
1710dm_free_gpu_mem(
1711 struct amdgpu_device *adev,
1712 enum dc_gpu_mem_alloc_type type,
1713 void *pvMem)
1714{
1715 struct dal_allocation *da;
1716
1717 /* walk the da list in DM */
1718 list_for_each_entry(da, &adev->dm.da_list, list) {
1719 if (pvMem == da->cpu_ptr) {
1720 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1721 list_del(&da->list);
1722 kfree(da);
1723 break;
1724 }
1725 }
1726
1727}
1728
1729static enum dmub_status
1730dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev,
1731 enum dmub_gpint_command command_code,
1732 uint16_t param,
1733 uint32_t timeout_us)
1734{
1735 union dmub_gpint_data_register reg, test;
1736 uint32_t i;
1737
1738 /* Assume that VBIOS DMUB is ready to take commands */
1739
1740 reg.bits.status = 1;
1741 reg.bits.command_code = command_code;
1742 reg.bits.param = param;
1743
1744 cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all);
1745
1746 for (i = 0; i < timeout_us; ++i) {
1747 udelay(1);
1748
1749 /* Check if our GPINT got acked */
1750 reg.bits.status = 0;
1751 test = (union dmub_gpint_data_register)
1752 cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8);
1753
1754 if (test.all == reg.all)
1755 return DMUB_STATUS_OK;
1756 }
1757
1758 return DMUB_STATUS_TIMEOUT;
1759}
1760
1761static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev)
1762{
1763 struct dml2_soc_bb *bb;
1764 long long addr;
1765 int i = 0;
1766 uint16_t chunk;
1767 enum dmub_gpint_command send_addrs[] = {
1768 DMUB_GPINT__SET_BB_ADDR_WORD0,
1769 DMUB_GPINT__SET_BB_ADDR_WORD1,
1770 DMUB_GPINT__SET_BB_ADDR_WORD2,
1771 DMUB_GPINT__SET_BB_ADDR_WORD3,
1772 };
1773 enum dmub_status ret;
1774
1775 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1776 case IP_VERSION(4, 0, 1):
1777 break;
1778 default:
1779 return NULL;
1780 }
1781
1782 bb = dm_allocate_gpu_mem(adev,
1783 DC_MEM_ALLOC_TYPE_GART,
1784 sizeof(struct dml2_soc_bb),
1785 &addr);
1786 if (!bb)
1787 return NULL;
1788
1789 for (i = 0; i < 4; i++) {
1790 /* Extract 16-bit chunk */
1791 chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF;
1792 /* Send the chunk */
1793 ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000);
1794 if (ret != DMUB_STATUS_OK)
1795 goto free_bb;
1796 }
1797
1798 /* Now ask DMUB to copy the bb */
1799 ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000);
1800 if (ret != DMUB_STATUS_OK)
1801 goto free_bb;
1802
1803 return bb;
1804
1805free_bb:
1806 dm_free_gpu_mem(adev, DC_MEM_ALLOC_TYPE_GART, (void *) bb);
1807 return NULL;
1808
1809}
1810
1811static enum dmub_ips_disable_type dm_get_default_ips_mode(
1812 struct amdgpu_device *adev)
1813{
1814 enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;
1815
1816 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1817 case IP_VERSION(3, 5, 0):
1818 case IP_VERSION(3, 6, 0):
1819 case IP_VERSION(3, 5, 1):
1820 ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1821 break;
1822 default:
1823 /* ASICs older than DCN35 do not have IPSs */
1824 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))
1825 ret = DMUB_IPS_DISABLE_ALL;
1826 break;
1827 }
1828
1829 return ret;
1830}
1831
1832static int amdgpu_dm_init(struct amdgpu_device *adev)
1833{
1834 struct dc_init_data init_data;
1835 struct dc_callback_init init_params;
1836 int r;
1837
1838 adev->dm.ddev = adev_to_drm(adev);
1839 adev->dm.adev = adev;
1840
1841 /* Zero all the fields */
1842 memset(&init_data, 0, sizeof(init_data));
1843 memset(&init_params, 0, sizeof(init_params));
1844
1845 mutex_init(&adev->dm.dpia_aux_lock);
1846 mutex_init(&adev->dm.dc_lock);
1847 mutex_init(&adev->dm.audio_lock);
1848
1849 if (amdgpu_dm_irq_init(adev)) {
1850 drm_err(adev_to_drm(adev), "amdgpu: failed to initialize DM IRQ support.\n");
1851 goto error;
1852 }
1853
1854 init_data.asic_id.chip_family = adev->family;
1855
1856 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1857 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1858 init_data.asic_id.chip_id = adev->pdev->device;
1859
1860 init_data.asic_id.vram_width = adev->gmc.vram_width;
1861 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1862 init_data.asic_id.atombios_base_address =
1863 adev->mode_info.atom_context->bios;
1864
1865 init_data.driver = adev;
1866
1867 /* cgs_device was created in dm_sw_init() */
1868 init_data.cgs_device = adev->dm.cgs_device;
1869
1870 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1871
1872 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1873 case IP_VERSION(2, 1, 0):
1874 switch (adev->dm.dmcub_fw_version) {
1875 case 0: /* development */
1876 case 0x1: /* linux-firmware.git hash 6d9f399 */
1877 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1878 init_data.flags.disable_dmcu = false;
1879 break;
1880 default:
1881 init_data.flags.disable_dmcu = true;
1882 }
1883 break;
1884 case IP_VERSION(2, 0, 3):
1885 init_data.flags.disable_dmcu = true;
1886 break;
1887 default:
1888 break;
1889 }
1890
1891 /* APU support S/G display by default except:
1892 * ASICs before Carrizo,
1893 * RAVEN1 (Users reported stability issue)
1894 */
1895
1896 if (adev->asic_type < CHIP_CARRIZO) {
1897 init_data.flags.gpu_vm_support = false;
1898 } else if (adev->asic_type == CHIP_RAVEN) {
1899 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1900 init_data.flags.gpu_vm_support = false;
1901 else
1902 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1903 } else {
1904 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3))
1905 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1);
1906 else
1907 init_data.flags.gpu_vm_support =
1908 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1909 }
1910
1911 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1912
1913 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1914 init_data.flags.fbc_support = true;
1915
1916 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1917 init_data.flags.multi_mon_pp_mclk_switch = true;
1918
1919 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1920 init_data.flags.disable_fractional_pwm = true;
1921
1922 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1923 init_data.flags.edp_no_power_sequencing = true;
1924
1925 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1926 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1927 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1928 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1929
1930 init_data.flags.seamless_boot_edp_requested = false;
1931
1932 if (amdgpu_device_seamless_boot_supported(adev)) {
1933 init_data.flags.seamless_boot_edp_requested = true;
1934 init_data.flags.allow_seamless_boot_optimization = true;
1935 drm_dbg(adev->dm.ddev, "Seamless boot requested\n");
1936 }
1937
1938 init_data.flags.enable_mipi_converter_optimization = true;
1939
1940 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1941 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1942 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1943
1944 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
1945 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1946 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC)
1947 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC;
1948 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC)
1949 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1950 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE)
1951 init_data.flags.disable_ips = DMUB_IPS_ENABLE;
1952 else
1953 init_data.flags.disable_ips = dm_get_default_ips_mode(adev);
1954
1955 init_data.flags.disable_ips_in_vpb = 0;
1956
1957 /* Enable DWB for tested platforms only */
1958 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
1959 init_data.num_virtual_links = 1;
1960
1961 retrieve_dmi_info(&adev->dm);
1962 if (adev->dm.edp0_on_dp1_quirk)
1963 init_data.flags.support_edp0_on_dp1 = true;
1964
1965 if (adev->dm.bb_from_dmub)
1966 init_data.bb_from_dmub = adev->dm.bb_from_dmub;
1967 else
1968 init_data.bb_from_dmub = NULL;
1969
1970 /* Display Core create. */
1971 adev->dm.dc = dc_create(&init_data);
1972
1973 if (adev->dm.dc) {
1974 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER,
1975 dce_version_to_string(adev->dm.dc->ctx->dce_version));
1976 } else {
1977 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER);
1978 goto error;
1979 }
1980
1981 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1982 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1983 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1984 }
1985
1986 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1987 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1988 if (dm_should_disable_stutter(adev->pdev))
1989 adev->dm.dc->debug.disable_stutter = true;
1990
1991 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1992 adev->dm.dc->debug.disable_stutter = true;
1993
1994 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1995 adev->dm.dc->debug.disable_dsc = true;
1996
1997 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1998 adev->dm.dc->debug.disable_clock_gate = true;
1999
2000 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
2001 adev->dm.dc->debug.force_subvp_mclk_switch = true;
2002
2003 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) {
2004 adev->dm.dc->debug.force_disable_subvp = true;
2005 adev->dm.dc->debug.fams2_config.bits.enable = false;
2006 }
2007
2008 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) {
2009 adev->dm.dc->debug.using_dml2 = true;
2010 adev->dm.dc->debug.using_dml21 = true;
2011 }
2012
2013 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE)
2014 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true;
2015
2016 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK)
2017 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true;
2018
2019 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT)
2020 adev->dm.dc->debug.skip_detection_link_training = true;
2021
2022 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
2023
2024 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
2025 adev->dm.dc->debug.ignore_cable_id = true;
2026
2027 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
2028 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n");
2029
2030 r = dm_dmub_hw_init(adev);
2031 if (r) {
2032 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);
2033 goto error;
2034 }
2035
2036 dc_hardware_init(adev->dm.dc);
2037
2038 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev);
2039 if (!adev->dm.hpd_rx_offload_wq) {
2040 drm_err(adev_to_drm(adev), "amdgpu: failed to create hpd rx offload workqueue.\n");
2041 goto error;
2042 }
2043
2044 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
2045 struct dc_phy_addr_space_config pa_config;
2046
2047 mmhub_read_system_context(adev, &pa_config);
2048
2049 // Call the DC init_memory func
2050 dc_setup_system_context(adev->dm.dc, &pa_config);
2051 }
2052
2053 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
2054 if (!adev->dm.freesync_module) {
2055 drm_err(adev_to_drm(adev),
2056 "amdgpu: failed to initialize freesync_module.\n");
2057 } else
2058 drm_dbg_driver(adev_to_drm(adev), "amdgpu: freesync_module init done %p.\n",
2059 adev->dm.freesync_module);
2060
2061 amdgpu_dm_init_color_mod();
2062
2063 if (adev->dm.dc->caps.max_links > 0) {
2064 adev->dm.vblank_control_workqueue =
2065 create_singlethread_workqueue("dm_vblank_control_workqueue");
2066 if (!adev->dm.vblank_control_workqueue)
2067 drm_err(adev_to_drm(adev), "amdgpu: failed to initialize vblank_workqueue.\n");
2068 }
2069
2070 if (adev->dm.dc->caps.ips_support &&
2071 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)
2072 adev->dm.idle_workqueue = idle_create_workqueue(adev);
2073
2074 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
2075 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
2076
2077 if (!adev->dm.hdcp_workqueue)
2078 drm_err(adev_to_drm(adev), "amdgpu: failed to initialize hdcp_workqueue.\n");
2079 else
2080 drm_dbg_driver(adev_to_drm(adev), "amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
2081
2082 dc_init_callbacks(adev->dm.dc, &init_params);
2083 }
2084 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2085 init_completion(&adev->dm.dmub_aux_transfer_done);
2086 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
2087 if (!adev->dm.dmub_notify) {
2088 drm_info(adev_to_drm(adev), "amdgpu: fail to allocate adev->dm.dmub_notify");
2089 goto error;
2090 }
2091
2092 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
2093 if (!adev->dm.delayed_hpd_wq) {
2094 drm_err(adev_to_drm(adev), "amdgpu: failed to create hpd offload workqueue.\n");
2095 goto error;
2096 }
2097
2098 amdgpu_dm_outbox_init(adev);
2099 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
2100 dmub_aux_setconfig_callback, false)) {
2101 drm_err(adev_to_drm(adev), "amdgpu: fail to register dmub aux callback");
2102 goto error;
2103 }
2104
2105 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++)
2106 init_completion(&adev->dm.fused_io[i].replied);
2107
2108 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO,
2109 dmub_aux_fused_io_callback, false)) {
2110 drm_err(adev_to_drm(adev), "amdgpu: fail to register dmub fused io callback");
2111 goto error;
2112 }
2113 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
2114 * It is expected that DMUB will resend any pending notifications at this point. Note
2115 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to
2116 * align legacy interface initialization sequence. Connection status will be proactivly
2117 * detected once in the amdgpu_dm_initialize_drm_device.
2118 */
2119 dc_enable_dmub_outbox(adev->dm.dc);
2120
2121 /* DPIA trace goes to dmesg logs only if outbox is enabled */
2122 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
2123 dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
2124 }
2125
2126 if (amdgpu_dm_initialize_drm_device(adev)) {
2127 drm_err(adev_to_drm(adev),
2128 "amdgpu: failed to initialize sw for display support.\n");
2129 goto error;
2130 }
2131
2132 /* create fake encoders for MST */
2133 dm_dp_create_fake_mst_encoders(adev);
2134
2135 /* TODO: Add_display_info? */
2136
2137 /* TODO use dynamic cursor width */
2138 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
2139 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
2140
2141 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
2142 drm_err(adev_to_drm(adev),
2143 "amdgpu: failed to initialize sw for display support.\n");
2144 goto error;
2145 }
2146
2147#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
2148 amdgpu_dm_crtc_secure_display_create_contexts(adev);
2149 if (!adev->dm.secure_display_ctx.crtc_ctx)
2150 drm_err(adev_to_drm(adev), "amdgpu: failed to initialize secure display contexts.\n");
2151
2152 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1))
2153 adev->dm.secure_display_ctx.support_mul_roi = true;
2154
2155#endif
2156
2157 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n");
2158
2159 return 0;
2160error:
2161 amdgpu_dm_fini(adev);
2162
2163 return -EINVAL;
2164}
2165
2166static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block)
2167{
2168 struct amdgpu_device *adev = ip_block->adev;
2169
2170 amdgpu_dm_audio_fini(adev);
2171
2172 return 0;
2173}
2174
2175static void amdgpu_dm_fini(struct amdgpu_device *adev)
2176{
2177 int i;
2178
2179 if (adev->dm.vblank_control_workqueue) {
2180 destroy_workqueue(adev->dm.vblank_control_workqueue);
2181 adev->dm.vblank_control_workqueue = NULL;
2182 }
2183
2184 if (adev->dm.idle_workqueue) {
2185 if (adev->dm.idle_workqueue->running) {
2186 adev->dm.idle_workqueue->enable = false;
2187 flush_work(&adev->dm.idle_workqueue->work);
2188 }
2189
2190 kfree(adev->dm.idle_workqueue);
2191 adev->dm.idle_workqueue = NULL;
2192 }
2193
2194 amdgpu_dm_destroy_drm_device(&adev->dm);
2195
2196#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
2197 if (adev->dm.secure_display_ctx.crtc_ctx) {
2198 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2199 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) {
2200 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work);
2201 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work);
2202 }
2203 }
2204 kfree(adev->dm.secure_display_ctx.crtc_ctx);
2205 adev->dm.secure_display_ctx.crtc_ctx = NULL;
2206 }
2207#endif
2208 if (adev->dm.hdcp_workqueue) {
2209 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
2210 adev->dm.hdcp_workqueue = NULL;
2211 }
2212
2213 if (adev->dm.dc) {
2214 dc_deinit_callbacks(adev->dm.dc);
2215 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
2216 if (dc_enable_dmub_notifications(adev->dm.dc)) {
2217 kfree(adev->dm.dmub_notify);
2218 adev->dm.dmub_notify = NULL;
2219 destroy_workqueue(adev->dm.delayed_hpd_wq);
2220 adev->dm.delayed_hpd_wq = NULL;
2221 }
2222 }
2223
2224 if (adev->dm.dmub_bo)
2225 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
2226 &adev->dm.dmub_bo_gpu_addr,
2227 &adev->dm.dmub_bo_cpu_addr);
2228
2229 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
2230 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
2231 if (adev->dm.hpd_rx_offload_wq[i].wq) {
2232 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
2233 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
2234 }
2235 }
2236
2237 kfree(adev->dm.hpd_rx_offload_wq);
2238 adev->dm.hpd_rx_offload_wq = NULL;
2239 }
2240
2241 /* DC Destroy TODO: Replace destroy DAL */
2242 if (adev->dm.dc)
2243 dc_destroy(&adev->dm.dc);
2244 /*
2245 * TODO: pageflip, vlank interrupt
2246 *
2247 * amdgpu_dm_irq_fini(adev);
2248 */
2249
2250 if (adev->dm.cgs_device) {
2251 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
2252 adev->dm.cgs_device = NULL;
2253 }
2254 if (adev->dm.freesync_module) {
2255 mod_freesync_destroy(adev->dm.freesync_module);
2256 adev->dm.freesync_module = NULL;
2257 }
2258
2259 mutex_destroy(&adev->dm.audio_lock);
2260 mutex_destroy(&adev->dm.dc_lock);
2261 mutex_destroy(&adev->dm.dpia_aux_lock);
2262}
2263
2264static int load_dmcu_fw(struct amdgpu_device *adev)
2265{
2266 const char *fw_name_dmcu = NULL;
2267 int r;
2268 const struct dmcu_firmware_header_v1_0 *hdr;
2269
2270 switch (adev->asic_type) {
2271#if defined(CONFIG_DRM_AMD_DC_SI)
2272 case CHIP_TAHITI:
2273 case CHIP_PITCAIRN:
2274 case CHIP_VERDE:
2275 case CHIP_OLAND:
2276#endif
2277 case CHIP_BONAIRE:
2278 case CHIP_HAWAII:
2279 case CHIP_KAVERI:
2280 case CHIP_KABINI:
2281 case CHIP_MULLINS:
2282 case CHIP_TONGA:
2283 case CHIP_FIJI:
2284 case CHIP_CARRIZO:
2285 case CHIP_STONEY:
2286 case CHIP_POLARIS11:
2287 case CHIP_POLARIS10:
2288 case CHIP_POLARIS12:
2289 case CHIP_VEGAM:
2290 case CHIP_VEGA10:
2291 case CHIP_VEGA12:
2292 case CHIP_VEGA20:
2293 return 0;
2294 case CHIP_NAVI12:
2295 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
2296 break;
2297 case CHIP_RAVEN:
2298 if (ASICREV_IS_PICASSO(adev->external_rev_id))
2299 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2300 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2301 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2302 else
2303 return 0;
2304 break;
2305 default:
2306 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2307 case IP_VERSION(2, 0, 2):
2308 case IP_VERSION(2, 0, 3):
2309 case IP_VERSION(2, 0, 0):
2310 case IP_VERSION(2, 1, 0):
2311 case IP_VERSION(3, 0, 0):
2312 case IP_VERSION(3, 0, 2):
2313 case IP_VERSION(3, 0, 3):
2314 case IP_VERSION(3, 0, 1):
2315 case IP_VERSION(3, 1, 2):
2316 case IP_VERSION(3, 1, 3):
2317 case IP_VERSION(3, 1, 4):
2318 case IP_VERSION(3, 1, 5):
2319 case IP_VERSION(3, 1, 6):
2320 case IP_VERSION(3, 2, 0):
2321 case IP_VERSION(3, 2, 1):
2322 case IP_VERSION(3, 5, 0):
2323 case IP_VERSION(3, 5, 1):
2324 case IP_VERSION(3, 6, 0):
2325 case IP_VERSION(4, 0, 1):
2326 return 0;
2327 default:
2328 break;
2329 }
2330 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type);
2331 return -EINVAL;
2332 }
2333
2334 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2335 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2336 return 0;
2337 }
2338
2339 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED,
2340 "%s", fw_name_dmcu);
2341 if (r == -ENODEV) {
2342 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2343 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2344 adev->dm.fw_dmcu = NULL;
2345 return 0;
2346 }
2347 if (r) {
2348 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n",
2349 fw_name_dmcu);
2350 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2351 return r;
2352 }
2353
2354 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2355 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2356 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2357 adev->firmware.fw_size +=
2358 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2359
2360 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2361 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2362 adev->firmware.fw_size +=
2363 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2364
2365 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2366
2367 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2368
2369 return 0;
2370}
2371
2372static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2373{
2374 struct amdgpu_device *adev = ctx;
2375
2376 return dm_read_reg(adev->dm.dc->ctx, address);
2377}
2378
2379static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2380 uint32_t value)
2381{
2382 struct amdgpu_device *adev = ctx;
2383
2384 return dm_write_reg(adev->dm.dc->ctx, address, value);
2385}
2386
2387static int dm_dmub_sw_init(struct amdgpu_device *adev)
2388{
2389 struct dmub_srv_create_params create_params;
2390 struct dmub_srv_region_params region_params;
2391 struct dmub_srv_region_info region_info;
2392 struct dmub_srv_memory_params memory_params;
2393 struct dmub_srv_fb_info *fb_info;
2394 struct dmub_srv *dmub_srv;
2395 const struct dmcub_firmware_header_v1_0 *hdr;
2396 enum dmub_asic dmub_asic;
2397 enum dmub_status status;
2398 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = {
2399 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST
2400 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK
2401 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA
2402 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS
2403 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX
2404 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF
2405 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE
2406 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM
2407 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE
2408 };
2409 int r;
2410
2411 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2412 case IP_VERSION(2, 1, 0):
2413 dmub_asic = DMUB_ASIC_DCN21;
2414 break;
2415 case IP_VERSION(3, 0, 0):
2416 dmub_asic = DMUB_ASIC_DCN30;
2417 break;
2418 case IP_VERSION(3, 0, 1):
2419 dmub_asic = DMUB_ASIC_DCN301;
2420 break;
2421 case IP_VERSION(3, 0, 2):
2422 dmub_asic = DMUB_ASIC_DCN302;
2423 break;
2424 case IP_VERSION(3, 0, 3):
2425 dmub_asic = DMUB_ASIC_DCN303;
2426 break;
2427 case IP_VERSION(3, 1, 2):
2428 case IP_VERSION(3, 1, 3):
2429 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2430 break;
2431 case IP_VERSION(3, 1, 4):
2432 dmub_asic = DMUB_ASIC_DCN314;
2433 break;
2434 case IP_VERSION(3, 1, 5):
2435 dmub_asic = DMUB_ASIC_DCN315;
2436 break;
2437 case IP_VERSION(3, 1, 6):
2438 dmub_asic = DMUB_ASIC_DCN316;
2439 break;
2440 case IP_VERSION(3, 2, 0):
2441 dmub_asic = DMUB_ASIC_DCN32;
2442 break;
2443 case IP_VERSION(3, 2, 1):
2444 dmub_asic = DMUB_ASIC_DCN321;
2445 break;
2446 case IP_VERSION(3, 5, 0):
2447 case IP_VERSION(3, 5, 1):
2448 dmub_asic = DMUB_ASIC_DCN35;
2449 break;
2450 case IP_VERSION(3, 6, 0):
2451 dmub_asic = DMUB_ASIC_DCN36;
2452 break;
2453 case IP_VERSION(4, 0, 1):
2454 dmub_asic = DMUB_ASIC_DCN401;
2455 break;
2456
2457 default:
2458 /* ASIC doesn't support DMUB. */
2459 return 0;
2460 }
2461
2462 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2463 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2464
2465 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2466 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2467 AMDGPU_UCODE_ID_DMCUB;
2468 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2469 adev->dm.dmub_fw;
2470 adev->firmware.fw_size +=
2471 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2472
2473 drm_info(adev_to_drm(adev), "Loading DMUB firmware via PSP: version=0x%08X\n",
2474 adev->dm.dmcub_fw_version);
2475 }
2476
2477
2478 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2479 dmub_srv = adev->dm.dmub_srv;
2480
2481 if (!dmub_srv) {
2482 drm_err(adev_to_drm(adev), "Failed to allocate DMUB service!\n");
2483 return -ENOMEM;
2484 }
2485
2486 memset(&create_params, 0, sizeof(create_params));
2487 create_params.user_ctx = adev;
2488 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2489 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2490 create_params.asic = dmub_asic;
2491
2492 /* Create the DMUB service. */
2493 status = dmub_srv_create(dmub_srv, &create_params);
2494 if (status != DMUB_STATUS_OK) {
2495 drm_err(adev_to_drm(adev), "Error creating DMUB service: %d\n", status);
2496 return -EINVAL;
2497 }
2498
2499 /* Calculate the size of all the regions for the DMUB service. */
2500 memset(&region_params, 0, sizeof(region_params));
2501
2502 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2503 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2504 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2505 region_params.vbios_size = adev->bios_size;
2506 region_params.fw_bss_data = region_params.bss_data_size ?
2507 adev->dm.dmub_fw->data +
2508 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2509 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2510 region_params.fw_inst_const =
2511 adev->dm.dmub_fw->data +
2512 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2513 PSP_HEADER_BYTES;
2514 region_params.window_memory_type = window_memory_type;
2515
2516 status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2517 &region_info);
2518
2519 if (status != DMUB_STATUS_OK) {
2520 drm_err(adev_to_drm(adev), "Error calculating DMUB region info: %d\n", status);
2521 return -EINVAL;
2522 }
2523
2524 /*
2525 * Allocate a framebuffer based on the total size of all the regions.
2526 * TODO: Move this into GART.
2527 */
2528 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2529 AMDGPU_GEM_DOMAIN_VRAM |
2530 AMDGPU_GEM_DOMAIN_GTT,
2531 &adev->dm.dmub_bo,
2532 &adev->dm.dmub_bo_gpu_addr,
2533 &adev->dm.dmub_bo_cpu_addr);
2534 if (r)
2535 return r;
2536
2537 /* Rebase the regions on the framebuffer address. */
2538 memset(&memory_params, 0, sizeof(memory_params));
2539 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2540 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2541 memory_params.region_info = &region_info;
2542 memory_params.window_memory_type = window_memory_type;
2543
2544 adev->dm.dmub_fb_info =
2545 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2546 fb_info = adev->dm.dmub_fb_info;
2547
2548 if (!fb_info) {
2549 drm_err(adev_to_drm(adev),
2550 "Failed to allocate framebuffer info for DMUB service!\n");
2551 return -ENOMEM;
2552 }
2553
2554 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2555 if (status != DMUB_STATUS_OK) {
2556 drm_err(adev_to_drm(adev), "Error calculating DMUB FB info: %d\n", status);
2557 return -EINVAL;
2558 }
2559
2560 adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev);
2561
2562 return 0;
2563}
2564
2565static int dm_sw_init(struct amdgpu_ip_block *ip_block)
2566{
2567 struct amdgpu_device *adev = ip_block->adev;
2568 int r;
2569
2570 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
2571
2572 if (!adev->dm.cgs_device) {
2573 drm_err(adev_to_drm(adev), "amdgpu: failed to create cgs device.\n");
2574 return -EINVAL;
2575 }
2576
2577 /* Moved from dm init since we need to use allocations for storing bounding box data */
2578 INIT_LIST_HEAD(&adev->dm.da_list);
2579
2580 r = dm_dmub_sw_init(adev);
2581 if (r)
2582 return r;
2583
2584 return load_dmcu_fw(adev);
2585}
2586
2587static int dm_sw_fini(struct amdgpu_ip_block *ip_block)
2588{
2589 struct amdgpu_device *adev = ip_block->adev;
2590 struct dal_allocation *da;
2591
2592 list_for_each_entry(da, &adev->dm.da_list, list) {
2593 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) {
2594 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
2595 list_del(&da->list);
2596 kfree(da);
2597 adev->dm.bb_from_dmub = NULL;
2598 break;
2599 }
2600 }
2601
2602
2603 kfree(adev->dm.dmub_fb_info);
2604 adev->dm.dmub_fb_info = NULL;
2605
2606 if (adev->dm.dmub_srv) {
2607 dmub_srv_destroy(adev->dm.dmub_srv);
2608 kfree(adev->dm.dmub_srv);
2609 adev->dm.dmub_srv = NULL;
2610 }
2611
2612 amdgpu_ucode_release(&adev->dm.dmub_fw);
2613 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2614
2615 return 0;
2616}
2617
2618static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2619{
2620 struct amdgpu_dm_connector *aconnector;
2621 struct drm_connector *connector;
2622 struct drm_connector_list_iter iter;
2623 int ret = 0;
2624
2625 drm_connector_list_iter_begin(dev, &iter);
2626 drm_for_each_connector_iter(connector, &iter) {
2627
2628 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2629 continue;
2630
2631 aconnector = to_amdgpu_dm_connector(connector);
2632 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2633 aconnector->mst_mgr.aux) {
2634 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n",
2635 aconnector,
2636 aconnector->base.base.id);
2637
2638 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2639 if (ret < 0) {
2640 drm_err(dev, "DM_MST: Failed to start MST\n");
2641 aconnector->dc_link->type =
2642 dc_connection_single;
2643 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2644 aconnector->dc_link);
2645 break;
2646 }
2647 }
2648 }
2649 drm_connector_list_iter_end(&iter);
2650
2651 return ret;
2652}
2653
2654static int dm_late_init(struct amdgpu_ip_block *ip_block)
2655{
2656 struct amdgpu_device *adev = ip_block->adev;
2657
2658 struct dmcu_iram_parameters params;
2659 unsigned int linear_lut[16];
2660 int i;
2661 struct dmcu *dmcu = NULL;
2662
2663 dmcu = adev->dm.dc->res_pool->dmcu;
2664
2665 for (i = 0; i < 16; i++)
2666 linear_lut[i] = 0xFFFF * i / 15;
2667
2668 params.set = 0;
2669 params.backlight_ramping_override = false;
2670 params.backlight_ramping_start = 0xCCCC;
2671 params.backlight_ramping_reduction = 0xCCCCCCCC;
2672 params.backlight_lut_array_size = 16;
2673 params.backlight_lut_array = linear_lut;
2674
2675 /* Min backlight level after ABM reduction, Don't allow below 1%
2676 * 0xFFFF x 0.01 = 0x28F
2677 */
2678 params.min_abm_backlight = 0x28F;
2679 /* In the case where abm is implemented on dmcub,
2680 * dmcu object will be null.
2681 * ABM 2.4 and up are implemented on dmcub.
2682 */
2683 if (dmcu) {
2684 if (!dmcu_load_iram(dmcu, params))
2685 return -EINVAL;
2686 } else if (adev->dm.dc->ctx->dmub_srv) {
2687 struct dc_link *edp_links[MAX_NUM_EDP];
2688 int edp_num;
2689
2690 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2691 for (i = 0; i < edp_num; i++) {
2692 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2693 return -EINVAL;
2694 }
2695 }
2696
2697 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2698}
2699
2700static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2701{
2702 u8 buf[UUID_SIZE];
2703 guid_t guid;
2704 int ret;
2705
2706 mutex_lock(&mgr->lock);
2707 if (!mgr->mst_primary)
2708 goto out_fail;
2709
2710 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2711 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2712 goto out_fail;
2713 }
2714
2715 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2716 DP_MST_EN |
2717 DP_UP_REQ_EN |
2718 DP_UPSTREAM_IS_SRC);
2719 if (ret < 0) {
2720 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2721 goto out_fail;
2722 }
2723
2724 /* Some hubs forget their guids after they resume */
2725 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf));
2726 if (ret != sizeof(buf)) {
2727 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2728 goto out_fail;
2729 }
2730
2731 import_guid(&guid, buf);
2732
2733 if (guid_is_null(&guid)) {
2734 guid_gen(&guid);
2735 export_guid(buf, &guid);
2736
2737 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));
2738
2739 if (ret != sizeof(buf)) {
2740 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2741 goto out_fail;
2742 }
2743 }
2744
2745 guid_copy(&mgr->mst_primary->guid, &guid);
2746
2747out_fail:
2748 mutex_unlock(&mgr->lock);
2749}
2750
2751void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector)
2752{
2753 struct cec_notifier *n = aconnector->notifier;
2754
2755 if (!n)
2756 return;
2757
2758 cec_notifier_phys_addr_invalidate(n);
2759}
2760
2761void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector)
2762{
2763 struct drm_connector *connector = &aconnector->base;
2764 struct cec_notifier *n = aconnector->notifier;
2765
2766 if (!n)
2767 return;
2768
2769 cec_notifier_set_phys_addr(n,
2770 connector->display_info.source_physical_address);
2771}
2772
2773static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend)
2774{
2775 struct amdgpu_dm_connector *aconnector;
2776 struct drm_connector *connector;
2777 struct drm_connector_list_iter conn_iter;
2778
2779 drm_connector_list_iter_begin(ddev, &conn_iter);
2780 drm_for_each_connector_iter(connector, &conn_iter) {
2781 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2782 continue;
2783
2784 aconnector = to_amdgpu_dm_connector(connector);
2785 if (suspend)
2786 hdmi_cec_unset_edid(aconnector);
2787 else
2788 hdmi_cec_set_edid(aconnector);
2789 }
2790 drm_connector_list_iter_end(&conn_iter);
2791}
2792
2793static void s3_handle_mst(struct drm_device *dev, bool suspend)
2794{
2795 struct amdgpu_dm_connector *aconnector;
2796 struct drm_connector *connector;
2797 struct drm_connector_list_iter iter;
2798 struct drm_dp_mst_topology_mgr *mgr;
2799
2800 drm_connector_list_iter_begin(dev, &iter);
2801 drm_for_each_connector_iter(connector, &iter) {
2802
2803 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2804 continue;
2805
2806 aconnector = to_amdgpu_dm_connector(connector);
2807 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2808 aconnector->mst_root)
2809 continue;
2810
2811 mgr = &aconnector->mst_mgr;
2812
2813 if (suspend) {
2814 drm_dp_mst_topology_mgr_suspend(mgr);
2815 } else {
2816 /* if extended timeout is supported in hardware,
2817 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2818 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2819 */
2820 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2821 if (!dp_is_lttpr_present(aconnector->dc_link))
2822 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2823
2824 /* TODO: move resume_mst_branch_status() into drm mst resume again
2825 * once topology probing work is pulled out from mst resume into mst
2826 * resume 2nd step. mst resume 2nd step should be called after old
2827 * state getting restored (i.e. drm_atomic_helper_resume()).
2828 */
2829 resume_mst_branch_status(mgr);
2830 }
2831 }
2832 drm_connector_list_iter_end(&iter);
2833}
2834
2835static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2836{
2837 int ret = 0;
2838
2839 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2840 * on window driver dc implementation.
2841 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2842 * should be passed to smu during boot up and resume from s3.
2843 * boot up: dc calculate dcn watermark clock settings within dc_create,
2844 * dcn20_resource_construct
2845 * then call pplib functions below to pass the settings to smu:
2846 * smu_set_watermarks_for_clock_ranges
2847 * smu_set_watermarks_table
2848 * navi10_set_watermarks_table
2849 * smu_write_watermarks_table
2850 *
2851 * For Renoir, clock settings of dcn watermark are also fixed values.
2852 * dc has implemented different flow for window driver:
2853 * dc_hardware_init / dc_set_power_state
2854 * dcn10_init_hw
2855 * notify_wm_ranges
2856 * set_wm_ranges
2857 * -- Linux
2858 * smu_set_watermarks_for_clock_ranges
2859 * renoir_set_watermarks_table
2860 * smu_write_watermarks_table
2861 *
2862 * For Linux,
2863 * dc_hardware_init -> amdgpu_dm_init
2864 * dc_set_power_state --> dm_resume
2865 *
2866 * therefore, this function apply to navi10/12/14 but not Renoir
2867 * *
2868 */
2869 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2870 case IP_VERSION(2, 0, 2):
2871 case IP_VERSION(2, 0, 0):
2872 break;
2873 default:
2874 return 0;
2875 }
2876
2877 ret = amdgpu_dpm_write_watermarks_table(adev);
2878 if (ret) {
2879 drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n");
2880 return ret;
2881 }
2882
2883 return 0;
2884}
2885
2886static int dm_oem_i2c_hw_init(struct amdgpu_device *adev)
2887{
2888 struct amdgpu_display_manager *dm = &adev->dm;
2889 struct amdgpu_i2c_adapter *oem_i2c;
2890 struct ddc_service *oem_ddc_service;
2891 int r;
2892
2893 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc);
2894 if (oem_ddc_service) {
2895 oem_i2c = create_i2c(oem_ddc_service, true);
2896 if (!oem_i2c) {
2897 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n");
2898 return -ENOMEM;
2899 }
2900
2901 r = i2c_add_adapter(&oem_i2c->base);
2902 if (r) {
2903 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n");
2904 kfree(oem_i2c);
2905 return r;
2906 }
2907 dm->oem_i2c = oem_i2c;
2908 }
2909
2910 return 0;
2911}
2912
2913/**
2914 * dm_hw_init() - Initialize DC device
2915 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
2916 *
2917 * Initialize the &struct amdgpu_display_manager device. This involves calling
2918 * the initializers of each DM component, then populating the struct with them.
2919 *
2920 * Although the function implies hardware initialization, both hardware and
2921 * software are initialized here. Splitting them out to their relevant init
2922 * hooks is a future TODO item.
2923 *
2924 * Some notable things that are initialized here:
2925 *
2926 * - Display Core, both software and hardware
2927 * - DC modules that we need (freesync and color management)
2928 * - DRM software states
2929 * - Interrupt sources and handlers
2930 * - Vblank support
2931 * - Debug FS entries, if enabled
2932 */
2933static int dm_hw_init(struct amdgpu_ip_block *ip_block)
2934{
2935 struct amdgpu_device *adev = ip_block->adev;
2936 int r;
2937
2938 /* Create DAL display manager */
2939 r = amdgpu_dm_init(adev);
2940 if (r)
2941 return r;
2942 amdgpu_dm_hpd_init(adev);
2943
2944 r = dm_oem_i2c_hw_init(adev);
2945 if (r)
2946 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n");
2947
2948 return 0;
2949}
2950
2951/**
2952 * dm_hw_fini() - Teardown DC device
2953 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
2954 *
2955 * Teardown components within &struct amdgpu_display_manager that require
2956 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2957 * were loaded. Also flush IRQ workqueues and disable them.
2958 */
2959static int dm_hw_fini(struct amdgpu_ip_block *ip_block)
2960{
2961 struct amdgpu_device *adev = ip_block->adev;
2962
2963 kfree(adev->dm.oem_i2c);
2964
2965 amdgpu_dm_hpd_fini(adev);
2966
2967 amdgpu_dm_irq_fini(adev);
2968 amdgpu_dm_fini(adev);
2969 return 0;
2970}
2971
2972
2973static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2974 struct dc_state *state, bool enable)
2975{
2976 enum dc_irq_source irq_source;
2977 struct amdgpu_crtc *acrtc;
2978 int rc = -EBUSY;
2979 int i = 0;
2980
2981 for (i = 0; i < state->stream_count; i++) {
2982 acrtc = get_crtc_by_otg_inst(
2983 adev, state->stream_status[i].primary_otg_inst);
2984
2985 if (acrtc && state->stream_status[i].plane_count != 0) {
2986 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2987 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2988 if (rc)
2989 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n",
2990 enable ? "enable" : "disable");
2991
2992 if (enable) {
2993 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2994 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2995 } else
2996 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2997
2998 if (rc)
2999 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
3000
3001 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3002 /* During gpu-reset we disable and then enable vblank irq, so
3003 * don't use amdgpu_irq_get/put() to avoid refcount change.
3004 */
3005 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
3006 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
3007 }
3008 }
3009
3010}
3011
3012DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T))
3013
3014static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
3015{
3016 struct dc_state *context __free(state_release) = NULL;
3017 int i;
3018 struct dc_stream_state *del_streams[MAX_PIPES];
3019 int del_streams_count = 0;
3020 struct dc_commit_streams_params params = {};
3021
3022 memset(del_streams, 0, sizeof(del_streams));
3023
3024 context = dc_state_create_current_copy(dc);
3025 if (context == NULL)
3026 return DC_ERROR_UNEXPECTED;
3027
3028 /* First remove from context all streams */
3029 for (i = 0; i < context->stream_count; i++) {
3030 struct dc_stream_state *stream = context->streams[i];
3031
3032 del_streams[del_streams_count++] = stream;
3033 }
3034
3035 /* Remove all planes for removed streams and then remove the streams */
3036 for (i = 0; i < del_streams_count; i++) {
3037 enum dc_status res;
3038
3039 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context))
3040 return DC_FAIL_DETACH_SURFACES;
3041
3042 res = dc_state_remove_stream(dc, context, del_streams[i]);
3043 if (res != DC_OK)
3044 return res;
3045 }
3046
3047 params.streams = context->streams;
3048 params.stream_count = context->stream_count;
3049
3050 return dc_commit_streams(dc, &params);
3051}
3052
3053static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
3054{
3055 int i;
3056
3057 if (dm->hpd_rx_offload_wq) {
3058 for (i = 0; i < dm->dc->caps.max_links; i++)
3059 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
3060 }
3061}
3062
3063static int dm_prepare_suspend(struct amdgpu_ip_block *ip_block)
3064{
3065 struct amdgpu_device *adev = ip_block->adev;
3066
3067 if (amdgpu_in_reset(adev))
3068 return 0;
3069
3070 WARN_ON(adev->dm.cached_state);
3071 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
3072 if (IS_ERR(adev->dm.cached_state))
3073 return PTR_ERR(adev->dm.cached_state);
3074
3075 return 0;
3076}
3077
3078static int dm_suspend(struct amdgpu_ip_block *ip_block)
3079{
3080 struct amdgpu_device *adev = ip_block->adev;
3081 struct amdgpu_display_manager *dm = &adev->dm;
3082
3083 if (amdgpu_in_reset(adev)) {
3084 enum dc_status res;
3085
3086 mutex_lock(&dm->dc_lock);
3087
3088 dc_allow_idle_optimizations(adev->dm.dc, false);
3089
3090 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
3091
3092 if (dm->cached_dc_state)
3093 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
3094
3095 res = amdgpu_dm_commit_zero_streams(dm->dc);
3096 if (res != DC_OK) {
3097 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res);
3098 return -EINVAL;
3099 }
3100
3101 amdgpu_dm_irq_suspend(adev);
3102
3103 hpd_rx_irq_work_suspend(dm);
3104
3105 return 0;
3106 }
3107
3108 if (!adev->dm.cached_state) {
3109 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
3110 if (IS_ERR(adev->dm.cached_state))
3111 return PTR_ERR(adev->dm.cached_state);
3112 }
3113
3114 s3_handle_hdmi_cec(adev_to_drm(adev), true);
3115
3116 s3_handle_mst(adev_to_drm(adev), true);
3117
3118 amdgpu_dm_irq_suspend(adev);
3119
3120 hpd_rx_irq_work_suspend(dm);
3121
3122 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
3123
3124 if (dm->dc->caps.ips_support && adev->in_s0ix)
3125 dc_allow_idle_optimizations(dm->dc, true);
3126
3127 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
3128
3129 return 0;
3130}
3131
3132struct drm_connector *
3133amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
3134 struct drm_crtc *crtc)
3135{
3136 u32 i;
3137 struct drm_connector_state *new_con_state;
3138 struct drm_connector *connector;
3139 struct drm_crtc *crtc_from_state;
3140
3141 for_each_new_connector_in_state(state, connector, new_con_state, i) {
3142 crtc_from_state = new_con_state->crtc;
3143
3144 if (crtc_from_state == crtc)
3145 return connector;
3146 }
3147
3148 return NULL;
3149}
3150
3151static void emulated_link_detect(struct dc_link *link)
3152{
3153 struct dc_sink_init_data sink_init_data = { 0 };
3154 struct display_sink_capability sink_caps = { 0 };
3155 enum dc_edid_status edid_status;
3156 struct dc_context *dc_ctx = link->ctx;
3157 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
3158 struct dc_sink *sink = NULL;
3159 struct dc_sink *prev_sink = NULL;
3160
3161 link->type = dc_connection_none;
3162 prev_sink = link->local_sink;
3163
3164 if (prev_sink)
3165 dc_sink_release(prev_sink);
3166
3167 switch (link->connector_signal) {
3168 case SIGNAL_TYPE_HDMI_TYPE_A: {
3169 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3170 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
3171 break;
3172 }
3173
3174 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
3175 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3176 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
3177 break;
3178 }
3179
3180 case SIGNAL_TYPE_DVI_DUAL_LINK: {
3181 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3182 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
3183 break;
3184 }
3185
3186 case SIGNAL_TYPE_LVDS: {
3187 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3188 sink_caps.signal = SIGNAL_TYPE_LVDS;
3189 break;
3190 }
3191
3192 case SIGNAL_TYPE_EDP: {
3193 sink_caps.transaction_type =
3194 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
3195 sink_caps.signal = SIGNAL_TYPE_EDP;
3196 break;
3197 }
3198
3199 case SIGNAL_TYPE_DISPLAY_PORT: {
3200 sink_caps.transaction_type =
3201 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
3202 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
3203 break;
3204 }
3205
3206 default:
3207 drm_err(dev, "Invalid connector type! signal:%d\n",
3208 link->connector_signal);
3209 return;
3210 }
3211
3212 sink_init_data.link = link;
3213 sink_init_data.sink_signal = sink_caps.signal;
3214
3215 sink = dc_sink_create(&sink_init_data);
3216 if (!sink) {
3217 drm_err(dev, "Failed to create sink!\n");
3218 return;
3219 }
3220
3221 /* dc_sink_create returns a new reference */
3222 link->local_sink = sink;
3223
3224 edid_status = dm_helpers_read_local_edid(
3225 link->ctx,
3226 link,
3227 sink);
3228
3229 if (edid_status != EDID_OK)
3230 drm_err(dev, "Failed to read EDID\n");
3231
3232}
3233
3234static void dm_gpureset_commit_state(struct dc_state *dc_state,
3235 struct amdgpu_display_manager *dm)
3236{
3237 struct {
3238 struct dc_surface_update surface_updates[MAX_SURFACES];
3239 struct dc_plane_info plane_infos[MAX_SURFACES];
3240 struct dc_scaling_info scaling_infos[MAX_SURFACES];
3241 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
3242 struct dc_stream_update stream_update;
3243 } *bundle __free(kfree);
3244 int k, m;
3245
3246 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
3247
3248 if (!bundle) {
3249 drm_err(dm->ddev, "Failed to allocate update bundle\n");
3250 return;
3251 }
3252
3253 for (k = 0; k < dc_state->stream_count; k++) {
3254 bundle->stream_update.stream = dc_state->streams[k];
3255
3256 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) {
3257 bundle->surface_updates[m].surface =
3258 dc_state->stream_status[k].plane_states[m];
3259 bundle->surface_updates[m].surface->force_full_update =
3260 true;
3261 }
3262
3263 update_planes_and_stream_adapter(dm->dc,
3264 UPDATE_TYPE_FULL,
3265 dc_state->stream_status[k].plane_count,
3266 dc_state->streams[k],
3267 &bundle->stream_update,
3268 bundle->surface_updates);
3269 }
3270}
3271
3272static void apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev,
3273 struct dc_sink *sink)
3274{
3275 struct dc_panel_patch *ppatch = NULL;
3276
3277 if (!sink)
3278 return;
3279
3280 ppatch = &sink->edid_caps.panel_patch;
3281 if (ppatch->wait_after_dpcd_poweroff_ms) {
3282 msleep(ppatch->wait_after_dpcd_poweroff_ms);
3283 drm_dbg_driver(adev_to_drm(adev),
3284 "%s: adding a %ds delay as w/a for panel\n",
3285 __func__,
3286 ppatch->wait_after_dpcd_poweroff_ms / 1000);
3287 }
3288}
3289
3290static int dm_resume(struct amdgpu_ip_block *ip_block)
3291{
3292 struct amdgpu_device *adev = ip_block->adev;
3293 struct drm_device *ddev = adev_to_drm(adev);
3294 struct amdgpu_display_manager *dm = &adev->dm;
3295 struct amdgpu_dm_connector *aconnector;
3296 struct drm_connector *connector;
3297 struct drm_connector_list_iter iter;
3298 struct drm_crtc *crtc;
3299 struct drm_crtc_state *new_crtc_state;
3300 struct dm_crtc_state *dm_new_crtc_state;
3301 struct drm_plane *plane;
3302 struct drm_plane_state *new_plane_state;
3303 struct dm_plane_state *dm_new_plane_state;
3304 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
3305 enum dc_connection_type new_connection_type = dc_connection_none;
3306 struct dc_state *dc_state;
3307 int i, r, j;
3308 struct dc_commit_streams_params commit_params = {};
3309
3310 if (dm->dc->caps.ips_support) {
3311 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
3312 }
3313
3314 if (amdgpu_in_reset(adev)) {
3315 dc_state = dm->cached_dc_state;
3316
3317 /*
3318 * The dc->current_state is backed up into dm->cached_dc_state
3319 * before we commit 0 streams.
3320 *
3321 * DC will clear link encoder assignments on the real state
3322 * but the changes won't propagate over to the copy we made
3323 * before the 0 streams commit.
3324 *
3325 * DC expects that link encoder assignments are *not* valid
3326 * when committing a state, so as a workaround we can copy
3327 * off of the current state.
3328 *
3329 * We lose the previous assignments, but we had already
3330 * commit 0 streams anyway.
3331 */
3332 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
3333
3334 r = dm_dmub_hw_init(adev);
3335 if (r)
3336 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);
3337
3338 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
3339 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
3340
3341 dc_resume(dm->dc);
3342
3343 amdgpu_dm_irq_resume_early(adev);
3344
3345 for (i = 0; i < dc_state->stream_count; i++) {
3346 dc_state->streams[i]->mode_changed = true;
3347 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
3348 dc_state->stream_status[i].plane_states[j]->update_flags.raw
3349 = 0xffffffff;
3350 }
3351 }
3352
3353 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
3354 amdgpu_dm_outbox_init(adev);
3355 dc_enable_dmub_outbox(adev->dm.dc);
3356 }
3357
3358 commit_params.streams = dc_state->streams;
3359 commit_params.stream_count = dc_state->stream_count;
3360 dc_exit_ips_for_hw_access(dm->dc);
3361 WARN_ON(!dc_commit_streams(dm->dc, &commit_params));
3362
3363 dm_gpureset_commit_state(dm->cached_dc_state, dm);
3364
3365 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
3366
3367 dc_state_release(dm->cached_dc_state);
3368 dm->cached_dc_state = NULL;
3369
3370 amdgpu_dm_irq_resume_late(adev);
3371
3372 mutex_unlock(&dm->dc_lock);
3373
3374 /* set the backlight after a reset */
3375 for (i = 0; i < dm->num_of_edps; i++) {
3376 if (dm->backlight_dev[i])
3377 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
3378 }
3379
3380 return 0;
3381 }
3382 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
3383 dc_state_release(dm_state->context);
3384 dm_state->context = dc_state_create(dm->dc, NULL);
3385 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
3386
3387 /* Before powering on DC we need to re-initialize DMUB. */
3388 dm_dmub_hw_resume(adev);
3389
3390 /* Re-enable outbox interrupts for DPIA. */
3391 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
3392 amdgpu_dm_outbox_init(adev);
3393 dc_enable_dmub_outbox(adev->dm.dc);
3394 }
3395
3396 /* power on hardware */
3397 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
3398 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
3399
3400 /* program HPD filter */
3401 dc_resume(dm->dc);
3402
3403 /*
3404 * early enable HPD Rx IRQ, should be done before set mode as short
3405 * pulse interrupts are used for MST
3406 */
3407 amdgpu_dm_irq_resume_early(adev);
3408
3409 s3_handle_hdmi_cec(ddev, false);
3410
3411 /* On resume we need to rewrite the MSTM control bits to enable MST*/
3412 s3_handle_mst(ddev, false);
3413
3414 /* Do detection*/
3415 drm_connector_list_iter_begin(ddev, &iter);
3416 drm_for_each_connector_iter(connector, &iter) {
3417 bool ret;
3418
3419 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3420 continue;
3421
3422 aconnector = to_amdgpu_dm_connector(connector);
3423
3424 if (!aconnector->dc_link)
3425 continue;
3426
3427 /*
3428 * this is the case when traversing through already created end sink
3429 * MST connectors, should be skipped
3430 */
3431 if (aconnector->mst_root)
3432 continue;
3433
3434 guard(mutex)(&aconnector->hpd_lock);
3435 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3436 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");
3437
3438 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3439 emulated_link_detect(aconnector->dc_link);
3440 } else {
3441 guard(mutex)(&dm->dc_lock);
3442 dc_exit_ips_for_hw_access(dm->dc);
3443 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4);
3444 if (ret) {
3445 /* w/a delay for certain panels */
3446 apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink);
3447 }
3448 }
3449
3450 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
3451 aconnector->fake_enable = false;
3452
3453 if (aconnector->dc_sink)
3454 dc_sink_release(aconnector->dc_sink);
3455 aconnector->dc_sink = NULL;
3456 amdgpu_dm_update_connector_after_detect(aconnector);
3457 }
3458 drm_connector_list_iter_end(&iter);
3459
3460 /* Force mode set in atomic commit */
3461 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3462 new_crtc_state->active_changed = true;
3463 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3464 reset_freesync_config_for_crtc(dm_new_crtc_state);
3465 }
3466
3467 /*
3468 * atomic_check is expected to create the dc states. We need to release
3469 * them here, since they were duplicated as part of the suspend
3470 * procedure.
3471 */
3472 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3473 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3474 if (dm_new_crtc_state->stream) {
3475 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
3476 dc_stream_release(dm_new_crtc_state->stream);
3477 dm_new_crtc_state->stream = NULL;
3478 }
3479 dm_new_crtc_state->base.color_mgmt_changed = true;
3480 }
3481
3482 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
3483 dm_new_plane_state = to_dm_plane_state(new_plane_state);
3484 if (dm_new_plane_state->dc_state) {
3485 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
3486 dc_plane_state_release(dm_new_plane_state->dc_state);
3487 dm_new_plane_state->dc_state = NULL;
3488 }
3489 }
3490
3491 drm_atomic_helper_resume(ddev, dm->cached_state);
3492
3493 dm->cached_state = NULL;
3494
3495 /* Do mst topology probing after resuming cached state*/
3496 drm_connector_list_iter_begin(ddev, &iter);
3497 drm_for_each_connector_iter(connector, &iter) {
3498
3499 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3500 continue;
3501
3502 aconnector = to_amdgpu_dm_connector(connector);
3503 if (aconnector->dc_link->type != dc_connection_mst_branch ||
3504 aconnector->mst_root)
3505 continue;
3506
3507 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr);
3508 }
3509 drm_connector_list_iter_end(&iter);
3510
3511 amdgpu_dm_irq_resume_late(adev);
3512
3513 amdgpu_dm_smu_write_watermarks_table(adev);
3514
3515 drm_kms_helper_hotplug_event(ddev);
3516
3517 return 0;
3518}
3519
3520/**
3521 * DOC: DM Lifecycle
3522 *
3523 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3524 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3525 * the base driver's device list to be initialized and torn down accordingly.
3526 *
3527 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3528 */
3529
3530static const struct amd_ip_funcs amdgpu_dm_funcs = {
3531 .name = "dm",
3532 .early_init = dm_early_init,
3533 .late_init = dm_late_init,
3534 .sw_init = dm_sw_init,
3535 .sw_fini = dm_sw_fini,
3536 .early_fini = amdgpu_dm_early_fini,
3537 .hw_init = dm_hw_init,
3538 .hw_fini = dm_hw_fini,
3539 .prepare_suspend = dm_prepare_suspend,
3540 .suspend = dm_suspend,
3541 .resume = dm_resume,
3542 .is_idle = dm_is_idle,
3543 .wait_for_idle = dm_wait_for_idle,
3544 .check_soft_reset = dm_check_soft_reset,
3545 .soft_reset = dm_soft_reset,
3546 .set_clockgating_state = dm_set_clockgating_state,
3547 .set_powergating_state = dm_set_powergating_state,
3548};
3549
3550const struct amdgpu_ip_block_version dm_ip_block = {
3551 .type = AMD_IP_BLOCK_TYPE_DCE,
3552 .major = 1,
3553 .minor = 0,
3554 .rev = 0,
3555 .funcs = &amdgpu_dm_funcs,
3556};
3557
3558
3559/**
3560 * DOC: atomic
3561 *
3562 * *WIP*
3563 */
3564
3565static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3566 .fb_create = amdgpu_display_user_framebuffer_create,
3567 .get_format_info = amdgpu_dm_plane_get_format_info,
3568 .atomic_check = amdgpu_dm_atomic_check,
3569 .atomic_commit = drm_atomic_helper_commit,
3570};
3571
3572static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3573 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3574 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3575};
3576
3577static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3578{
3579 struct amdgpu_dm_backlight_caps *caps;
3580 struct drm_connector *conn_base;
3581 struct amdgpu_device *adev;
3582 struct drm_luminance_range_info *luminance_range;
3583 int min_input_signal_override;
3584
3585 if (aconnector->bl_idx == -1 ||
3586 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3587 return;
3588
3589 conn_base = &aconnector->base;
3590 adev = drm_to_adev(conn_base->dev);
3591
3592 caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3593 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3594 caps->aux_support = false;
3595
3596 if (caps->ext_caps->bits.oled == 1
3597 /*
3598 * ||
3599 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3600 * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3601 */)
3602 caps->aux_support = true;
3603
3604 if (amdgpu_backlight == 0)
3605 caps->aux_support = false;
3606 else if (amdgpu_backlight == 1)
3607 caps->aux_support = true;
3608 if (caps->aux_support)
3609 aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX;
3610
3611 luminance_range = &conn_base->display_info.luminance_range;
3612
3613 if (luminance_range->max_luminance)
3614 caps->aux_max_input_signal = luminance_range->max_luminance;
3615 else
3616 caps->aux_max_input_signal = 512;
3617
3618 if (luminance_range->min_luminance)
3619 caps->aux_min_input_signal = luminance_range->min_luminance;
3620 else
3621 caps->aux_min_input_signal = 1;
3622
3623 min_input_signal_override = drm_get_panel_min_brightness_quirk(aconnector->drm_edid);
3624 if (min_input_signal_override >= 0)
3625 caps->min_input_signal = min_input_signal_override;
3626}
3627
3628DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T))
3629
3630void amdgpu_dm_update_connector_after_detect(
3631 struct amdgpu_dm_connector *aconnector)
3632{
3633 struct drm_connector *connector = &aconnector->base;
3634 struct dc_sink *sink __free(sink_release) = NULL;
3635 struct drm_device *dev = connector->dev;
3636
3637 /* MST handled by drm_mst framework */
3638 if (aconnector->mst_mgr.mst_state == true)
3639 return;
3640
3641 sink = aconnector->dc_link->local_sink;
3642 if (sink)
3643 dc_sink_retain(sink);
3644
3645 /*
3646 * Edid mgmt connector gets first update only in mode_valid hook and then
3647 * the connector sink is set to either fake or physical sink depends on link status.
3648 * Skip if already done during boot.
3649 */
3650 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3651 && aconnector->dc_em_sink) {
3652
3653 /*
3654 * For S3 resume with headless use eml_sink to fake stream
3655 * because on resume connector->sink is set to NULL
3656 */
3657 guard(mutex)(&dev->mode_config.mutex);
3658
3659 if (sink) {
3660 if (aconnector->dc_sink) {
3661 amdgpu_dm_update_freesync_caps(connector, NULL);
3662 /*
3663 * retain and release below are used to
3664 * bump up refcount for sink because the link doesn't point
3665 * to it anymore after disconnect, so on next crtc to connector
3666 * reshuffle by UMD we will get into unwanted dc_sink release
3667 */
3668 dc_sink_release(aconnector->dc_sink);
3669 }
3670 aconnector->dc_sink = sink;
3671 dc_sink_retain(aconnector->dc_sink);
3672 amdgpu_dm_update_freesync_caps(connector,
3673 aconnector->drm_edid);
3674 } else {
3675 amdgpu_dm_update_freesync_caps(connector, NULL);
3676 if (!aconnector->dc_sink) {
3677 aconnector->dc_sink = aconnector->dc_em_sink;
3678 dc_sink_retain(aconnector->dc_sink);
3679 }
3680 }
3681
3682 return;
3683 }
3684
3685 /*
3686 * TODO: temporary guard to look for proper fix
3687 * if this sink is MST sink, we should not do anything
3688 */
3689 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3690 return;
3691
3692 if (aconnector->dc_sink == sink) {
3693 /*
3694 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3695 * Do nothing!!
3696 */
3697 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n",
3698 aconnector->connector_id);
3699 return;
3700 }
3701
3702 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3703 aconnector->connector_id, aconnector->dc_sink, sink);
3704
3705 guard(mutex)(&dev->mode_config.mutex);
3706
3707 /*
3708 * 1. Update status of the drm connector
3709 * 2. Send an event and let userspace tell us what to do
3710 */
3711 if (sink) {
3712 /*
3713 * TODO: check if we still need the S3 mode update workaround.
3714 * If yes, put it here.
3715 */
3716 if (aconnector->dc_sink) {
3717 amdgpu_dm_update_freesync_caps(connector, NULL);
3718 dc_sink_release(aconnector->dc_sink);
3719 }
3720
3721 aconnector->dc_sink = sink;
3722 dc_sink_retain(aconnector->dc_sink);
3723 if (sink->dc_edid.length == 0) {
3724 aconnector->drm_edid = NULL;
3725 hdmi_cec_unset_edid(aconnector);
3726 if (aconnector->dc_link->aux_mode) {
3727 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3728 }
3729 } else {
3730 const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid;
3731
3732 aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length);
3733 drm_edid_connector_update(connector, aconnector->drm_edid);
3734
3735 hdmi_cec_set_edid(aconnector);
3736 if (aconnector->dc_link->aux_mode)
3737 drm_dp_cec_attach(&aconnector->dm_dp_aux.aux,
3738 connector->display_info.source_physical_address);
3739 }
3740
3741 if (!aconnector->timing_requested) {
3742 aconnector->timing_requested =
3743 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3744 if (!aconnector->timing_requested)
3745 drm_err(dev,
3746 "failed to create aconnector->requested_timing\n");
3747 }
3748
3749 amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid);
3750 update_connector_ext_caps(aconnector);
3751 } else {
3752 hdmi_cec_unset_edid(aconnector);
3753 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3754 amdgpu_dm_update_freesync_caps(connector, NULL);
3755 aconnector->num_modes = 0;
3756 dc_sink_release(aconnector->dc_sink);
3757 aconnector->dc_sink = NULL;
3758 drm_edid_free(aconnector->drm_edid);
3759 aconnector->drm_edid = NULL;
3760 kfree(aconnector->timing_requested);
3761 aconnector->timing_requested = NULL;
3762 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3763 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3764 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3765 }
3766
3767 update_subconnector_property(aconnector);
3768}
3769
3770static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3771{
3772 struct drm_connector *connector = &aconnector->base;
3773 struct drm_device *dev = connector->dev;
3774 enum dc_connection_type new_connection_type = dc_connection_none;
3775 struct amdgpu_device *adev = drm_to_adev(dev);
3776 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3777 struct dc *dc = aconnector->dc_link->ctx->dc;
3778 bool ret = false;
3779
3780 if (adev->dm.disable_hpd_irq)
3781 return;
3782
3783 /*
3784 * In case of failure or MST no need to update connector status or notify the OS
3785 * since (for MST case) MST does this in its own context.
3786 */
3787 guard(mutex)(&aconnector->hpd_lock);
3788
3789 if (adev->dm.hdcp_workqueue) {
3790 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3791 dm_con_state->update_hdcp = true;
3792 }
3793 if (aconnector->fake_enable)
3794 aconnector->fake_enable = false;
3795
3796 aconnector->timing_changed = false;
3797
3798 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3799 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");
3800
3801 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3802 emulated_link_detect(aconnector->dc_link);
3803
3804 drm_modeset_lock_all(dev);
3805 dm_restore_drm_connector_state(dev, connector);
3806 drm_modeset_unlock_all(dev);
3807
3808 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3809 drm_kms_helper_connector_hotplug_event(connector);
3810 } else {
3811 scoped_guard(mutex, &adev->dm.dc_lock) {
3812 dc_exit_ips_for_hw_access(dc);
3813 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3814 }
3815 if (ret) {
3816 /* w/a delay for certain panels */
3817 apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink);
3818 amdgpu_dm_update_connector_after_detect(aconnector);
3819
3820 drm_modeset_lock_all(dev);
3821 dm_restore_drm_connector_state(dev, connector);
3822 drm_modeset_unlock_all(dev);
3823
3824 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3825 drm_kms_helper_connector_hotplug_event(connector);
3826 }
3827 }
3828}
3829
3830static void handle_hpd_irq(void *param)
3831{
3832 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3833
3834 handle_hpd_irq_helper(aconnector);
3835
3836}
3837
3838static void schedule_hpd_rx_offload_work(struct amdgpu_device *adev, struct hpd_rx_irq_offload_work_queue *offload_wq,
3839 union hpd_irq_data hpd_irq_data)
3840{
3841 struct hpd_rx_irq_offload_work *offload_work =
3842 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3843
3844 if (!offload_work) {
3845 drm_err(adev_to_drm(adev), "Failed to allocate hpd_rx_irq_offload_work.\n");
3846 return;
3847 }
3848
3849 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3850 offload_work->data = hpd_irq_data;
3851 offload_work->offload_wq = offload_wq;
3852 offload_work->adev = adev;
3853
3854 queue_work(offload_wq->wq, &offload_work->work);
3855 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3856}
3857
3858static void handle_hpd_rx_irq(void *param)
3859{
3860 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3861 struct drm_connector *connector = &aconnector->base;
3862 struct drm_device *dev = connector->dev;
3863 struct dc_link *dc_link = aconnector->dc_link;
3864 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3865 bool result = false;
3866 enum dc_connection_type new_connection_type = dc_connection_none;
3867 struct amdgpu_device *adev = drm_to_adev(dev);
3868 union hpd_irq_data hpd_irq_data;
3869 bool link_loss = false;
3870 bool has_left_work = false;
3871 int idx = dc_link->link_index;
3872 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3873 struct dc *dc = aconnector->dc_link->ctx->dc;
3874
3875 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3876
3877 if (adev->dm.disable_hpd_irq)
3878 return;
3879
3880 /*
3881 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3882 * conflict, after implement i2c helper, this mutex should be
3883 * retired.
3884 */
3885 mutex_lock(&aconnector->hpd_lock);
3886
3887 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3888 &link_loss, true, &has_left_work);
3889
3890 if (!has_left_work)
3891 goto out;
3892
3893 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3894 schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data);
3895 goto out;
3896 }
3897
3898 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3899 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3900 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3901 bool skip = false;
3902
3903 /*
3904 * DOWN_REP_MSG_RDY is also handled by polling method
3905 * mgr->cbs->poll_hpd_irq()
3906 */
3907 spin_lock(&offload_wq->offload_lock);
3908 skip = offload_wq->is_handling_mst_msg_rdy_event;
3909
3910 if (!skip)
3911 offload_wq->is_handling_mst_msg_rdy_event = true;
3912
3913 spin_unlock(&offload_wq->offload_lock);
3914
3915 if (!skip)
3916 schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data);
3917
3918 goto out;
3919 }
3920
3921 if (link_loss) {
3922 bool skip = false;
3923
3924 spin_lock(&offload_wq->offload_lock);
3925 skip = offload_wq->is_handling_link_loss;
3926
3927 if (!skip)
3928 offload_wq->is_handling_link_loss = true;
3929
3930 spin_unlock(&offload_wq->offload_lock);
3931
3932 if (!skip)
3933 schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data);
3934
3935 goto out;
3936 }
3937 }
3938
3939out:
3940 if (result && !is_mst_root_connector) {
3941 /* Downstream Port status changed. */
3942 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3943 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");
3944
3945 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3946 emulated_link_detect(dc_link);
3947
3948 if (aconnector->fake_enable)
3949 aconnector->fake_enable = false;
3950
3951 amdgpu_dm_update_connector_after_detect(aconnector);
3952
3953
3954 drm_modeset_lock_all(dev);
3955 dm_restore_drm_connector_state(dev, connector);
3956 drm_modeset_unlock_all(dev);
3957
3958 drm_kms_helper_connector_hotplug_event(connector);
3959 } else {
3960 bool ret = false;
3961
3962 mutex_lock(&adev->dm.dc_lock);
3963 dc_exit_ips_for_hw_access(dc);
3964 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3965 mutex_unlock(&adev->dm.dc_lock);
3966
3967 if (ret) {
3968 if (aconnector->fake_enable)
3969 aconnector->fake_enable = false;
3970
3971 amdgpu_dm_update_connector_after_detect(aconnector);
3972
3973 drm_modeset_lock_all(dev);
3974 dm_restore_drm_connector_state(dev, connector);
3975 drm_modeset_unlock_all(dev);
3976
3977 drm_kms_helper_connector_hotplug_event(connector);
3978 }
3979 }
3980 }
3981 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3982 if (adev->dm.hdcp_workqueue)
3983 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3984 }
3985
3986 if (dc_link->type != dc_connection_mst_branch)
3987 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3988
3989 mutex_unlock(&aconnector->hpd_lock);
3990}
3991
3992static int register_hpd_handlers(struct amdgpu_device *adev)
3993{
3994 struct drm_device *dev = adev_to_drm(adev);
3995 struct drm_connector *connector;
3996 struct amdgpu_dm_connector *aconnector;
3997 const struct dc_link *dc_link;
3998 struct dc_interrupt_params int_params = {0};
3999
4000 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4001 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4002
4003 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
4004 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,
4005 dmub_hpd_callback, true)) {
4006 drm_err(adev_to_drm(adev), "amdgpu: fail to register dmub hpd callback");
4007 return -EINVAL;
4008 }
4009
4010 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ,
4011 dmub_hpd_callback, true)) {
4012 drm_err(adev_to_drm(adev), "amdgpu: fail to register dmub hpd callback");
4013 return -EINVAL;
4014 }
4015
4016 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY,
4017 dmub_hpd_sense_callback, true)) {
4018 drm_err(adev_to_drm(adev), "amdgpu: fail to register dmub hpd sense callback");
4019 return -EINVAL;
4020 }
4021 }
4022
4023 list_for_each_entry(connector,
4024 &dev->mode_config.connector_list, head) {
4025
4026 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
4027 continue;
4028
4029 aconnector = to_amdgpu_dm_connector(connector);
4030 dc_link = aconnector->dc_link;
4031
4032 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
4033 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
4034 int_params.irq_source = dc_link->irq_source_hpd;
4035
4036 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4037 int_params.irq_source < DC_IRQ_SOURCE_HPD1 ||
4038 int_params.irq_source > DC_IRQ_SOURCE_HPD6) {
4039 drm_err(adev_to_drm(adev), "Failed to register hpd irq!\n");
4040 return -EINVAL;
4041 }
4042
4043 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4044 handle_hpd_irq, (void *) aconnector))
4045 return -ENOMEM;
4046 }
4047
4048 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
4049
4050 /* Also register for DP short pulse (hpd_rx). */
4051 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
4052 int_params.irq_source = dc_link->irq_source_hpd_rx;
4053
4054 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4055 int_params.irq_source < DC_IRQ_SOURCE_HPD1RX ||
4056 int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) {
4057 drm_err(adev_to_drm(adev), "Failed to register hpd rx irq!\n");
4058 return -EINVAL;
4059 }
4060
4061 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4062 handle_hpd_rx_irq, (void *) aconnector))
4063 return -ENOMEM;
4064 }
4065 }
4066 return 0;
4067}
4068
4069#if defined(CONFIG_DRM_AMD_DC_SI)
4070/* Register IRQ sources and initialize IRQ callbacks */
4071static int dce60_register_irq_handlers(struct amdgpu_device *adev)
4072{
4073 struct dc *dc = adev->dm.dc;
4074 struct common_irq_params *c_irq_params;
4075 struct dc_interrupt_params int_params = {0};
4076 int r;
4077 int i;
4078 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
4079
4080 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4081 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4082
4083 /*
4084 * Actions of amdgpu_irq_add_id():
4085 * 1. Register a set() function with base driver.
4086 * Base driver will call set() function to enable/disable an
4087 * interrupt in DC hardware.
4088 * 2. Register amdgpu_dm_irq_handler().
4089 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
4090 * coming from DC hardware.
4091 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
4092 * for acknowledging and handling.
4093 */
4094
4095 /* Use VBLANK interrupt */
4096 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4097 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
4098 if (r) {
4099 drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");
4100 return r;
4101 }
4102
4103 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4104 int_params.irq_source =
4105 dc_interrupt_to_irq_source(dc, i + 1, 0);
4106
4107 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4108 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||
4109 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {
4110 drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");
4111 return -EINVAL;
4112 }
4113
4114 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4115
4116 c_irq_params->adev = adev;
4117 c_irq_params->irq_src = int_params.irq_source;
4118
4119 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4120 dm_crtc_high_irq, c_irq_params))
4121 return -ENOMEM;
4122 }
4123
4124 /* Use GRPH_PFLIP interrupt */
4125 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
4126 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
4127 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4128 if (r) {
4129 drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");
4130 return r;
4131 }
4132
4133 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4134 int_params.irq_source =
4135 dc_interrupt_to_irq_source(dc, i, 0);
4136
4137 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4138 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||
4139 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {
4140 drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");
4141 return -EINVAL;
4142 }
4143
4144 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
4145
4146 c_irq_params->adev = adev;
4147 c_irq_params->irq_src = int_params.irq_source;
4148
4149 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4150 dm_pflip_high_irq, c_irq_params))
4151 return -ENOMEM;
4152 }
4153
4154 /* HPD */
4155 r = amdgpu_irq_add_id(adev, client_id,
4156 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4157 if (r) {
4158 drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");
4159 return r;
4160 }
4161
4162 r = register_hpd_handlers(adev);
4163
4164 return r;
4165}
4166#endif
4167
4168/* Register IRQ sources and initialize IRQ callbacks */
4169static int dce110_register_irq_handlers(struct amdgpu_device *adev)
4170{
4171 struct dc *dc = adev->dm.dc;
4172 struct common_irq_params *c_irq_params;
4173 struct dc_interrupt_params int_params = {0};
4174 int r;
4175 int i;
4176 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
4177
4178 if (adev->family >= AMDGPU_FAMILY_AI)
4179 client_id = SOC15_IH_CLIENTID_DCE;
4180
4181 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4182 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4183
4184 /*
4185 * Actions of amdgpu_irq_add_id():
4186 * 1. Register a set() function with base driver.
4187 * Base driver will call set() function to enable/disable an
4188 * interrupt in DC hardware.
4189 * 2. Register amdgpu_dm_irq_handler().
4190 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
4191 * coming from DC hardware.
4192 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
4193 * for acknowledging and handling.
4194 */
4195
4196 /* Use VBLANK interrupt */
4197 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
4198 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4199 if (r) {
4200 drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");
4201 return r;
4202 }
4203
4204 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4205 int_params.irq_source =
4206 dc_interrupt_to_irq_source(dc, i, 0);
4207
4208 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4209 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||
4210 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {
4211 drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");
4212 return -EINVAL;
4213 }
4214
4215 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4216
4217 c_irq_params->adev = adev;
4218 c_irq_params->irq_src = int_params.irq_source;
4219
4220 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4221 dm_crtc_high_irq, c_irq_params))
4222 return -ENOMEM;
4223 }
4224
4225 /* Use VUPDATE interrupt */
4226 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
4227 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
4228 if (r) {
4229 drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n");
4230 return r;
4231 }
4232
4233 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4234 int_params.irq_source =
4235 dc_interrupt_to_irq_source(dc, i, 0);
4236
4237 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4238 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 ||
4239 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) {
4240 drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n");
4241 return -EINVAL;
4242 }
4243
4244 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
4245
4246 c_irq_params->adev = adev;
4247 c_irq_params->irq_src = int_params.irq_source;
4248
4249 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4250 dm_vupdate_high_irq, c_irq_params))
4251 return -ENOMEM;
4252 }
4253
4254 /* Use GRPH_PFLIP interrupt */
4255 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
4256 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
4257 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4258 if (r) {
4259 drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");
4260 return r;
4261 }
4262
4263 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4264 int_params.irq_source =
4265 dc_interrupt_to_irq_source(dc, i, 0);
4266
4267 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4268 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||
4269 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {
4270 drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");
4271 return -EINVAL;
4272 }
4273
4274 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
4275
4276 c_irq_params->adev = adev;
4277 c_irq_params->irq_src = int_params.irq_source;
4278
4279 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4280 dm_pflip_high_irq, c_irq_params))
4281 return -ENOMEM;
4282 }
4283
4284 /* HPD */
4285 r = amdgpu_irq_add_id(adev, client_id,
4286 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4287 if (r) {
4288 drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");
4289 return r;
4290 }
4291
4292 r = register_hpd_handlers(adev);
4293
4294 return r;
4295}
4296
4297/* Register IRQ sources and initialize IRQ callbacks */
4298static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
4299{
4300 struct dc *dc = adev->dm.dc;
4301 struct common_irq_params *c_irq_params;
4302 struct dc_interrupt_params int_params = {0};
4303 int r;
4304 int i;
4305#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
4306 static const unsigned int vrtl_int_srcid[] = {
4307 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
4308 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
4309 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
4310 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
4311 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
4312 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
4313 };
4314#endif
4315
4316 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4317 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4318
4319 /*
4320 * Actions of amdgpu_irq_add_id():
4321 * 1. Register a set() function with base driver.
4322 * Base driver will call set() function to enable/disable an
4323 * interrupt in DC hardware.
4324 * 2. Register amdgpu_dm_irq_handler().
4325 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
4326 * coming from DC hardware.
4327 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
4328 * for acknowledging and handling.
4329 */
4330
4331 /* Use VSTARTUP interrupt */
4332 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
4333 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
4334 i++) {
4335 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
4336
4337 if (r) {
4338 drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");
4339 return r;
4340 }
4341
4342 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4343 int_params.irq_source =
4344 dc_interrupt_to_irq_source(dc, i, 0);
4345
4346 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4347 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||
4348 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {
4349 drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");
4350 return -EINVAL;
4351 }
4352
4353 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4354
4355 c_irq_params->adev = adev;
4356 c_irq_params->irq_src = int_params.irq_source;
4357
4358 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4359 dm_crtc_high_irq, c_irq_params))
4360 return -ENOMEM;
4361 }
4362
4363 /* Use otg vertical line interrupt */
4364#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
4365 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
4366 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
4367 vrtl_int_srcid[i], &adev->vline0_irq);
4368
4369 if (r) {
4370 drm_err(adev_to_drm(adev), "Failed to add vline0 irq id!\n");
4371 return r;
4372 }
4373
4374 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4375 int_params.irq_source =
4376 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
4377
4378 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4379 int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 ||
4380 int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) {
4381 drm_err(adev_to_drm(adev), "Failed to register vline0 irq!\n");
4382 return -EINVAL;
4383 }
4384
4385 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
4386 - DC_IRQ_SOURCE_DC1_VLINE0];
4387
4388 c_irq_params->adev = adev;
4389 c_irq_params->irq_src = int_params.irq_source;
4390
4391 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4392 dm_dcn_vertical_interrupt0_high_irq,
4393 c_irq_params))
4394 return -ENOMEM;
4395 }
4396#endif
4397
4398 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
4399 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
4400 * to trigger at end of each vblank, regardless of state of the lock,
4401 * matching DCE behaviour.
4402 */
4403 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
4404 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
4405 i++) {
4406 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
4407
4408 if (r) {
4409 drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n");
4410 return r;
4411 }
4412
4413 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4414 int_params.irq_source =
4415 dc_interrupt_to_irq_source(dc, i, 0);
4416
4417 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4418 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 ||
4419 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) {
4420 drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n");
4421 return -EINVAL;
4422 }
4423
4424 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
4425
4426 c_irq_params->adev = adev;
4427 c_irq_params->irq_src = int_params.irq_source;
4428
4429 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4430 dm_vupdate_high_irq, c_irq_params))
4431 return -ENOMEM;
4432 }
4433
4434 /* Use GRPH_PFLIP interrupt */
4435 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
4436 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
4437 i++) {
4438 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
4439 if (r) {
4440 drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");
4441 return r;
4442 }
4443
4444 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4445 int_params.irq_source =
4446 dc_interrupt_to_irq_source(dc, i, 0);
4447
4448 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4449 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||
4450 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {
4451 drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");
4452 return -EINVAL;
4453 }
4454
4455 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
4456
4457 c_irq_params->adev = adev;
4458 c_irq_params->irq_src = int_params.irq_source;
4459
4460 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4461 dm_pflip_high_irq, c_irq_params))
4462 return -ENOMEM;
4463 }
4464
4465 /* HPD */
4466 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
4467 &adev->hpd_irq);
4468 if (r) {
4469 drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");
4470 return r;
4471 }
4472
4473 r = register_hpd_handlers(adev);
4474
4475 return r;
4476}
4477/* Register Outbox IRQ sources and initialize IRQ callbacks */
4478static int register_outbox_irq_handlers(struct amdgpu_device *adev)
4479{
4480 struct dc *dc = adev->dm.dc;
4481 struct common_irq_params *c_irq_params;
4482 struct dc_interrupt_params int_params = {0};
4483 int r, i;
4484
4485 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4486 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4487
4488 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
4489 &adev->dmub_outbox_irq);
4490 if (r) {
4491 drm_err(adev_to_drm(adev), "Failed to add outbox irq id!\n");
4492 return r;
4493 }
4494
4495 if (dc->ctx->dmub_srv) {
4496 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
4497 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
4498 int_params.irq_source =
4499 dc_interrupt_to_irq_source(dc, i, 0);
4500
4501 c_irq_params = &adev->dm.dmub_outbox_params[0];
4502
4503 c_irq_params->adev = adev;
4504 c_irq_params->irq_src = int_params.irq_source;
4505
4506 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4507 dm_dmub_outbox1_low_irq, c_irq_params))
4508 return -ENOMEM;
4509 }
4510
4511 return 0;
4512}
4513
4514/*
4515 * Acquires the lock for the atomic state object and returns
4516 * the new atomic state.
4517 *
4518 * This should only be called during atomic check.
4519 */
4520int dm_atomic_get_state(struct drm_atomic_state *state,
4521 struct dm_atomic_state **dm_state)
4522{
4523 struct drm_device *dev = state->dev;
4524 struct amdgpu_device *adev = drm_to_adev(dev);
4525 struct amdgpu_display_manager *dm = &adev->dm;
4526 struct drm_private_state *priv_state;
4527
4528 if (*dm_state)
4529 return 0;
4530
4531 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
4532 if (IS_ERR(priv_state))
4533 return PTR_ERR(priv_state);
4534
4535 *dm_state = to_dm_atomic_state(priv_state);
4536
4537 return 0;
4538}
4539
4540static struct dm_atomic_state *
4541dm_atomic_get_new_state(struct drm_atomic_state *state)
4542{
4543 struct drm_device *dev = state->dev;
4544 struct amdgpu_device *adev = drm_to_adev(dev);
4545 struct amdgpu_display_manager *dm = &adev->dm;
4546 struct drm_private_obj *obj;
4547 struct drm_private_state *new_obj_state;
4548 int i;
4549
4550 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
4551 if (obj->funcs == dm->atomic_obj.funcs)
4552 return to_dm_atomic_state(new_obj_state);
4553 }
4554
4555 return NULL;
4556}
4557
4558static struct drm_private_state *
4559dm_atomic_duplicate_state(struct drm_private_obj *obj)
4560{
4561 struct dm_atomic_state *old_state, *new_state;
4562
4563 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
4564 if (!new_state)
4565 return NULL;
4566
4567 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
4568
4569 old_state = to_dm_atomic_state(obj->state);
4570
4571 if (old_state && old_state->context)
4572 new_state->context = dc_state_create_copy(old_state->context);
4573
4574 if (!new_state->context) {
4575 kfree(new_state);
4576 return NULL;
4577 }
4578
4579 return &new_state->base;
4580}
4581
4582static void dm_atomic_destroy_state(struct drm_private_obj *obj,
4583 struct drm_private_state *state)
4584{
4585 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4586
4587 if (dm_state && dm_state->context)
4588 dc_state_release(dm_state->context);
4589
4590 kfree(dm_state);
4591}
4592
4593static struct drm_private_state_funcs dm_atomic_state_funcs = {
4594 .atomic_duplicate_state = dm_atomic_duplicate_state,
4595 .atomic_destroy_state = dm_atomic_destroy_state,
4596};
4597
4598static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4599{
4600 struct dm_atomic_state *state;
4601 int r;
4602
4603 adev->mode_info.mode_config_initialized = true;
4604
4605 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
4606 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4607
4608 adev_to_drm(adev)->mode_config.max_width = 16384;
4609 adev_to_drm(adev)->mode_config.max_height = 16384;
4610
4611 adev_to_drm(adev)->mode_config.preferred_depth = 24;
4612 if (adev->asic_type == CHIP_HAWAII)
4613 /* disable prefer shadow for now due to hibernation issues */
4614 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4615 else
4616 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4617 /* indicates support for immediate flip */
4618 adev_to_drm(adev)->mode_config.async_page_flip = true;
4619
4620 state = kzalloc(sizeof(*state), GFP_KERNEL);
4621 if (!state)
4622 return -ENOMEM;
4623
4624 state->context = dc_state_create_current_copy(adev->dm.dc);
4625 if (!state->context) {
4626 kfree(state);
4627 return -ENOMEM;
4628 }
4629
4630 drm_atomic_private_obj_init(adev_to_drm(adev),
4631 &adev->dm.atomic_obj,
4632 &state->base,
4633 &dm_atomic_state_funcs);
4634
4635 r = amdgpu_display_modeset_create_props(adev);
4636 if (r) {
4637 dc_state_release(state->context);
4638 kfree(state);
4639 return r;
4640 }
4641
4642#ifdef AMD_PRIVATE_COLOR
4643 if (amdgpu_dm_create_color_properties(adev)) {
4644 dc_state_release(state->context);
4645 kfree(state);
4646 return -ENOMEM;
4647 }
4648#endif
4649
4650 r = amdgpu_dm_audio_init(adev);
4651 if (r) {
4652 dc_state_release(state->context);
4653 kfree(state);
4654 return r;
4655 }
4656
4657 return 0;
4658}
4659
4660#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4661#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4662#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)
4663#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4664
4665static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4666 int bl_idx)
4667{
4668 struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx];
4669
4670 if (caps->caps_valid)
4671 return;
4672
4673#if defined(CONFIG_ACPI)
4674 amdgpu_acpi_get_backlight_caps(caps);
4675
4676 /* validate the firmware value is sane */
4677 if (caps->caps_valid) {
4678 int spread = caps->max_input_signal - caps->min_input_signal;
4679
4680 if (caps->max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
4681 caps->min_input_signal < 0 ||
4682 spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
4683 spread < AMDGPU_DM_MIN_SPREAD) {
4684 DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",
4685 caps->min_input_signal, caps->max_input_signal);
4686 caps->caps_valid = false;
4687 }
4688 }
4689
4690 if (!caps->caps_valid) {
4691 caps->min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4692 caps->max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4693 caps->caps_valid = true;
4694 }
4695#else
4696 if (caps->aux_support)
4697 return;
4698
4699 caps->min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4700 caps->max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4701 caps->caps_valid = true;
4702#endif
4703}
4704
4705static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4706 unsigned int *min, unsigned int *max)
4707{
4708 if (!caps)
4709 return 0;
4710
4711 if (caps->aux_support) {
4712 // Firmware limits are in nits, DC API wants millinits.
4713 *max = 1000 * caps->aux_max_input_signal;
4714 *min = 1000 * caps->aux_min_input_signal;
4715 } else {
4716 // Firmware limits are 8-bit, PWM control is 16-bit.
4717 *max = 0x101 * caps->max_input_signal;
4718 *min = 0x101 * caps->min_input_signal;
4719 }
4720 return 1;
4721}
4722
4723/* Rescale from [min..max] to [0..MAX_BACKLIGHT_LEVEL] */
4724static inline u32 scale_input_to_fw(int min, int max, u64 input)
4725{
4726 return DIV_ROUND_CLOSEST_ULL(input * MAX_BACKLIGHT_LEVEL, max - min);
4727}
4728
4729/* Rescale from [0..MAX_BACKLIGHT_LEVEL] to [min..max] */
4730static inline u32 scale_fw_to_input(int min, int max, u64 input)
4731{
4732 return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), MAX_BACKLIGHT_LEVEL);
4733}
4734
4735static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
4736 unsigned int min, unsigned int max,
4737 uint32_t *user_brightness)
4738{
4739 u32 brightness = scale_input_to_fw(min, max, *user_brightness);
4740 u8 prev_signal = 0, prev_lum = 0;
4741 int i = 0;
4742
4743 if (amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)
4744 return;
4745
4746 if (!caps->data_points)
4747 return;
4748
4749 /* choose start to run less interpolation steps */
4750 if (caps->luminance_data[caps->data_points/2].input_signal > brightness)
4751 i = caps->data_points/2;
4752 do {
4753 u8 signal = caps->luminance_data[i].input_signal;
4754 u8 lum = caps->luminance_data[i].luminance;
4755
4756 /*
4757 * brightness == signal: luminance is percent numerator
4758 * brightness < signal: interpolate between previous and current luminance numerator
4759 * brightness > signal: find next data point
4760 */
4761 if (brightness > signal) {
4762 prev_signal = signal;
4763 prev_lum = lum;
4764 i++;
4765 continue;
4766 }
4767 if (brightness < signal)
4768 lum = prev_lum + DIV_ROUND_CLOSEST((lum - prev_lum) *
4769 (brightness - prev_signal),
4770 signal - prev_signal);
4771 *user_brightness = scale_fw_to_input(min, max,
4772 DIV_ROUND_CLOSEST(lum * brightness, 101));
4773 return;
4774 } while (i < caps->data_points);
4775}
4776
4777static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4778 uint32_t brightness)
4779{
4780 unsigned int min, max;
4781
4782 if (!get_brightness_range(caps, &min, &max))
4783 return brightness;
4784
4785 convert_custom_brightness(caps, min, max, &brightness);
4786
4787 // Rescale 0..max to min..max
4788 return min + DIV_ROUND_CLOSEST_ULL((u64)(max - min) * brightness, max);
4789}
4790
4791static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4792 uint32_t brightness)
4793{
4794 unsigned int min, max;
4795
4796 if (!get_brightness_range(caps, &min, &max))
4797 return brightness;
4798
4799 if (brightness < min)
4800 return 0;
4801 // Rescale min..max to 0..max
4802 return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min),
4803 max - min);
4804}
4805
4806static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4807 int bl_idx,
4808 u32 user_brightness)
4809{
4810 struct amdgpu_dm_backlight_caps *caps;
4811 struct dc_link *link;
4812 u32 brightness;
4813 bool rc, reallow_idle = false;
4814
4815 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4816 caps = &dm->backlight_caps[bl_idx];
4817
4818 dm->brightness[bl_idx] = user_brightness;
4819 /* update scratch register */
4820 if (bl_idx == 0)
4821 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4822 brightness = convert_brightness_from_user(caps, dm->brightness[bl_idx]);
4823 link = (struct dc_link *)dm->backlight_link[bl_idx];
4824
4825 /* Change brightness based on AUX property */
4826 mutex_lock(&dm->dc_lock);
4827 if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
4828 dc_allow_idle_optimizations(dm->dc, false);
4829 reallow_idle = true;
4830 }
4831
4832 if (caps->aux_support) {
4833 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4834 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4835 if (!rc)
4836 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4837 } else {
4838 struct set_backlight_level_params backlight_level_params = { 0 };
4839
4840 backlight_level_params.backlight_pwm_u16_16 = brightness;
4841 backlight_level_params.transition_time_in_ms = 0;
4842
4843 rc = dc_link_set_backlight_level(link, &backlight_level_params);
4844 if (!rc)
4845 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4846 }
4847
4848 if (dm->dc->caps.ips_support && reallow_idle)
4849 dc_allow_idle_optimizations(dm->dc, true);
4850
4851 mutex_unlock(&dm->dc_lock);
4852
4853 if (rc)
4854 dm->actual_brightness[bl_idx] = user_brightness;
4855}
4856
4857static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4858{
4859 struct amdgpu_display_manager *dm = bl_get_data(bd);
4860 int i;
4861
4862 for (i = 0; i < dm->num_of_edps; i++) {
4863 if (bd == dm->backlight_dev[i])
4864 break;
4865 }
4866 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4867 i = 0;
4868 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4869
4870 return 0;
4871}
4872
4873static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4874 int bl_idx)
4875{
4876 int ret;
4877 struct amdgpu_dm_backlight_caps caps;
4878 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4879
4880 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4881 caps = dm->backlight_caps[bl_idx];
4882
4883 if (caps.aux_support) {
4884 u32 avg, peak;
4885 bool rc;
4886
4887 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4888 if (!rc)
4889 return dm->brightness[bl_idx];
4890 return convert_brightness_to_user(&caps, avg);
4891 }
4892
4893 ret = dc_link_get_backlight_level(link);
4894
4895 if (ret == DC_ERROR_UNEXPECTED)
4896 return dm->brightness[bl_idx];
4897
4898 return convert_brightness_to_user(&caps, ret);
4899}
4900
4901static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4902{
4903 struct amdgpu_display_manager *dm = bl_get_data(bd);
4904 int i;
4905
4906 for (i = 0; i < dm->num_of_edps; i++) {
4907 if (bd == dm->backlight_dev[i])
4908 break;
4909 }
4910 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4911 i = 0;
4912 return amdgpu_dm_backlight_get_level(dm, i);
4913}
4914
4915static const struct backlight_ops amdgpu_dm_backlight_ops = {
4916 .options = BL_CORE_SUSPENDRESUME,
4917 .get_brightness = amdgpu_dm_backlight_get_brightness,
4918 .update_status = amdgpu_dm_backlight_update_status,
4919};
4920
4921static void
4922amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4923{
4924 struct drm_device *drm = aconnector->base.dev;
4925 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4926 struct backlight_properties props = { 0 };
4927 struct amdgpu_dm_backlight_caps *caps;
4928 char bl_name[16];
4929 int min, max;
4930
4931 if (aconnector->bl_idx == -1)
4932 return;
4933
4934 if (!acpi_video_backlight_use_native()) {
4935 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4936 /* Try registering an ACPI video backlight device instead. */
4937 acpi_video_register_backlight();
4938 return;
4939 }
4940
4941 caps = &dm->backlight_caps[aconnector->bl_idx];
4942 if (get_brightness_range(caps, &min, &max)) {
4943 if (power_supply_is_system_supplied() > 0)
4944 props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->ac_level, 100);
4945 else
4946 props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->dc_level, 100);
4947 /* min is zero, so max needs to be adjusted */
4948 props.max_brightness = max - min;
4949 drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
4950 caps->ac_level, caps->dc_level);
4951 } else
4952 props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL;
4953
4954 if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
4955 drm_info(drm, "Using custom brightness curve\n");
4956 props.type = BACKLIGHT_RAW;
4957
4958 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4959 drm->primary->index + aconnector->bl_idx);
4960
4961 dm->backlight_dev[aconnector->bl_idx] =
4962 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4963 &amdgpu_dm_backlight_ops, &props);
4964 dm->brightness[aconnector->bl_idx] = props.brightness;
4965
4966 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4967 drm_err(drm, "DM: Backlight registration failed!\n");
4968 dm->backlight_dev[aconnector->bl_idx] = NULL;
4969 } else
4970 drm_dbg_driver(drm, "DM: Registered Backlight device: %s\n", bl_name);
4971}
4972
4973static int initialize_plane(struct amdgpu_display_manager *dm,
4974 struct amdgpu_mode_info *mode_info, int plane_id,
4975 enum drm_plane_type plane_type,
4976 const struct dc_plane_cap *plane_cap)
4977{
4978 struct drm_plane *plane;
4979 unsigned long possible_crtcs;
4980 int ret = 0;
4981
4982 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4983 if (!plane) {
4984 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n");
4985 return -ENOMEM;
4986 }
4987 plane->type = plane_type;
4988
4989 /*
4990 * HACK: IGT tests expect that the primary plane for a CRTC
4991 * can only have one possible CRTC. Only expose support for
4992 * any CRTC if they're not going to be used as a primary plane
4993 * for a CRTC - like overlay or underlay planes.
4994 */
4995 possible_crtcs = 1 << plane_id;
4996 if (plane_id >= dm->dc->caps.max_streams)
4997 possible_crtcs = 0xff;
4998
4999 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
5000
5001 if (ret) {
5002 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n");
5003 kfree(plane);
5004 return ret;
5005 }
5006
5007 if (mode_info)
5008 mode_info->planes[plane_id] = plane;
5009
5010 return ret;
5011}
5012
5013
5014static void setup_backlight_device(struct amdgpu_display_manager *dm,
5015 struct amdgpu_dm_connector *aconnector)
5016{
5017 struct dc_link *link = aconnector->dc_link;
5018 int bl_idx = dm->num_of_edps;
5019
5020 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
5021 link->type == dc_connection_none)
5022 return;
5023
5024 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
5025 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
5026 return;
5027 }
5028
5029 aconnector->bl_idx = bl_idx;
5030
5031 amdgpu_dm_update_backlight_caps(dm, bl_idx);
5032 dm->backlight_link[bl_idx] = link;
5033 dm->num_of_edps++;
5034
5035 update_connector_ext_caps(aconnector);
5036}
5037
5038static void amdgpu_set_panel_orientation(struct drm_connector *connector);
5039
5040/*
5041 * In this architecture, the association
5042 * connector -> encoder -> crtc
5043 * id not really requried. The crtc and connector will hold the
5044 * display_index as an abstraction to use with DAL component
5045 *
5046 * Returns 0 on success
5047 */
5048static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
5049{
5050 struct amdgpu_display_manager *dm = &adev->dm;
5051 s32 i;
5052 struct amdgpu_dm_connector *aconnector = NULL;
5053 struct amdgpu_encoder *aencoder = NULL;
5054 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5055 u32 link_cnt;
5056 s32 primary_planes;
5057 enum dc_connection_type new_connection_type = dc_connection_none;
5058 const struct dc_plane_cap *plane;
5059 bool psr_feature_enabled = false;
5060 bool replay_feature_enabled = false;
5061 int max_overlay = dm->dc->caps.max_slave_planes;
5062
5063 dm->display_indexes_num = dm->dc->caps.max_streams;
5064 /* Update the actual used number of crtc */
5065 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
5066
5067 amdgpu_dm_set_irq_funcs(adev);
5068
5069 link_cnt = dm->dc->caps.max_links;
5070 if (amdgpu_dm_mode_config_init(dm->adev)) {
5071 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n");
5072 return -EINVAL;
5073 }
5074
5075 /* There is one primary plane per CRTC */
5076 primary_planes = dm->dc->caps.max_streams;
5077 if (primary_planes > AMDGPU_MAX_PLANES) {
5078 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n");
5079 return -EINVAL;
5080 }
5081
5082 /*
5083 * Initialize primary planes, implicit planes for legacy IOCTLS.
5084 * Order is reversed to match iteration order in atomic check.
5085 */
5086 for (i = (primary_planes - 1); i >= 0; i--) {
5087 plane = &dm->dc->caps.planes[i];
5088
5089 if (initialize_plane(dm, mode_info, i,
5090 DRM_PLANE_TYPE_PRIMARY, plane)) {
5091 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n");
5092 goto fail;
5093 }
5094 }
5095
5096 /*
5097 * Initialize overlay planes, index starting after primary planes.
5098 * These planes have a higher DRM index than the primary planes since
5099 * they should be considered as having a higher z-order.
5100 * Order is reversed to match iteration order in atomic check.
5101 *
5102 * Only support DCN for now, and only expose one so we don't encourage
5103 * userspace to use up all the pipes.
5104 */
5105 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
5106 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
5107
5108 /* Do not create overlay if MPO disabled */
5109 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
5110 break;
5111
5112 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
5113 continue;
5114
5115 if (!plane->pixel_format_support.argb8888)
5116 continue;
5117
5118 if (max_overlay-- == 0)
5119 break;
5120
5121 if (initialize_plane(dm, NULL, primary_planes + i,
5122 DRM_PLANE_TYPE_OVERLAY, plane)) {
5123 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n");
5124 goto fail;
5125 }
5126 }
5127
5128 for (i = 0; i < dm->dc->caps.max_streams; i++)
5129 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
5130 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n");
5131 goto fail;
5132 }
5133
5134 /* Use Outbox interrupt */
5135 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5136 case IP_VERSION(3, 0, 0):
5137 case IP_VERSION(3, 1, 2):
5138 case IP_VERSION(3, 1, 3):
5139 case IP_VERSION(3, 1, 4):
5140 case IP_VERSION(3, 1, 5):
5141 case IP_VERSION(3, 1, 6):
5142 case IP_VERSION(3, 2, 0):
5143 case IP_VERSION(3, 2, 1):
5144 case IP_VERSION(2, 1, 0):
5145 case IP_VERSION(3, 5, 0):
5146 case IP_VERSION(3, 5, 1):
5147 case IP_VERSION(3, 6, 0):
5148 case IP_VERSION(4, 0, 1):
5149 if (register_outbox_irq_handlers(dm->adev)) {
5150 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
5151 goto fail;
5152 }
5153 break;
5154 default:
5155 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
5156 amdgpu_ip_version(adev, DCE_HWIP, 0));
5157 }
5158
5159 /* Determine whether to enable PSR support by default. */
5160 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
5161 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5162 case IP_VERSION(3, 1, 2):
5163 case IP_VERSION(3, 1, 3):
5164 case IP_VERSION(3, 1, 4):
5165 case IP_VERSION(3, 1, 5):
5166 case IP_VERSION(3, 1, 6):
5167 case IP_VERSION(3, 2, 0):
5168 case IP_VERSION(3, 2, 1):
5169 case IP_VERSION(3, 5, 0):
5170 case IP_VERSION(3, 5, 1):
5171 case IP_VERSION(3, 6, 0):
5172 case IP_VERSION(4, 0, 1):
5173 psr_feature_enabled = true;
5174 break;
5175 default:
5176 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
5177 break;
5178 }
5179 }
5180
5181 /* Determine whether to enable Replay support by default. */
5182 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
5183 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5184 case IP_VERSION(3, 1, 4):
5185 case IP_VERSION(3, 2, 0):
5186 case IP_VERSION(3, 2, 1):
5187 case IP_VERSION(3, 5, 0):
5188 case IP_VERSION(3, 5, 1):
5189 case IP_VERSION(3, 6, 0):
5190 replay_feature_enabled = true;
5191 break;
5192
5193 default:
5194 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
5195 break;
5196 }
5197 }
5198
5199 if (link_cnt > MAX_LINKS) {
5200 drm_err(adev_to_drm(adev),
5201 "KMS: Cannot support more than %d display indexes\n",
5202 MAX_LINKS);
5203 goto fail;
5204 }
5205
5206 /* loops over all connectors on the board */
5207 for (i = 0; i < link_cnt; i++) {
5208 struct dc_link *link = NULL;
5209
5210 link = dc_get_link_at_index(dm->dc, i);
5211
5212 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {
5213 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);
5214
5215 if (!wbcon) {
5216 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n");
5217 continue;
5218 }
5219
5220 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {
5221 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n");
5222 kfree(wbcon);
5223 continue;
5224 }
5225
5226 link->psr_settings.psr_feature_enabled = false;
5227 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
5228
5229 continue;
5230 }
5231
5232 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
5233 if (!aconnector)
5234 goto fail;
5235
5236 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
5237 if (!aencoder)
5238 goto fail;
5239
5240 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
5241 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n");
5242 goto fail;
5243 }
5244
5245 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
5246 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n");
5247 goto fail;
5248 }
5249
5250 if (dm->hpd_rx_offload_wq)
5251 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector =
5252 aconnector;
5253
5254 if (!dc_link_detect_connection_type(link, &new_connection_type))
5255 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");
5256
5257 if (aconnector->base.force && new_connection_type == dc_connection_none) {
5258 emulated_link_detect(link);
5259 amdgpu_dm_update_connector_after_detect(aconnector);
5260 } else {
5261 bool ret = false;
5262
5263 mutex_lock(&dm->dc_lock);
5264 dc_exit_ips_for_hw_access(dm->dc);
5265 ret = dc_link_detect(link, DETECT_REASON_BOOT);
5266 mutex_unlock(&dm->dc_lock);
5267
5268 if (ret) {
5269 amdgpu_dm_update_connector_after_detect(aconnector);
5270 setup_backlight_device(dm, aconnector);
5271
5272 /* Disable PSR if Replay can be enabled */
5273 if (replay_feature_enabled)
5274 if (amdgpu_dm_set_replay_caps(link, aconnector))
5275 psr_feature_enabled = false;
5276
5277 if (psr_feature_enabled) {
5278 amdgpu_dm_set_psr_caps(link);
5279 drm_info(adev_to_drm(adev), "PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
5280 link->psr_settings.psr_feature_enabled,
5281 link->psr_settings.psr_version,
5282 link->dpcd_caps.psr_info.psr_version,
5283 link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
5284 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
5285 }
5286 }
5287 }
5288 amdgpu_set_panel_orientation(&aconnector->base);
5289 }
5290
5291 /* Software is initialized. Now we can register interrupt handlers. */
5292 switch (adev->asic_type) {
5293#if defined(CONFIG_DRM_AMD_DC_SI)
5294 case CHIP_TAHITI:
5295 case CHIP_PITCAIRN:
5296 case CHIP_VERDE:
5297 case CHIP_OLAND:
5298 if (dce60_register_irq_handlers(dm->adev)) {
5299 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
5300 goto fail;
5301 }
5302 break;
5303#endif
5304 case CHIP_BONAIRE:
5305 case CHIP_HAWAII:
5306 case CHIP_KAVERI:
5307 case CHIP_KABINI:
5308 case CHIP_MULLINS:
5309 case CHIP_TONGA:
5310 case CHIP_FIJI:
5311 case CHIP_CARRIZO:
5312 case CHIP_STONEY:
5313 case CHIP_POLARIS11:
5314 case CHIP_POLARIS10:
5315 case CHIP_POLARIS12:
5316 case CHIP_VEGAM:
5317 case CHIP_VEGA10:
5318 case CHIP_VEGA12:
5319 case CHIP_VEGA20:
5320 if (dce110_register_irq_handlers(dm->adev)) {
5321 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
5322 goto fail;
5323 }
5324 break;
5325 default:
5326 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5327 case IP_VERSION(1, 0, 0):
5328 case IP_VERSION(1, 0, 1):
5329 case IP_VERSION(2, 0, 2):
5330 case IP_VERSION(2, 0, 3):
5331 case IP_VERSION(2, 0, 0):
5332 case IP_VERSION(2, 1, 0):
5333 case IP_VERSION(3, 0, 0):
5334 case IP_VERSION(3, 0, 2):
5335 case IP_VERSION(3, 0, 3):
5336 case IP_VERSION(3, 0, 1):
5337 case IP_VERSION(3, 1, 2):
5338 case IP_VERSION(3, 1, 3):
5339 case IP_VERSION(3, 1, 4):
5340 case IP_VERSION(3, 1, 5):
5341 case IP_VERSION(3, 1, 6):
5342 case IP_VERSION(3, 2, 0):
5343 case IP_VERSION(3, 2, 1):
5344 case IP_VERSION(3, 5, 0):
5345 case IP_VERSION(3, 5, 1):
5346 case IP_VERSION(3, 6, 0):
5347 case IP_VERSION(4, 0, 1):
5348 if (dcn10_register_irq_handlers(dm->adev)) {
5349 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
5350 goto fail;
5351 }
5352 break;
5353 default:
5354 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n",
5355 amdgpu_ip_version(adev, DCE_HWIP, 0));
5356 goto fail;
5357 }
5358 break;
5359 }
5360
5361 return 0;
5362fail:
5363 kfree(aencoder);
5364 kfree(aconnector);
5365
5366 return -EINVAL;
5367}
5368
5369static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
5370{
5371 drm_atomic_private_obj_fini(&dm->atomic_obj);
5372}
5373
5374/******************************************************************************
5375 * amdgpu_display_funcs functions
5376 *****************************************************************************/
5377
5378/*
5379 * dm_bandwidth_update - program display watermarks
5380 *
5381 * @adev: amdgpu_device pointer
5382 *
5383 * Calculate and program the display watermarks and line buffer allocation.
5384 */
5385static void dm_bandwidth_update(struct amdgpu_device *adev)
5386{
5387 /* TODO: implement later */
5388}
5389
5390static const struct amdgpu_display_funcs dm_display_funcs = {
5391 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
5392 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
5393 .backlight_set_level = NULL, /* never called for DC */
5394 .backlight_get_level = NULL, /* never called for DC */
5395 .hpd_sense = NULL,/* called unconditionally */
5396 .hpd_set_polarity = NULL, /* called unconditionally */
5397 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
5398 .page_flip_get_scanoutpos =
5399 dm_crtc_get_scanoutpos,/* called unconditionally */
5400 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
5401 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
5402};
5403
5404#if defined(CONFIG_DEBUG_KERNEL_DC)
5405
5406static ssize_t s3_debug_store(struct device *device,
5407 struct device_attribute *attr,
5408 const char *buf,
5409 size_t count)
5410{
5411 int ret;
5412 int s3_state;
5413 struct drm_device *drm_dev = dev_get_drvdata(device);
5414 struct amdgpu_device *adev = drm_to_adev(drm_dev);
5415 struct amdgpu_ip_block *ip_block;
5416
5417 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE);
5418 if (!ip_block)
5419 return -EINVAL;
5420
5421 ret = kstrtoint(buf, 0, &s3_state);
5422
5423 if (ret == 0) {
5424 if (s3_state) {
5425 dm_resume(ip_block);
5426 drm_kms_helper_hotplug_event(adev_to_drm(adev));
5427 } else
5428 dm_suspend(ip_block);
5429 }
5430
5431 return ret == 0 ? count : 0;
5432}
5433
5434DEVICE_ATTR_WO(s3_debug);
5435
5436#endif
5437
5438static int dm_init_microcode(struct amdgpu_device *adev)
5439{
5440 char *fw_name_dmub;
5441 int r;
5442
5443 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5444 case IP_VERSION(2, 1, 0):
5445 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
5446 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
5447 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
5448 break;
5449 case IP_VERSION(3, 0, 0):
5450 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
5451 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
5452 else
5453 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
5454 break;
5455 case IP_VERSION(3, 0, 1):
5456 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
5457 break;
5458 case IP_VERSION(3, 0, 2):
5459 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
5460 break;
5461 case IP_VERSION(3, 0, 3):
5462 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
5463 break;
5464 case IP_VERSION(3, 1, 2):
5465 case IP_VERSION(3, 1, 3):
5466 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
5467 break;
5468 case IP_VERSION(3, 1, 4):
5469 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
5470 break;
5471 case IP_VERSION(3, 1, 5):
5472 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
5473 break;
5474 case IP_VERSION(3, 1, 6):
5475 fw_name_dmub = FIRMWARE_DCN316_DMUB;
5476 break;
5477 case IP_VERSION(3, 2, 0):
5478 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
5479 break;
5480 case IP_VERSION(3, 2, 1):
5481 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
5482 break;
5483 case IP_VERSION(3, 5, 0):
5484 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
5485 break;
5486 case IP_VERSION(3, 5, 1):
5487 fw_name_dmub = FIRMWARE_DCN_351_DMUB;
5488 break;
5489 case IP_VERSION(3, 6, 0):
5490 fw_name_dmub = FIRMWARE_DCN_36_DMUB;
5491 break;
5492 case IP_VERSION(4, 0, 1):
5493 fw_name_dmub = FIRMWARE_DCN_401_DMUB;
5494 break;
5495 default:
5496 /* ASIC doesn't support DMUB. */
5497 return 0;
5498 }
5499 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, AMDGPU_UCODE_REQUIRED,
5500 "%s", fw_name_dmub);
5501 return r;
5502}
5503
5504static int dm_early_init(struct amdgpu_ip_block *ip_block)
5505{
5506 struct amdgpu_device *adev = ip_block->adev;
5507 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5508 struct atom_context *ctx = mode_info->atom_context;
5509 int index = GetIndexIntoMasterTable(DATA, Object_Header);
5510 u16 data_offset;
5511
5512 /* if there is no object header, skip DM */
5513 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
5514 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
5515 drm_info(adev_to_drm(adev), "No object header, skipping DM\n");
5516 return -ENOENT;
5517 }
5518
5519 switch (adev->asic_type) {
5520#if defined(CONFIG_DRM_AMD_DC_SI)
5521 case CHIP_TAHITI:
5522 case CHIP_PITCAIRN:
5523 case CHIP_VERDE:
5524 adev->mode_info.num_crtc = 6;
5525 adev->mode_info.num_hpd = 6;
5526 adev->mode_info.num_dig = 6;
5527 break;
5528 case CHIP_OLAND:
5529 adev->mode_info.num_crtc = 2;
5530 adev->mode_info.num_hpd = 2;
5531 adev->mode_info.num_dig = 2;
5532 break;
5533#endif
5534 case CHIP_BONAIRE:
5535 case CHIP_HAWAII:
5536 adev->mode_info.num_crtc = 6;
5537 adev->mode_info.num_hpd = 6;
5538 adev->mode_info.num_dig = 6;
5539 break;
5540 case CHIP_KAVERI:
5541 adev->mode_info.num_crtc = 4;
5542 adev->mode_info.num_hpd = 6;
5543 adev->mode_info.num_dig = 7;
5544 break;
5545 case CHIP_KABINI:
5546 case CHIP_MULLINS:
5547 adev->mode_info.num_crtc = 2;
5548 adev->mode_info.num_hpd = 6;
5549 adev->mode_info.num_dig = 6;
5550 break;
5551 case CHIP_FIJI:
5552 case CHIP_TONGA:
5553 adev->mode_info.num_crtc = 6;
5554 adev->mode_info.num_hpd = 6;
5555 adev->mode_info.num_dig = 7;
5556 break;
5557 case CHIP_CARRIZO:
5558 adev->mode_info.num_crtc = 3;
5559 adev->mode_info.num_hpd = 6;
5560 adev->mode_info.num_dig = 9;
5561 break;
5562 case CHIP_STONEY:
5563 adev->mode_info.num_crtc = 2;
5564 adev->mode_info.num_hpd = 6;
5565 adev->mode_info.num_dig = 9;
5566 break;
5567 case CHIP_POLARIS11:
5568 case CHIP_POLARIS12:
5569 adev->mode_info.num_crtc = 5;
5570 adev->mode_info.num_hpd = 5;
5571 adev->mode_info.num_dig = 5;
5572 break;
5573 case CHIP_POLARIS10:
5574 case CHIP_VEGAM:
5575 adev->mode_info.num_crtc = 6;
5576 adev->mode_info.num_hpd = 6;
5577 adev->mode_info.num_dig = 6;
5578 break;
5579 case CHIP_VEGA10:
5580 case CHIP_VEGA12:
5581 case CHIP_VEGA20:
5582 adev->mode_info.num_crtc = 6;
5583 adev->mode_info.num_hpd = 6;
5584 adev->mode_info.num_dig = 6;
5585 break;
5586 default:
5587
5588 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5589 case IP_VERSION(2, 0, 2):
5590 case IP_VERSION(3, 0, 0):
5591 adev->mode_info.num_crtc = 6;
5592 adev->mode_info.num_hpd = 6;
5593 adev->mode_info.num_dig = 6;
5594 break;
5595 case IP_VERSION(2, 0, 0):
5596 case IP_VERSION(3, 0, 2):
5597 adev->mode_info.num_crtc = 5;
5598 adev->mode_info.num_hpd = 5;
5599 adev->mode_info.num_dig = 5;
5600 break;
5601 case IP_VERSION(2, 0, 3):
5602 case IP_VERSION(3, 0, 3):
5603 adev->mode_info.num_crtc = 2;
5604 adev->mode_info.num_hpd = 2;
5605 adev->mode_info.num_dig = 2;
5606 break;
5607 case IP_VERSION(1, 0, 0):
5608 case IP_VERSION(1, 0, 1):
5609 case IP_VERSION(3, 0, 1):
5610 case IP_VERSION(2, 1, 0):
5611 case IP_VERSION(3, 1, 2):
5612 case IP_VERSION(3, 1, 3):
5613 case IP_VERSION(3, 1, 4):
5614 case IP_VERSION(3, 1, 5):
5615 case IP_VERSION(3, 1, 6):
5616 case IP_VERSION(3, 2, 0):
5617 case IP_VERSION(3, 2, 1):
5618 case IP_VERSION(3, 5, 0):
5619 case IP_VERSION(3, 5, 1):
5620 case IP_VERSION(3, 6, 0):
5621 case IP_VERSION(4, 0, 1):
5622 adev->mode_info.num_crtc = 4;
5623 adev->mode_info.num_hpd = 4;
5624 adev->mode_info.num_dig = 4;
5625 break;
5626 default:
5627 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n",
5628 amdgpu_ip_version(adev, DCE_HWIP, 0));
5629 return -EINVAL;
5630 }
5631 break;
5632 }
5633
5634 if (adev->mode_info.funcs == NULL)
5635 adev->mode_info.funcs = &dm_display_funcs;
5636
5637 /*
5638 * Note: Do NOT change adev->audio_endpt_rreg and
5639 * adev->audio_endpt_wreg because they are initialised in
5640 * amdgpu_device_init()
5641 */
5642#if defined(CONFIG_DEBUG_KERNEL_DC)
5643 device_create_file(
5644 adev_to_drm(adev)->dev,
5645 &dev_attr_s3_debug);
5646#endif
5647 adev->dc_enabled = true;
5648
5649 return dm_init_microcode(adev);
5650}
5651
5652static bool modereset_required(struct drm_crtc_state *crtc_state)
5653{
5654 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
5655}
5656
5657static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
5658{
5659 drm_encoder_cleanup(encoder);
5660 kfree(encoder);
5661}
5662
5663static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
5664 .destroy = amdgpu_dm_encoder_destroy,
5665};
5666
5667static int
5668fill_plane_color_attributes(const struct drm_plane_state *plane_state,
5669 const enum surface_pixel_format format,
5670 enum dc_color_space *color_space)
5671{
5672 bool full_range;
5673
5674 *color_space = COLOR_SPACE_SRGB;
5675
5676 /* DRM color properties only affect non-RGB formats. */
5677 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
5678 return 0;
5679
5680 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
5681
5682 switch (plane_state->color_encoding) {
5683 case DRM_COLOR_YCBCR_BT601:
5684 if (full_range)
5685 *color_space = COLOR_SPACE_YCBCR601;
5686 else
5687 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
5688 break;
5689
5690 case DRM_COLOR_YCBCR_BT709:
5691 if (full_range)
5692 *color_space = COLOR_SPACE_YCBCR709;
5693 else
5694 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
5695 break;
5696
5697 case DRM_COLOR_YCBCR_BT2020:
5698 if (full_range)
5699 *color_space = COLOR_SPACE_2020_YCBCR_FULL;
5700 else
5701 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED;
5702 break;
5703
5704 default:
5705 return -EINVAL;
5706 }
5707
5708 return 0;
5709}
5710
5711static int
5712fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
5713 const struct drm_plane_state *plane_state,
5714 const u64 tiling_flags,
5715 struct dc_plane_info *plane_info,
5716 struct dc_plane_address *address,
5717 bool tmz_surface)
5718{
5719 const struct drm_framebuffer *fb = plane_state->fb;
5720 const struct amdgpu_framebuffer *afb =
5721 to_amdgpu_framebuffer(plane_state->fb);
5722 int ret;
5723
5724 memset(plane_info, 0, sizeof(*plane_info));
5725
5726 switch (fb->format->format) {
5727 case DRM_FORMAT_C8:
5728 plane_info->format =
5729 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
5730 break;
5731 case DRM_FORMAT_RGB565:
5732 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
5733 break;
5734 case DRM_FORMAT_XRGB8888:
5735 case DRM_FORMAT_ARGB8888:
5736 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
5737 break;
5738 case DRM_FORMAT_XRGB2101010:
5739 case DRM_FORMAT_ARGB2101010:
5740 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
5741 break;
5742 case DRM_FORMAT_XBGR2101010:
5743 case DRM_FORMAT_ABGR2101010:
5744 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
5745 break;
5746 case DRM_FORMAT_XBGR8888:
5747 case DRM_FORMAT_ABGR8888:
5748 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
5749 break;
5750 case DRM_FORMAT_NV21:
5751 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
5752 break;
5753 case DRM_FORMAT_NV12:
5754 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
5755 break;
5756 case DRM_FORMAT_P010:
5757 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
5758 break;
5759 case DRM_FORMAT_XRGB16161616F:
5760 case DRM_FORMAT_ARGB16161616F:
5761 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
5762 break;
5763 case DRM_FORMAT_XBGR16161616F:
5764 case DRM_FORMAT_ABGR16161616F:
5765 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
5766 break;
5767 case DRM_FORMAT_XRGB16161616:
5768 case DRM_FORMAT_ARGB16161616:
5769 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5770 break;
5771 case DRM_FORMAT_XBGR16161616:
5772 case DRM_FORMAT_ABGR16161616:
5773 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5774 break;
5775 default:
5776 drm_err(adev_to_drm(adev),
5777 "Unsupported screen format %p4cc\n",
5778 &fb->format->format);
5779 return -EINVAL;
5780 }
5781
5782 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5783 case DRM_MODE_ROTATE_0:
5784 plane_info->rotation = ROTATION_ANGLE_0;
5785 break;
5786 case DRM_MODE_ROTATE_90:
5787 plane_info->rotation = ROTATION_ANGLE_90;
5788 break;
5789 case DRM_MODE_ROTATE_180:
5790 plane_info->rotation = ROTATION_ANGLE_180;
5791 break;
5792 case DRM_MODE_ROTATE_270:
5793 plane_info->rotation = ROTATION_ANGLE_270;
5794 break;
5795 default:
5796 plane_info->rotation = ROTATION_ANGLE_0;
5797 break;
5798 }
5799
5800
5801 plane_info->visible = true;
5802 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5803
5804 plane_info->layer_index = plane_state->normalized_zpos;
5805
5806 ret = fill_plane_color_attributes(plane_state, plane_info->format,
5807 &plane_info->color_space);
5808 if (ret)
5809 return ret;
5810
5811 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5812 plane_info->rotation, tiling_flags,
5813 &plane_info->tiling_info,
5814 &plane_info->plane_size,
5815 &plane_info->dcc, address,
5816 tmz_surface);
5817 if (ret)
5818 return ret;
5819
5820 amdgpu_dm_plane_fill_blending_from_plane_state(
5821 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5822 &plane_info->global_alpha, &plane_info->global_alpha_value);
5823
5824 return 0;
5825}
5826
5827static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5828 struct dc_plane_state *dc_plane_state,
5829 struct drm_plane_state *plane_state,
5830 struct drm_crtc_state *crtc_state)
5831{
5832 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5833 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5834 struct dc_scaling_info scaling_info;
5835 struct dc_plane_info plane_info;
5836 int ret;
5837
5838 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5839 if (ret)
5840 return ret;
5841
5842 dc_plane_state->src_rect = scaling_info.src_rect;
5843 dc_plane_state->dst_rect = scaling_info.dst_rect;
5844 dc_plane_state->clip_rect = scaling_info.clip_rect;
5845 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5846
5847 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5848 afb->tiling_flags,
5849 &plane_info,
5850 &dc_plane_state->address,
5851 afb->tmz_surface);
5852 if (ret)
5853 return ret;
5854
5855 dc_plane_state->format = plane_info.format;
5856 dc_plane_state->color_space = plane_info.color_space;
5857 dc_plane_state->format = plane_info.format;
5858 dc_plane_state->plane_size = plane_info.plane_size;
5859 dc_plane_state->rotation = plane_info.rotation;
5860 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5861 dc_plane_state->stereo_format = plane_info.stereo_format;
5862 dc_plane_state->tiling_info = plane_info.tiling_info;
5863 dc_plane_state->visible = plane_info.visible;
5864 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5865 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5866 dc_plane_state->global_alpha = plane_info.global_alpha;
5867 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5868 dc_plane_state->dcc = plane_info.dcc;
5869 dc_plane_state->layer_index = plane_info.layer_index;
5870 dc_plane_state->flip_int_enabled = true;
5871
5872 /*
5873 * Always set input transfer function, since plane state is refreshed
5874 * every time.
5875 */
5876 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,
5877 plane_state,
5878 dc_plane_state);
5879 if (ret)
5880 return ret;
5881
5882 return 0;
5883}
5884
5885static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5886 struct rect *dirty_rect, int32_t x,
5887 s32 y, s32 width, s32 height,
5888 int *i, bool ffu)
5889{
5890 WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5891
5892 dirty_rect->x = x;
5893 dirty_rect->y = y;
5894 dirty_rect->width = width;
5895 dirty_rect->height = height;
5896
5897 if (ffu)
5898 drm_dbg(plane->dev,
5899 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5900 plane->base.id, width, height);
5901 else
5902 drm_dbg(plane->dev,
5903 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5904 plane->base.id, x, y, width, height);
5905
5906 (*i)++;
5907}
5908
5909/**
5910 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5911 *
5912 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5913 * remote fb
5914 * @old_plane_state: Old state of @plane
5915 * @new_plane_state: New state of @plane
5916 * @crtc_state: New state of CRTC connected to the @plane
5917 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5918 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled.
5919 * If PSR SU is enabled and damage clips are available, only the regions of the screen
5920 * that have changed will be updated. If PSR SU is not enabled,
5921 * or if damage clips are not available, the entire screen will be updated.
5922 * @dirty_regions_changed: dirty regions changed
5923 *
5924 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5925 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5926 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5927 * amdgpu_dm's.
5928 *
5929 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5930 * plane with regions that require flushing to the eDP remote buffer. In
5931 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5932 * implicitly provide damage clips without any client support via the plane
5933 * bounds.
5934 */
5935static void fill_dc_dirty_rects(struct drm_plane *plane,
5936 struct drm_plane_state *old_plane_state,
5937 struct drm_plane_state *new_plane_state,
5938 struct drm_crtc_state *crtc_state,
5939 struct dc_flip_addrs *flip_addrs,
5940 bool is_psr_su,
5941 bool *dirty_regions_changed)
5942{
5943 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5944 struct rect *dirty_rects = flip_addrs->dirty_rects;
5945 u32 num_clips;
5946 struct drm_mode_rect *clips;
5947 bool bb_changed;
5948 bool fb_changed;
5949 u32 i = 0;
5950 *dirty_regions_changed = false;
5951
5952 /*
5953 * Cursor plane has it's own dirty rect update interface. See
5954 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5955 */
5956 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5957 return;
5958
5959 if (new_plane_state->rotation != DRM_MODE_ROTATE_0)
5960 goto ffu;
5961
5962 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5963 clips = drm_plane_get_damage_clips(new_plane_state);
5964
5965 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 &&
5966 is_psr_su)))
5967 goto ffu;
5968
5969 if (!dm_crtc_state->mpo_requested) {
5970 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5971 goto ffu;
5972
5973 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5974 fill_dc_dirty_rect(new_plane_state->plane,
5975 &dirty_rects[flip_addrs->dirty_rect_count],
5976 clips->x1, clips->y1,
5977 clips->x2 - clips->x1, clips->y2 - clips->y1,
5978 &flip_addrs->dirty_rect_count,
5979 false);
5980 return;
5981 }
5982
5983 /*
5984 * MPO is requested. Add entire plane bounding box to dirty rects if
5985 * flipped to or damaged.
5986 *
5987 * If plane is moved or resized, also add old bounding box to dirty
5988 * rects.
5989 */
5990 fb_changed = old_plane_state->fb->base.id !=
5991 new_plane_state->fb->base.id;
5992 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5993 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5994 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5995 old_plane_state->crtc_h != new_plane_state->crtc_h);
5996
5997 drm_dbg(plane->dev,
5998 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5999 new_plane_state->plane->base.id,
6000 bb_changed, fb_changed, num_clips);
6001
6002 *dirty_regions_changed = bb_changed;
6003
6004 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
6005 goto ffu;
6006
6007 if (bb_changed) {
6008 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
6009 new_plane_state->crtc_x,
6010 new_plane_state->crtc_y,
6011 new_plane_state->crtc_w,
6012 new_plane_state->crtc_h, &i, false);
6013
6014 /* Add old plane bounding-box if plane is moved or resized */
6015 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
6016 old_plane_state->crtc_x,
6017 old_plane_state->crtc_y,
6018 old_plane_state->crtc_w,
6019 old_plane_state->crtc_h, &i, false);
6020 }
6021
6022 if (num_clips) {
6023 for (; i < num_clips; clips++)
6024 fill_dc_dirty_rect(new_plane_state->plane,
6025 &dirty_rects[i], clips->x1,
6026 clips->y1, clips->x2 - clips->x1,
6027 clips->y2 - clips->y1, &i, false);
6028 } else if (fb_changed && !bb_changed) {
6029 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
6030 new_plane_state->crtc_x,
6031 new_plane_state->crtc_y,
6032 new_plane_state->crtc_w,
6033 new_plane_state->crtc_h, &i, false);
6034 }
6035
6036 flip_addrs->dirty_rect_count = i;
6037 return;
6038
6039ffu:
6040 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
6041 dm_crtc_state->base.mode.crtc_hdisplay,
6042 dm_crtc_state->base.mode.crtc_vdisplay,
6043 &flip_addrs->dirty_rect_count, true);
6044}
6045
6046static void update_stream_scaling_settings(const struct drm_display_mode *mode,
6047 const struct dm_connector_state *dm_state,
6048 struct dc_stream_state *stream)
6049{
6050 enum amdgpu_rmx_type rmx_type;
6051
6052 struct rect src = { 0 }; /* viewport in composition space*/
6053 struct rect dst = { 0 }; /* stream addressable area */
6054
6055 /* no mode. nothing to be done */
6056 if (!mode)
6057 return;
6058
6059 /* Full screen scaling by default */
6060 src.width = mode->hdisplay;
6061 src.height = mode->vdisplay;
6062 dst.width = stream->timing.h_addressable;
6063 dst.height = stream->timing.v_addressable;
6064
6065 if (dm_state) {
6066 rmx_type = dm_state->scaling;
6067 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
6068 if (src.width * dst.height <
6069 src.height * dst.width) {
6070 /* height needs less upscaling/more downscaling */
6071 dst.width = src.width *
6072 dst.height / src.height;
6073 } else {
6074 /* width needs less upscaling/more downscaling */
6075 dst.height = src.height *
6076 dst.width / src.width;
6077 }
6078 } else if (rmx_type == RMX_CENTER) {
6079 dst = src;
6080 }
6081
6082 dst.x = (stream->timing.h_addressable - dst.width) / 2;
6083 dst.y = (stream->timing.v_addressable - dst.height) / 2;
6084
6085 if (dm_state->underscan_enable) {
6086 dst.x += dm_state->underscan_hborder / 2;
6087 dst.y += dm_state->underscan_vborder / 2;
6088 dst.width -= dm_state->underscan_hborder;
6089 dst.height -= dm_state->underscan_vborder;
6090 }
6091 }
6092
6093 stream->src = src;
6094 stream->dst = dst;
6095
6096 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
6097 dst.x, dst.y, dst.width, dst.height);
6098
6099}
6100
6101static enum dc_color_depth
6102convert_color_depth_from_display_info(const struct drm_connector *connector,
6103 bool is_y420, int requested_bpc)
6104{
6105 u8 bpc;
6106
6107 if (is_y420) {
6108 bpc = 8;
6109
6110 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
6111 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
6112 bpc = 16;
6113 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
6114 bpc = 12;
6115 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
6116 bpc = 10;
6117 } else {
6118 bpc = (uint8_t)connector->display_info.bpc;
6119 /* Assume 8 bpc by default if no bpc is specified. */
6120 bpc = bpc ? bpc : 8;
6121 }
6122
6123 if (requested_bpc > 0) {
6124 /*
6125 * Cap display bpc based on the user requested value.
6126 *
6127 * The value for state->max_bpc may not correctly updated
6128 * depending on when the connector gets added to the state
6129 * or if this was called outside of atomic check, so it
6130 * can't be used directly.
6131 */
6132 bpc = min_t(u8, bpc, requested_bpc);
6133
6134 /* Round down to the nearest even number. */
6135 bpc = bpc - (bpc & 1);
6136 }
6137
6138 switch (bpc) {
6139 case 0:
6140 /*
6141 * Temporary Work around, DRM doesn't parse color depth for
6142 * EDID revision before 1.4
6143 * TODO: Fix edid parsing
6144 */
6145 return COLOR_DEPTH_888;
6146 case 6:
6147 return COLOR_DEPTH_666;
6148 case 8:
6149 return COLOR_DEPTH_888;
6150 case 10:
6151 return COLOR_DEPTH_101010;
6152 case 12:
6153 return COLOR_DEPTH_121212;
6154 case 14:
6155 return COLOR_DEPTH_141414;
6156 case 16:
6157 return COLOR_DEPTH_161616;
6158 default:
6159 return COLOR_DEPTH_UNDEFINED;
6160 }
6161}
6162
6163static enum dc_aspect_ratio
6164get_aspect_ratio(const struct drm_display_mode *mode_in)
6165{
6166 /* 1-1 mapping, since both enums follow the HDMI spec. */
6167 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
6168}
6169
6170static enum dc_color_space
6171get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
6172 const struct drm_connector_state *connector_state)
6173{
6174 enum dc_color_space color_space = COLOR_SPACE_SRGB;
6175
6176 switch (connector_state->colorspace) {
6177 case DRM_MODE_COLORIMETRY_BT601_YCC:
6178 if (dc_crtc_timing->flags.Y_ONLY)
6179 color_space = COLOR_SPACE_YCBCR601_LIMITED;
6180 else
6181 color_space = COLOR_SPACE_YCBCR601;
6182 break;
6183 case DRM_MODE_COLORIMETRY_BT709_YCC:
6184 if (dc_crtc_timing->flags.Y_ONLY)
6185 color_space = COLOR_SPACE_YCBCR709_LIMITED;
6186 else
6187 color_space = COLOR_SPACE_YCBCR709;
6188 break;
6189 case DRM_MODE_COLORIMETRY_OPRGB:
6190 color_space = COLOR_SPACE_ADOBERGB;
6191 break;
6192 case DRM_MODE_COLORIMETRY_BT2020_RGB:
6193 case DRM_MODE_COLORIMETRY_BT2020_YCC:
6194 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
6195 color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
6196 else
6197 color_space = COLOR_SPACE_2020_YCBCR_LIMITED;
6198 break;
6199 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
6200 default:
6201 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
6202 color_space = COLOR_SPACE_SRGB;
6203 if (connector_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED)
6204 color_space = COLOR_SPACE_SRGB_LIMITED;
6205 /*
6206 * 27030khz is the separation point between HDTV and SDTV
6207 * according to HDMI spec, we use YCbCr709 and YCbCr601
6208 * respectively
6209 */
6210 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
6211 if (dc_crtc_timing->flags.Y_ONLY)
6212 color_space =
6213 COLOR_SPACE_YCBCR709_LIMITED;
6214 else
6215 color_space = COLOR_SPACE_YCBCR709;
6216 } else {
6217 if (dc_crtc_timing->flags.Y_ONLY)
6218 color_space =
6219 COLOR_SPACE_YCBCR601_LIMITED;
6220 else
6221 color_space = COLOR_SPACE_YCBCR601;
6222 }
6223 break;
6224 }
6225
6226 return color_space;
6227}
6228
6229static enum display_content_type
6230get_output_content_type(const struct drm_connector_state *connector_state)
6231{
6232 switch (connector_state->content_type) {
6233 default:
6234 case DRM_MODE_CONTENT_TYPE_NO_DATA:
6235 return DISPLAY_CONTENT_TYPE_NO_DATA;
6236 case DRM_MODE_CONTENT_TYPE_GRAPHICS:
6237 return DISPLAY_CONTENT_TYPE_GRAPHICS;
6238 case DRM_MODE_CONTENT_TYPE_PHOTO:
6239 return DISPLAY_CONTENT_TYPE_PHOTO;
6240 case DRM_MODE_CONTENT_TYPE_CINEMA:
6241 return DISPLAY_CONTENT_TYPE_CINEMA;
6242 case DRM_MODE_CONTENT_TYPE_GAME:
6243 return DISPLAY_CONTENT_TYPE_GAME;
6244 }
6245}
6246
6247static bool adjust_colour_depth_from_display_info(
6248 struct dc_crtc_timing *timing_out,
6249 const struct drm_display_info *info)
6250{
6251 enum dc_color_depth depth = timing_out->display_color_depth;
6252 int normalized_clk;
6253
6254 do {
6255 normalized_clk = timing_out->pix_clk_100hz / 10;
6256 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
6257 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
6258 normalized_clk /= 2;
6259 /* Adjusting pix clock following on HDMI spec based on colour depth */
6260 switch (depth) {
6261 case COLOR_DEPTH_888:
6262 break;
6263 case COLOR_DEPTH_101010:
6264 normalized_clk = (normalized_clk * 30) / 24;
6265 break;
6266 case COLOR_DEPTH_121212:
6267 normalized_clk = (normalized_clk * 36) / 24;
6268 break;
6269 case COLOR_DEPTH_161616:
6270 normalized_clk = (normalized_clk * 48) / 24;
6271 break;
6272 default:
6273 /* The above depths are the only ones valid for HDMI. */
6274 return false;
6275 }
6276 if (normalized_clk <= info->max_tmds_clock) {
6277 timing_out->display_color_depth = depth;
6278 return true;
6279 }
6280 } while (--depth > COLOR_DEPTH_666);
6281 return false;
6282}
6283
6284static void fill_stream_properties_from_drm_display_mode(
6285 struct dc_stream_state *stream,
6286 const struct drm_display_mode *mode_in,
6287 const struct drm_connector *connector,
6288 const struct drm_connector_state *connector_state,
6289 const struct dc_stream_state *old_stream,
6290 int requested_bpc)
6291{
6292 struct dc_crtc_timing *timing_out = &stream->timing;
6293 const struct drm_display_info *info = &connector->display_info;
6294 struct amdgpu_dm_connector *aconnector = NULL;
6295 struct hdmi_vendor_infoframe hv_frame;
6296 struct hdmi_avi_infoframe avi_frame;
6297 ssize_t err;
6298
6299 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
6300 aconnector = to_amdgpu_dm_connector(connector);
6301
6302 memset(&hv_frame, 0, sizeof(hv_frame));
6303 memset(&avi_frame, 0, sizeof(avi_frame));
6304
6305 timing_out->h_border_left = 0;
6306 timing_out->h_border_right = 0;
6307 timing_out->v_border_top = 0;
6308 timing_out->v_border_bottom = 0;
6309 /* TODO: un-hardcode */
6310 if (drm_mode_is_420_only(info, mode_in)
6311 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6312 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
6313 else if (drm_mode_is_420_also(info, mode_in)
6314 && aconnector
6315 && aconnector->force_yuv420_output)
6316 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
6317 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
6318 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6319 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
6320 else
6321 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
6322
6323 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
6324 timing_out->display_color_depth = convert_color_depth_from_display_info(
6325 connector,
6326 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
6327 requested_bpc);
6328 timing_out->scan_type = SCANNING_TYPE_NODATA;
6329 timing_out->hdmi_vic = 0;
6330
6331 if (old_stream) {
6332 timing_out->vic = old_stream->timing.vic;
6333 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
6334 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
6335 } else {
6336 timing_out->vic = drm_match_cea_mode(mode_in);
6337 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
6338 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
6339 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
6340 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
6341 }
6342
6343 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
6344 err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame,
6345 (struct drm_connector *)connector,
6346 mode_in);
6347 if (err < 0)
6348 drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd \n", connector->name, err);
6349 timing_out->vic = avi_frame.video_code;
6350 err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame,
6351 (struct drm_connector *)connector,
6352 mode_in);
6353 if (err < 0)
6354 drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd \n", connector->name, err);
6355 timing_out->hdmi_vic = hv_frame.vic;
6356 }
6357
6358 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) {
6359 timing_out->h_addressable = mode_in->hdisplay;
6360 timing_out->h_total = mode_in->htotal;
6361 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
6362 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
6363 timing_out->v_total = mode_in->vtotal;
6364 timing_out->v_addressable = mode_in->vdisplay;
6365 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
6366 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
6367 timing_out->pix_clk_100hz = mode_in->clock * 10;
6368 } else {
6369 timing_out->h_addressable = mode_in->crtc_hdisplay;
6370 timing_out->h_total = mode_in->crtc_htotal;
6371 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
6372 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
6373 timing_out->v_total = mode_in->crtc_vtotal;
6374 timing_out->v_addressable = mode_in->crtc_vdisplay;
6375 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
6376 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
6377 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
6378 }
6379
6380 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
6381
6382 stream->out_transfer_func.type = TF_TYPE_PREDEFINED;
6383 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB;
6384 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
6385 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
6386 drm_mode_is_420_also(info, mode_in) &&
6387 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
6388 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
6389 adjust_colour_depth_from_display_info(timing_out, info);
6390 }
6391 }
6392
6393 stream->output_color_space = get_output_color_space(timing_out, connector_state);
6394 stream->content_type = get_output_content_type(connector_state);
6395}
6396
6397static void fill_audio_info(struct audio_info *audio_info,
6398 const struct drm_connector *drm_connector,
6399 const struct dc_sink *dc_sink)
6400{
6401 int i = 0;
6402 int cea_revision = 0;
6403 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
6404
6405 audio_info->manufacture_id = edid_caps->manufacturer_id;
6406 audio_info->product_id = edid_caps->product_id;
6407
6408 cea_revision = drm_connector->display_info.cea_rev;
6409
6410 strscpy(audio_info->display_name,
6411 edid_caps->display_name,
6412 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
6413
6414 if (cea_revision >= 3) {
6415 audio_info->mode_count = edid_caps->audio_mode_count;
6416
6417 for (i = 0; i < audio_info->mode_count; ++i) {
6418 audio_info->modes[i].format_code =
6419 (enum audio_format_code)
6420 (edid_caps->audio_modes[i].format_code);
6421 audio_info->modes[i].channel_count =
6422 edid_caps->audio_modes[i].channel_count;
6423 audio_info->modes[i].sample_rates.all =
6424 edid_caps->audio_modes[i].sample_rate;
6425 audio_info->modes[i].sample_size =
6426 edid_caps->audio_modes[i].sample_size;
6427 }
6428 }
6429
6430 audio_info->flags.all = edid_caps->speaker_flags;
6431
6432 /* TODO: We only check for the progressive mode, check for interlace mode too */
6433 if (drm_connector->latency_present[0]) {
6434 audio_info->video_latency = drm_connector->video_latency[0];
6435 audio_info->audio_latency = drm_connector->audio_latency[0];
6436 }
6437
6438 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
6439
6440}
6441
6442static void
6443copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
6444 struct drm_display_mode *dst_mode)
6445{
6446 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
6447 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
6448 dst_mode->crtc_clock = src_mode->crtc_clock;
6449 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
6450 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
6451 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
6452 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
6453 dst_mode->crtc_htotal = src_mode->crtc_htotal;
6454 dst_mode->crtc_hskew = src_mode->crtc_hskew;
6455 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
6456 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
6457 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
6458 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
6459 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
6460}
6461
6462static void
6463decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
6464 const struct drm_display_mode *native_mode,
6465 bool scale_enabled)
6466{
6467 if (scale_enabled || (
6468 native_mode->clock == drm_mode->clock &&
6469 native_mode->htotal == drm_mode->htotal &&
6470 native_mode->vtotal == drm_mode->vtotal)) {
6471 if (native_mode->crtc_clock)
6472 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
6473 } else {
6474 /* no scaling nor amdgpu inserted, no need to patch */
6475 }
6476}
6477
6478static struct dc_sink *
6479create_fake_sink(struct drm_device *dev, struct dc_link *link)
6480{
6481 struct dc_sink_init_data sink_init_data = { 0 };
6482 struct dc_sink *sink = NULL;
6483
6484 sink_init_data.link = link;
6485 sink_init_data.sink_signal = link->connector_signal;
6486
6487 sink = dc_sink_create(&sink_init_data);
6488 if (!sink) {
6489 drm_err(dev, "Failed to create sink!\n");
6490 return NULL;
6491 }
6492 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
6493
6494 return sink;
6495}
6496
6497static void set_multisync_trigger_params(
6498 struct dc_stream_state *stream)
6499{
6500 struct dc_stream_state *master = NULL;
6501
6502 if (stream->triggered_crtc_reset.enabled) {
6503 master = stream->triggered_crtc_reset.event_source;
6504 stream->triggered_crtc_reset.event =
6505 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
6506 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
6507 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
6508 }
6509}
6510
6511static void set_master_stream(struct dc_stream_state *stream_set[],
6512 int stream_count)
6513{
6514 int j, highest_rfr = 0, master_stream = 0;
6515
6516 for (j = 0; j < stream_count; j++) {
6517 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
6518 int refresh_rate = 0;
6519
6520 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
6521 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
6522 if (refresh_rate > highest_rfr) {
6523 highest_rfr = refresh_rate;
6524 master_stream = j;
6525 }
6526 }
6527 }
6528 for (j = 0; j < stream_count; j++) {
6529 if (stream_set[j])
6530 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
6531 }
6532}
6533
6534static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
6535{
6536 int i = 0;
6537 struct dc_stream_state *stream;
6538
6539 if (context->stream_count < 2)
6540 return;
6541 for (i = 0; i < context->stream_count ; i++) {
6542 if (!context->streams[i])
6543 continue;
6544 /*
6545 * TODO: add a function to read AMD VSDB bits and set
6546 * crtc_sync_master.multi_sync_enabled flag
6547 * For now it's set to false
6548 */
6549 }
6550
6551 set_master_stream(context->streams, context->stream_count);
6552
6553 for (i = 0; i < context->stream_count ; i++) {
6554 stream = context->streams[i];
6555
6556 if (!stream)
6557 continue;
6558
6559 set_multisync_trigger_params(stream);
6560 }
6561}
6562
6563/**
6564 * DOC: FreeSync Video
6565 *
6566 * When a userspace application wants to play a video, the content follows a
6567 * standard format definition that usually specifies the FPS for that format.
6568 * The below list illustrates some video format and the expected FPS,
6569 * respectively:
6570 *
6571 * - TV/NTSC (23.976 FPS)
6572 * - Cinema (24 FPS)
6573 * - TV/PAL (25 FPS)
6574 * - TV/NTSC (29.97 FPS)
6575 * - TV/NTSC (30 FPS)
6576 * - Cinema HFR (48 FPS)
6577 * - TV/PAL (50 FPS)
6578 * - Commonly used (60 FPS)
6579 * - Multiples of 24 (48,72,96 FPS)
6580 *
6581 * The list of standards video format is not huge and can be added to the
6582 * connector modeset list beforehand. With that, userspace can leverage
6583 * FreeSync to extends the front porch in order to attain the target refresh
6584 * rate. Such a switch will happen seamlessly, without screen blanking or
6585 * reprogramming of the output in any other way. If the userspace requests a
6586 * modesetting change compatible with FreeSync modes that only differ in the
6587 * refresh rate, DC will skip the full update and avoid blink during the
6588 * transition. For example, the video player can change the modesetting from
6589 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
6590 * causing any display blink. This same concept can be applied to a mode
6591 * setting change.
6592 */
6593static struct drm_display_mode *
6594get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
6595 bool use_probed_modes)
6596{
6597 struct drm_display_mode *m, *m_pref = NULL;
6598 u16 current_refresh, highest_refresh;
6599 struct list_head *list_head = use_probed_modes ?
6600 &aconnector->base.probed_modes :
6601 &aconnector->base.modes;
6602
6603 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
6604 return NULL;
6605
6606 if (aconnector->freesync_vid_base.clock != 0)
6607 return &aconnector->freesync_vid_base;
6608
6609 /* Find the preferred mode */
6610 list_for_each_entry(m, list_head, head) {
6611 if (m->type & DRM_MODE_TYPE_PREFERRED) {
6612 m_pref = m;
6613 break;
6614 }
6615 }
6616
6617 if (!m_pref) {
6618 /* Probably an EDID with no preferred mode. Fallback to first entry */
6619 m_pref = list_first_entry_or_null(
6620 &aconnector->base.modes, struct drm_display_mode, head);
6621 if (!m_pref) {
6622 drm_dbg_driver(aconnector->base.dev, "No preferred mode found in EDID\n");
6623 return NULL;
6624 }
6625 }
6626
6627 highest_refresh = drm_mode_vrefresh(m_pref);
6628
6629 /*
6630 * Find the mode with highest refresh rate with same resolution.
6631 * For some monitors, preferred mode is not the mode with highest
6632 * supported refresh rate.
6633 */
6634 list_for_each_entry(m, list_head, head) {
6635 current_refresh = drm_mode_vrefresh(m);
6636
6637 if (m->hdisplay == m_pref->hdisplay &&
6638 m->vdisplay == m_pref->vdisplay &&
6639 highest_refresh < current_refresh) {
6640 highest_refresh = current_refresh;
6641 m_pref = m;
6642 }
6643 }
6644
6645 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
6646 return m_pref;
6647}
6648
6649static bool is_freesync_video_mode(const struct drm_display_mode *mode,
6650 struct amdgpu_dm_connector *aconnector)
6651{
6652 struct drm_display_mode *high_mode;
6653 int timing_diff;
6654
6655 high_mode = get_highest_refresh_rate_mode(aconnector, false);
6656 if (!high_mode || !mode)
6657 return false;
6658
6659 timing_diff = high_mode->vtotal - mode->vtotal;
6660
6661 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
6662 high_mode->hdisplay != mode->hdisplay ||
6663 high_mode->vdisplay != mode->vdisplay ||
6664 high_mode->hsync_start != mode->hsync_start ||
6665 high_mode->hsync_end != mode->hsync_end ||
6666 high_mode->htotal != mode->htotal ||
6667 high_mode->hskew != mode->hskew ||
6668 high_mode->vscan != mode->vscan ||
6669 high_mode->vsync_start - mode->vsync_start != timing_diff ||
6670 high_mode->vsync_end - mode->vsync_end != timing_diff)
6671 return false;
6672 else
6673 return true;
6674}
6675
6676#if defined(CONFIG_DRM_AMD_DC_FP)
6677static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
6678 struct dc_sink *sink, struct dc_stream_state *stream,
6679 struct dsc_dec_dpcd_caps *dsc_caps)
6680{
6681 stream->timing.flags.DSC = 0;
6682 dsc_caps->is_dsc_supported = false;
6683
6684 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
6685 sink->sink_signal == SIGNAL_TYPE_EDP)) {
6686 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
6687 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
6688 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
6689 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
6690 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
6691 dsc_caps);
6692 }
6693}
6694
6695static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
6696 struct dc_sink *sink, struct dc_stream_state *stream,
6697 struct dsc_dec_dpcd_caps *dsc_caps,
6698 uint32_t max_dsc_target_bpp_limit_override)
6699{
6700 const struct dc_link_settings *verified_link_cap = NULL;
6701 u32 link_bw_in_kbps;
6702 u32 edp_min_bpp_x16, edp_max_bpp_x16;
6703 struct dc *dc = sink->ctx->dc;
6704 struct dc_dsc_bw_range bw_range = {0};
6705 struct dc_dsc_config dsc_cfg = {0};
6706 struct dc_dsc_config_options dsc_options = {0};
6707
6708 dc_dsc_get_default_config_option(dc, &dsc_options);
6709 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6710
6711 verified_link_cap = dc_link_get_link_cap(stream->link);
6712 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
6713 edp_min_bpp_x16 = 8 * 16;
6714 edp_max_bpp_x16 = 8 * 16;
6715
6716 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
6717 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
6718
6719 if (edp_max_bpp_x16 < edp_min_bpp_x16)
6720 edp_min_bpp_x16 = edp_max_bpp_x16;
6721
6722 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
6723 dc->debug.dsc_min_slice_height_override,
6724 edp_min_bpp_x16, edp_max_bpp_x16,
6725 dsc_caps,
6726 &stream->timing,
6727 dc_link_get_highest_encoding_format(aconnector->dc_link),
6728 &bw_range)) {
6729
6730 if (bw_range.max_kbps < link_bw_in_kbps) {
6731 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6732 dsc_caps,
6733 &dsc_options,
6734 0,
6735 &stream->timing,
6736 dc_link_get_highest_encoding_format(aconnector->dc_link),
6737 &dsc_cfg)) {
6738 stream->timing.dsc_cfg = dsc_cfg;
6739 stream->timing.flags.DSC = 1;
6740 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6741 }
6742 return;
6743 }
6744 }
6745
6746 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6747 dsc_caps,
6748 &dsc_options,
6749 link_bw_in_kbps,
6750 &stream->timing,
6751 dc_link_get_highest_encoding_format(aconnector->dc_link),
6752 &dsc_cfg)) {
6753 stream->timing.dsc_cfg = dsc_cfg;
6754 stream->timing.flags.DSC = 1;
6755 }
6756}
6757
6758static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
6759 struct dc_sink *sink, struct dc_stream_state *stream,
6760 struct dsc_dec_dpcd_caps *dsc_caps)
6761{
6762 struct drm_connector *drm_connector = &aconnector->base;
6763 u32 link_bandwidth_kbps;
6764 struct dc *dc = sink->ctx->dc;
6765 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
6766 u32 dsc_max_supported_bw_in_kbps;
6767 u32 max_dsc_target_bpp_limit_override =
6768 drm_connector->display_info.max_dsc_bpp;
6769 struct dc_dsc_config_options dsc_options = {0};
6770
6771 dc_dsc_get_default_config_option(dc, &dsc_options);
6772 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6773
6774 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
6775 dc_link_get_link_cap(aconnector->dc_link));
6776
6777 /* Set DSC policy according to dsc_clock_en */
6778 dc_dsc_policy_set_enable_dsc_when_not_needed(
6779 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
6780
6781 if (sink->sink_signal == SIGNAL_TYPE_EDP &&
6782 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
6783 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
6784
6785 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
6786
6787 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6788 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
6789 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6790 dsc_caps,
6791 &dsc_options,
6792 link_bandwidth_kbps,
6793 &stream->timing,
6794 dc_link_get_highest_encoding_format(aconnector->dc_link),
6795 &stream->timing.dsc_cfg)) {
6796 stream->timing.flags.DSC = 1;
6797 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from SST RX\n",
6798 __func__, drm_connector->name);
6799 }
6800 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6801 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6802 dc_link_get_highest_encoding_format(aconnector->dc_link));
6803 max_supported_bw_in_kbps = link_bandwidth_kbps;
6804 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6805
6806 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6807 max_supported_bw_in_kbps > 0 &&
6808 dsc_max_supported_bw_in_kbps > 0)
6809 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6810 dsc_caps,
6811 &dsc_options,
6812 dsc_max_supported_bw_in_kbps,
6813 &stream->timing,
6814 dc_link_get_highest_encoding_format(aconnector->dc_link),
6815 &stream->timing.dsc_cfg)) {
6816 stream->timing.flags.DSC = 1;
6817 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n",
6818 __func__, drm_connector->name);
6819 }
6820 }
6821 }
6822
6823 /* Overwrite the stream flag if DSC is enabled through debugfs */
6824 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6825 stream->timing.flags.DSC = 1;
6826
6827 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6828 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6829
6830 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6831 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6832
6833 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6834 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6835}
6836#endif
6837
6838static struct dc_stream_state *
6839create_stream_for_sink(struct drm_connector *connector,
6840 const struct drm_display_mode *drm_mode,
6841 const struct dm_connector_state *dm_state,
6842 const struct dc_stream_state *old_stream,
6843 int requested_bpc)
6844{
6845 struct drm_device *dev = connector->dev;
6846 struct amdgpu_dm_connector *aconnector = NULL;
6847 struct drm_display_mode *preferred_mode = NULL;
6848 const struct drm_connector_state *con_state = &dm_state->base;
6849 struct dc_stream_state *stream = NULL;
6850 struct drm_display_mode mode;
6851 struct drm_display_mode saved_mode;
6852 struct drm_display_mode *freesync_mode = NULL;
6853 bool native_mode_found = false;
6854 bool recalculate_timing = false;
6855 bool scale = dm_state->scaling != RMX_OFF;
6856 int mode_refresh;
6857 int preferred_refresh = 0;
6858 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6859#if defined(CONFIG_DRM_AMD_DC_FP)
6860 struct dsc_dec_dpcd_caps dsc_caps;
6861#endif
6862 struct dc_link *link = NULL;
6863 struct dc_sink *sink = NULL;
6864
6865 drm_mode_init(&mode, drm_mode);
6866 memset(&saved_mode, 0, sizeof(saved_mode));
6867
6868 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {
6869 aconnector = NULL;
6870 aconnector = to_amdgpu_dm_connector(connector);
6871 link = aconnector->dc_link;
6872 } else {
6873 struct drm_writeback_connector *wbcon = NULL;
6874 struct amdgpu_dm_wb_connector *dm_wbcon = NULL;
6875
6876 wbcon = drm_connector_to_writeback(connector);
6877 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);
6878 link = dm_wbcon->link;
6879 }
6880
6881 if (!aconnector || !aconnector->dc_sink) {
6882 sink = create_fake_sink(dev, link);
6883 if (!sink)
6884 return stream;
6885
6886 } else {
6887 sink = aconnector->dc_sink;
6888 dc_sink_retain(sink);
6889 }
6890
6891 stream = dc_create_stream_for_sink(sink);
6892
6893 if (stream == NULL) {
6894 drm_err(dev, "Failed to create stream for sink!\n");
6895 goto finish;
6896 }
6897
6898 /* We leave this NULL for writeback connectors */
6899 stream->dm_stream_context = aconnector;
6900
6901 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6902 connector->display_info.hdmi.scdc.scrambling.low_rates;
6903
6904 list_for_each_entry(preferred_mode, &connector->modes, head) {
6905 /* Search for preferred mode */
6906 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6907 native_mode_found = true;
6908 break;
6909 }
6910 }
6911 if (!native_mode_found)
6912 preferred_mode = list_first_entry_or_null(
6913 &connector->modes,
6914 struct drm_display_mode,
6915 head);
6916
6917 mode_refresh = drm_mode_vrefresh(&mode);
6918
6919 if (preferred_mode == NULL) {
6920 /*
6921 * This may not be an error, the use case is when we have no
6922 * usermode calls to reset and set mode upon hotplug. In this
6923 * case, we call set mode ourselves to restore the previous mode
6924 * and the modelist may not be filled in time.
6925 */
6926 drm_dbg_driver(dev, "No preferred mode found\n");
6927 } else if (aconnector) {
6928 recalculate_timing = amdgpu_freesync_vid_mode &&
6929 is_freesync_video_mode(&mode, aconnector);
6930 if (recalculate_timing) {
6931 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6932 drm_mode_copy(&saved_mode, &mode);
6933 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio;
6934 drm_mode_copy(&mode, freesync_mode);
6935 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio;
6936 } else {
6937 decide_crtc_timing_for_drm_display_mode(
6938 &mode, preferred_mode, scale);
6939
6940 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6941 }
6942 }
6943
6944 if (recalculate_timing)
6945 drm_mode_set_crtcinfo(&saved_mode, 0);
6946
6947 /*
6948 * If scaling is enabled and refresh rate didn't change
6949 * we copy the vic and polarities of the old timings
6950 */
6951 if (!scale || mode_refresh != preferred_refresh)
6952 fill_stream_properties_from_drm_display_mode(
6953 stream, &mode, connector, con_state, NULL,
6954 requested_bpc);
6955 else
6956 fill_stream_properties_from_drm_display_mode(
6957 stream, &mode, connector, con_state, old_stream,
6958 requested_bpc);
6959
6960 /* The rest isn't needed for writeback connectors */
6961 if (!aconnector)
6962 goto finish;
6963
6964 if (aconnector->timing_changed) {
6965 drm_dbg(aconnector->base.dev,
6966 "overriding timing for automated test, bpc %d, changing to %d\n",
6967 stream->timing.display_color_depth,
6968 aconnector->timing_requested->display_color_depth);
6969 stream->timing = *aconnector->timing_requested;
6970 }
6971
6972#if defined(CONFIG_DRM_AMD_DC_FP)
6973 /* SST DSC determination policy */
6974 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6975 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6976 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6977#endif
6978
6979 update_stream_scaling_settings(&mode, dm_state, stream);
6980
6981 fill_audio_info(
6982 &stream->audio_info,
6983 connector,
6984 sink);
6985
6986 update_stream_signal(stream, sink);
6987
6988 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6989 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6990
6991 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6992 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6993 stream->signal == SIGNAL_TYPE_EDP) {
6994 const struct dc_edid_caps *edid_caps;
6995 unsigned int disable_colorimetry = 0;
6996
6997 if (aconnector->dc_sink) {
6998 edid_caps = &aconnector->dc_sink->edid_caps;
6999 disable_colorimetry = edid_caps->panel_patch.disable_colorimetry;
7000 }
7001
7002 //
7003 // should decide stream support vsc sdp colorimetry capability
7004 // before building vsc info packet
7005 //
7006 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
7007 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
7008 !disable_colorimetry;
7009
7010 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
7011 tf = TRANSFER_FUNC_GAMMA_22;
7012 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
7013 aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
7014
7015 }
7016finish:
7017 dc_sink_release(sink);
7018
7019 return stream;
7020}
7021
7022static enum drm_connector_status
7023amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
7024{
7025 bool connected;
7026 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7027
7028 /*
7029 * Notes:
7030 * 1. This interface is NOT called in context of HPD irq.
7031 * 2. This interface *is called* in context of user-mode ioctl. Which
7032 * makes it a bad place for *any* MST-related activity.
7033 */
7034
7035 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
7036 !aconnector->fake_enable)
7037 connected = (aconnector->dc_sink != NULL);
7038 else
7039 connected = (aconnector->base.force == DRM_FORCE_ON ||
7040 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
7041
7042 update_subconnector_property(aconnector);
7043
7044 return (connected ? connector_status_connected :
7045 connector_status_disconnected);
7046}
7047
7048int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
7049 struct drm_connector_state *connector_state,
7050 struct drm_property *property,
7051 uint64_t val)
7052{
7053 struct drm_device *dev = connector->dev;
7054 struct amdgpu_device *adev = drm_to_adev(dev);
7055 struct dm_connector_state *dm_old_state =
7056 to_dm_connector_state(connector->state);
7057 struct dm_connector_state *dm_new_state =
7058 to_dm_connector_state(connector_state);
7059
7060 int ret = -EINVAL;
7061
7062 if (property == dev->mode_config.scaling_mode_property) {
7063 enum amdgpu_rmx_type rmx_type;
7064
7065 switch (val) {
7066 case DRM_MODE_SCALE_CENTER:
7067 rmx_type = RMX_CENTER;
7068 break;
7069 case DRM_MODE_SCALE_ASPECT:
7070 rmx_type = RMX_ASPECT;
7071 break;
7072 case DRM_MODE_SCALE_FULLSCREEN:
7073 rmx_type = RMX_FULL;
7074 break;
7075 case DRM_MODE_SCALE_NONE:
7076 default:
7077 rmx_type = RMX_OFF;
7078 break;
7079 }
7080
7081 if (dm_old_state->scaling == rmx_type)
7082 return 0;
7083
7084 dm_new_state->scaling = rmx_type;
7085 ret = 0;
7086 } else if (property == adev->mode_info.underscan_hborder_property) {
7087 dm_new_state->underscan_hborder = val;
7088 ret = 0;
7089 } else if (property == adev->mode_info.underscan_vborder_property) {
7090 dm_new_state->underscan_vborder = val;
7091 ret = 0;
7092 } else if (property == adev->mode_info.underscan_property) {
7093 dm_new_state->underscan_enable = val;
7094 ret = 0;
7095 }
7096
7097 return ret;
7098}
7099
7100int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
7101 const struct drm_connector_state *state,
7102 struct drm_property *property,
7103 uint64_t *val)
7104{
7105 struct drm_device *dev = connector->dev;
7106 struct amdgpu_device *adev = drm_to_adev(dev);
7107 struct dm_connector_state *dm_state =
7108 to_dm_connector_state(state);
7109 int ret = -EINVAL;
7110
7111 if (property == dev->mode_config.scaling_mode_property) {
7112 switch (dm_state->scaling) {
7113 case RMX_CENTER:
7114 *val = DRM_MODE_SCALE_CENTER;
7115 break;
7116 case RMX_ASPECT:
7117 *val = DRM_MODE_SCALE_ASPECT;
7118 break;
7119 case RMX_FULL:
7120 *val = DRM_MODE_SCALE_FULLSCREEN;
7121 break;
7122 case RMX_OFF:
7123 default:
7124 *val = DRM_MODE_SCALE_NONE;
7125 break;
7126 }
7127 ret = 0;
7128 } else if (property == adev->mode_info.underscan_hborder_property) {
7129 *val = dm_state->underscan_hborder;
7130 ret = 0;
7131 } else if (property == adev->mode_info.underscan_vborder_property) {
7132 *val = dm_state->underscan_vborder;
7133 ret = 0;
7134 } else if (property == adev->mode_info.underscan_property) {
7135 *val = dm_state->underscan_enable;
7136 ret = 0;
7137 }
7138
7139 return ret;
7140}
7141
7142/**
7143 * DOC: panel power savings
7144 *
7145 * The display manager allows you to set your desired **panel power savings**
7146 * level (between 0-4, with 0 representing off), e.g. using the following::
7147 *
7148 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings
7149 *
7150 * Modifying this value can have implications on color accuracy, so tread
7151 * carefully.
7152 */
7153
7154static ssize_t panel_power_savings_show(struct device *device,
7155 struct device_attribute *attr,
7156 char *buf)
7157{
7158 struct drm_connector *connector = dev_get_drvdata(device);
7159 struct drm_device *dev = connector->dev;
7160 u8 val;
7161
7162 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
7163 val = to_dm_connector_state(connector->state)->abm_level ==
7164 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 :
7165 to_dm_connector_state(connector->state)->abm_level;
7166 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7167
7168 return sysfs_emit(buf, "%u\n", val);
7169}
7170
7171static ssize_t panel_power_savings_store(struct device *device,
7172 struct device_attribute *attr,
7173 const char *buf, size_t count)
7174{
7175 struct drm_connector *connector = dev_get_drvdata(device);
7176 struct drm_device *dev = connector->dev;
7177 long val;
7178 int ret;
7179
7180 ret = kstrtol(buf, 0, &val);
7181
7182 if (ret)
7183 return ret;
7184
7185 if (val < 0 || val > 4)
7186 return -EINVAL;
7187
7188 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
7189 to_dm_connector_state(connector->state)->abm_level = val ?:
7190 ABM_LEVEL_IMMEDIATE_DISABLE;
7191 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7192
7193 drm_kms_helper_hotplug_event(dev);
7194
7195 return count;
7196}
7197
7198static DEVICE_ATTR_RW(panel_power_savings);
7199
7200static struct attribute *amdgpu_attrs[] = {
7201 &dev_attr_panel_power_savings.attr,
7202 NULL
7203};
7204
7205static const struct attribute_group amdgpu_group = {
7206 .name = "amdgpu",
7207 .attrs = amdgpu_attrs
7208};
7209
7210static bool
7211amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector)
7212{
7213 if (amdgpu_dm_abm_level >= 0)
7214 return false;
7215
7216 if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
7217 return false;
7218
7219 /* check for OLED panels */
7220 if (amdgpu_dm_connector->bl_idx >= 0) {
7221 struct drm_device *drm = amdgpu_dm_connector->base.dev;
7222 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
7223 struct amdgpu_dm_backlight_caps *caps;
7224
7225 caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx];
7226 if (caps->aux_support)
7227 return false;
7228 }
7229
7230 return true;
7231}
7232
7233static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
7234{
7235 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
7236
7237 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector))
7238 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group);
7239
7240 cec_notifier_conn_unregister(amdgpu_dm_connector->notifier);
7241 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
7242}
7243
7244static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
7245{
7246 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7247 struct amdgpu_device *adev = drm_to_adev(connector->dev);
7248 struct amdgpu_display_manager *dm = &adev->dm;
7249
7250 /*
7251 * Call only if mst_mgr was initialized before since it's not done
7252 * for all connector types.
7253 */
7254 if (aconnector->mst_mgr.dev)
7255 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
7256
7257 if (aconnector->bl_idx != -1) {
7258 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
7259 dm->backlight_dev[aconnector->bl_idx] = NULL;
7260 }
7261
7262 if (aconnector->dc_em_sink)
7263 dc_sink_release(aconnector->dc_em_sink);
7264 aconnector->dc_em_sink = NULL;
7265 if (aconnector->dc_sink)
7266 dc_sink_release(aconnector->dc_sink);
7267 aconnector->dc_sink = NULL;
7268
7269 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
7270 drm_connector_unregister(connector);
7271 drm_connector_cleanup(connector);
7272 if (aconnector->i2c) {
7273 i2c_del_adapter(&aconnector->i2c->base);
7274 kfree(aconnector->i2c);
7275 }
7276 kfree(aconnector->dm_dp_aux.aux.name);
7277
7278 kfree(connector);
7279}
7280
7281void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
7282{
7283 struct dm_connector_state *state =
7284 to_dm_connector_state(connector->state);
7285
7286 if (connector->state)
7287 __drm_atomic_helper_connector_destroy_state(connector->state);
7288
7289 kfree(state);
7290
7291 state = kzalloc(sizeof(*state), GFP_KERNEL);
7292
7293 if (state) {
7294 state->scaling = RMX_OFF;
7295 state->underscan_enable = false;
7296 state->underscan_hborder = 0;
7297 state->underscan_vborder = 0;
7298 state->base.max_requested_bpc = 8;
7299 state->vcpi_slots = 0;
7300 state->pbn = 0;
7301
7302 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
7303 if (amdgpu_dm_abm_level <= 0)
7304 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE;
7305 else
7306 state->abm_level = amdgpu_dm_abm_level;
7307 }
7308
7309 __drm_atomic_helper_connector_reset(connector, &state->base);
7310 }
7311}
7312
7313struct drm_connector_state *
7314amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
7315{
7316 struct dm_connector_state *state =
7317 to_dm_connector_state(connector->state);
7318
7319 struct dm_connector_state *new_state =
7320 kmemdup(state, sizeof(*state), GFP_KERNEL);
7321
7322 if (!new_state)
7323 return NULL;
7324
7325 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
7326
7327 new_state->freesync_capable = state->freesync_capable;
7328 new_state->abm_level = state->abm_level;
7329 new_state->scaling = state->scaling;
7330 new_state->underscan_enable = state->underscan_enable;
7331 new_state->underscan_hborder = state->underscan_hborder;
7332 new_state->underscan_vborder = state->underscan_vborder;
7333 new_state->vcpi_slots = state->vcpi_slots;
7334 new_state->pbn = state->pbn;
7335 return &new_state->base;
7336}
7337
7338static int
7339amdgpu_dm_connector_late_register(struct drm_connector *connector)
7340{
7341 struct amdgpu_dm_connector *amdgpu_dm_connector =
7342 to_amdgpu_dm_connector(connector);
7343 int r;
7344
7345 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) {
7346 r = sysfs_create_group(&connector->kdev->kobj,
7347 &amdgpu_group);
7348 if (r)
7349 return r;
7350 }
7351
7352 amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
7353
7354 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
7355 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
7356 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
7357 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
7358 if (r)
7359 return r;
7360 }
7361
7362#if defined(CONFIG_DEBUG_FS)
7363 connector_debugfs_init(amdgpu_dm_connector);
7364#endif
7365
7366 return 0;
7367}
7368
7369static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
7370{
7371 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7372 struct dc_link *dc_link = aconnector->dc_link;
7373 struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
7374 const struct drm_edid *drm_edid;
7375 struct i2c_adapter *ddc;
7376 struct drm_device *dev = connector->dev;
7377
7378 if (dc_link && dc_link->aux_mode)
7379 ddc = &aconnector->dm_dp_aux.aux.ddc;
7380 else
7381 ddc = &aconnector->i2c->base;
7382
7383 drm_edid = drm_edid_read_ddc(connector, ddc);
7384 drm_edid_connector_update(connector, drm_edid);
7385 if (!drm_edid) {
7386 drm_err(dev, "No EDID found on connector: %s.\n", connector->name);
7387 return;
7388 }
7389
7390 aconnector->drm_edid = drm_edid;
7391 /* Update emulated (virtual) sink's EDID */
7392 if (dc_em_sink && dc_link) {
7393 // FIXME: Get rid of drm_edid_raw()
7394 const struct edid *edid = drm_edid_raw(drm_edid);
7395
7396 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
7397 memmove(dc_em_sink->dc_edid.raw_edid, edid,
7398 (edid->extensions + 1) * EDID_LENGTH);
7399 dm_helpers_parse_edid_caps(
7400 dc_link,
7401 &dc_em_sink->dc_edid,
7402 &dc_em_sink->edid_caps);
7403 }
7404}
7405
7406static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
7407 .reset = amdgpu_dm_connector_funcs_reset,
7408 .detect = amdgpu_dm_connector_detect,
7409 .fill_modes = drm_helper_probe_single_connector_modes,
7410 .destroy = amdgpu_dm_connector_destroy,
7411 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
7412 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7413 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
7414 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
7415 .late_register = amdgpu_dm_connector_late_register,
7416 .early_unregister = amdgpu_dm_connector_unregister,
7417 .force = amdgpu_dm_connector_funcs_force
7418};
7419
7420static int get_modes(struct drm_connector *connector)
7421{
7422 return amdgpu_dm_connector_get_modes(connector);
7423}
7424
7425static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
7426{
7427 struct drm_connector *connector = &aconnector->base;
7428 struct dc_link *dc_link = aconnector->dc_link;
7429 struct dc_sink_init_data init_params = {
7430 .link = aconnector->dc_link,
7431 .sink_signal = SIGNAL_TYPE_VIRTUAL
7432 };
7433 const struct drm_edid *drm_edid;
7434 const struct edid *edid;
7435 struct i2c_adapter *ddc;
7436
7437 if (dc_link && dc_link->aux_mode)
7438 ddc = &aconnector->dm_dp_aux.aux.ddc;
7439 else
7440 ddc = &aconnector->i2c->base;
7441
7442 drm_edid = drm_edid_read_ddc(connector, ddc);
7443 drm_edid_connector_update(connector, drm_edid);
7444 if (!drm_edid) {
7445 drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name);
7446 return;
7447 }
7448
7449 if (connector->display_info.is_hdmi)
7450 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
7451
7452 aconnector->drm_edid = drm_edid;
7453
7454 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
7455 aconnector->dc_em_sink = dc_link_add_remote_sink(
7456 aconnector->dc_link,
7457 (uint8_t *)edid,
7458 (edid->extensions + 1) * EDID_LENGTH,
7459 &init_params);
7460
7461 if (aconnector->base.force == DRM_FORCE_ON) {
7462 aconnector->dc_sink = aconnector->dc_link->local_sink ?
7463 aconnector->dc_link->local_sink :
7464 aconnector->dc_em_sink;
7465 if (aconnector->dc_sink)
7466 dc_sink_retain(aconnector->dc_sink);
7467 }
7468}
7469
7470static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
7471{
7472 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
7473
7474 /*
7475 * In case of headless boot with force on for DP managed connector
7476 * Those settings have to be != 0 to get initial modeset
7477 */
7478 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
7479 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
7480 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
7481 }
7482
7483 create_eml_sink(aconnector);
7484}
7485
7486static enum dc_status dm_validate_stream_and_context(struct dc *dc,
7487 struct dc_stream_state *stream)
7488{
7489 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
7490 struct dc_plane_state *dc_plane_state = NULL;
7491 struct dc_state *dc_state = NULL;
7492
7493 if (!stream)
7494 goto cleanup;
7495
7496 dc_plane_state = dc_create_plane_state(dc);
7497 if (!dc_plane_state)
7498 goto cleanup;
7499
7500 dc_state = dc_state_create(dc, NULL);
7501 if (!dc_state)
7502 goto cleanup;
7503
7504 /* populate stream to plane */
7505 dc_plane_state->src_rect.height = stream->src.height;
7506 dc_plane_state->src_rect.width = stream->src.width;
7507 dc_plane_state->dst_rect.height = stream->src.height;
7508 dc_plane_state->dst_rect.width = stream->src.width;
7509 dc_plane_state->clip_rect.height = stream->src.height;
7510 dc_plane_state->clip_rect.width = stream->src.width;
7511 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
7512 dc_plane_state->plane_size.surface_size.height = stream->src.height;
7513 dc_plane_state->plane_size.surface_size.width = stream->src.width;
7514 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
7515 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
7516 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
7517 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
7518 dc_plane_state->rotation = ROTATION_ANGLE_0;
7519 dc_plane_state->is_tiling_rotated = false;
7520 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
7521
7522 dc_result = dc_validate_stream(dc, stream);
7523 if (dc_result == DC_OK)
7524 dc_result = dc_validate_plane(dc, dc_plane_state);
7525
7526 if (dc_result == DC_OK)
7527 dc_result = dc_state_add_stream(dc, dc_state, stream);
7528
7529 if (dc_result == DC_OK && !dc_state_add_plane(
7530 dc,
7531 stream,
7532 dc_plane_state,
7533 dc_state))
7534 dc_result = DC_FAIL_ATTACH_SURFACES;
7535
7536 if (dc_result == DC_OK)
7537 dc_result = dc_validate_global_state(dc, dc_state, true);
7538
7539cleanup:
7540 if (dc_state)
7541 dc_state_release(dc_state);
7542
7543 if (dc_plane_state)
7544 dc_plane_state_release(dc_plane_state);
7545
7546 return dc_result;
7547}
7548
7549struct dc_stream_state *
7550create_validate_stream_for_sink(struct drm_connector *connector,
7551 const struct drm_display_mode *drm_mode,
7552 const struct dm_connector_state *dm_state,
7553 const struct dc_stream_state *old_stream)
7554{
7555 struct amdgpu_dm_connector *aconnector = NULL;
7556 struct amdgpu_device *adev = drm_to_adev(connector->dev);
7557 struct dc_stream_state *stream;
7558 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
7559 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
7560 enum dc_status dc_result = DC_OK;
7561 uint8_t bpc_limit = 6;
7562
7563 if (!dm_state)
7564 return NULL;
7565
7566 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
7567 aconnector = to_amdgpu_dm_connector(connector);
7568
7569 if (aconnector &&
7570 (aconnector->dc_link->connector_signal == SIGNAL_TYPE_HDMI_TYPE_A ||
7571 aconnector->dc_link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER))
7572 bpc_limit = 8;
7573
7574 do {
7575 stream = create_stream_for_sink(connector, drm_mode,
7576 dm_state, old_stream,
7577 requested_bpc);
7578 if (stream == NULL) {
7579 drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n");
7580 break;
7581 }
7582
7583 dc_result = dc_validate_stream(adev->dm.dc, stream);
7584
7585 if (!aconnector) /* writeback connector */
7586 return stream;
7587
7588 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
7589 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
7590
7591 if (dc_result == DC_OK)
7592 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
7593
7594 if (dc_result != DC_OK) {
7595 DRM_DEBUG_KMS("Mode %dx%d (clk %d) pixel_encoding:%s color_depth:%s failed validation -- %s\n",
7596 drm_mode->hdisplay,
7597 drm_mode->vdisplay,
7598 drm_mode->clock,
7599 dc_pixel_encoding_to_str(stream->timing.pixel_encoding),
7600 dc_color_depth_to_str(stream->timing.display_color_depth),
7601 dc_status_to_str(dc_result));
7602
7603 dc_stream_release(stream);
7604 stream = NULL;
7605 requested_bpc -= 2; /* lower bpc to retry validation */
7606 }
7607
7608 } while (stream == NULL && requested_bpc >= bpc_limit);
7609
7610 if ((dc_result == DC_FAIL_ENC_VALIDATE ||
7611 dc_result == DC_EXCEED_DONGLE_CAP) &&
7612 !aconnector->force_yuv420_output) {
7613 DRM_DEBUG_KMS("%s:%d Retry forcing yuv420 encoding\n",
7614 __func__, __LINE__);
7615
7616 aconnector->force_yuv420_output = true;
7617 stream = create_validate_stream_for_sink(connector, drm_mode,
7618 dm_state, old_stream);
7619 aconnector->force_yuv420_output = false;
7620 }
7621
7622 return stream;
7623}
7624
7625enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
7626 const struct drm_display_mode *mode)
7627{
7628 int result = MODE_ERROR;
7629 struct dc_sink *dc_sink;
7630 struct drm_display_mode *test_mode;
7631 /* TODO: Unhardcode stream count */
7632 struct dc_stream_state *stream;
7633 /* we always have an amdgpu_dm_connector here since we got
7634 * here via the amdgpu_dm_connector_helper_funcs
7635 */
7636 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7637
7638 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
7639 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
7640 return result;
7641
7642 /*
7643 * Only run this the first time mode_valid is called to initilialize
7644 * EDID mgmt
7645 */
7646 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
7647 !aconnector->dc_em_sink)
7648 handle_edid_mgmt(aconnector);
7649
7650 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
7651
7652 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
7653 aconnector->base.force != DRM_FORCE_ON) {
7654 drm_err(connector->dev, "dc_sink is NULL!\n");
7655 goto fail;
7656 }
7657
7658 test_mode = drm_mode_duplicate(connector->dev, mode);
7659 if (!test_mode)
7660 goto fail;
7661
7662 drm_mode_set_crtcinfo(test_mode, 0);
7663
7664 stream = create_validate_stream_for_sink(connector, test_mode,
7665 to_dm_connector_state(connector->state),
7666 NULL);
7667 drm_mode_destroy(connector->dev, test_mode);
7668 if (stream) {
7669 dc_stream_release(stream);
7670 result = MODE_OK;
7671 }
7672
7673fail:
7674 /* TODO: error handling*/
7675 return result;
7676}
7677
7678static int fill_hdr_info_packet(const struct drm_connector_state *state,
7679 struct dc_info_packet *out)
7680{
7681 struct hdmi_drm_infoframe frame;
7682 unsigned char buf[30]; /* 26 + 4 */
7683 ssize_t len;
7684 int ret, i;
7685
7686 memset(out, 0, sizeof(*out));
7687
7688 if (!state->hdr_output_metadata)
7689 return 0;
7690
7691 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
7692 if (ret)
7693 return ret;
7694
7695 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
7696 if (len < 0)
7697 return (int)len;
7698
7699 /* Static metadata is a fixed 26 bytes + 4 byte header. */
7700 if (len != 30)
7701 return -EINVAL;
7702
7703 /* Prepare the infopacket for DC. */
7704 switch (state->connector->connector_type) {
7705 case DRM_MODE_CONNECTOR_HDMIA:
7706 out->hb0 = 0x87; /* type */
7707 out->hb1 = 0x01; /* version */
7708 out->hb2 = 0x1A; /* length */
7709 out->sb[0] = buf[3]; /* checksum */
7710 i = 1;
7711 break;
7712
7713 case DRM_MODE_CONNECTOR_DisplayPort:
7714 case DRM_MODE_CONNECTOR_eDP:
7715 out->hb0 = 0x00; /* sdp id, zero */
7716 out->hb1 = 0x87; /* type */
7717 out->hb2 = 0x1D; /* payload len - 1 */
7718 out->hb3 = (0x13 << 2); /* sdp version */
7719 out->sb[0] = 0x01; /* version */
7720 out->sb[1] = 0x1A; /* length */
7721 i = 2;
7722 break;
7723
7724 default:
7725 return -EINVAL;
7726 }
7727
7728 memcpy(&out->sb[i], &buf[4], 26);
7729 out->valid = true;
7730
7731 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
7732 sizeof(out->sb), false);
7733
7734 return 0;
7735}
7736
7737static int
7738amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
7739 struct drm_atomic_state *state)
7740{
7741 struct drm_connector_state *new_con_state =
7742 drm_atomic_get_new_connector_state(state, conn);
7743 struct drm_connector_state *old_con_state =
7744 drm_atomic_get_old_connector_state(state, conn);
7745 struct drm_crtc *crtc = new_con_state->crtc;
7746 struct drm_crtc_state *new_crtc_state;
7747 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
7748 int ret;
7749
7750 trace_amdgpu_dm_connector_atomic_check(new_con_state);
7751
7752 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
7753 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
7754 if (ret < 0)
7755 return ret;
7756 }
7757
7758 if (!crtc)
7759 return 0;
7760
7761 if (new_con_state->colorspace != old_con_state->colorspace) {
7762 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7763 if (IS_ERR(new_crtc_state))
7764 return PTR_ERR(new_crtc_state);
7765
7766 new_crtc_state->mode_changed = true;
7767 }
7768
7769 if (new_con_state->content_type != old_con_state->content_type) {
7770 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7771 if (IS_ERR(new_crtc_state))
7772 return PTR_ERR(new_crtc_state);
7773
7774 new_crtc_state->mode_changed = true;
7775 }
7776
7777 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
7778 struct dc_info_packet hdr_infopacket;
7779
7780 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
7781 if (ret)
7782 return ret;
7783
7784 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7785 if (IS_ERR(new_crtc_state))
7786 return PTR_ERR(new_crtc_state);
7787
7788 /*
7789 * DC considers the stream backends changed if the
7790 * static metadata changes. Forcing the modeset also
7791 * gives a simple way for userspace to switch from
7792 * 8bpc to 10bpc when setting the metadata to enter
7793 * or exit HDR.
7794 *
7795 * Changing the static metadata after it's been
7796 * set is permissible, however. So only force a
7797 * modeset if we're entering or exiting HDR.
7798 */
7799 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
7800 !old_con_state->hdr_output_metadata ||
7801 !new_con_state->hdr_output_metadata;
7802 }
7803
7804 return 0;
7805}
7806
7807static const struct drm_connector_helper_funcs
7808amdgpu_dm_connector_helper_funcs = {
7809 /*
7810 * If hotplugging a second bigger display in FB Con mode, bigger resolution
7811 * modes will be filtered by drm_mode_validate_size(), and those modes
7812 * are missing after user start lightdm. So we need to renew modes list.
7813 * in get_modes call back, not just return the modes count
7814 */
7815 .get_modes = get_modes,
7816 .mode_valid = amdgpu_dm_connector_mode_valid,
7817 .atomic_check = amdgpu_dm_connector_atomic_check,
7818};
7819
7820static void dm_encoder_helper_disable(struct drm_encoder *encoder)
7821{
7822
7823}
7824
7825int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
7826{
7827 switch (display_color_depth) {
7828 case COLOR_DEPTH_666:
7829 return 6;
7830 case COLOR_DEPTH_888:
7831 return 8;
7832 case COLOR_DEPTH_101010:
7833 return 10;
7834 case COLOR_DEPTH_121212:
7835 return 12;
7836 case COLOR_DEPTH_141414:
7837 return 14;
7838 case COLOR_DEPTH_161616:
7839 return 16;
7840 default:
7841 break;
7842 }
7843 return 0;
7844}
7845
7846static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
7847 struct drm_crtc_state *crtc_state,
7848 struct drm_connector_state *conn_state)
7849{
7850 struct drm_atomic_state *state = crtc_state->state;
7851 struct drm_connector *connector = conn_state->connector;
7852 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7853 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
7854 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
7855 struct drm_dp_mst_topology_mgr *mst_mgr;
7856 struct drm_dp_mst_port *mst_port;
7857 struct drm_dp_mst_topology_state *mst_state;
7858 enum dc_color_depth color_depth;
7859 int clock, bpp = 0;
7860 bool is_y420 = false;
7861
7862 if (!aconnector->mst_output_port)
7863 return 0;
7864
7865 mst_port = aconnector->mst_output_port;
7866 mst_mgr = &aconnector->mst_root->mst_mgr;
7867
7868 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
7869 return 0;
7870
7871 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
7872 if (IS_ERR(mst_state))
7873 return PTR_ERR(mst_state);
7874
7875 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
7876
7877 if (!state->duplicated) {
7878 int max_bpc = conn_state->max_requested_bpc;
7879
7880 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
7881 aconnector->force_yuv420_output;
7882 color_depth = convert_color_depth_from_display_info(connector,
7883 is_y420,
7884 max_bpc);
7885 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
7886 clock = adjusted_mode->clock;
7887 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
7888 }
7889
7890 dm_new_connector_state->vcpi_slots =
7891 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
7892 dm_new_connector_state->pbn);
7893 if (dm_new_connector_state->vcpi_slots < 0) {
7894 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
7895 return dm_new_connector_state->vcpi_slots;
7896 }
7897 return 0;
7898}
7899
7900const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
7901 .disable = dm_encoder_helper_disable,
7902 .atomic_check = dm_encoder_helper_atomic_check
7903};
7904
7905static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
7906 struct dc_state *dc_state,
7907 struct dsc_mst_fairness_vars *vars)
7908{
7909 struct dc_stream_state *stream = NULL;
7910 struct drm_connector *connector;
7911 struct drm_connector_state *new_con_state;
7912 struct amdgpu_dm_connector *aconnector;
7913 struct dm_connector_state *dm_conn_state;
7914 int i, j, ret;
7915 int vcpi, pbn_div, pbn = 0, slot_num = 0;
7916
7917 for_each_new_connector_in_state(state, connector, new_con_state, i) {
7918
7919 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
7920 continue;
7921
7922 aconnector = to_amdgpu_dm_connector(connector);
7923
7924 if (!aconnector->mst_output_port)
7925 continue;
7926
7927 if (!new_con_state || !new_con_state->crtc)
7928 continue;
7929
7930 dm_conn_state = to_dm_connector_state(new_con_state);
7931
7932 for (j = 0; j < dc_state->stream_count; j++) {
7933 stream = dc_state->streams[j];
7934 if (!stream)
7935 continue;
7936
7937 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
7938 break;
7939
7940 stream = NULL;
7941 }
7942
7943 if (!stream)
7944 continue;
7945
7946 pbn_div = dm_mst_get_pbn_divider(stream->link);
7947 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
7948 for (j = 0; j < dc_state->stream_count; j++) {
7949 if (vars[j].aconnector == aconnector) {
7950 pbn = vars[j].pbn;
7951 break;
7952 }
7953 }
7954
7955 if (j == dc_state->stream_count || pbn_div == 0)
7956 continue;
7957
7958 slot_num = DIV_ROUND_UP(pbn, pbn_div);
7959
7960 if (stream->timing.flags.DSC != 1) {
7961 dm_conn_state->pbn = pbn;
7962 dm_conn_state->vcpi_slots = slot_num;
7963
7964 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7965 dm_conn_state->pbn, false);
7966 if (ret < 0)
7967 return ret;
7968
7969 continue;
7970 }
7971
7972 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7973 if (vcpi < 0)
7974 return vcpi;
7975
7976 dm_conn_state->pbn = pbn;
7977 dm_conn_state->vcpi_slots = vcpi;
7978 }
7979 return 0;
7980}
7981
7982static int to_drm_connector_type(enum signal_type st)
7983{
7984 switch (st) {
7985 case SIGNAL_TYPE_HDMI_TYPE_A:
7986 return DRM_MODE_CONNECTOR_HDMIA;
7987 case SIGNAL_TYPE_EDP:
7988 return DRM_MODE_CONNECTOR_eDP;
7989 case SIGNAL_TYPE_LVDS:
7990 return DRM_MODE_CONNECTOR_LVDS;
7991 case SIGNAL_TYPE_RGB:
7992 return DRM_MODE_CONNECTOR_VGA;
7993 case SIGNAL_TYPE_DISPLAY_PORT:
7994 case SIGNAL_TYPE_DISPLAY_PORT_MST:
7995 return DRM_MODE_CONNECTOR_DisplayPort;
7996 case SIGNAL_TYPE_DVI_DUAL_LINK:
7997 case SIGNAL_TYPE_DVI_SINGLE_LINK:
7998 return DRM_MODE_CONNECTOR_DVID;
7999 case SIGNAL_TYPE_VIRTUAL:
8000 return DRM_MODE_CONNECTOR_VIRTUAL;
8001
8002 default:
8003 return DRM_MODE_CONNECTOR_Unknown;
8004 }
8005}
8006
8007static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
8008{
8009 struct drm_encoder *encoder;
8010
8011 /* There is only one encoder per connector */
8012 drm_connector_for_each_possible_encoder(connector, encoder)
8013 return encoder;
8014
8015 return NULL;
8016}
8017
8018static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
8019{
8020 struct drm_encoder *encoder;
8021 struct amdgpu_encoder *amdgpu_encoder;
8022
8023 encoder = amdgpu_dm_connector_to_encoder(connector);
8024
8025 if (encoder == NULL)
8026 return;
8027
8028 amdgpu_encoder = to_amdgpu_encoder(encoder);
8029
8030 amdgpu_encoder->native_mode.clock = 0;
8031
8032 if (!list_empty(&connector->probed_modes)) {
8033 struct drm_display_mode *preferred_mode = NULL;
8034
8035 list_for_each_entry(preferred_mode,
8036 &connector->probed_modes,
8037 head) {
8038 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
8039 amdgpu_encoder->native_mode = *preferred_mode;
8040
8041 break;
8042 }
8043
8044 }
8045}
8046
8047static struct drm_display_mode *
8048amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
8049 char *name,
8050 int hdisplay, int vdisplay)
8051{
8052 struct drm_device *dev = encoder->dev;
8053 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
8054 struct drm_display_mode *mode = NULL;
8055 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
8056
8057 mode = drm_mode_duplicate(dev, native_mode);
8058
8059 if (mode == NULL)
8060 return NULL;
8061
8062 mode->hdisplay = hdisplay;
8063 mode->vdisplay = vdisplay;
8064 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
8065 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
8066
8067 return mode;
8068
8069}
8070
8071static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
8072 struct drm_connector *connector)
8073{
8074 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
8075 struct drm_display_mode *mode = NULL;
8076 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
8077 struct amdgpu_dm_connector *amdgpu_dm_connector =
8078 to_amdgpu_dm_connector(connector);
8079 int i;
8080 int n;
8081 struct mode_size {
8082 char name[DRM_DISPLAY_MODE_LEN];
8083 int w;
8084 int h;
8085 } common_modes[] = {
8086 { "640x480", 640, 480},
8087 { "800x600", 800, 600},
8088 { "1024x768", 1024, 768},
8089 { "1280x720", 1280, 720},
8090 { "1280x800", 1280, 800},
8091 {"1280x1024", 1280, 1024},
8092 { "1440x900", 1440, 900},
8093 {"1680x1050", 1680, 1050},
8094 {"1600x1200", 1600, 1200},
8095 {"1920x1080", 1920, 1080},
8096 {"1920x1200", 1920, 1200}
8097 };
8098
8099 n = ARRAY_SIZE(common_modes);
8100
8101 for (i = 0; i < n; i++) {
8102 struct drm_display_mode *curmode = NULL;
8103 bool mode_existed = false;
8104
8105 if (common_modes[i].w > native_mode->hdisplay ||
8106 common_modes[i].h > native_mode->vdisplay ||
8107 (common_modes[i].w == native_mode->hdisplay &&
8108 common_modes[i].h == native_mode->vdisplay))
8109 continue;
8110
8111 list_for_each_entry(curmode, &connector->probed_modes, head) {
8112 if (common_modes[i].w == curmode->hdisplay &&
8113 common_modes[i].h == curmode->vdisplay) {
8114 mode_existed = true;
8115 break;
8116 }
8117 }
8118
8119 if (mode_existed)
8120 continue;
8121
8122 mode = amdgpu_dm_create_common_mode(encoder,
8123 common_modes[i].name, common_modes[i].w,
8124 common_modes[i].h);
8125 if (!mode)
8126 continue;
8127
8128 drm_mode_probed_add(connector, mode);
8129 amdgpu_dm_connector->num_modes++;
8130 }
8131}
8132
8133static void amdgpu_set_panel_orientation(struct drm_connector *connector)
8134{
8135 struct drm_encoder *encoder;
8136 struct amdgpu_encoder *amdgpu_encoder;
8137 const struct drm_display_mode *native_mode;
8138
8139 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
8140 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
8141 return;
8142
8143 mutex_lock(&connector->dev->mode_config.mutex);
8144 amdgpu_dm_connector_get_modes(connector);
8145 mutex_unlock(&connector->dev->mode_config.mutex);
8146
8147 encoder = amdgpu_dm_connector_to_encoder(connector);
8148 if (!encoder)
8149 return;
8150
8151 amdgpu_encoder = to_amdgpu_encoder(encoder);
8152
8153 native_mode = &amdgpu_encoder->native_mode;
8154 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
8155 return;
8156
8157 drm_connector_set_panel_orientation_with_quirk(connector,
8158 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
8159 native_mode->hdisplay,
8160 native_mode->vdisplay);
8161}
8162
8163static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
8164 const struct drm_edid *drm_edid)
8165{
8166 struct amdgpu_dm_connector *amdgpu_dm_connector =
8167 to_amdgpu_dm_connector(connector);
8168
8169 if (drm_edid) {
8170 /* empty probed_modes */
8171 INIT_LIST_HEAD(&connector->probed_modes);
8172 amdgpu_dm_connector->num_modes =
8173 drm_edid_connector_add_modes(connector);
8174
8175 /* sorting the probed modes before calling function
8176 * amdgpu_dm_get_native_mode() since EDID can have
8177 * more than one preferred mode. The modes that are
8178 * later in the probed mode list could be of higher
8179 * and preferred resolution. For example, 3840x2160
8180 * resolution in base EDID preferred timing and 4096x2160
8181 * preferred resolution in DID extension block later.
8182 */
8183 drm_mode_sort(&connector->probed_modes);
8184 amdgpu_dm_get_native_mode(connector);
8185
8186 /* Freesync capabilities are reset by calling
8187 * drm_edid_connector_add_modes() and need to be
8188 * restored here.
8189 */
8190 amdgpu_dm_update_freesync_caps(connector, drm_edid);
8191 } else {
8192 amdgpu_dm_connector->num_modes = 0;
8193 }
8194}
8195
8196static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
8197 struct drm_display_mode *mode)
8198{
8199 struct drm_display_mode *m;
8200
8201 list_for_each_entry(m, &aconnector->base.probed_modes, head) {
8202 if (drm_mode_equal(m, mode))
8203 return true;
8204 }
8205
8206 return false;
8207}
8208
8209static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
8210{
8211 const struct drm_display_mode *m;
8212 struct drm_display_mode *new_mode;
8213 uint i;
8214 u32 new_modes_count = 0;
8215
8216 /* Standard FPS values
8217 *
8218 * 23.976 - TV/NTSC
8219 * 24 - Cinema
8220 * 25 - TV/PAL
8221 * 29.97 - TV/NTSC
8222 * 30 - TV/NTSC
8223 * 48 - Cinema HFR
8224 * 50 - TV/PAL
8225 * 60 - Commonly used
8226 * 48,72,96,120 - Multiples of 24
8227 */
8228 static const u32 common_rates[] = {
8229 23976, 24000, 25000, 29970, 30000,
8230 48000, 50000, 60000, 72000, 96000, 120000
8231 };
8232
8233 /*
8234 * Find mode with highest refresh rate with the same resolution
8235 * as the preferred mode. Some monitors report a preferred mode
8236 * with lower resolution than the highest refresh rate supported.
8237 */
8238
8239 m = get_highest_refresh_rate_mode(aconnector, true);
8240 if (!m)
8241 return 0;
8242
8243 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
8244 u64 target_vtotal, target_vtotal_diff;
8245 u64 num, den;
8246
8247 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
8248 continue;
8249
8250 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
8251 common_rates[i] > aconnector->max_vfreq * 1000)
8252 continue;
8253
8254 num = (unsigned long long)m->clock * 1000 * 1000;
8255 den = common_rates[i] * (unsigned long long)m->htotal;
8256 target_vtotal = div_u64(num, den);
8257 target_vtotal_diff = target_vtotal - m->vtotal;
8258
8259 /* Check for illegal modes */
8260 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
8261 m->vsync_end + target_vtotal_diff < m->vsync_start ||
8262 m->vtotal + target_vtotal_diff < m->vsync_end)
8263 continue;
8264
8265 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
8266 if (!new_mode)
8267 goto out;
8268
8269 new_mode->vtotal += (u16)target_vtotal_diff;
8270 new_mode->vsync_start += (u16)target_vtotal_diff;
8271 new_mode->vsync_end += (u16)target_vtotal_diff;
8272 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
8273 new_mode->type |= DRM_MODE_TYPE_DRIVER;
8274
8275 if (!is_duplicate_mode(aconnector, new_mode)) {
8276 drm_mode_probed_add(&aconnector->base, new_mode);
8277 new_modes_count += 1;
8278 } else
8279 drm_mode_destroy(aconnector->base.dev, new_mode);
8280 }
8281 out:
8282 return new_modes_count;
8283}
8284
8285static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
8286 const struct drm_edid *drm_edid)
8287{
8288 struct amdgpu_dm_connector *amdgpu_dm_connector =
8289 to_amdgpu_dm_connector(connector);
8290
8291 if (!(amdgpu_freesync_vid_mode && drm_edid))
8292 return;
8293
8294 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
8295 amdgpu_dm_connector->num_modes +=
8296 add_fs_modes(amdgpu_dm_connector);
8297}
8298
8299static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
8300{
8301 struct amdgpu_dm_connector *amdgpu_dm_connector =
8302 to_amdgpu_dm_connector(connector);
8303 struct drm_encoder *encoder;
8304 const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid;
8305 struct dc_link_settings *verified_link_cap =
8306 &amdgpu_dm_connector->dc_link->verified_link_cap;
8307 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
8308
8309 encoder = amdgpu_dm_connector_to_encoder(connector);
8310
8311 if (!drm_edid) {
8312 amdgpu_dm_connector->num_modes =
8313 drm_add_modes_noedid(connector, 640, 480);
8314 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
8315 amdgpu_dm_connector->num_modes +=
8316 drm_add_modes_noedid(connector, 1920, 1080);
8317 } else {
8318 amdgpu_dm_connector_ddc_get_modes(connector, drm_edid);
8319 if (encoder)
8320 amdgpu_dm_connector_add_common_modes(encoder, connector);
8321 amdgpu_dm_connector_add_freesync_modes(connector, drm_edid);
8322 }
8323 amdgpu_dm_fbc_init(connector);
8324
8325 return amdgpu_dm_connector->num_modes;
8326}
8327
8328static const u32 supported_colorspaces =
8329 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
8330 BIT(DRM_MODE_COLORIMETRY_OPRGB) |
8331 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
8332 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
8333
8334void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
8335 struct amdgpu_dm_connector *aconnector,
8336 int connector_type,
8337 struct dc_link *link,
8338 int link_index)
8339{
8340 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
8341
8342 /*
8343 * Some of the properties below require access to state, like bpc.
8344 * Allocate some default initial connector state with our reset helper.
8345 */
8346 if (aconnector->base.funcs->reset)
8347 aconnector->base.funcs->reset(&aconnector->base);
8348
8349 aconnector->connector_id = link_index;
8350 aconnector->bl_idx = -1;
8351 aconnector->dc_link = link;
8352 aconnector->base.interlace_allowed = false;
8353 aconnector->base.doublescan_allowed = false;
8354 aconnector->base.stereo_allowed = false;
8355 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
8356 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
8357 aconnector->audio_inst = -1;
8358 aconnector->pack_sdp_v1_3 = false;
8359 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
8360 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
8361 mutex_init(&aconnector->hpd_lock);
8362 mutex_init(&aconnector->handle_mst_msg_ready);
8363
8364 /*
8365 * configure support HPD hot plug connector_>polled default value is 0
8366 * which means HPD hot plug not supported
8367 */
8368 switch (connector_type) {
8369 case DRM_MODE_CONNECTOR_HDMIA:
8370 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
8371 aconnector->base.ycbcr_420_allowed =
8372 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
8373 break;
8374 case DRM_MODE_CONNECTOR_DisplayPort:
8375 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
8376 link->link_enc = link_enc_cfg_get_link_enc(link);
8377 ASSERT(link->link_enc);
8378 if (link->link_enc)
8379 aconnector->base.ycbcr_420_allowed =
8380 link->link_enc->features.dp_ycbcr420_supported ? true : false;
8381 break;
8382 case DRM_MODE_CONNECTOR_DVID:
8383 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
8384 break;
8385 default:
8386 break;
8387 }
8388
8389 drm_object_attach_property(&aconnector->base.base,
8390 dm->ddev->mode_config.scaling_mode_property,
8391 DRM_MODE_SCALE_NONE);
8392
8393 if (connector_type == DRM_MODE_CONNECTOR_HDMIA
8394 || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root))
8395 drm_connector_attach_broadcast_rgb_property(&aconnector->base);
8396
8397 drm_object_attach_property(&aconnector->base.base,
8398 adev->mode_info.underscan_property,
8399 UNDERSCAN_OFF);
8400 drm_object_attach_property(&aconnector->base.base,
8401 adev->mode_info.underscan_hborder_property,
8402 0);
8403 drm_object_attach_property(&aconnector->base.base,
8404 adev->mode_info.underscan_vborder_property,
8405 0);
8406
8407 if (!aconnector->mst_root)
8408 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
8409
8410 aconnector->base.state->max_bpc = 16;
8411 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
8412
8413 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
8414 /* Content Type is currently only implemented for HDMI. */
8415 drm_connector_attach_content_type_property(&aconnector->base);
8416 }
8417
8418 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
8419 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
8420 drm_connector_attach_colorspace_property(&aconnector->base);
8421 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
8422 connector_type == DRM_MODE_CONNECTOR_eDP) {
8423 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
8424 drm_connector_attach_colorspace_property(&aconnector->base);
8425 }
8426
8427 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
8428 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
8429 connector_type == DRM_MODE_CONNECTOR_eDP) {
8430 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
8431
8432 if (!aconnector->mst_root)
8433 drm_connector_attach_vrr_capable_property(&aconnector->base);
8434
8435 if (adev->dm.hdcp_workqueue)
8436 drm_connector_attach_content_protection_property(&aconnector->base, true);
8437 }
8438}
8439
8440static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
8441 struct i2c_msg *msgs, int num)
8442{
8443 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
8444 struct ddc_service *ddc_service = i2c->ddc_service;
8445 struct i2c_command cmd;
8446 int i;
8447 int result = -EIO;
8448
8449 if (!ddc_service->ddc_pin)
8450 return result;
8451
8452 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
8453
8454 if (!cmd.payloads)
8455 return result;
8456
8457 cmd.number_of_payloads = num;
8458 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
8459 cmd.speed = 100;
8460
8461 for (i = 0; i < num; i++) {
8462 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
8463 cmd.payloads[i].address = msgs[i].addr;
8464 cmd.payloads[i].length = msgs[i].len;
8465 cmd.payloads[i].data = msgs[i].buf;
8466 }
8467
8468 if (i2c->oem) {
8469 if (dc_submit_i2c_oem(
8470 ddc_service->ctx->dc,
8471 &cmd))
8472 result = num;
8473 } else {
8474 if (dc_submit_i2c(
8475 ddc_service->ctx->dc,
8476 ddc_service->link->link_index,
8477 &cmd))
8478 result = num;
8479 }
8480
8481 kfree(cmd.payloads);
8482 return result;
8483}
8484
8485static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
8486{
8487 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
8488}
8489
8490static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
8491 .master_xfer = amdgpu_dm_i2c_xfer,
8492 .functionality = amdgpu_dm_i2c_func,
8493};
8494
8495static struct amdgpu_i2c_adapter *
8496create_i2c(struct ddc_service *ddc_service, bool oem)
8497{
8498 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
8499 struct amdgpu_i2c_adapter *i2c;
8500
8501 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
8502 if (!i2c)
8503 return NULL;
8504 i2c->base.owner = THIS_MODULE;
8505 i2c->base.dev.parent = &adev->pdev->dev;
8506 i2c->base.algo = &amdgpu_dm_i2c_algo;
8507 if (oem)
8508 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c OEM bus");
8509 else
8510 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d",
8511 ddc_service->link->link_index);
8512 i2c_set_adapdata(&i2c->base, i2c);
8513 i2c->ddc_service = ddc_service;
8514 i2c->oem = oem;
8515
8516 return i2c;
8517}
8518
8519int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector)
8520{
8521 struct cec_connector_info conn_info;
8522 struct drm_device *ddev = aconnector->base.dev;
8523 struct device *hdmi_dev = ddev->dev;
8524
8525 if (amdgpu_dc_debug_mask & DC_DISABLE_HDMI_CEC) {
8526 drm_info(ddev, "HDMI-CEC feature masked\n");
8527 return -EINVAL;
8528 }
8529
8530 cec_fill_conn_info_from_drm(&conn_info, &aconnector->base);
8531 aconnector->notifier =
8532 cec_notifier_conn_register(hdmi_dev, NULL, &conn_info);
8533 if (!aconnector->notifier) {
8534 drm_err(ddev, "Failed to create cec notifier\n");
8535 return -ENOMEM;
8536 }
8537
8538 return 0;
8539}
8540
8541/*
8542 * Note: this function assumes that dc_link_detect() was called for the
8543 * dc_link which will be represented by this aconnector.
8544 */
8545static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
8546 struct amdgpu_dm_connector *aconnector,
8547 u32 link_index,
8548 struct amdgpu_encoder *aencoder)
8549{
8550 int res = 0;
8551 int connector_type;
8552 struct dc *dc = dm->dc;
8553 struct dc_link *link = dc_get_link_at_index(dc, link_index);
8554 struct amdgpu_i2c_adapter *i2c;
8555
8556 /* Not needed for writeback connector */
8557 link->priv = aconnector;
8558
8559
8560 i2c = create_i2c(link->ddc, false);
8561 if (!i2c) {
8562 drm_err(adev_to_drm(dm->adev), "Failed to create i2c adapter data\n");
8563 return -ENOMEM;
8564 }
8565
8566 aconnector->i2c = i2c;
8567 res = i2c_add_adapter(&i2c->base);
8568
8569 if (res) {
8570 drm_err(adev_to_drm(dm->adev), "Failed to register hw i2c %d\n", link->link_index);
8571 goto out_free;
8572 }
8573
8574 connector_type = to_drm_connector_type(link->connector_signal);
8575
8576 res = drm_connector_init_with_ddc(
8577 dm->ddev,
8578 &aconnector->base,
8579 &amdgpu_dm_connector_funcs,
8580 connector_type,
8581 &i2c->base);
8582
8583 if (res) {
8584 drm_err(adev_to_drm(dm->adev), "connector_init failed\n");
8585 aconnector->connector_id = -1;
8586 goto out_free;
8587 }
8588
8589 drm_connector_helper_add(
8590 &aconnector->base,
8591 &amdgpu_dm_connector_helper_funcs);
8592
8593 amdgpu_dm_connector_init_helper(
8594 dm,
8595 aconnector,
8596 connector_type,
8597 link,
8598 link_index);
8599
8600 drm_connector_attach_encoder(
8601 &aconnector->base, &aencoder->base);
8602
8603 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
8604 connector_type == DRM_MODE_CONNECTOR_HDMIB)
8605 amdgpu_dm_initialize_hdmi_connector(aconnector);
8606
8607 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
8608 || connector_type == DRM_MODE_CONNECTOR_eDP)
8609 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
8610
8611out_free:
8612 if (res) {
8613 kfree(i2c);
8614 aconnector->i2c = NULL;
8615 }
8616 return res;
8617}
8618
8619int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
8620{
8621 switch (adev->mode_info.num_crtc) {
8622 case 1:
8623 return 0x1;
8624 case 2:
8625 return 0x3;
8626 case 3:
8627 return 0x7;
8628 case 4:
8629 return 0xf;
8630 case 5:
8631 return 0x1f;
8632 case 6:
8633 default:
8634 return 0x3f;
8635 }
8636}
8637
8638static int amdgpu_dm_encoder_init(struct drm_device *dev,
8639 struct amdgpu_encoder *aencoder,
8640 uint32_t link_index)
8641{
8642 struct amdgpu_device *adev = drm_to_adev(dev);
8643
8644 int res = drm_encoder_init(dev,
8645 &aencoder->base,
8646 &amdgpu_dm_encoder_funcs,
8647 DRM_MODE_ENCODER_TMDS,
8648 NULL);
8649
8650 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
8651
8652 if (!res)
8653 aencoder->encoder_id = link_index;
8654 else
8655 aencoder->encoder_id = -1;
8656
8657 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
8658
8659 return res;
8660}
8661
8662static void manage_dm_interrupts(struct amdgpu_device *adev,
8663 struct amdgpu_crtc *acrtc,
8664 struct dm_crtc_state *acrtc_state)
8665{
8666 struct drm_vblank_crtc_config config = {0};
8667 struct dc_crtc_timing *timing;
8668 int offdelay;
8669
8670 if (acrtc_state) {
8671 timing = &acrtc_state->stream->timing;
8672
8673 /*
8674 * Depending on when the HW latching event of double-buffered
8675 * registers happen relative to the PSR SDP deadline, and how
8676 * bad the Panel clock has drifted since the last ALPM off
8677 * event, there can be up to 3 frames of delay between sending
8678 * the PSR exit cmd to DMUB fw, and when the panel starts
8679 * displaying live frames.
8680 *
8681 * We can set:
8682 *
8683 * 20/100 * offdelay_ms = 3_frames_ms
8684 * => offdelay_ms = 5 * 3_frames_ms
8685 *
8686 * This ensures that `3_frames_ms` will only be experienced as a
8687 * 20% delay on top how long the display has been static, and
8688 * thus make the delay less perceivable.
8689 */
8690 if (acrtc_state->stream->link->psr_settings.psr_version <
8691 DC_PSR_VERSION_UNSUPPORTED) {
8692 offdelay = DIV64_U64_ROUND_UP((u64)5 * 3 * 10 *
8693 timing->v_total *
8694 timing->h_total,
8695 timing->pix_clk_100hz);
8696 config.offdelay_ms = offdelay ?: 30;
8697 } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
8698 IP_VERSION(3, 5, 0) ||
8699 !(adev->flags & AMD_IS_APU)) {
8700 /*
8701 * Older HW and DGPU have issues with instant off;
8702 * use a 2 frame offdelay.
8703 */
8704 offdelay = DIV64_U64_ROUND_UP((u64)20 *
8705 timing->v_total *
8706 timing->h_total,
8707 timing->pix_clk_100hz);
8708
8709 config.offdelay_ms = offdelay ?: 30;
8710 } else {
8711 /* offdelay_ms = 0 will never disable vblank */
8712 config.offdelay_ms = 1;
8713 config.disable_immediate = true;
8714 }
8715
8716 drm_crtc_vblank_on_config(&acrtc->base,
8717 &config);
8718 } else {
8719 drm_crtc_vblank_off(&acrtc->base);
8720 }
8721}
8722
8723static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
8724 struct amdgpu_crtc *acrtc)
8725{
8726 int irq_type =
8727 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
8728
8729 /**
8730 * This reads the current state for the IRQ and force reapplies
8731 * the setting to hardware.
8732 */
8733 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
8734}
8735
8736static bool
8737is_scaling_state_different(const struct dm_connector_state *dm_state,
8738 const struct dm_connector_state *old_dm_state)
8739{
8740 if (dm_state->scaling != old_dm_state->scaling)
8741 return true;
8742 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
8743 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
8744 return true;
8745 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
8746 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
8747 return true;
8748 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
8749 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
8750 return true;
8751 return false;
8752}
8753
8754static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
8755 struct drm_crtc_state *old_crtc_state,
8756 struct drm_connector_state *new_conn_state,
8757 struct drm_connector_state *old_conn_state,
8758 const struct drm_connector *connector,
8759 struct hdcp_workqueue *hdcp_w)
8760{
8761 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8762 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
8763
8764 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8765 connector->index, connector->status, connector->dpms);
8766 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8767 old_conn_state->content_protection, new_conn_state->content_protection);
8768
8769 if (old_crtc_state)
8770 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8771 old_crtc_state->enable,
8772 old_crtc_state->active,
8773 old_crtc_state->mode_changed,
8774 old_crtc_state->active_changed,
8775 old_crtc_state->connectors_changed);
8776
8777 if (new_crtc_state)
8778 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8779 new_crtc_state->enable,
8780 new_crtc_state->active,
8781 new_crtc_state->mode_changed,
8782 new_crtc_state->active_changed,
8783 new_crtc_state->connectors_changed);
8784
8785 /* hdcp content type change */
8786 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
8787 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
8788 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8789 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
8790 return true;
8791 }
8792
8793 /* CP is being re enabled, ignore this */
8794 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
8795 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8796 if (new_crtc_state && new_crtc_state->mode_changed) {
8797 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8798 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
8799 return true;
8800 }
8801 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
8802 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
8803 return false;
8804 }
8805
8806 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
8807 *
8808 * Handles: UNDESIRED -> ENABLED
8809 */
8810 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
8811 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
8812 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8813
8814 /* Stream removed and re-enabled
8815 *
8816 * Can sometimes overlap with the HPD case,
8817 * thus set update_hdcp to false to avoid
8818 * setting HDCP multiple times.
8819 *
8820 * Handles: DESIRED -> DESIRED (Special case)
8821 */
8822 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
8823 new_conn_state->crtc && new_conn_state->crtc->enabled &&
8824 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8825 dm_con_state->update_hdcp = false;
8826 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
8827 __func__);
8828 return true;
8829 }
8830
8831 /* Hot-plug, headless s3, dpms
8832 *
8833 * Only start HDCP if the display is connected/enabled.
8834 * update_hdcp flag will be set to false until the next
8835 * HPD comes in.
8836 *
8837 * Handles: DESIRED -> DESIRED (Special case)
8838 */
8839 if (dm_con_state->update_hdcp &&
8840 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
8841 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
8842 dm_con_state->update_hdcp = false;
8843 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
8844 __func__);
8845 return true;
8846 }
8847
8848 if (old_conn_state->content_protection == new_conn_state->content_protection) {
8849 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8850 if (new_crtc_state && new_crtc_state->mode_changed) {
8851 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
8852 __func__);
8853 return true;
8854 }
8855 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
8856 __func__);
8857 return false;
8858 }
8859
8860 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
8861 return false;
8862 }
8863
8864 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8865 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
8866 __func__);
8867 return true;
8868 }
8869
8870 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
8871 return false;
8872}
8873
8874static void remove_stream(struct amdgpu_device *adev,
8875 struct amdgpu_crtc *acrtc,
8876 struct dc_stream_state *stream)
8877{
8878 /* this is the update mode case */
8879
8880 acrtc->otg_inst = -1;
8881 acrtc->enabled = false;
8882}
8883
8884static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
8885{
8886
8887 assert_spin_locked(&acrtc->base.dev->event_lock);
8888 WARN_ON(acrtc->event);
8889
8890 acrtc->event = acrtc->base.state->event;
8891
8892 /* Set the flip status */
8893 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
8894
8895 /* Mark this event as consumed */
8896 acrtc->base.state->event = NULL;
8897
8898 drm_dbg_state(acrtc->base.dev,
8899 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
8900 acrtc->crtc_id);
8901}
8902
8903static void update_freesync_state_on_stream(
8904 struct amdgpu_display_manager *dm,
8905 struct dm_crtc_state *new_crtc_state,
8906 struct dc_stream_state *new_stream,
8907 struct dc_plane_state *surface,
8908 u32 flip_timestamp_in_us)
8909{
8910 struct mod_vrr_params vrr_params;
8911 struct dc_info_packet vrr_infopacket = {0};
8912 struct amdgpu_device *adev = dm->adev;
8913 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8914 unsigned long flags;
8915 bool pack_sdp_v1_3 = false;
8916 struct amdgpu_dm_connector *aconn;
8917 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
8918
8919 if (!new_stream)
8920 return;
8921
8922 /*
8923 * TODO: Determine why min/max totals and vrefresh can be 0 here.
8924 * For now it's sufficient to just guard against these conditions.
8925 */
8926
8927 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8928 return;
8929
8930 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8931 vrr_params = acrtc->dm_irq_params.vrr_params;
8932
8933 if (surface) {
8934 mod_freesync_handle_preflip(
8935 dm->freesync_module,
8936 surface,
8937 new_stream,
8938 flip_timestamp_in_us,
8939 &vrr_params);
8940
8941 if (adev->family < AMDGPU_FAMILY_AI &&
8942 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
8943 mod_freesync_handle_v_update(dm->freesync_module,
8944 new_stream, &vrr_params);
8945
8946 /* Need to call this before the frame ends. */
8947 dc_stream_adjust_vmin_vmax(dm->dc,
8948 new_crtc_state->stream,
8949 &vrr_params.adjust);
8950 }
8951 }
8952
8953 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
8954
8955 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
8956 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
8957
8958 if (aconn->vsdb_info.amd_vsdb_version == 1)
8959 packet_type = PACKET_TYPE_FS_V1;
8960 else if (aconn->vsdb_info.amd_vsdb_version == 2)
8961 packet_type = PACKET_TYPE_FS_V2;
8962 else if (aconn->vsdb_info.amd_vsdb_version == 3)
8963 packet_type = PACKET_TYPE_FS_V3;
8964
8965 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
8966 &new_stream->adaptive_sync_infopacket);
8967 }
8968
8969 mod_freesync_build_vrr_infopacket(
8970 dm->freesync_module,
8971 new_stream,
8972 &vrr_params,
8973 packet_type,
8974 TRANSFER_FUNC_UNKNOWN,
8975 &vrr_infopacket,
8976 pack_sdp_v1_3);
8977
8978 new_crtc_state->freesync_vrr_info_changed |=
8979 (memcmp(&new_crtc_state->vrr_infopacket,
8980 &vrr_infopacket,
8981 sizeof(vrr_infopacket)) != 0);
8982
8983 acrtc->dm_irq_params.vrr_params = vrr_params;
8984 new_crtc_state->vrr_infopacket = vrr_infopacket;
8985
8986 new_stream->vrr_infopacket = vrr_infopacket;
8987 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
8988
8989 if (new_crtc_state->freesync_vrr_info_changed)
8990 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8991 new_crtc_state->base.crtc->base.id,
8992 (int)new_crtc_state->base.vrr_enabled,
8993 (int)vrr_params.state);
8994
8995 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8996}
8997
8998static void update_stream_irq_parameters(
8999 struct amdgpu_display_manager *dm,
9000 struct dm_crtc_state *new_crtc_state)
9001{
9002 struct dc_stream_state *new_stream = new_crtc_state->stream;
9003 struct mod_vrr_params vrr_params;
9004 struct mod_freesync_config config = new_crtc_state->freesync_config;
9005 struct amdgpu_device *adev = dm->adev;
9006 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
9007 unsigned long flags;
9008
9009 if (!new_stream)
9010 return;
9011
9012 /*
9013 * TODO: Determine why min/max totals and vrefresh can be 0 here.
9014 * For now it's sufficient to just guard against these conditions.
9015 */
9016 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
9017 return;
9018
9019 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9020 vrr_params = acrtc->dm_irq_params.vrr_params;
9021
9022 if (new_crtc_state->vrr_supported &&
9023 config.min_refresh_in_uhz &&
9024 config.max_refresh_in_uhz) {
9025 /*
9026 * if freesync compatible mode was set, config.state will be set
9027 * in atomic check
9028 */
9029 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
9030 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
9031 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
9032 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
9033 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
9034 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
9035 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
9036 } else {
9037 config.state = new_crtc_state->base.vrr_enabled ?
9038 VRR_STATE_ACTIVE_VARIABLE :
9039 VRR_STATE_INACTIVE;
9040 }
9041 } else {
9042 config.state = VRR_STATE_UNSUPPORTED;
9043 }
9044
9045 mod_freesync_build_vrr_params(dm->freesync_module,
9046 new_stream,
9047 &config, &vrr_params);
9048
9049 new_crtc_state->freesync_config = config;
9050 /* Copy state for access from DM IRQ handler */
9051 acrtc->dm_irq_params.freesync_config = config;
9052 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
9053 acrtc->dm_irq_params.vrr_params = vrr_params;
9054 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9055}
9056
9057static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
9058 struct dm_crtc_state *new_state)
9059{
9060 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
9061 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
9062
9063 if (!old_vrr_active && new_vrr_active) {
9064 /* Transition VRR inactive -> active:
9065 * While VRR is active, we must not disable vblank irq, as a
9066 * reenable after disable would compute bogus vblank/pflip
9067 * timestamps if it likely happened inside display front-porch.
9068 *
9069 * We also need vupdate irq for the actual core vblank handling
9070 * at end of vblank.
9071 */
9072 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
9073 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
9074 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n",
9075 __func__, new_state->base.crtc->base.id);
9076 } else if (old_vrr_active && !new_vrr_active) {
9077 /* Transition VRR active -> inactive:
9078 * Allow vblank irq disable again for fixed refresh rate.
9079 */
9080 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
9081 drm_crtc_vblank_put(new_state->base.crtc);
9082 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n",
9083 __func__, new_state->base.crtc->base.id);
9084 }
9085}
9086
9087static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
9088{
9089 struct drm_plane *plane;
9090 struct drm_plane_state *old_plane_state;
9091 int i;
9092
9093 /*
9094 * TODO: Make this per-stream so we don't issue redundant updates for
9095 * commits with multiple streams.
9096 */
9097 for_each_old_plane_in_state(state, plane, old_plane_state, i)
9098 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9099 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
9100}
9101
9102static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
9103{
9104 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
9105
9106 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
9107}
9108
9109static void amdgpu_dm_update_cursor(struct drm_plane *plane,
9110 struct drm_plane_state *old_plane_state,
9111 struct dc_stream_update *update)
9112{
9113 struct amdgpu_device *adev = drm_to_adev(plane->dev);
9114 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
9115 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
9116 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
9117 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
9118 uint64_t address = afb ? afb->address : 0;
9119 struct dc_cursor_position position = {0};
9120 struct dc_cursor_attributes attributes;
9121 int ret;
9122
9123 if (!plane->state->fb && !old_plane_state->fb)
9124 return;
9125
9126 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n",
9127 amdgpu_crtc->crtc_id, plane->state->crtc_w,
9128 plane->state->crtc_h);
9129
9130 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);
9131 if (ret)
9132 return;
9133
9134 if (!position.enable) {
9135 /* turn off cursor */
9136 if (crtc_state && crtc_state->stream) {
9137 dc_stream_set_cursor_position(crtc_state->stream,
9138 &position);
9139 update->cursor_position = &crtc_state->stream->cursor_position;
9140 }
9141 return;
9142 }
9143
9144 amdgpu_crtc->cursor_width = plane->state->crtc_w;
9145 amdgpu_crtc->cursor_height = plane->state->crtc_h;
9146
9147 memset(&attributes, 0, sizeof(attributes));
9148 attributes.address.high_part = upper_32_bits(address);
9149 attributes.address.low_part = lower_32_bits(address);
9150 attributes.width = plane->state->crtc_w;
9151 attributes.height = plane->state->crtc_h;
9152 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
9153 attributes.rotation_angle = 0;
9154 attributes.attribute_flags.value = 0;
9155
9156 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
9157 * legacy gamma setup.
9158 */
9159 if (crtc_state->cm_is_degamma_srgb &&
9160 adev->dm.dc->caps.color.dpp.gamma_corr)
9161 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
9162
9163 if (afb)
9164 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
9165
9166 if (crtc_state->stream) {
9167 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
9168 &attributes))
9169 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n");
9170
9171 update->cursor_attributes = &crtc_state->stream->cursor_attributes;
9172
9173 if (!dc_stream_set_cursor_position(crtc_state->stream,
9174 &position))
9175 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n");
9176
9177 update->cursor_position = &crtc_state->stream->cursor_position;
9178 }
9179}
9180
9181static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
9182 const struct dm_crtc_state *acrtc_state,
9183 const u64 current_ts)
9184{
9185 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
9186 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
9187 struct amdgpu_dm_connector *aconn =
9188 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
9189 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
9190
9191 if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9192 if (pr->config.replay_supported && !pr->replay_feature_enabled)
9193 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
9194 else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
9195 !psr->psr_feature_enabled)
9196 if (!aconn->disallow_edp_enter_psr)
9197 amdgpu_dm_link_setup_psr(acrtc_state->stream);
9198 }
9199
9200 /* Decrement skip count when SR is enabled and we're doing fast updates. */
9201 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
9202 (psr->psr_feature_enabled || pr->config.replay_supported)) {
9203 if (aconn->sr_skip_count > 0)
9204 aconn->sr_skip_count--;
9205
9206 /* Allow SR when skip count is 0. */
9207 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
9208
9209 /*
9210 * If sink supports PSR SU/Panel Replay, there is no need to rely on
9211 * a vblank event disable request to enable PSR/RP. PSR SU/RP
9212 * can be enabled immediately once OS demonstrates an
9213 * adequate number of fast atomic commits to notify KMD
9214 * of update events. See `vblank_control_worker()`.
9215 */
9216 if (!vrr_active &&
9217 acrtc_attach->dm_irq_params.allow_sr_entry &&
9218#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9219 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9220#endif
9221 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
9222 if (pr->replay_feature_enabled && !pr->replay_allow_active)
9223 amdgpu_dm_replay_enable(acrtc_state->stream, true);
9224 if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
9225 !psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
9226 amdgpu_dm_psr_enable(acrtc_state->stream);
9227 }
9228 } else {
9229 acrtc_attach->dm_irq_params.allow_sr_entry = false;
9230 }
9231}
9232
9233static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
9234 struct drm_device *dev,
9235 struct amdgpu_display_manager *dm,
9236 struct drm_crtc *pcrtc,
9237 bool wait_for_vblank)
9238{
9239 u32 i;
9240 u64 timestamp_ns = ktime_get_ns();
9241 struct drm_plane *plane;
9242 struct drm_plane_state *old_plane_state, *new_plane_state;
9243 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
9244 struct drm_crtc_state *new_pcrtc_state =
9245 drm_atomic_get_new_crtc_state(state, pcrtc);
9246 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
9247 struct dm_crtc_state *dm_old_crtc_state =
9248 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
9249 int planes_count = 0, vpos, hpos;
9250 unsigned long flags;
9251 u32 target_vblank, last_flip_vblank;
9252 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
9253 bool cursor_update = false;
9254 bool pflip_present = false;
9255 bool dirty_rects_changed = false;
9256 bool updated_planes_and_streams = false;
9257 struct {
9258 struct dc_surface_update surface_updates[MAX_SURFACES];
9259 struct dc_plane_info plane_infos[MAX_SURFACES];
9260 struct dc_scaling_info scaling_infos[MAX_SURFACES];
9261 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
9262 struct dc_stream_update stream_update;
9263 } *bundle;
9264
9265 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
9266
9267 if (!bundle) {
9268 drm_err(dev, "Failed to allocate update bundle\n");
9269 goto cleanup;
9270 }
9271
9272 /*
9273 * Disable the cursor first if we're disabling all the planes.
9274 * It'll remain on the screen after the planes are re-enabled
9275 * if we don't.
9276 *
9277 * If the cursor is transitioning from native to overlay mode, the
9278 * native cursor needs to be disabled first.
9279 */
9280 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE &&
9281 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
9282 struct dc_cursor_position cursor_position = {0};
9283
9284 if (!dc_stream_set_cursor_position(acrtc_state->stream,
9285 &cursor_position))
9286 drm_err(dev, "DC failed to disable native cursor\n");
9287
9288 bundle->stream_update.cursor_position =
9289 &acrtc_state->stream->cursor_position;
9290 }
9291
9292 if (acrtc_state->active_planes == 0 &&
9293 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
9294 amdgpu_dm_commit_cursors(state);
9295
9296 /* update planes when needed */
9297 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9298 struct drm_crtc *crtc = new_plane_state->crtc;
9299 struct drm_crtc_state *new_crtc_state;
9300 struct drm_framebuffer *fb = new_plane_state->fb;
9301 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
9302 bool plane_needs_flip;
9303 struct dc_plane_state *dc_plane;
9304 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
9305
9306 /* Cursor plane is handled after stream updates */
9307 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
9308 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
9309 if ((fb && crtc == pcrtc) ||
9310 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) {
9311 cursor_update = true;
9312 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0)
9313 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update);
9314 }
9315
9316 continue;
9317 }
9318
9319 if (!fb || !crtc || pcrtc != crtc)
9320 continue;
9321
9322 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
9323 if (!new_crtc_state->active)
9324 continue;
9325
9326 dc_plane = dm_new_plane_state->dc_state;
9327 if (!dc_plane)
9328 continue;
9329
9330 bundle->surface_updates[planes_count].surface = dc_plane;
9331 if (new_pcrtc_state->color_mgmt_changed) {
9332 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction;
9333 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func;
9334 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
9335 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult;
9336 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func;
9337 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func;
9338 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf;
9339 }
9340
9341 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
9342 &bundle->scaling_infos[planes_count]);
9343
9344 bundle->surface_updates[planes_count].scaling_info =
9345 &bundle->scaling_infos[planes_count];
9346
9347 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
9348
9349 pflip_present = pflip_present || plane_needs_flip;
9350
9351 if (!plane_needs_flip) {
9352 planes_count += 1;
9353 continue;
9354 }
9355
9356 fill_dc_plane_info_and_addr(
9357 dm->adev, new_plane_state,
9358 afb->tiling_flags,
9359 &bundle->plane_infos[planes_count],
9360 &bundle->flip_addrs[planes_count].address,
9361 afb->tmz_surface);
9362
9363 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
9364 new_plane_state->plane->index,
9365 bundle->plane_infos[planes_count].dcc.enable);
9366
9367 bundle->surface_updates[planes_count].plane_info =
9368 &bundle->plane_infos[planes_count];
9369
9370 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
9371 acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
9372 fill_dc_dirty_rects(plane, old_plane_state,
9373 new_plane_state, new_crtc_state,
9374 &bundle->flip_addrs[planes_count],
9375 acrtc_state->stream->link->psr_settings.psr_version ==
9376 DC_PSR_VERSION_SU_1,
9377 &dirty_rects_changed);
9378
9379 /*
9380 * If the dirty regions changed, PSR-SU need to be disabled temporarily
9381 * and enabled it again after dirty regions are stable to avoid video glitch.
9382 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
9383 * during the PSR-SU was disabled.
9384 */
9385 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
9386 acrtc_attach->dm_irq_params.allow_sr_entry &&
9387#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9388 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9389#endif
9390 dirty_rects_changed) {
9391 mutex_lock(&dm->dc_lock);
9392 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
9393 timestamp_ns;
9394 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9395 amdgpu_dm_psr_disable(acrtc_state->stream, true);
9396 mutex_unlock(&dm->dc_lock);
9397 }
9398 }
9399
9400 /*
9401 * Only allow immediate flips for fast updates that don't
9402 * change memory domain, FB pitch, DCC state, rotation or
9403 * mirroring.
9404 *
9405 * dm_crtc_helper_atomic_check() only accepts async flips with
9406 * fast updates.
9407 */
9408 if (crtc->state->async_flip &&
9409 (acrtc_state->update_type != UPDATE_TYPE_FAST ||
9410 get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
9411 drm_warn_once(state->dev,
9412 "[PLANE:%d:%s] async flip with non-fast update\n",
9413 plane->base.id, plane->name);
9414
9415 bundle->flip_addrs[planes_count].flip_immediate =
9416 crtc->state->async_flip &&
9417 acrtc_state->update_type == UPDATE_TYPE_FAST &&
9418 get_mem_type(old_plane_state->fb) == get_mem_type(fb);
9419
9420 timestamp_ns = ktime_get_ns();
9421 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
9422 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
9423 bundle->surface_updates[planes_count].surface = dc_plane;
9424
9425 if (!bundle->surface_updates[planes_count].surface) {
9426 drm_err(dev, "No surface for CRTC: id=%d\n",
9427 acrtc_attach->crtc_id);
9428 continue;
9429 }
9430
9431 if (plane == pcrtc->primary)
9432 update_freesync_state_on_stream(
9433 dm,
9434 acrtc_state,
9435 acrtc_state->stream,
9436 dc_plane,
9437 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
9438
9439 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
9440 __func__,
9441 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
9442 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
9443
9444 planes_count += 1;
9445
9446 }
9447
9448 if (pflip_present) {
9449 if (!vrr_active) {
9450 /* Use old throttling in non-vrr fixed refresh rate mode
9451 * to keep flip scheduling based on target vblank counts
9452 * working in a backwards compatible way, e.g., for
9453 * clients using the GLX_OML_sync_control extension or
9454 * DRI3/Present extension with defined target_msc.
9455 */
9456 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
9457 } else {
9458 /* For variable refresh rate mode only:
9459 * Get vblank of last completed flip to avoid > 1 vrr
9460 * flips per video frame by use of throttling, but allow
9461 * flip programming anywhere in the possibly large
9462 * variable vrr vblank interval for fine-grained flip
9463 * timing control and more opportunity to avoid stutter
9464 * on late submission of flips.
9465 */
9466 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9467 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
9468 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9469 }
9470
9471 target_vblank = last_flip_vblank + wait_for_vblank;
9472
9473 /*
9474 * Wait until we're out of the vertical blank period before the one
9475 * targeted by the flip
9476 */
9477 while ((acrtc_attach->enabled &&
9478 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
9479 0, &vpos, &hpos, NULL,
9480 NULL, &pcrtc->hwmode)
9481 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
9482 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
9483 (int)(target_vblank -
9484 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
9485 usleep_range(1000, 1100);
9486 }
9487
9488 /**
9489 * Prepare the flip event for the pageflip interrupt to handle.
9490 *
9491 * This only works in the case where we've already turned on the
9492 * appropriate hardware blocks (eg. HUBP) so in the transition case
9493 * from 0 -> n planes we have to skip a hardware generated event
9494 * and rely on sending it from software.
9495 */
9496 if (acrtc_attach->base.state->event &&
9497 acrtc_state->active_planes > 0) {
9498 drm_crtc_vblank_get(pcrtc);
9499
9500 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9501
9502 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
9503 prepare_flip_isr(acrtc_attach);
9504
9505 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9506 }
9507
9508 if (acrtc_state->stream) {
9509 if (acrtc_state->freesync_vrr_info_changed)
9510 bundle->stream_update.vrr_infopacket =
9511 &acrtc_state->stream->vrr_infopacket;
9512 }
9513 } else if (cursor_update && acrtc_state->active_planes > 0) {
9514 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9515 if (acrtc_attach->base.state->event) {
9516 drm_crtc_vblank_get(pcrtc);
9517 acrtc_attach->event = acrtc_attach->base.state->event;
9518 acrtc_attach->base.state->event = NULL;
9519 }
9520 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9521 }
9522
9523 /* Update the planes if changed or disable if we don't have any. */
9524 if ((planes_count || acrtc_state->active_planes == 0) &&
9525 acrtc_state->stream) {
9526 /*
9527 * If PSR or idle optimizations are enabled then flush out
9528 * any pending work before hardware programming.
9529 */
9530 if (dm->vblank_control_workqueue)
9531 flush_workqueue(dm->vblank_control_workqueue);
9532
9533 bundle->stream_update.stream = acrtc_state->stream;
9534 if (new_pcrtc_state->mode_changed) {
9535 bundle->stream_update.src = acrtc_state->stream->src;
9536 bundle->stream_update.dst = acrtc_state->stream->dst;
9537 }
9538
9539 if (new_pcrtc_state->color_mgmt_changed) {
9540 /*
9541 * TODO: This isn't fully correct since we've actually
9542 * already modified the stream in place.
9543 */
9544 bundle->stream_update.gamut_remap =
9545 &acrtc_state->stream->gamut_remap_matrix;
9546 bundle->stream_update.output_csc_transform =
9547 &acrtc_state->stream->csc_color_matrix;
9548 bundle->stream_update.out_transfer_func =
9549 &acrtc_state->stream->out_transfer_func;
9550 bundle->stream_update.lut3d_func =
9551 (struct dc_3dlut *) acrtc_state->stream->lut3d_func;
9552 bundle->stream_update.func_shaper =
9553 (struct dc_transfer_func *) acrtc_state->stream->func_shaper;
9554 }
9555
9556 acrtc_state->stream->abm_level = acrtc_state->abm_level;
9557 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
9558 bundle->stream_update.abm_level = &acrtc_state->abm_level;
9559
9560 mutex_lock(&dm->dc_lock);
9561 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) {
9562 if (acrtc_state->stream->link->replay_settings.replay_allow_active)
9563 amdgpu_dm_replay_disable(acrtc_state->stream);
9564 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9565 amdgpu_dm_psr_disable(acrtc_state->stream, true);
9566 }
9567 mutex_unlock(&dm->dc_lock);
9568
9569 /*
9570 * If FreeSync state on the stream has changed then we need to
9571 * re-adjust the min/max bounds now that DC doesn't handle this
9572 * as part of commit.
9573 */
9574 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
9575 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9576 dc_stream_adjust_vmin_vmax(
9577 dm->dc, acrtc_state->stream,
9578 &acrtc_attach->dm_irq_params.vrr_params.adjust);
9579 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9580 }
9581 mutex_lock(&dm->dc_lock);
9582 update_planes_and_stream_adapter(dm->dc,
9583 acrtc_state->update_type,
9584 planes_count,
9585 acrtc_state->stream,
9586 &bundle->stream_update,
9587 bundle->surface_updates);
9588 updated_planes_and_streams = true;
9589
9590 /**
9591 * Enable or disable the interrupts on the backend.
9592 *
9593 * Most pipes are put into power gating when unused.
9594 *
9595 * When power gating is enabled on a pipe we lose the
9596 * interrupt enablement state when power gating is disabled.
9597 *
9598 * So we need to update the IRQ control state in hardware
9599 * whenever the pipe turns on (since it could be previously
9600 * power gated) or off (since some pipes can't be power gated
9601 * on some ASICs).
9602 */
9603 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
9604 dm_update_pflip_irq_state(drm_to_adev(dev),
9605 acrtc_attach);
9606
9607 amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
9608 mutex_unlock(&dm->dc_lock);
9609 }
9610
9611 /*
9612 * Update cursor state *after* programming all the planes.
9613 * This avoids redundant programming in the case where we're going
9614 * to be disabling a single plane - those pipes are being disabled.
9615 */
9616 if (acrtc_state->active_planes &&
9617 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) &&
9618 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
9619 amdgpu_dm_commit_cursors(state);
9620
9621cleanup:
9622 kfree(bundle);
9623}
9624
9625static void amdgpu_dm_commit_audio(struct drm_device *dev,
9626 struct drm_atomic_state *state)
9627{
9628 struct amdgpu_device *adev = drm_to_adev(dev);
9629 struct amdgpu_dm_connector *aconnector;
9630 struct drm_connector *connector;
9631 struct drm_connector_state *old_con_state, *new_con_state;
9632 struct drm_crtc_state *new_crtc_state;
9633 struct dm_crtc_state *new_dm_crtc_state;
9634 const struct dc_stream_status *status;
9635 int i, inst;
9636
9637 /* Notify device removals. */
9638 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9639 if (old_con_state->crtc != new_con_state->crtc) {
9640 /* CRTC changes require notification. */
9641 goto notify;
9642 }
9643
9644 if (!new_con_state->crtc)
9645 continue;
9646
9647 new_crtc_state = drm_atomic_get_new_crtc_state(
9648 state, new_con_state->crtc);
9649
9650 if (!new_crtc_state)
9651 continue;
9652
9653 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9654 continue;
9655
9656notify:
9657 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9658 continue;
9659
9660 aconnector = to_amdgpu_dm_connector(connector);
9661
9662 mutex_lock(&adev->dm.audio_lock);
9663 inst = aconnector->audio_inst;
9664 aconnector->audio_inst = -1;
9665 mutex_unlock(&adev->dm.audio_lock);
9666
9667 amdgpu_dm_audio_eld_notify(adev, inst);
9668 }
9669
9670 /* Notify audio device additions. */
9671 for_each_new_connector_in_state(state, connector, new_con_state, i) {
9672 if (!new_con_state->crtc)
9673 continue;
9674
9675 new_crtc_state = drm_atomic_get_new_crtc_state(
9676 state, new_con_state->crtc);
9677
9678 if (!new_crtc_state)
9679 continue;
9680
9681 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9682 continue;
9683
9684 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
9685 if (!new_dm_crtc_state->stream)
9686 continue;
9687
9688 status = dc_stream_get_status(new_dm_crtc_state->stream);
9689 if (!status)
9690 continue;
9691
9692 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9693 continue;
9694
9695 aconnector = to_amdgpu_dm_connector(connector);
9696
9697 mutex_lock(&adev->dm.audio_lock);
9698 inst = status->audio_inst;
9699 aconnector->audio_inst = inst;
9700 mutex_unlock(&adev->dm.audio_lock);
9701
9702 amdgpu_dm_audio_eld_notify(adev, inst);
9703 }
9704}
9705
9706/*
9707 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
9708 * @crtc_state: the DRM CRTC state
9709 * @stream_state: the DC stream state.
9710 *
9711 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
9712 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
9713 */
9714static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
9715 struct dc_stream_state *stream_state)
9716{
9717 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
9718}
9719
9720static void dm_clear_writeback(struct amdgpu_display_manager *dm,
9721 struct dm_crtc_state *crtc_state)
9722{
9723 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
9724}
9725
9726static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
9727 struct dc_state *dc_state)
9728{
9729 struct drm_device *dev = state->dev;
9730 struct amdgpu_device *adev = drm_to_adev(dev);
9731 struct amdgpu_display_manager *dm = &adev->dm;
9732 struct drm_crtc *crtc;
9733 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9734 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9735 struct drm_connector_state *old_con_state;
9736 struct drm_connector *connector;
9737 bool mode_set_reset_required = false;
9738 u32 i;
9739 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};
9740 bool set_backlight_level = false;
9741
9742 /* Disable writeback */
9743 for_each_old_connector_in_state(state, connector, old_con_state, i) {
9744 struct dm_connector_state *dm_old_con_state;
9745 struct amdgpu_crtc *acrtc;
9746
9747 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
9748 continue;
9749
9750 old_crtc_state = NULL;
9751
9752 dm_old_con_state = to_dm_connector_state(old_con_state);
9753 if (!dm_old_con_state->base.crtc)
9754 continue;
9755
9756 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);
9757 if (acrtc)
9758 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9759
9760 if (!acrtc || !acrtc->wb_enabled)
9761 continue;
9762
9763 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9764
9765 dm_clear_writeback(dm, dm_old_crtc_state);
9766 acrtc->wb_enabled = false;
9767 }
9768
9769 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
9770 new_crtc_state, i) {
9771 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9772
9773 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9774
9775 if (old_crtc_state->active &&
9776 (!new_crtc_state->active ||
9777 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9778 manage_dm_interrupts(adev, acrtc, NULL);
9779 dc_stream_release(dm_old_crtc_state->stream);
9780 }
9781 }
9782
9783 drm_atomic_helper_calc_timestamping_constants(state);
9784
9785 /* update changed items */
9786 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9787 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9788
9789 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9790 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9791
9792 drm_dbg_state(state->dev,
9793 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9794 acrtc->crtc_id,
9795 new_crtc_state->enable,
9796 new_crtc_state->active,
9797 new_crtc_state->planes_changed,
9798 new_crtc_state->mode_changed,
9799 new_crtc_state->active_changed,
9800 new_crtc_state->connectors_changed);
9801
9802 /* Disable cursor if disabling crtc */
9803 if (old_crtc_state->active && !new_crtc_state->active) {
9804 struct dc_cursor_position position;
9805
9806 memset(&position, 0, sizeof(position));
9807 mutex_lock(&dm->dc_lock);
9808 dc_exit_ips_for_hw_access(dm->dc);
9809 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position);
9810 mutex_unlock(&dm->dc_lock);
9811 }
9812
9813 /* Copy all transient state flags into dc state */
9814 if (dm_new_crtc_state->stream) {
9815 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
9816 dm_new_crtc_state->stream);
9817 }
9818
9819 /* handles headless hotplug case, updating new_state and
9820 * aconnector as needed
9821 */
9822
9823 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
9824
9825 drm_dbg_atomic(dev,
9826 "Atomic commit: SET crtc id %d: [%p]\n",
9827 acrtc->crtc_id, acrtc);
9828
9829 if (!dm_new_crtc_state->stream) {
9830 /*
9831 * this could happen because of issues with
9832 * userspace notifications delivery.
9833 * In this case userspace tries to set mode on
9834 * display which is disconnected in fact.
9835 * dc_sink is NULL in this case on aconnector.
9836 * We expect reset mode will come soon.
9837 *
9838 * This can also happen when unplug is done
9839 * during resume sequence ended
9840 *
9841 * In this case, we want to pretend we still
9842 * have a sink to keep the pipe running so that
9843 * hw state is consistent with the sw state
9844 */
9845 drm_dbg_atomic(dev,
9846 "Failed to create new stream for crtc %d\n",
9847 acrtc->base.base.id);
9848 continue;
9849 }
9850
9851 if (dm_old_crtc_state->stream)
9852 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
9853
9854 pm_runtime_get_noresume(dev->dev);
9855
9856 acrtc->enabled = true;
9857 acrtc->hw_mode = new_crtc_state->mode;
9858 crtc->hwmode = new_crtc_state->mode;
9859 mode_set_reset_required = true;
9860 set_backlight_level = true;
9861 } else if (modereset_required(new_crtc_state)) {
9862 drm_dbg_atomic(dev,
9863 "Atomic commit: RESET. crtc id %d:[%p]\n",
9864 acrtc->crtc_id, acrtc);
9865 /* i.e. reset mode */
9866 if (dm_old_crtc_state->stream)
9867 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
9868
9869 mode_set_reset_required = true;
9870 }
9871 } /* for_each_crtc_in_state() */
9872
9873 /* if there mode set or reset, disable eDP PSR, Replay */
9874 if (mode_set_reset_required) {
9875 if (dm->vblank_control_workqueue)
9876 flush_workqueue(dm->vblank_control_workqueue);
9877
9878 amdgpu_dm_replay_disable_all(dm);
9879 amdgpu_dm_psr_disable_all(dm);
9880 }
9881
9882 dm_enable_per_frame_crtc_master_sync(dc_state);
9883 mutex_lock(&dm->dc_lock);
9884 dc_exit_ips_for_hw_access(dm->dc);
9885 WARN_ON(!dc_commit_streams(dm->dc, &params));
9886
9887 /* Allow idle optimization when vblank count is 0 for display off */
9888 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev))
9889 dc_allow_idle_optimizations(dm->dc, true);
9890 mutex_unlock(&dm->dc_lock);
9891
9892 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9893 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9894
9895 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9896
9897 if (dm_new_crtc_state->stream != NULL) {
9898 const struct dc_stream_status *status =
9899 dc_stream_get_status(dm_new_crtc_state->stream);
9900
9901 if (!status)
9902 status = dc_state_get_stream_status(dc_state,
9903 dm_new_crtc_state->stream);
9904 if (!status)
9905 drm_err(dev,
9906 "got no status for stream %p on acrtc%p\n",
9907 dm_new_crtc_state->stream, acrtc);
9908 else
9909 acrtc->otg_inst = status->primary_otg_inst;
9910 }
9911 }
9912
9913 /* During boot up and resume the DC layer will reset the panel brightness
9914 * to fix a flicker issue.
9915 * It will cause the dm->actual_brightness is not the current panel brightness
9916 * level. (the dm->brightness is the correct panel level)
9917 * So we set the backlight level with dm->brightness value after set mode
9918 */
9919 if (set_backlight_level) {
9920 for (i = 0; i < dm->num_of_edps; i++) {
9921 if (dm->backlight_dev[i])
9922 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9923 }
9924 }
9925}
9926
9927static void dm_set_writeback(struct amdgpu_display_manager *dm,
9928 struct dm_crtc_state *crtc_state,
9929 struct drm_connector *connector,
9930 struct drm_connector_state *new_con_state)
9931{
9932 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
9933 struct amdgpu_device *adev = dm->adev;
9934 struct amdgpu_crtc *acrtc;
9935 struct dc_writeback_info *wb_info;
9936 struct pipe_ctx *pipe = NULL;
9937 struct amdgpu_framebuffer *afb;
9938 int i = 0;
9939
9940 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);
9941 if (!wb_info) {
9942 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n");
9943 return;
9944 }
9945
9946 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);
9947 if (!acrtc) {
9948 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n");
9949 kfree(wb_info);
9950 return;
9951 }
9952
9953 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);
9954 if (!afb) {
9955 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n");
9956 kfree(wb_info);
9957 return;
9958 }
9959
9960 for (i = 0; i < MAX_PIPES; i++) {
9961 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
9962 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
9963 break;
9964 }
9965 }
9966
9967 /* fill in wb_info */
9968 wb_info->wb_enabled = true;
9969
9970 wb_info->dwb_pipe_inst = 0;
9971 wb_info->dwb_params.dwbscl_black_color = 0;
9972 wb_info->dwb_params.hdr_mult = 0x1F000;
9973 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;
9974 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
9975 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;
9976 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;
9977
9978 /* width & height from crtc */
9979 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;
9980 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;
9981 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;
9982 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;
9983
9984 wb_info->dwb_params.cnv_params.crop_en = false;
9985 wb_info->dwb_params.stereo_params.stereo_enabled = false;
9986
9987 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits
9988 wb_info->dwb_params.cnv_params.out_min_pix_val = 0;
9989 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;
9990 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;
9991
9992 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;
9993
9994 wb_info->dwb_params.capture_rate = dwb_capture_rate_0;
9995
9996 wb_info->dwb_params.scaler_taps.h_taps = 4;
9997 wb_info->dwb_params.scaler_taps.v_taps = 4;
9998 wb_info->dwb_params.scaler_taps.h_taps_c = 2;
9999 wb_info->dwb_params.scaler_taps.v_taps_c = 2;
10000 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;
10001
10002 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];
10003 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];
10004
10005 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {
10006 wb_info->mcif_buf_params.luma_address[i] = afb->address;
10007 wb_info->mcif_buf_params.chroma_address[i] = 0;
10008 }
10009
10010 wb_info->mcif_buf_params.p_vmid = 1;
10011 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) {
10012 wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
10013 wb_info->mcif_warmup_params.region_size =
10014 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
10015 }
10016 wb_info->mcif_warmup_params.p_vmid = 1;
10017 wb_info->writeback_source_plane = pipe->plane_state;
10018
10019 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
10020
10021 acrtc->wb_pending = true;
10022 acrtc->wb_conn = wb_conn;
10023 drm_writeback_queue_job(wb_conn, new_con_state);
10024}
10025
10026/**
10027 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
10028 * @state: The atomic state to commit
10029 *
10030 * This will tell DC to commit the constructed DC state from atomic_check,
10031 * programming the hardware. Any failures here implies a hardware failure, since
10032 * atomic check should have filtered anything non-kosher.
10033 */
10034static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
10035{
10036 struct drm_device *dev = state->dev;
10037 struct amdgpu_device *adev = drm_to_adev(dev);
10038 struct amdgpu_display_manager *dm = &adev->dm;
10039 struct dm_atomic_state *dm_state;
10040 struct dc_state *dc_state = NULL;
10041 u32 i, j;
10042 struct drm_crtc *crtc;
10043 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10044 unsigned long flags;
10045 bool wait_for_vblank = true;
10046 struct drm_connector *connector;
10047 struct drm_connector_state *old_con_state, *new_con_state;
10048 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10049 int crtc_disable_count = 0;
10050
10051 trace_amdgpu_dm_atomic_commit_tail_begin(state);
10052
10053 drm_atomic_helper_update_legacy_modeset_state(dev, state);
10054 drm_dp_mst_atomic_wait_for_dependencies(state);
10055
10056 dm_state = dm_atomic_get_new_state(state);
10057 if (dm_state && dm_state->context) {
10058 dc_state = dm_state->context;
10059 amdgpu_dm_commit_streams(state, dc_state);
10060 }
10061
10062 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10063 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10064 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10065 struct amdgpu_dm_connector *aconnector;
10066
10067 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10068 continue;
10069
10070 aconnector = to_amdgpu_dm_connector(connector);
10071
10072 if (!adev->dm.hdcp_workqueue)
10073 continue;
10074
10075 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
10076
10077 if (!connector)
10078 continue;
10079
10080 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
10081 connector->index, connector->status, connector->dpms);
10082 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
10083 old_con_state->content_protection, new_con_state->content_protection);
10084
10085 if (aconnector->dc_sink) {
10086 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
10087 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
10088 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
10089 aconnector->dc_sink->edid_caps.display_name);
10090 }
10091 }
10092
10093 new_crtc_state = NULL;
10094 old_crtc_state = NULL;
10095
10096 if (acrtc) {
10097 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
10098 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
10099 }
10100
10101 if (old_crtc_state)
10102 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
10103 old_crtc_state->enable,
10104 old_crtc_state->active,
10105 old_crtc_state->mode_changed,
10106 old_crtc_state->active_changed,
10107 old_crtc_state->connectors_changed);
10108
10109 if (new_crtc_state)
10110 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
10111 new_crtc_state->enable,
10112 new_crtc_state->active,
10113 new_crtc_state->mode_changed,
10114 new_crtc_state->active_changed,
10115 new_crtc_state->connectors_changed);
10116 }
10117
10118 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10119 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10120 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10121 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
10122
10123 if (!adev->dm.hdcp_workqueue)
10124 continue;
10125
10126 new_crtc_state = NULL;
10127 old_crtc_state = NULL;
10128
10129 if (acrtc) {
10130 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
10131 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
10132 }
10133
10134 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10135
10136 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
10137 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
10138 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
10139 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
10140 dm_new_con_state->update_hdcp = true;
10141 continue;
10142 }
10143
10144 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
10145 old_con_state, connector, adev->dm.hdcp_workqueue)) {
10146 /* when display is unplugged from mst hub, connctor will
10147 * be destroyed within dm_dp_mst_connector_destroy. connector
10148 * hdcp perperties, like type, undesired, desired, enabled,
10149 * will be lost. So, save hdcp properties into hdcp_work within
10150 * amdgpu_dm_atomic_commit_tail. if the same display is
10151 * plugged back with same display index, its hdcp properties
10152 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
10153 */
10154
10155 bool enable_encryption = false;
10156
10157 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
10158 enable_encryption = true;
10159
10160 if (aconnector->dc_link && aconnector->dc_sink &&
10161 aconnector->dc_link->type == dc_connection_mst_branch) {
10162 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
10163 struct hdcp_workqueue *hdcp_w =
10164 &hdcp_work[aconnector->dc_link->link_index];
10165
10166 hdcp_w->hdcp_content_type[connector->index] =
10167 new_con_state->hdcp_content_type;
10168 hdcp_w->content_protection[connector->index] =
10169 new_con_state->content_protection;
10170 }
10171
10172 if (new_crtc_state && new_crtc_state->mode_changed &&
10173 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
10174 enable_encryption = true;
10175
10176 drm_info(adev_to_drm(adev), "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
10177
10178 if (aconnector->dc_link)
10179 hdcp_update_display(
10180 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
10181 new_con_state->hdcp_content_type, enable_encryption);
10182 }
10183 }
10184
10185 /* Handle connector state changes */
10186 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10187 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10188 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10189 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10190 struct dc_surface_update *dummy_updates;
10191 struct dc_stream_update stream_update;
10192 struct dc_info_packet hdr_packet;
10193 struct dc_stream_status *status = NULL;
10194 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false;
10195
10196 memset(&stream_update, 0, sizeof(stream_update));
10197
10198 if (acrtc) {
10199 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
10200 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
10201 }
10202
10203 /* Skip any modesets/resets */
10204 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
10205 continue;
10206
10207 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10208 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10209
10210 scaling_changed = is_scaling_state_different(dm_new_con_state,
10211 dm_old_con_state);
10212
10213 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) &&
10214 (dm_old_crtc_state->stream->output_color_space !=
10215 get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state)))
10216 output_color_space_changed = true;
10217
10218 abm_changed = dm_new_crtc_state->abm_level !=
10219 dm_old_crtc_state->abm_level;
10220
10221 hdr_changed =
10222 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
10223
10224 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed)
10225 continue;
10226
10227 stream_update.stream = dm_new_crtc_state->stream;
10228 if (scaling_changed) {
10229 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
10230 dm_new_con_state, dm_new_crtc_state->stream);
10231
10232 stream_update.src = dm_new_crtc_state->stream->src;
10233 stream_update.dst = dm_new_crtc_state->stream->dst;
10234 }
10235
10236 if (output_color_space_changed) {
10237 dm_new_crtc_state->stream->output_color_space
10238 = get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state);
10239
10240 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space;
10241 }
10242
10243 if (abm_changed) {
10244 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
10245
10246 stream_update.abm_level = &dm_new_crtc_state->abm_level;
10247 }
10248
10249 if (hdr_changed) {
10250 fill_hdr_info_packet(new_con_state, &hdr_packet);
10251 stream_update.hdr_static_metadata = &hdr_packet;
10252 }
10253
10254 status = dc_stream_get_status(dm_new_crtc_state->stream);
10255
10256 if (WARN_ON(!status))
10257 continue;
10258
10259 WARN_ON(!status->plane_count);
10260
10261 /*
10262 * TODO: DC refuses to perform stream updates without a dc_surface_update.
10263 * Here we create an empty update on each plane.
10264 * To fix this, DC should permit updating only stream properties.
10265 */
10266 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
10267 if (!dummy_updates) {
10268 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n");
10269 continue;
10270 }
10271 for (j = 0; j < status->plane_count; j++)
10272 dummy_updates[j].surface = status->plane_states[0];
10273
10274 sort(dummy_updates, status->plane_count,
10275 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
10276
10277 mutex_lock(&dm->dc_lock);
10278 dc_exit_ips_for_hw_access(dm->dc);
10279 dc_update_planes_and_stream(dm->dc,
10280 dummy_updates,
10281 status->plane_count,
10282 dm_new_crtc_state->stream,
10283 &stream_update);
10284 mutex_unlock(&dm->dc_lock);
10285 kfree(dummy_updates);
10286 }
10287
10288 /**
10289 * Enable interrupts for CRTCs that are newly enabled or went through
10290 * a modeset. It was intentionally deferred until after the front end
10291 * state was modified to wait until the OTG was on and so the IRQ
10292 * handlers didn't access stale or invalid state.
10293 */
10294 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10295 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
10296#ifdef CONFIG_DEBUG_FS
10297 enum amdgpu_dm_pipe_crc_source cur_crc_src;
10298#endif
10299 /* Count number of newly disabled CRTCs for dropping PM refs later. */
10300 if (old_crtc_state->active && !new_crtc_state->active)
10301 crtc_disable_count++;
10302
10303 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10304 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10305
10306 /* For freesync config update on crtc state and params for irq */
10307 update_stream_irq_parameters(dm, dm_new_crtc_state);
10308
10309#ifdef CONFIG_DEBUG_FS
10310 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
10311 cur_crc_src = acrtc->dm_irq_params.crc_src;
10312 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10313#endif
10314
10315 if (new_crtc_state->active &&
10316 (!old_crtc_state->active ||
10317 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
10318 dc_stream_retain(dm_new_crtc_state->stream);
10319 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
10320 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state);
10321 }
10322 /* Handle vrr on->off / off->on transitions */
10323 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
10324
10325#ifdef CONFIG_DEBUG_FS
10326 if (new_crtc_state->active &&
10327 (!old_crtc_state->active ||
10328 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
10329 /**
10330 * Frontend may have changed so reapply the CRC capture
10331 * settings for the stream.
10332 */
10333 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
10334#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
10335 if (amdgpu_dm_crc_window_is_activated(crtc)) {
10336 uint8_t cnt;
10337 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
10338 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) {
10339 if (acrtc->dm_irq_params.window_param[cnt].enable) {
10340 acrtc->dm_irq_params.window_param[cnt].update_win = true;
10341
10342 /**
10343 * It takes 2 frames for HW to stably generate CRC when
10344 * resuming from suspend, so we set skip_frame_cnt 2.
10345 */
10346 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2;
10347 }
10348 }
10349 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10350 }
10351#endif
10352 if (amdgpu_dm_crtc_configure_crc_source(
10353 crtc, dm_new_crtc_state, cur_crc_src))
10354 drm_dbg_atomic(dev, "Failed to configure crc source");
10355 }
10356 }
10357#endif
10358 }
10359
10360 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
10361 if (new_crtc_state->async_flip)
10362 wait_for_vblank = false;
10363
10364 /* update planes when needed per crtc*/
10365 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
10366 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10367
10368 if (dm_new_crtc_state->stream)
10369 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
10370 }
10371
10372 /* Enable writeback */
10373 for_each_new_connector_in_state(state, connector, new_con_state, i) {
10374 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10375 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10376
10377 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
10378 continue;
10379
10380 if (!new_con_state->writeback_job)
10381 continue;
10382
10383 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
10384
10385 if (!new_crtc_state)
10386 continue;
10387
10388 if (acrtc->wb_enabled)
10389 continue;
10390
10391 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10392
10393 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
10394 acrtc->wb_enabled = true;
10395 }
10396
10397 /* Update audio instances for each connector. */
10398 amdgpu_dm_commit_audio(dev, state);
10399
10400 /* restore the backlight level */
10401 for (i = 0; i < dm->num_of_edps; i++) {
10402 if (dm->backlight_dev[i] &&
10403 (dm->actual_brightness[i] != dm->brightness[i]))
10404 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
10405 }
10406
10407 /*
10408 * send vblank event on all events not handled in flip and
10409 * mark consumed event for drm_atomic_helper_commit_hw_done
10410 */
10411 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
10412 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10413
10414 if (new_crtc_state->event)
10415 drm_send_event_locked(dev, &new_crtc_state->event->base);
10416
10417 new_crtc_state->event = NULL;
10418 }
10419 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10420
10421 /* Signal HW programming completion */
10422 drm_atomic_helper_commit_hw_done(state);
10423
10424 if (wait_for_vblank)
10425 drm_atomic_helper_wait_for_flip_done(dev, state);
10426
10427 drm_atomic_helper_cleanup_planes(dev, state);
10428
10429 /* Don't free the memory if we are hitting this as part of suspend.
10430 * This way we don't free any memory during suspend; see
10431 * amdgpu_bo_free_kernel(). The memory will be freed in the first
10432 * non-suspend modeset or when the driver is torn down.
10433 */
10434 if (!adev->in_suspend) {
10435 /* return the stolen vga memory back to VRAM */
10436 if (!adev->mman.keep_stolen_vga_memory)
10437 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
10438 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
10439 }
10440
10441 /*
10442 * Finally, drop a runtime PM reference for each newly disabled CRTC,
10443 * so we can put the GPU into runtime suspend if we're not driving any
10444 * displays anymore
10445 */
10446 for (i = 0; i < crtc_disable_count; i++)
10447 pm_runtime_put_autosuspend(dev->dev);
10448 pm_runtime_mark_last_busy(dev->dev);
10449
10450 trace_amdgpu_dm_atomic_commit_tail_finish(state);
10451}
10452
10453static int dm_force_atomic_commit(struct drm_connector *connector)
10454{
10455 int ret = 0;
10456 struct drm_device *ddev = connector->dev;
10457 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
10458 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
10459 struct drm_plane *plane = disconnected_acrtc->base.primary;
10460 struct drm_connector_state *conn_state;
10461 struct drm_crtc_state *crtc_state;
10462 struct drm_plane_state *plane_state;
10463
10464 if (!state)
10465 return -ENOMEM;
10466
10467 state->acquire_ctx = ddev->mode_config.acquire_ctx;
10468
10469 /* Construct an atomic state to restore previous display setting */
10470
10471 /*
10472 * Attach connectors to drm_atomic_state
10473 */
10474 conn_state = drm_atomic_get_connector_state(state, connector);
10475
10476 /* Check for error in getting connector state */
10477 if (IS_ERR(conn_state)) {
10478 ret = PTR_ERR(conn_state);
10479 goto out;
10480 }
10481
10482 /* Attach crtc to drm_atomic_state*/
10483 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
10484
10485 /* Check for error in getting crtc state */
10486 if (IS_ERR(crtc_state)) {
10487 ret = PTR_ERR(crtc_state);
10488 goto out;
10489 }
10490
10491 /* force a restore */
10492 crtc_state->mode_changed = true;
10493
10494 /* Attach plane to drm_atomic_state */
10495 plane_state = drm_atomic_get_plane_state(state, plane);
10496
10497 /* Check for error in getting plane state */
10498 if (IS_ERR(plane_state)) {
10499 ret = PTR_ERR(plane_state);
10500 goto out;
10501 }
10502
10503 /* Call commit internally with the state we just constructed */
10504 ret = drm_atomic_commit(state);
10505
10506out:
10507 drm_atomic_state_put(state);
10508 if (ret)
10509 drm_err(ddev, "Restoring old state failed with %i\n", ret);
10510
10511 return ret;
10512}
10513
10514/*
10515 * This function handles all cases when set mode does not come upon hotplug.
10516 * This includes when a display is unplugged then plugged back into the
10517 * same port and when running without usermode desktop manager supprot
10518 */
10519void dm_restore_drm_connector_state(struct drm_device *dev,
10520 struct drm_connector *connector)
10521{
10522 struct amdgpu_dm_connector *aconnector;
10523 struct amdgpu_crtc *disconnected_acrtc;
10524 struct dm_crtc_state *acrtc_state;
10525
10526 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10527 return;
10528
10529 aconnector = to_amdgpu_dm_connector(connector);
10530
10531 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
10532 return;
10533
10534 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
10535 if (!disconnected_acrtc)
10536 return;
10537
10538 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
10539 if (!acrtc_state->stream)
10540 return;
10541
10542 /*
10543 * If the previous sink is not released and different from the current,
10544 * we deduce we are in a state where we can not rely on usermode call
10545 * to turn on the display, so we do it here
10546 */
10547 if (acrtc_state->stream->sink != aconnector->dc_sink)
10548 dm_force_atomic_commit(&aconnector->base);
10549}
10550
10551/*
10552 * Grabs all modesetting locks to serialize against any blocking commits,
10553 * Waits for completion of all non blocking commits.
10554 */
10555static int do_aquire_global_lock(struct drm_device *dev,
10556 struct drm_atomic_state *state)
10557{
10558 struct drm_crtc *crtc;
10559 struct drm_crtc_commit *commit;
10560 long ret;
10561
10562 /*
10563 * Adding all modeset locks to aquire_ctx will
10564 * ensure that when the framework release it the
10565 * extra locks we are locking here will get released to
10566 */
10567 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
10568 if (ret)
10569 return ret;
10570
10571 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10572 spin_lock(&crtc->commit_lock);
10573 commit = list_first_entry_or_null(&crtc->commit_list,
10574 struct drm_crtc_commit, commit_entry);
10575 if (commit)
10576 drm_crtc_commit_get(commit);
10577 spin_unlock(&crtc->commit_lock);
10578
10579 if (!commit)
10580 continue;
10581
10582 /*
10583 * Make sure all pending HW programming completed and
10584 * page flips done
10585 */
10586 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
10587
10588 if (ret > 0)
10589 ret = wait_for_completion_interruptible_timeout(
10590 &commit->flip_done, 10*HZ);
10591
10592 if (ret == 0)
10593 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n",
10594 crtc->base.id, crtc->name);
10595
10596 drm_crtc_commit_put(commit);
10597 }
10598
10599 return ret < 0 ? ret : 0;
10600}
10601
10602static void get_freesync_config_for_crtc(
10603 struct dm_crtc_state *new_crtc_state,
10604 struct dm_connector_state *new_con_state)
10605{
10606 struct mod_freesync_config config = {0};
10607 struct amdgpu_dm_connector *aconnector;
10608 struct drm_display_mode *mode = &new_crtc_state->base.mode;
10609 int vrefresh = drm_mode_vrefresh(mode);
10610 bool fs_vid_mode = false;
10611
10612 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10613 return;
10614
10615 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);
10616
10617 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
10618 vrefresh >= aconnector->min_vfreq &&
10619 vrefresh <= aconnector->max_vfreq;
10620
10621 if (new_crtc_state->vrr_supported) {
10622 new_crtc_state->stream->ignore_msa_timing_param = true;
10623 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
10624
10625 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
10626 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
10627 config.vsif_supported = true;
10628 config.btr = true;
10629
10630 if (fs_vid_mode) {
10631 config.state = VRR_STATE_ACTIVE_FIXED;
10632 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
10633 goto out;
10634 } else if (new_crtc_state->base.vrr_enabled) {
10635 config.state = VRR_STATE_ACTIVE_VARIABLE;
10636 } else {
10637 config.state = VRR_STATE_INACTIVE;
10638 }
10639 }
10640out:
10641 new_crtc_state->freesync_config = config;
10642}
10643
10644static void reset_freesync_config_for_crtc(
10645 struct dm_crtc_state *new_crtc_state)
10646{
10647 new_crtc_state->vrr_supported = false;
10648
10649 memset(&new_crtc_state->vrr_infopacket, 0,
10650 sizeof(new_crtc_state->vrr_infopacket));
10651}
10652
10653static bool
10654is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
10655 struct drm_crtc_state *new_crtc_state)
10656{
10657 const struct drm_display_mode *old_mode, *new_mode;
10658
10659 if (!old_crtc_state || !new_crtc_state)
10660 return false;
10661
10662 old_mode = &old_crtc_state->mode;
10663 new_mode = &new_crtc_state->mode;
10664
10665 if (old_mode->clock == new_mode->clock &&
10666 old_mode->hdisplay == new_mode->hdisplay &&
10667 old_mode->vdisplay == new_mode->vdisplay &&
10668 old_mode->htotal == new_mode->htotal &&
10669 old_mode->vtotal != new_mode->vtotal &&
10670 old_mode->hsync_start == new_mode->hsync_start &&
10671 old_mode->vsync_start != new_mode->vsync_start &&
10672 old_mode->hsync_end == new_mode->hsync_end &&
10673 old_mode->vsync_end != new_mode->vsync_end &&
10674 old_mode->hskew == new_mode->hskew &&
10675 old_mode->vscan == new_mode->vscan &&
10676 (old_mode->vsync_end - old_mode->vsync_start) ==
10677 (new_mode->vsync_end - new_mode->vsync_start))
10678 return true;
10679
10680 return false;
10681}
10682
10683static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
10684{
10685 u64 num, den, res;
10686 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
10687
10688 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
10689
10690 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
10691 den = (unsigned long long)new_crtc_state->mode.htotal *
10692 (unsigned long long)new_crtc_state->mode.vtotal;
10693
10694 res = div_u64(num, den);
10695 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
10696}
10697
10698static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
10699 struct drm_atomic_state *state,
10700 struct drm_crtc *crtc,
10701 struct drm_crtc_state *old_crtc_state,
10702 struct drm_crtc_state *new_crtc_state,
10703 bool enable,
10704 bool *lock_and_validation_needed)
10705{
10706 struct dm_atomic_state *dm_state = NULL;
10707 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10708 struct dc_stream_state *new_stream;
10709 struct amdgpu_device *adev = dm->adev;
10710 int ret = 0;
10711
10712 /*
10713 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
10714 * update changed items
10715 */
10716 struct amdgpu_crtc *acrtc = NULL;
10717 struct drm_connector *connector = NULL;
10718 struct amdgpu_dm_connector *aconnector = NULL;
10719 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
10720 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
10721
10722 new_stream = NULL;
10723
10724 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10725 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10726 acrtc = to_amdgpu_crtc(crtc);
10727 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
10728 if (connector)
10729 aconnector = to_amdgpu_dm_connector(connector);
10730
10731 /* TODO This hack should go away */
10732 if (connector && enable) {
10733 /* Make sure fake sink is created in plug-in scenario */
10734 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
10735 connector);
10736 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
10737 connector);
10738
10739 if (WARN_ON(!drm_new_conn_state)) {
10740 ret = -EINVAL;
10741 goto fail;
10742 }
10743
10744 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
10745 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
10746
10747 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
10748 goto skip_modeset;
10749
10750 new_stream = create_validate_stream_for_sink(connector,
10751 &new_crtc_state->mode,
10752 dm_new_conn_state,
10753 dm_old_crtc_state->stream);
10754
10755 /*
10756 * we can have no stream on ACTION_SET if a display
10757 * was disconnected during S3, in this case it is not an
10758 * error, the OS will be updated after detection, and
10759 * will do the right thing on next atomic commit
10760 */
10761
10762 if (!new_stream) {
10763 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n",
10764 __func__, acrtc->base.base.id);
10765 ret = -ENOMEM;
10766 goto fail;
10767 }
10768
10769 /*
10770 * TODO: Check VSDB bits to decide whether this should
10771 * be enabled or not.
10772 */
10773 new_stream->triggered_crtc_reset.enabled =
10774 dm->force_timing_sync;
10775
10776 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
10777
10778 ret = fill_hdr_info_packet(drm_new_conn_state,
10779 &new_stream->hdr_static_metadata);
10780 if (ret)
10781 goto fail;
10782
10783 /*
10784 * If we already removed the old stream from the context
10785 * (and set the new stream to NULL) then we can't reuse
10786 * the old stream even if the stream and scaling are unchanged.
10787 * We'll hit the BUG_ON and black screen.
10788 *
10789 * TODO: Refactor this function to allow this check to work
10790 * in all conditions.
10791 */
10792 if (amdgpu_freesync_vid_mode &&
10793 dm_new_crtc_state->stream &&
10794 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
10795 goto skip_modeset;
10796
10797 if (dm_new_crtc_state->stream &&
10798 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
10799 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
10800 new_crtc_state->mode_changed = false;
10801 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d",
10802 new_crtc_state->mode_changed);
10803 }
10804 }
10805
10806 /* mode_changed flag may get updated above, need to check again */
10807 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
10808 goto skip_modeset;
10809
10810 drm_dbg_state(state->dev,
10811 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
10812 acrtc->crtc_id,
10813 new_crtc_state->enable,
10814 new_crtc_state->active,
10815 new_crtc_state->planes_changed,
10816 new_crtc_state->mode_changed,
10817 new_crtc_state->active_changed,
10818 new_crtc_state->connectors_changed);
10819
10820 /* Remove stream for any changed/disabled CRTC */
10821 if (!enable) {
10822
10823 if (!dm_old_crtc_state->stream)
10824 goto skip_modeset;
10825
10826 /* Unset freesync video if it was active before */
10827 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
10828 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
10829 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
10830 }
10831
10832 /* Now check if we should set freesync video mode */
10833 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
10834 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
10835 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
10836 is_timing_unchanged_for_freesync(new_crtc_state,
10837 old_crtc_state)) {
10838 new_crtc_state->mode_changed = false;
10839 drm_dbg_driver(adev_to_drm(adev),
10840 "Mode change not required for front porch change, setting mode_changed to %d",
10841 new_crtc_state->mode_changed);
10842
10843 set_freesync_fixed_config(dm_new_crtc_state);
10844
10845 goto skip_modeset;
10846 } else if (amdgpu_freesync_vid_mode && aconnector &&
10847 is_freesync_video_mode(&new_crtc_state->mode,
10848 aconnector)) {
10849 struct drm_display_mode *high_mode;
10850
10851 high_mode = get_highest_refresh_rate_mode(aconnector, false);
10852 if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
10853 set_freesync_fixed_config(dm_new_crtc_state);
10854 }
10855
10856 ret = dm_atomic_get_state(state, &dm_state);
10857 if (ret)
10858 goto fail;
10859
10860 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n",
10861 crtc->base.id);
10862
10863 /* i.e. reset mode */
10864 if (dc_state_remove_stream(
10865 dm->dc,
10866 dm_state->context,
10867 dm_old_crtc_state->stream) != DC_OK) {
10868 ret = -EINVAL;
10869 goto fail;
10870 }
10871
10872 dc_stream_release(dm_old_crtc_state->stream);
10873 dm_new_crtc_state->stream = NULL;
10874
10875 reset_freesync_config_for_crtc(dm_new_crtc_state);
10876
10877 *lock_and_validation_needed = true;
10878
10879 } else {/* Add stream for any updated/enabled CRTC */
10880 /*
10881 * Quick fix to prevent NULL pointer on new_stream when
10882 * added MST connectors not found in existing crtc_state in the chained mode
10883 * TODO: need to dig out the root cause of that
10884 */
10885 if (!connector)
10886 goto skip_modeset;
10887
10888 if (modereset_required(new_crtc_state))
10889 goto skip_modeset;
10890
10891 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
10892 dm_old_crtc_state->stream)) {
10893
10894 WARN_ON(dm_new_crtc_state->stream);
10895
10896 ret = dm_atomic_get_state(state, &dm_state);
10897 if (ret)
10898 goto fail;
10899
10900 dm_new_crtc_state->stream = new_stream;
10901
10902 dc_stream_retain(new_stream);
10903
10904 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
10905 crtc->base.id);
10906
10907 if (dc_state_add_stream(
10908 dm->dc,
10909 dm_state->context,
10910 dm_new_crtc_state->stream) != DC_OK) {
10911 ret = -EINVAL;
10912 goto fail;
10913 }
10914
10915 *lock_and_validation_needed = true;
10916 }
10917 }
10918
10919skip_modeset:
10920 /* Release extra reference */
10921 if (new_stream)
10922 dc_stream_release(new_stream);
10923
10924 /*
10925 * We want to do dc stream updates that do not require a
10926 * full modeset below.
10927 */
10928 if (!(enable && connector && new_crtc_state->active))
10929 return 0;
10930 /*
10931 * Given above conditions, the dc state cannot be NULL because:
10932 * 1. We're in the process of enabling CRTCs (just been added
10933 * to the dc context, or already is on the context)
10934 * 2. Has a valid connector attached, and
10935 * 3. Is currently active and enabled.
10936 * => The dc stream state currently exists.
10937 */
10938 BUG_ON(dm_new_crtc_state->stream == NULL);
10939
10940 /* Scaling or underscan settings */
10941 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
10942 drm_atomic_crtc_needs_modeset(new_crtc_state))
10943 update_stream_scaling_settings(
10944 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
10945
10946 /* ABM settings */
10947 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
10948
10949 /*
10950 * Color management settings. We also update color properties
10951 * when a modeset is needed, to ensure it gets reprogrammed.
10952 */
10953 if (dm_new_crtc_state->base.color_mgmt_changed ||
10954 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf ||
10955 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10956 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
10957 if (ret)
10958 goto fail;
10959 }
10960
10961 /* Update Freesync settings. */
10962 get_freesync_config_for_crtc(dm_new_crtc_state,
10963 dm_new_conn_state);
10964
10965 return ret;
10966
10967fail:
10968 if (new_stream)
10969 dc_stream_release(new_stream);
10970 return ret;
10971}
10972
10973static bool should_reset_plane(struct drm_atomic_state *state,
10974 struct drm_plane *plane,
10975 struct drm_plane_state *old_plane_state,
10976 struct drm_plane_state *new_plane_state)
10977{
10978 struct drm_plane *other;
10979 struct drm_plane_state *old_other_state, *new_other_state;
10980 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10981 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state;
10982 struct amdgpu_device *adev = drm_to_adev(plane->dev);
10983 int i;
10984
10985 /*
10986 * TODO: Remove this hack for all asics once it proves that the
10987 * fast updates works fine on DCN3.2+.
10988 */
10989 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) &&
10990 state->allow_modeset)
10991 return true;
10992
10993 if (amdgpu_in_reset(adev) && state->allow_modeset)
10994 return true;
10995
10996 /* Exit early if we know that we're adding or removing the plane. */
10997 if (old_plane_state->crtc != new_plane_state->crtc)
10998 return true;
10999
11000 /* old crtc == new_crtc == NULL, plane not in context. */
11001 if (!new_plane_state->crtc)
11002 return false;
11003
11004 new_crtc_state =
11005 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
11006 old_crtc_state =
11007 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc);
11008
11009 if (!new_crtc_state)
11010 return true;
11011
11012 /*
11013 * A change in cursor mode means a new dc pipe needs to be acquired or
11014 * released from the state
11015 */
11016 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
11017 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
11018 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11019 old_dm_crtc_state != NULL &&
11020 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) {
11021 return true;
11022 }
11023
11024 /* CRTC Degamma changes currently require us to recreate planes. */
11025 if (new_crtc_state->color_mgmt_changed)
11026 return true;
11027
11028 /*
11029 * On zpos change, planes need to be reordered by removing and re-adding
11030 * them one by one to the dc state, in order of descending zpos.
11031 *
11032 * TODO: We can likely skip bandwidth validation if the only thing that
11033 * changed about the plane was it'z z-ordering.
11034 */
11035 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos)
11036 return true;
11037
11038 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
11039 return true;
11040
11041 /*
11042 * If there are any new primary or overlay planes being added or
11043 * removed then the z-order can potentially change. To ensure
11044 * correct z-order and pipe acquisition the current DC architecture
11045 * requires us to remove and recreate all existing planes.
11046 *
11047 * TODO: Come up with a more elegant solution for this.
11048 */
11049 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
11050 struct amdgpu_framebuffer *old_afb, *new_afb;
11051 struct dm_plane_state *dm_new_other_state, *dm_old_other_state;
11052
11053 dm_new_other_state = to_dm_plane_state(new_other_state);
11054 dm_old_other_state = to_dm_plane_state(old_other_state);
11055
11056 if (other->type == DRM_PLANE_TYPE_CURSOR)
11057 continue;
11058
11059 if (old_other_state->crtc != new_plane_state->crtc &&
11060 new_other_state->crtc != new_plane_state->crtc)
11061 continue;
11062
11063 if (old_other_state->crtc != new_other_state->crtc)
11064 return true;
11065
11066 /* Src/dst size and scaling updates. */
11067 if (old_other_state->src_w != new_other_state->src_w ||
11068 old_other_state->src_h != new_other_state->src_h ||
11069 old_other_state->crtc_w != new_other_state->crtc_w ||
11070 old_other_state->crtc_h != new_other_state->crtc_h)
11071 return true;
11072
11073 /* Rotation / mirroring updates. */
11074 if (old_other_state->rotation != new_other_state->rotation)
11075 return true;
11076
11077 /* Blending updates. */
11078 if (old_other_state->pixel_blend_mode !=
11079 new_other_state->pixel_blend_mode)
11080 return true;
11081
11082 /* Alpha updates. */
11083 if (old_other_state->alpha != new_other_state->alpha)
11084 return true;
11085
11086 /* Colorspace changes. */
11087 if (old_other_state->color_range != new_other_state->color_range ||
11088 old_other_state->color_encoding != new_other_state->color_encoding)
11089 return true;
11090
11091 /* HDR/Transfer Function changes. */
11092 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf ||
11093 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut ||
11094 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult ||
11095 dm_old_other_state->ctm != dm_new_other_state->ctm ||
11096 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut ||
11097 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf ||
11098 dm_old_other_state->lut3d != dm_new_other_state->lut3d ||
11099 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut ||
11100 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf)
11101 return true;
11102
11103 /* Framebuffer checks fall at the end. */
11104 if (!old_other_state->fb || !new_other_state->fb)
11105 continue;
11106
11107 /* Pixel format changes can require bandwidth updates. */
11108 if (old_other_state->fb->format != new_other_state->fb->format)
11109 return true;
11110
11111 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
11112 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
11113
11114 /* Tiling and DCC changes also require bandwidth updates. */
11115 if (old_afb->tiling_flags != new_afb->tiling_flags ||
11116 old_afb->base.modifier != new_afb->base.modifier)
11117 return true;
11118 }
11119
11120 return false;
11121}
11122
11123static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
11124 struct drm_plane_state *new_plane_state,
11125 struct drm_framebuffer *fb)
11126{
11127 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
11128 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
11129 unsigned int pitch;
11130 bool linear;
11131
11132 if (fb->width > new_acrtc->max_cursor_width ||
11133 fb->height > new_acrtc->max_cursor_height) {
11134 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
11135 new_plane_state->fb->width,
11136 new_plane_state->fb->height);
11137 return -EINVAL;
11138 }
11139 if (new_plane_state->src_w != fb->width << 16 ||
11140 new_plane_state->src_h != fb->height << 16) {
11141 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
11142 return -EINVAL;
11143 }
11144
11145 /* Pitch in pixels */
11146 pitch = fb->pitches[0] / fb->format->cpp[0];
11147
11148 if (fb->width != pitch) {
11149 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
11150 fb->width, pitch);
11151 return -EINVAL;
11152 }
11153
11154 switch (pitch) {
11155 case 64:
11156 case 128:
11157 case 256:
11158 /* FB pitch is supported by cursor plane */
11159 break;
11160 default:
11161 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
11162 return -EINVAL;
11163 }
11164
11165 /* Core DRM takes care of checking FB modifiers, so we only need to
11166 * check tiling flags when the FB doesn't have a modifier.
11167 */
11168 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
11169 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) {
11170 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0;
11171 } else if (adev->family >= AMDGPU_FAMILY_AI) {
11172 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
11173 } else {
11174 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
11175 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
11176 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
11177 }
11178 if (!linear) {
11179 DRM_DEBUG_ATOMIC("Cursor FB not linear");
11180 return -EINVAL;
11181 }
11182 }
11183
11184 return 0;
11185}
11186
11187/*
11188 * Helper function for checking the cursor in native mode
11189 */
11190static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc,
11191 struct drm_plane *plane,
11192 struct drm_plane_state *new_plane_state,
11193 bool enable)
11194{
11195
11196 struct amdgpu_crtc *new_acrtc;
11197 int ret;
11198
11199 if (!enable || !new_plane_crtc ||
11200 drm_atomic_plane_disabling(plane->state, new_plane_state))
11201 return 0;
11202
11203 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
11204
11205 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
11206 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
11207 return -EINVAL;
11208 }
11209
11210 if (new_plane_state->fb) {
11211 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
11212 new_plane_state->fb);
11213 if (ret)
11214 return ret;
11215 }
11216
11217 return 0;
11218}
11219
11220static bool dm_should_update_native_cursor(struct drm_atomic_state *state,
11221 struct drm_crtc *old_plane_crtc,
11222 struct drm_crtc *new_plane_crtc,
11223 bool enable)
11224{
11225 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11226 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
11227
11228 if (!enable) {
11229 if (old_plane_crtc == NULL)
11230 return true;
11231
11232 old_crtc_state = drm_atomic_get_old_crtc_state(
11233 state, old_plane_crtc);
11234 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
11235
11236 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;
11237 } else {
11238 if (new_plane_crtc == NULL)
11239 return true;
11240
11241 new_crtc_state = drm_atomic_get_new_crtc_state(
11242 state, new_plane_crtc);
11243 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11244
11245 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;
11246 }
11247}
11248
11249static int dm_update_plane_state(struct dc *dc,
11250 struct drm_atomic_state *state,
11251 struct drm_plane *plane,
11252 struct drm_plane_state *old_plane_state,
11253 struct drm_plane_state *new_plane_state,
11254 bool enable,
11255 bool *lock_and_validation_needed,
11256 bool *is_top_most_overlay)
11257{
11258
11259 struct dm_atomic_state *dm_state = NULL;
11260 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
11261 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11262 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
11263 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
11264 bool needs_reset, update_native_cursor;
11265 int ret = 0;
11266
11267
11268 new_plane_crtc = new_plane_state->crtc;
11269 old_plane_crtc = old_plane_state->crtc;
11270 dm_new_plane_state = to_dm_plane_state(new_plane_state);
11271 dm_old_plane_state = to_dm_plane_state(old_plane_state);
11272
11273 update_native_cursor = dm_should_update_native_cursor(state,
11274 old_plane_crtc,
11275 new_plane_crtc,
11276 enable);
11277
11278 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) {
11279 ret = dm_check_native_cursor_state(new_plane_crtc, plane,
11280 new_plane_state, enable);
11281 if (ret)
11282 return ret;
11283
11284 return 0;
11285 }
11286
11287 needs_reset = should_reset_plane(state, plane, old_plane_state,
11288 new_plane_state);
11289
11290 /* Remove any changed/removed planes */
11291 if (!enable) {
11292 if (!needs_reset)
11293 return 0;
11294
11295 if (!old_plane_crtc)
11296 return 0;
11297
11298 old_crtc_state = drm_atomic_get_old_crtc_state(
11299 state, old_plane_crtc);
11300 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
11301
11302 if (!dm_old_crtc_state->stream)
11303 return 0;
11304
11305 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
11306 plane->base.id, old_plane_crtc->base.id);
11307
11308 ret = dm_atomic_get_state(state, &dm_state);
11309 if (ret)
11310 return ret;
11311
11312 if (!dc_state_remove_plane(
11313 dc,
11314 dm_old_crtc_state->stream,
11315 dm_old_plane_state->dc_state,
11316 dm_state->context)) {
11317
11318 return -EINVAL;
11319 }
11320
11321 if (dm_old_plane_state->dc_state)
11322 dc_plane_state_release(dm_old_plane_state->dc_state);
11323
11324 dm_new_plane_state->dc_state = NULL;
11325
11326 *lock_and_validation_needed = true;
11327
11328 } else { /* Add new planes */
11329 struct dc_plane_state *dc_new_plane_state;
11330
11331 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
11332 return 0;
11333
11334 if (!new_plane_crtc)
11335 return 0;
11336
11337 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
11338 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11339
11340 if (!dm_new_crtc_state->stream)
11341 return 0;
11342
11343 if (!needs_reset)
11344 return 0;
11345
11346 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
11347 if (ret)
11348 goto out;
11349
11350 WARN_ON(dm_new_plane_state->dc_state);
11351
11352 dc_new_plane_state = dc_create_plane_state(dc);
11353 if (!dc_new_plane_state) {
11354 ret = -ENOMEM;
11355 goto out;
11356 }
11357
11358 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
11359 plane->base.id, new_plane_crtc->base.id);
11360
11361 ret = fill_dc_plane_attributes(
11362 drm_to_adev(new_plane_crtc->dev),
11363 dc_new_plane_state,
11364 new_plane_state,
11365 new_crtc_state);
11366 if (ret) {
11367 dc_plane_state_release(dc_new_plane_state);
11368 goto out;
11369 }
11370
11371 ret = dm_atomic_get_state(state, &dm_state);
11372 if (ret) {
11373 dc_plane_state_release(dc_new_plane_state);
11374 goto out;
11375 }
11376
11377 /*
11378 * Any atomic check errors that occur after this will
11379 * not need a release. The plane state will be attached
11380 * to the stream, and therefore part of the atomic
11381 * state. It'll be released when the atomic state is
11382 * cleaned.
11383 */
11384 if (!dc_state_add_plane(
11385 dc,
11386 dm_new_crtc_state->stream,
11387 dc_new_plane_state,
11388 dm_state->context)) {
11389
11390 dc_plane_state_release(dc_new_plane_state);
11391 ret = -EINVAL;
11392 goto out;
11393 }
11394
11395 dm_new_plane_state->dc_state = dc_new_plane_state;
11396
11397 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
11398
11399 /* Tell DC to do a full surface update every time there
11400 * is a plane change. Inefficient, but works for now.
11401 */
11402 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
11403
11404 *lock_and_validation_needed = true;
11405 }
11406
11407out:
11408 /* If enabling cursor overlay failed, attempt fallback to native mode */
11409 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) {
11410 ret = dm_check_native_cursor_state(new_plane_crtc, plane,
11411 new_plane_state, enable);
11412 if (ret)
11413 return ret;
11414
11415 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE;
11416 }
11417
11418 return ret;
11419}
11420
11421static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
11422 int *src_w, int *src_h)
11423{
11424 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
11425 case DRM_MODE_ROTATE_90:
11426 case DRM_MODE_ROTATE_270:
11427 *src_w = plane_state->src_h >> 16;
11428 *src_h = plane_state->src_w >> 16;
11429 break;
11430 case DRM_MODE_ROTATE_0:
11431 case DRM_MODE_ROTATE_180:
11432 default:
11433 *src_w = plane_state->src_w >> 16;
11434 *src_h = plane_state->src_h >> 16;
11435 break;
11436 }
11437}
11438
11439static void
11440dm_get_plane_scale(struct drm_plane_state *plane_state,
11441 int *out_plane_scale_w, int *out_plane_scale_h)
11442{
11443 int plane_src_w, plane_src_h;
11444
11445 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
11446 *out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0;
11447 *out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0;
11448}
11449
11450/*
11451 * The normalized_zpos value cannot be used by this iterator directly. It's only
11452 * calculated for enabled planes, potentially causing normalized_zpos collisions
11453 * between enabled/disabled planes in the atomic state. We need a unique value
11454 * so that the iterator will not generate the same object twice, or loop
11455 * indefinitely.
11456 */
11457static inline struct __drm_planes_state *__get_next_zpos(
11458 struct drm_atomic_state *state,
11459 struct __drm_planes_state *prev)
11460{
11461 unsigned int highest_zpos = 0, prev_zpos = 256;
11462 uint32_t highest_id = 0, prev_id = UINT_MAX;
11463 struct drm_plane_state *new_plane_state;
11464 struct drm_plane *plane;
11465 int i, highest_i = -1;
11466
11467 if (prev != NULL) {
11468 prev_zpos = prev->new_state->zpos;
11469 prev_id = prev->ptr->base.id;
11470 }
11471
11472 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
11473 /* Skip planes with higher zpos than the previously returned */
11474 if (new_plane_state->zpos > prev_zpos ||
11475 (new_plane_state->zpos == prev_zpos &&
11476 plane->base.id >= prev_id))
11477 continue;
11478
11479 /* Save the index of the plane with highest zpos */
11480 if (new_plane_state->zpos > highest_zpos ||
11481 (new_plane_state->zpos == highest_zpos &&
11482 plane->base.id > highest_id)) {
11483 highest_zpos = new_plane_state->zpos;
11484 highest_id = plane->base.id;
11485 highest_i = i;
11486 }
11487 }
11488
11489 if (highest_i < 0)
11490 return NULL;
11491
11492 return &state->planes[highest_i];
11493}
11494
11495/*
11496 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate
11497 * by descending zpos, as read from the new plane state. This is the same
11498 * ordering as defined by drm_atomic_normalize_zpos().
11499 */
11500#define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \
11501 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \
11502 __i != NULL; __i = __get_next_zpos((__state), __i)) \
11503 for_each_if(((plane) = __i->ptr, \
11504 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \
11505 (old_plane_state) = __i->old_state, \
11506 (new_plane_state) = __i->new_state, 1))
11507
11508static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
11509{
11510 struct drm_connector *connector;
11511 struct drm_connector_state *conn_state, *old_conn_state;
11512 struct amdgpu_dm_connector *aconnector = NULL;
11513 int i;
11514
11515 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
11516 if (!conn_state->crtc)
11517 conn_state = old_conn_state;
11518
11519 if (conn_state->crtc != crtc)
11520 continue;
11521
11522 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
11523 continue;
11524
11525 aconnector = to_amdgpu_dm_connector(connector);
11526 if (!aconnector->mst_output_port || !aconnector->mst_root)
11527 aconnector = NULL;
11528 else
11529 break;
11530 }
11531
11532 if (!aconnector)
11533 return 0;
11534
11535 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
11536}
11537
11538/**
11539 * DOC: Cursor Modes - Native vs Overlay
11540 *
11541 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw
11542 * plane. It does not require a dedicated hw plane to enable, but it is
11543 * subjected to the same z-order and scaling as the hw plane. It also has format
11544 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB
11545 * hw plane.
11546 *
11547 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its
11548 * own scaling and z-pos. It also has no blending restrictions. It lends to a
11549 * cursor behavior more akin to a DRM client's expectations. However, it does
11550 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is
11551 * available.
11552 */
11553
11554/**
11555 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc
11556 * @adev: amdgpu device
11557 * @state: DRM atomic state
11558 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor
11559 * @cursor_mode: Returns the required cursor mode on dm_crtc_state
11560 *
11561 * Get whether the cursor should be enabled in native mode, or overlay mode, on
11562 * the dm_crtc_state.
11563 *
11564 * The cursor should be enabled in overlay mode if there exists an underlying
11565 * plane - on which the cursor may be blended - that is either YUV formatted, or
11566 * scaled differently from the cursor.
11567 *
11568 * Since zpos info is required, drm_atomic_normalize_zpos must be called before
11569 * calling this function.
11570 *
11571 * Return: 0 on success, or an error code if getting the cursor plane state
11572 * failed.
11573 */
11574static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
11575 struct drm_atomic_state *state,
11576 struct dm_crtc_state *dm_crtc_state,
11577 enum amdgpu_dm_cursor_mode *cursor_mode)
11578{
11579 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;
11580 struct drm_crtc_state *crtc_state = &dm_crtc_state->base;
11581 struct drm_plane *plane;
11582 bool consider_mode_change = false;
11583 bool entire_crtc_covered = false;
11584 bool cursor_changed = false;
11585 int underlying_scale_w, underlying_scale_h;
11586 int cursor_scale_w, cursor_scale_h;
11587 int i;
11588
11589 /* Overlay cursor not supported on HW before DCN
11590 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
11591 * as previous DCN generations, so enable native mode on DCN401 in addition to DCE
11592 */
11593 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 ||
11594 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
11595 *cursor_mode = DM_CURSOR_NATIVE_MODE;
11596 return 0;
11597 }
11598
11599 /* Init cursor_mode to be the same as current */
11600 *cursor_mode = dm_crtc_state->cursor_mode;
11601
11602 /*
11603 * Cursor mode can change if a plane's format changes, scale changes, is
11604 * enabled/disabled, or z-order changes.
11605 */
11606 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {
11607 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
11608
11609 /* Only care about planes on this CRTC */
11610 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)
11611 continue;
11612
11613 if (plane->type == DRM_PLANE_TYPE_CURSOR)
11614 cursor_changed = true;
11615
11616 if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||
11617 drm_atomic_plane_disabling(old_plane_state, plane_state) ||
11618 old_plane_state->fb->format != plane_state->fb->format) {
11619 consider_mode_change = true;
11620 break;
11621 }
11622
11623 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h);
11624 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
11625 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
11626 consider_mode_change = true;
11627 break;
11628 }
11629 }
11630
11631 if (!consider_mode_change && !crtc_state->zpos_changed)
11632 return 0;
11633
11634 /*
11635 * If no cursor change on this CRTC, and not enabled on this CRTC, then
11636 * no need to set cursor mode. This avoids needlessly locking the cursor
11637 * state.
11638 */
11639 if (!cursor_changed &&
11640 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) {
11641 return 0;
11642 }
11643
11644 cursor_state = drm_atomic_get_plane_state(state,
11645 crtc_state->crtc->cursor);
11646 if (IS_ERR(cursor_state))
11647 return PTR_ERR(cursor_state);
11648
11649 /* Cursor is disabled */
11650 if (!cursor_state->fb)
11651 return 0;
11652
11653 /* For all planes in descending z-order (all of which are below cursor
11654 * as per zpos definitions), check their scaling and format
11655 */
11656 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {
11657
11658 /* Only care about non-cursor planes on this CRTC */
11659 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||
11660 plane->type == DRM_PLANE_TYPE_CURSOR)
11661 continue;
11662
11663 /* Underlying plane is YUV format - use overlay cursor */
11664 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) {
11665 *cursor_mode = DM_CURSOR_OVERLAY_MODE;
11666 return 0;
11667 }
11668
11669 dm_get_plane_scale(plane_state,
11670 &underlying_scale_w, &underlying_scale_h);
11671 dm_get_plane_scale(cursor_state,
11672 &cursor_scale_w, &cursor_scale_h);
11673
11674 /* Underlying plane has different scale - use overlay cursor */
11675 if (cursor_scale_w != underlying_scale_w &&
11676 cursor_scale_h != underlying_scale_h) {
11677 *cursor_mode = DM_CURSOR_OVERLAY_MODE;
11678 return 0;
11679 }
11680
11681 /* If this plane covers the whole CRTC, no need to check planes underneath */
11682 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 &&
11683 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&
11684 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {
11685 entire_crtc_covered = true;
11686 break;
11687 }
11688 }
11689
11690 /* If planes do not cover the entire CRTC, use overlay mode to enable
11691 * cursor over holes
11692 */
11693 if (entire_crtc_covered)
11694 *cursor_mode = DM_CURSOR_NATIVE_MODE;
11695 else
11696 *cursor_mode = DM_CURSOR_OVERLAY_MODE;
11697
11698 return 0;
11699}
11700
11701static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,
11702 struct drm_atomic_state *state,
11703 struct drm_crtc_state *crtc_state)
11704{
11705 struct drm_plane *plane;
11706 struct drm_plane_state *new_plane_state, *old_plane_state;
11707
11708 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
11709 new_plane_state = drm_atomic_get_plane_state(state, plane);
11710 old_plane_state = drm_atomic_get_plane_state(state, plane);
11711
11712 if (IS_ERR(new_plane_state) || IS_ERR(old_plane_state)) {
11713 drm_err(dev, "Failed to get plane state for plane %s\n", plane->name);
11714 return false;
11715 }
11716
11717 if (old_plane_state->fb && new_plane_state->fb &&
11718 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb))
11719 return true;
11720 }
11721
11722 return false;
11723}
11724
11725/**
11726 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
11727 *
11728 * @dev: The DRM device
11729 * @state: The atomic state to commit
11730 *
11731 * Validate that the given atomic state is programmable by DC into hardware.
11732 * This involves constructing a &struct dc_state reflecting the new hardware
11733 * state we wish to commit, then querying DC to see if it is programmable. It's
11734 * important not to modify the existing DC state. Otherwise, atomic_check
11735 * may unexpectedly commit hardware changes.
11736 *
11737 * When validating the DC state, it's important that the right locks are
11738 * acquired. For full updates case which removes/adds/updates streams on one
11739 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
11740 * that any such full update commit will wait for completion of any outstanding
11741 * flip using DRMs synchronization events.
11742 *
11743 * Note that DM adds the affected connectors for all CRTCs in state, when that
11744 * might not seem necessary. This is because DC stream creation requires the
11745 * DC sink, which is tied to the DRM connector state. Cleaning this up should
11746 * be possible but non-trivial - a possible TODO item.
11747 *
11748 * Return: -Error code if validation failed.
11749 */
11750static int amdgpu_dm_atomic_check(struct drm_device *dev,
11751 struct drm_atomic_state *state)
11752{
11753 struct amdgpu_device *adev = drm_to_adev(dev);
11754 struct dm_atomic_state *dm_state = NULL;
11755 struct dc *dc = adev->dm.dc;
11756 struct drm_connector *connector;
11757 struct drm_connector_state *old_con_state, *new_con_state;
11758 struct drm_crtc *crtc;
11759 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11760 struct drm_plane *plane;
11761 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state;
11762 enum dc_status status;
11763 int ret, i;
11764 bool lock_and_validation_needed = false;
11765 bool is_top_most_overlay = true;
11766 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
11767 struct drm_dp_mst_topology_mgr *mgr;
11768 struct drm_dp_mst_topology_state *mst_state;
11769 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};
11770
11771 trace_amdgpu_dm_atomic_check_begin(state);
11772
11773 ret = drm_atomic_helper_check_modeset(dev, state);
11774 if (ret) {
11775 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n");
11776 goto fail;
11777 }
11778
11779 /* Check connector changes */
11780 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
11781 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
11782 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
11783
11784 /* Skip connectors that are disabled or part of modeset already. */
11785 if (!new_con_state->crtc)
11786 continue;
11787
11788 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
11789 if (IS_ERR(new_crtc_state)) {
11790 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n");
11791 ret = PTR_ERR(new_crtc_state);
11792 goto fail;
11793 }
11794
11795 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
11796 dm_old_con_state->scaling != dm_new_con_state->scaling)
11797 new_crtc_state->connectors_changed = true;
11798 }
11799
11800 if (dc_resource_is_dsc_encoding_supported(dc)) {
11801 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11802 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
11803 ret = add_affected_mst_dsc_crtcs(state, crtc);
11804 if (ret) {
11805 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n");
11806 goto fail;
11807 }
11808 }
11809 }
11810 }
11811 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11812 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
11813
11814 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
11815 !new_crtc_state->color_mgmt_changed &&
11816 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
11817 dm_old_crtc_state->dsc_force_changed == false)
11818 continue;
11819
11820 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
11821 if (ret) {
11822 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n");
11823 goto fail;
11824 }
11825
11826 if (!new_crtc_state->enable)
11827 continue;
11828
11829 ret = drm_atomic_add_affected_connectors(state, crtc);
11830 if (ret) {
11831 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n");
11832 goto fail;
11833 }
11834
11835 ret = drm_atomic_add_affected_planes(state, crtc);
11836 if (ret) {
11837 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n");
11838 goto fail;
11839 }
11840
11841 if (dm_old_crtc_state->dsc_force_changed)
11842 new_crtc_state->mode_changed = true;
11843 }
11844
11845 /*
11846 * Add all primary and overlay planes on the CRTC to the state
11847 * whenever a plane is enabled to maintain correct z-ordering
11848 * and to enable fast surface updates.
11849 */
11850 drm_for_each_crtc(crtc, dev) {
11851 bool modified = false;
11852
11853 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
11854 if (plane->type == DRM_PLANE_TYPE_CURSOR)
11855 continue;
11856
11857 if (new_plane_state->crtc == crtc ||
11858 old_plane_state->crtc == crtc) {
11859 modified = true;
11860 break;
11861 }
11862 }
11863
11864 if (!modified)
11865 continue;
11866
11867 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
11868 if (plane->type == DRM_PLANE_TYPE_CURSOR)
11869 continue;
11870
11871 new_plane_state =
11872 drm_atomic_get_plane_state(state, plane);
11873
11874 if (IS_ERR(new_plane_state)) {
11875 ret = PTR_ERR(new_plane_state);
11876 drm_dbg_atomic(dev, "new_plane_state is BAD\n");
11877 goto fail;
11878 }
11879 }
11880 }
11881
11882 /*
11883 * DC consults the zpos (layer_index in DC terminology) to determine the
11884 * hw plane on which to enable the hw cursor (see
11885 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
11886 * atomic state, so call drm helper to normalize zpos.
11887 */
11888 ret = drm_atomic_normalize_zpos(dev, state);
11889 if (ret) {
11890 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
11891 goto fail;
11892 }
11893
11894 /*
11895 * Determine whether cursors on each CRTC should be enabled in native or
11896 * overlay mode.
11897 */
11898 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11899 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11900
11901 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,
11902 &dm_new_crtc_state->cursor_mode);
11903 if (ret) {
11904 drm_dbg(dev, "Failed to determine cursor mode\n");
11905 goto fail;
11906 }
11907
11908 /*
11909 * If overlay cursor is needed, DC cannot go through the
11910 * native cursor update path. All enabled planes on the CRTC
11911 * need to be added for DC to not disable a plane by mistake
11912 */
11913 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) {
11914 ret = drm_atomic_add_affected_planes(state, crtc);
11915 if (ret)
11916 goto fail;
11917 }
11918 }
11919
11920 /* Remove exiting planes if they are modified */
11921 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
11922
11923 ret = dm_update_plane_state(dc, state, plane,
11924 old_plane_state,
11925 new_plane_state,
11926 false,
11927 &lock_and_validation_needed,
11928 &is_top_most_overlay);
11929 if (ret) {
11930 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");
11931 goto fail;
11932 }
11933 }
11934
11935 /* Disable all crtcs which require disable */
11936 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11937 ret = dm_update_crtc_state(&adev->dm, state, crtc,
11938 old_crtc_state,
11939 new_crtc_state,
11940 false,
11941 &lock_and_validation_needed);
11942 if (ret) {
11943 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n");
11944 goto fail;
11945 }
11946 }
11947
11948 /* Enable all crtcs which require enable */
11949 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11950 ret = dm_update_crtc_state(&adev->dm, state, crtc,
11951 old_crtc_state,
11952 new_crtc_state,
11953 true,
11954 &lock_and_validation_needed);
11955 if (ret) {
11956 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n");
11957 goto fail;
11958 }
11959 }
11960
11961 /* Add new/modified planes */
11962 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
11963 ret = dm_update_plane_state(dc, state, plane,
11964 old_plane_state,
11965 new_plane_state,
11966 true,
11967 &lock_and_validation_needed,
11968 &is_top_most_overlay);
11969 if (ret) {
11970 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");
11971 goto fail;
11972 }
11973 }
11974
11975#if defined(CONFIG_DRM_AMD_DC_FP)
11976 if (dc_resource_is_dsc_encoding_supported(dc)) {
11977 ret = pre_validate_dsc(state, &dm_state, vars);
11978 if (ret != 0)
11979 goto fail;
11980 }
11981#endif
11982
11983 /* Run this here since we want to validate the streams we created */
11984 ret = drm_atomic_helper_check_planes(dev, state);
11985 if (ret) {
11986 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n");
11987 goto fail;
11988 }
11989
11990 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11991 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11992 if (dm_new_crtc_state->mpo_requested)
11993 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc);
11994 }
11995
11996 /* Check cursor restrictions */
11997 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11998 enum amdgpu_dm_cursor_mode required_cursor_mode;
11999 int is_rotated, is_scaled;
12000
12001 /* Overlay cusor not subject to native cursor restrictions */
12002 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
12003 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE)
12004 continue;
12005
12006 /* Check if rotation or scaling is enabled on DCN401 */
12007 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) &&
12008 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
12009 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
12010
12011 is_rotated = new_cursor_state &&
12012 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0);
12013 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) ||
12014 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h));
12015
12016 if (is_rotated || is_scaled) {
12017 drm_dbg_driver(
12018 crtc->dev,
12019 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n",
12020 crtc->base.id, crtc->name);
12021 ret = -EINVAL;
12022 goto fail;
12023 }
12024 }
12025
12026 /* If HW can only do native cursor, check restrictions again */
12027 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,
12028 &required_cursor_mode);
12029 if (ret) {
12030 drm_dbg_driver(crtc->dev,
12031 "[CRTC:%d:%s] Checking cursor mode failed\n",
12032 crtc->base.id, crtc->name);
12033 goto fail;
12034 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) {
12035 drm_dbg_driver(crtc->dev,
12036 "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n",
12037 crtc->base.id, crtc->name);
12038 ret = -EINVAL;
12039 goto fail;
12040 }
12041 }
12042
12043 if (state->legacy_cursor_update) {
12044 /*
12045 * This is a fast cursor update coming from the plane update
12046 * helper, check if it can be done asynchronously for better
12047 * performance.
12048 */
12049 state->async_update =
12050 !drm_atomic_helper_async_check(dev, state);
12051
12052 /*
12053 * Skip the remaining global validation if this is an async
12054 * update. Cursor updates can be done without affecting
12055 * state or bandwidth calcs and this avoids the performance
12056 * penalty of locking the private state object and
12057 * allocating a new dc_state.
12058 */
12059 if (state->async_update)
12060 return 0;
12061 }
12062
12063 /* Check scaling and underscan changes*/
12064 /* TODO Removed scaling changes validation due to inability to commit
12065 * new stream into context w\o causing full reset. Need to
12066 * decide how to handle.
12067 */
12068 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
12069 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
12070 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
12071 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
12072
12073 /* Skip any modesets/resets */
12074 if (!acrtc || drm_atomic_crtc_needs_modeset(
12075 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
12076 continue;
12077
12078 /* Skip any thing not scale or underscan changes */
12079 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
12080 continue;
12081
12082 lock_and_validation_needed = true;
12083 }
12084
12085 /* set the slot info for each mst_state based on the link encoding format */
12086 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
12087 struct amdgpu_dm_connector *aconnector;
12088 struct drm_connector *connector;
12089 struct drm_connector_list_iter iter;
12090 u8 link_coding_cap;
12091
12092 drm_connector_list_iter_begin(dev, &iter);
12093 drm_for_each_connector_iter(connector, &iter) {
12094 if (connector->index == mst_state->mgr->conn_base_id) {
12095 aconnector = to_amdgpu_dm_connector(connector);
12096 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
12097 drm_dp_mst_update_slots(mst_state, link_coding_cap);
12098
12099 break;
12100 }
12101 }
12102 drm_connector_list_iter_end(&iter);
12103 }
12104
12105 /**
12106 * Streams and planes are reset when there are changes that affect
12107 * bandwidth. Anything that affects bandwidth needs to go through
12108 * DC global validation to ensure that the configuration can be applied
12109 * to hardware.
12110 *
12111 * We have to currently stall out here in atomic_check for outstanding
12112 * commits to finish in this case because our IRQ handlers reference
12113 * DRM state directly - we can end up disabling interrupts too early
12114 * if we don't.
12115 *
12116 * TODO: Remove this stall and drop DM state private objects.
12117 */
12118 if (lock_and_validation_needed) {
12119 ret = dm_atomic_get_state(state, &dm_state);
12120 if (ret) {
12121 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n");
12122 goto fail;
12123 }
12124
12125 ret = do_aquire_global_lock(dev, state);
12126 if (ret) {
12127 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n");
12128 goto fail;
12129 }
12130
12131#if defined(CONFIG_DRM_AMD_DC_FP)
12132 if (dc_resource_is_dsc_encoding_supported(dc)) {
12133 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
12134 if (ret) {
12135 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n");
12136 ret = -EINVAL;
12137 goto fail;
12138 }
12139 }
12140#endif
12141
12142 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
12143 if (ret) {
12144 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n");
12145 goto fail;
12146 }
12147
12148 /*
12149 * Perform validation of MST topology in the state:
12150 * We need to perform MST atomic check before calling
12151 * dc_validate_global_state(), or there is a chance
12152 * to get stuck in an infinite loop and hang eventually.
12153 */
12154 ret = drm_dp_mst_atomic_check(state);
12155 if (ret) {
12156 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n");
12157 goto fail;
12158 }
12159 status = dc_validate_global_state(dc, dm_state->context, true);
12160 if (status != DC_OK) {
12161 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)",
12162 dc_status_to_str(status), status);
12163 ret = -EINVAL;
12164 goto fail;
12165 }
12166 } else {
12167 /*
12168 * The commit is a fast update. Fast updates shouldn't change
12169 * the DC context, affect global validation, and can have their
12170 * commit work done in parallel with other commits not touching
12171 * the same resource. If we have a new DC context as part of
12172 * the DM atomic state from validation we need to free it and
12173 * retain the existing one instead.
12174 *
12175 * Furthermore, since the DM atomic state only contains the DC
12176 * context and can safely be annulled, we can free the state
12177 * and clear the associated private object now to free
12178 * some memory and avoid a possible use-after-free later.
12179 */
12180
12181 for (i = 0; i < state->num_private_objs; i++) {
12182 struct drm_private_obj *obj = state->private_objs[i].ptr;
12183
12184 if (obj->funcs == adev->dm.atomic_obj.funcs) {
12185 int j = state->num_private_objs-1;
12186
12187 dm_atomic_destroy_state(obj,
12188 state->private_objs[i].state);
12189
12190 /* If i is not at the end of the array then the
12191 * last element needs to be moved to where i was
12192 * before the array can safely be truncated.
12193 */
12194 if (i != j)
12195 state->private_objs[i] =
12196 state->private_objs[j];
12197
12198 state->private_objs[j].ptr = NULL;
12199 state->private_objs[j].state = NULL;
12200 state->private_objs[j].old_state = NULL;
12201 state->private_objs[j].new_state = NULL;
12202
12203 state->num_private_objs = j;
12204 break;
12205 }
12206 }
12207 }
12208
12209 /* Store the overall update type for use later in atomic check. */
12210 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12211 struct dm_crtc_state *dm_new_crtc_state =
12212 to_dm_crtc_state(new_crtc_state);
12213
12214 /*
12215 * Only allow async flips for fast updates that don't change
12216 * the FB pitch, the DCC state, rotation, mem_type, etc.
12217 */
12218 if (new_crtc_state->async_flip &&
12219 (lock_and_validation_needed ||
12220 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) {
12221 drm_dbg_atomic(crtc->dev,
12222 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
12223 crtc->base.id, crtc->name);
12224 ret = -EINVAL;
12225 goto fail;
12226 }
12227
12228 dm_new_crtc_state->update_type = lock_and_validation_needed ?
12229 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
12230 }
12231
12232 /* Must be success */
12233 WARN_ON(ret);
12234
12235 trace_amdgpu_dm_atomic_check_finish(state, ret);
12236
12237 return ret;
12238
12239fail:
12240 if (ret == -EDEADLK)
12241 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n");
12242 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
12243 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n");
12244 else
12245 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret);
12246
12247 trace_amdgpu_dm_atomic_check_finish(state, ret);
12248
12249 return ret;
12250}
12251
12252static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
12253 unsigned int offset,
12254 unsigned int total_length,
12255 u8 *data,
12256 unsigned int length,
12257 struct amdgpu_hdmi_vsdb_info *vsdb)
12258{
12259 bool res;
12260 union dmub_rb_cmd cmd;
12261 struct dmub_cmd_send_edid_cea *input;
12262 struct dmub_cmd_edid_cea_output *output;
12263
12264 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
12265 return false;
12266
12267 memset(&cmd, 0, sizeof(cmd));
12268
12269 input = &cmd.edid_cea.data.input;
12270
12271 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
12272 cmd.edid_cea.header.sub_type = 0;
12273 cmd.edid_cea.header.payload_bytes =
12274 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
12275 input->offset = offset;
12276 input->length = length;
12277 input->cea_total_length = total_length;
12278 memcpy(input->payload, data, length);
12279
12280 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
12281 if (!res) {
12282 drm_err(adev_to_drm(dm->adev), "EDID CEA parser failed\n");
12283 return false;
12284 }
12285
12286 output = &cmd.edid_cea.data.output;
12287
12288 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
12289 if (!output->ack.success) {
12290 drm_err(adev_to_drm(dm->adev), "EDID CEA ack failed at offset %d\n",
12291 output->ack.offset);
12292 }
12293 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
12294 if (!output->amd_vsdb.vsdb_found)
12295 return false;
12296
12297 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
12298 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
12299 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
12300 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
12301 } else {
12302 drm_warn(adev_to_drm(dm->adev), "Unknown EDID CEA parser results\n");
12303 return false;
12304 }
12305
12306 return true;
12307}
12308
12309static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
12310 u8 *edid_ext, int len,
12311 struct amdgpu_hdmi_vsdb_info *vsdb_info)
12312{
12313 int i;
12314
12315 /* send extension block to DMCU for parsing */
12316 for (i = 0; i < len; i += 8) {
12317 bool res;
12318 int offset;
12319
12320 /* send 8 bytes a time */
12321 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
12322 return false;
12323
12324 if (i+8 == len) {
12325 /* EDID block sent completed, expect result */
12326 int version, min_rate, max_rate;
12327
12328 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
12329 if (res) {
12330 /* amd vsdb found */
12331 vsdb_info->freesync_supported = 1;
12332 vsdb_info->amd_vsdb_version = version;
12333 vsdb_info->min_refresh_rate_hz = min_rate;
12334 vsdb_info->max_refresh_rate_hz = max_rate;
12335 return true;
12336 }
12337 /* not amd vsdb */
12338 return false;
12339 }
12340
12341 /* check for ack*/
12342 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
12343 if (!res)
12344 return false;
12345 }
12346
12347 return false;
12348}
12349
12350static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
12351 u8 *edid_ext, int len,
12352 struct amdgpu_hdmi_vsdb_info *vsdb_info)
12353{
12354 int i;
12355
12356 /* send extension block to DMCU for parsing */
12357 for (i = 0; i < len; i += 8) {
12358 /* send 8 bytes a time */
12359 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
12360 return false;
12361 }
12362
12363 return vsdb_info->freesync_supported;
12364}
12365
12366static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
12367 u8 *edid_ext, int len,
12368 struct amdgpu_hdmi_vsdb_info *vsdb_info)
12369{
12370 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
12371 bool ret;
12372
12373 mutex_lock(&adev->dm.dc_lock);
12374 if (adev->dm.dmub_srv)
12375 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
12376 else
12377 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
12378 mutex_unlock(&adev->dm.dc_lock);
12379 return ret;
12380}
12381
12382static void parse_edid_displayid_vrr(struct drm_connector *connector,
12383 const struct edid *edid)
12384{
12385 u8 *edid_ext = NULL;
12386 int i;
12387 int j = 0;
12388 u16 min_vfreq;
12389 u16 max_vfreq;
12390
12391 if (edid == NULL || edid->extensions == 0)
12392 return;
12393
12394 /* Find DisplayID extension */
12395 for (i = 0; i < edid->extensions; i++) {
12396 edid_ext = (void *)(edid + (i + 1));
12397 if (edid_ext[0] == DISPLAYID_EXT)
12398 break;
12399 }
12400
12401 if (edid_ext == NULL)
12402 return;
12403
12404 while (j < EDID_LENGTH) {
12405 /* Get dynamic video timing range from DisplayID if available */
12406 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 &&
12407 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) {
12408 min_vfreq = edid_ext[j+9];
12409 if (edid_ext[j+1] & 7)
12410 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8);
12411 else
12412 max_vfreq = edid_ext[j+10];
12413
12414 if (max_vfreq && min_vfreq) {
12415 connector->display_info.monitor_range.max_vfreq = max_vfreq;
12416 connector->display_info.monitor_range.min_vfreq = min_vfreq;
12417
12418 return;
12419 }
12420 }
12421 j++;
12422 }
12423}
12424
12425static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
12426 const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
12427{
12428 u8 *edid_ext = NULL;
12429 int i;
12430 int j = 0;
12431
12432 if (edid == NULL || edid->extensions == 0)
12433 return -ENODEV;
12434
12435 /* Find DisplayID extension */
12436 for (i = 0; i < edid->extensions; i++) {
12437 edid_ext = (void *)(edid + (i + 1));
12438 if (edid_ext[0] == DISPLAYID_EXT)
12439 break;
12440 }
12441
12442 while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
12443 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
12444 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
12445
12446 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
12447 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
12448 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
12449 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
12450 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
12451
12452 return true;
12453 }
12454 j++;
12455 }
12456
12457 return false;
12458}
12459
12460static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
12461 const struct edid *edid,
12462 struct amdgpu_hdmi_vsdb_info *vsdb_info)
12463{
12464 u8 *edid_ext = NULL;
12465 int i;
12466 bool valid_vsdb_found = false;
12467
12468 /*----- drm_find_cea_extension() -----*/
12469 /* No EDID or EDID extensions */
12470 if (edid == NULL || edid->extensions == 0)
12471 return -ENODEV;
12472
12473 /* Find CEA extension */
12474 for (i = 0; i < edid->extensions; i++) {
12475 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
12476 if (edid_ext[0] == CEA_EXT)
12477 break;
12478 }
12479
12480 if (i == edid->extensions)
12481 return -ENODEV;
12482
12483 /*----- cea_db_offsets() -----*/
12484 if (edid_ext[0] != CEA_EXT)
12485 return -ENODEV;
12486
12487 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
12488
12489 return valid_vsdb_found ? i : -ENODEV;
12490}
12491
12492/**
12493 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
12494 *
12495 * @connector: Connector to query.
12496 * @drm_edid: DRM EDID from monitor
12497 *
12498 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
12499 * track of some of the display information in the internal data struct used by
12500 * amdgpu_dm. This function checks which type of connector we need to set the
12501 * FreeSync parameters.
12502 */
12503void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
12504 const struct drm_edid *drm_edid)
12505{
12506 int i = 0;
12507 struct amdgpu_dm_connector *amdgpu_dm_connector =
12508 to_amdgpu_dm_connector(connector);
12509 struct dm_connector_state *dm_con_state = NULL;
12510 struct dc_sink *sink;
12511 struct amdgpu_device *adev = drm_to_adev(connector->dev);
12512 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
12513 const struct edid *edid;
12514 bool freesync_capable = false;
12515 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
12516
12517 if (!connector->state) {
12518 drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__);
12519 goto update;
12520 }
12521
12522 sink = amdgpu_dm_connector->dc_sink ?
12523 amdgpu_dm_connector->dc_sink :
12524 amdgpu_dm_connector->dc_em_sink;
12525
12526 drm_edid_connector_update(connector, drm_edid);
12527
12528 if (!drm_edid || !sink) {
12529 dm_con_state = to_dm_connector_state(connector->state);
12530
12531 amdgpu_dm_connector->min_vfreq = 0;
12532 amdgpu_dm_connector->max_vfreq = 0;
12533 freesync_capable = false;
12534
12535 goto update;
12536 }
12537
12538 dm_con_state = to_dm_connector_state(connector->state);
12539
12540 if (!adev->dm.freesync_module)
12541 goto update;
12542
12543 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
12544
12545 /* Some eDP panels only have the refresh rate range info in DisplayID */
12546 if ((connector->display_info.monitor_range.min_vfreq == 0 ||
12547 connector->display_info.monitor_range.max_vfreq == 0))
12548 parse_edid_displayid_vrr(connector, edid);
12549
12550 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
12551 sink->sink_signal == SIGNAL_TYPE_EDP)) {
12552 if (amdgpu_dm_connector->dc_link &&
12553 amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
12554 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
12555 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
12556 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12557 freesync_capable = true;
12558 }
12559
12560 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12561
12562 if (vsdb_info.replay_mode) {
12563 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
12564 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
12565 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
12566 }
12567
12568 } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
12569 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12570 if (i >= 0 && vsdb_info.freesync_supported) {
12571 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
12572 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
12573 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12574 freesync_capable = true;
12575
12576 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
12577 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
12578 }
12579 }
12580
12581 if (amdgpu_dm_connector->dc_link)
12582 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
12583
12584 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
12585 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12586 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
12587
12588 amdgpu_dm_connector->pack_sdp_v1_3 = true;
12589 amdgpu_dm_connector->as_type = as_type;
12590 amdgpu_dm_connector->vsdb_info = vsdb_info;
12591
12592 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
12593 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
12594 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12595 freesync_capable = true;
12596
12597 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
12598 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
12599 }
12600 }
12601
12602update:
12603 if (dm_con_state)
12604 dm_con_state->freesync_capable = freesync_capable;
12605
12606 if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable &&
12607 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) {
12608 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false;
12609 amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false;
12610 }
12611
12612 if (connector->vrr_capable_property)
12613 drm_connector_set_vrr_capable_property(connector,
12614 freesync_capable);
12615}
12616
12617void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
12618{
12619 struct amdgpu_device *adev = drm_to_adev(dev);
12620 struct dc *dc = adev->dm.dc;
12621 int i;
12622
12623 mutex_lock(&adev->dm.dc_lock);
12624 if (dc->current_state) {
12625 for (i = 0; i < dc->current_state->stream_count; ++i)
12626 dc->current_state->streams[i]
12627 ->triggered_crtc_reset.enabled =
12628 adev->dm.force_timing_sync;
12629
12630 dm_enable_per_frame_crtc_master_sync(dc->current_state);
12631 dc_trigger_sync(dc, dc->current_state);
12632 }
12633 mutex_unlock(&adev->dm.dc_lock);
12634}
12635
12636static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)
12637{
12638 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
12639 dc_exit_ips_for_hw_access(dc);
12640}
12641
12642void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
12643 u32 value, const char *func_name)
12644{
12645#ifdef DM_CHECK_ADDR_0
12646 if (address == 0) {
12647 drm_err(adev_to_drm(ctx->driver_context),
12648 "invalid register write. address = 0");
12649 return;
12650 }
12651#endif
12652
12653 amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
12654 cgs_write_register(ctx->cgs_device, address, value);
12655 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
12656}
12657
12658uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
12659 const char *func_name)
12660{
12661 u32 value;
12662#ifdef DM_CHECK_ADDR_0
12663 if (address == 0) {
12664 drm_err(adev_to_drm(ctx->driver_context),
12665 "invalid register read; address = 0\n");
12666 return 0;
12667 }
12668#endif
12669
12670 if (ctx->dmub_srv &&
12671 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
12672 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
12673 ASSERT(false);
12674 return 0;
12675 }
12676
12677 amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
12678
12679 value = cgs_read_register(ctx->cgs_device, address);
12680
12681 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
12682
12683 return value;
12684}
12685
12686int amdgpu_dm_process_dmub_aux_transfer_sync(
12687 struct dc_context *ctx,
12688 unsigned int link_index,
12689 struct aux_payload *payload,
12690 enum aux_return_code_type *operation_result)
12691{
12692 struct amdgpu_device *adev = ctx->driver_context;
12693 struct dmub_notification *p_notify = adev->dm.dmub_notify;
12694 int ret = -1;
12695
12696 mutex_lock(&adev->dm.dpia_aux_lock);
12697 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
12698 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
12699 goto out;
12700 }
12701
12702 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
12703 drm_err(adev_to_drm(adev), "wait_for_completion_timeout timeout!");
12704 *operation_result = AUX_RET_ERROR_TIMEOUT;
12705 goto out;
12706 }
12707
12708 if (p_notify->result != AUX_RET_SUCCESS) {
12709 /*
12710 * Transient states before tunneling is enabled could
12711 * lead to this error. We can ignore this for now.
12712 */
12713 if (p_notify->result == AUX_RET_ERROR_PROTOCOL_ERROR) {
12714 drm_warn(adev_to_drm(adev), "DPIA AUX failed on 0x%x(%d), error %d\n",
12715 payload->address, payload->length,
12716 p_notify->result);
12717 }
12718 *operation_result = p_notify->result;
12719 goto out;
12720 }
12721
12722 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command & 0xF;
12723 if (adev->dm.dmub_notify->aux_reply.command & 0xF0)
12724 /* The reply is stored in the top nibble of the command. */
12725 payload->reply[0] = (adev->dm.dmub_notify->aux_reply.command >> 4) & 0xF;
12726
12727 /*write req may receive a byte indicating partially written number as well*/
12728 if (p_notify->aux_reply.length)
12729 memcpy(payload->data, p_notify->aux_reply.data,
12730 p_notify->aux_reply.length);
12731
12732 /* success */
12733 ret = p_notify->aux_reply.length;
12734 *operation_result = p_notify->result;
12735out:
12736 reinit_completion(&adev->dm.dmub_aux_transfer_done);
12737 mutex_unlock(&adev->dm.dpia_aux_lock);
12738 return ret;
12739}
12740
12741static void abort_fused_io(
12742 struct dc_context *ctx,
12743 const struct dmub_cmd_fused_request *request
12744)
12745{
12746 union dmub_rb_cmd command = { 0 };
12747 struct dmub_rb_cmd_fused_io *io = &command.fused_io;
12748
12749 io->header.type = DMUB_CMD__FUSED_IO;
12750 io->header.sub_type = DMUB_CMD__FUSED_IO_ABORT;
12751 io->header.payload_bytes = sizeof(*io) - sizeof(io->header);
12752 io->request = *request;
12753 dm_execute_dmub_cmd(ctx, &command, DM_DMUB_WAIT_TYPE_NO_WAIT);
12754}
12755
12756static bool execute_fused_io(
12757 struct amdgpu_device *dev,
12758 struct dc_context *ctx,
12759 union dmub_rb_cmd *commands,
12760 uint8_t count,
12761 uint32_t timeout_us
12762)
12763{
12764 const uint8_t ddc_line = commands[0].fused_io.request.u.aux.ddc_line;
12765
12766 if (ddc_line >= ARRAY_SIZE(dev->dm.fused_io))
12767 return false;
12768
12769 struct fused_io_sync *sync = &dev->dm.fused_io[ddc_line];
12770 struct dmub_rb_cmd_fused_io *first = &commands[0].fused_io;
12771 const bool result = dm_execute_dmub_cmd_list(ctx, count, commands, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
12772 && first->header.ret_status
12773 && first->request.status == FUSED_REQUEST_STATUS_SUCCESS;
12774
12775 if (!result)
12776 return false;
12777
12778 while (wait_for_completion_timeout(&sync->replied, usecs_to_jiffies(timeout_us))) {
12779 reinit_completion(&sync->replied);
12780
12781 struct dmub_cmd_fused_request *reply = (struct dmub_cmd_fused_request *) sync->reply_data;
12782
12783 static_assert(sizeof(*reply) <= sizeof(sync->reply_data), "Size mismatch");
12784
12785 if (reply->identifier == first->request.identifier) {
12786 first->request = *reply;
12787 return true;
12788 }
12789 }
12790
12791 reinit_completion(&sync->replied);
12792 first->request.status = FUSED_REQUEST_STATUS_TIMEOUT;
12793 abort_fused_io(ctx, &first->request);
12794 return false;
12795}
12796
12797bool amdgpu_dm_execute_fused_io(
12798 struct amdgpu_device *dev,
12799 struct dc_link *link,
12800 union dmub_rb_cmd *commands,
12801 uint8_t count,
12802 uint32_t timeout_us)
12803{
12804 struct amdgpu_display_manager *dm = &dev->dm;
12805
12806 mutex_lock(&dm->dpia_aux_lock);
12807
12808 const bool result = execute_fused_io(dev, link->ctx, commands, count, timeout_us);
12809
12810 mutex_unlock(&dm->dpia_aux_lock);
12811 return result;
12812}
12813
12814int amdgpu_dm_process_dmub_set_config_sync(
12815 struct dc_context *ctx,
12816 unsigned int link_index,
12817 struct set_config_cmd_payload *payload,
12818 enum set_config_status *operation_result)
12819{
12820 struct amdgpu_device *adev = ctx->driver_context;
12821 bool is_cmd_complete;
12822 int ret;
12823
12824 mutex_lock(&adev->dm.dpia_aux_lock);
12825 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
12826 link_index, payload, adev->dm.dmub_notify);
12827
12828 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
12829 ret = 0;
12830 *operation_result = adev->dm.dmub_notify->sc_status;
12831 } else {
12832 drm_err(adev_to_drm(adev), "wait_for_completion_timeout timeout!");
12833 ret = -1;
12834 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
12835 }
12836
12837 if (!is_cmd_complete)
12838 reinit_completion(&adev->dm.dmub_aux_transfer_done);
12839 mutex_unlock(&adev->dm.dpia_aux_lock);
12840 return ret;
12841}
12842
12843bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
12844{
12845 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
12846}
12847
12848bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
12849{
12850 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
12851}
12852
12853void dm_acpi_process_phy_transition_interlock(
12854 const struct dc_context *ctx,
12855 struct dm_process_phy_transition_init_params process_phy_transition_init_params)
12856{
12857 // Not yet implemented
12858}
Linux 6.x block layer and io_uring tree(s)